Amit Gandhi / sensen_copy_2

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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
158:b23ee177fd68 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f429xx.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V2.6.1
AnnaBridge 167:e84263d55307 6 * @date 14-February-2017
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file contains:
<> 144:ef7eb2e8f9f7 10 * - Data structures and the address mapping for all peripherals
<> 144:ef7eb2e8f9f7 11 * - peripherals registers declarations and bits definition
AnnaBridge 167:e84263d55307 12 * - Macros to access peripheral's registers hardware
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 ******************************************************************************
<> 144:ef7eb2e8f9f7 15 * @attention
<> 144:ef7eb2e8f9f7 16 *
AnnaBridge 167:e84263d55307 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 20 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 22 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 24 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 25 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 27 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 28 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 29 *
<> 144:ef7eb2e8f9f7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 40 *
<> 144:ef7eb2e8f9f7 41 ******************************************************************************
<> 144:ef7eb2e8f9f7 42 */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /** @addtogroup CMSIS_Device
<> 144:ef7eb2e8f9f7 45 * @{
<> 144:ef7eb2e8f9f7 46 */
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /** @addtogroup stm32f429xx
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 #ifndef __STM32F429xx_H
<> 144:ef7eb2e8f9f7 53 #define __STM32F429xx_H
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 56 extern "C" {
<> 144:ef7eb2e8f9f7 57 #endif /* __cplusplus */
AnnaBridge 167:e84263d55307 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup Configuration_section_for_CMSIS
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
<> 144:ef7eb2e8f9f7 67 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
<> 144:ef7eb2e8f9f7 68 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
<> 144:ef7eb2e8f9f7 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 70 #ifndef __FPU_PRESENT
<> 144:ef7eb2e8f9f7 71 #define __FPU_PRESENT 1U /*!< FPU present */
<> 144:ef7eb2e8f9f7 72 #endif /* __FPU_PRESENT */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /**
<> 144:ef7eb2e8f9f7 75 * @}
<> 144:ef7eb2e8f9f7 76 */
AnnaBridge 167:e84263d55307 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup Peripheral_interrupt_number_definition
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /**
<> 144:ef7eb2e8f9f7 83 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
<> 144:ef7eb2e8f9f7 84 * in @ref Library_configuration_section
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86 typedef enum
<> 144:ef7eb2e8f9f7 87 {
<> 144:ef7eb2e8f9f7 88 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
<> 144:ef7eb2e8f9f7 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 91 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 93 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 95 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 96 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 97 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 144:ef7eb2e8f9f7 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 144:ef7eb2e8f9f7 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 144:ef7eb2e8f9f7 100 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 144:ef7eb2e8f9f7 101 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 144:ef7eb2e8f9f7 102 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 144:ef7eb2e8f9f7 103 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 144:ef7eb2e8f9f7 104 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 144:ef7eb2e8f9f7 105 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 144:ef7eb2e8f9f7 106 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 144:ef7eb2e8f9f7 107 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 144:ef7eb2e8f9f7 108 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 144:ef7eb2e8f9f7 109 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 110 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 111 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 112 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 113 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 114 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 144:ef7eb2e8f9f7 115 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 144:ef7eb2e8f9f7 116 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 144:ef7eb2e8f9f7 117 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
<> 144:ef7eb2e8f9f7 118 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 119 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 120 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
<> 144:ef7eb2e8f9f7 121 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 144:ef7eb2e8f9f7 122 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 144:ef7eb2e8f9f7 123 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 144:ef7eb2e8f9f7 124 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 144:ef7eb2e8f9f7 125 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 144:ef7eb2e8f9f7 126 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 144:ef7eb2e8f9f7 127 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 144:ef7eb2e8f9f7 128 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 144:ef7eb2e8f9f7 129 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 144:ef7eb2e8f9f7 130 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 144:ef7eb2e8f9f7 131 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 167:e84263d55307 132 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 144:ef7eb2e8f9f7 133 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 144:ef7eb2e8f9f7 134 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 144:ef7eb2e8f9f7 135 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 144:ef7eb2e8f9f7 136 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 144:ef7eb2e8f9f7 137 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 144:ef7eb2e8f9f7 138 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 144:ef7eb2e8f9f7 139 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
AnnaBridge 167:e84263d55307 140 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 144:ef7eb2e8f9f7 141 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
<> 144:ef7eb2e8f9f7 142 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
<> 144:ef7eb2e8f9f7 143 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
AnnaBridge 167:e84263d55307 144 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
<> 144:ef7eb2e8f9f7 145 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 144:ef7eb2e8f9f7 146 FMC_IRQn = 48, /*!< FMC global Interrupt */
<> 144:ef7eb2e8f9f7 147 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
<> 144:ef7eb2e8f9f7 148 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 144:ef7eb2e8f9f7 149 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 144:ef7eb2e8f9f7 150 UART4_IRQn = 52, /*!< UART4 global Interrupt */
<> 144:ef7eb2e8f9f7 151 UART5_IRQn = 53, /*!< UART5 global Interrupt */
<> 144:ef7eb2e8f9f7 152 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
<> 144:ef7eb2e8f9f7 153 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
<> 144:ef7eb2e8f9f7 154 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 144:ef7eb2e8f9f7 155 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 144:ef7eb2e8f9f7 156 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 144:ef7eb2e8f9f7 157 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 144:ef7eb2e8f9f7 158 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 144:ef7eb2e8f9f7 159 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
<> 144:ef7eb2e8f9f7 160 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
<> 144:ef7eb2e8f9f7 161 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
<> 144:ef7eb2e8f9f7 162 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
<> 144:ef7eb2e8f9f7 163 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
<> 144:ef7eb2e8f9f7 164 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
<> 144:ef7eb2e8f9f7 165 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 144:ef7eb2e8f9f7 166 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 144:ef7eb2e8f9f7 167 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 144:ef7eb2e8f9f7 168 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 144:ef7eb2e8f9f7 169 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 144:ef7eb2e8f9f7 170 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 144:ef7eb2e8f9f7 171 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 144:ef7eb2e8f9f7 172 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
<> 144:ef7eb2e8f9f7 173 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
<> 144:ef7eb2e8f9f7 174 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
<> 144:ef7eb2e8f9f7 175 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
<> 144:ef7eb2e8f9f7 176 DCMI_IRQn = 78, /*!< DCMI global interrupt */
AnnaBridge 167:e84263d55307 177 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
<> 144:ef7eb2e8f9f7 178 FPU_IRQn = 81, /*!< FPU global interrupt */
<> 144:ef7eb2e8f9f7 179 UART7_IRQn = 82, /*!< UART7 global interrupt */
<> 144:ef7eb2e8f9f7 180 UART8_IRQn = 83, /*!< UART8 global interrupt */
<> 144:ef7eb2e8f9f7 181 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
<> 144:ef7eb2e8f9f7 182 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
<> 144:ef7eb2e8f9f7 183 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
<> 144:ef7eb2e8f9f7 184 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
<> 144:ef7eb2e8f9f7 185 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
<> 144:ef7eb2e8f9f7 186 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
<> 144:ef7eb2e8f9f7 187 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
<> 144:ef7eb2e8f9f7 188 } IRQn_Type;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 144:ef7eb2e8f9f7 195 #include "system_stm32f4xx.h"
<> 144:ef7eb2e8f9f7 196 #include <stdint.h>
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** @addtogroup Peripheral_registers_structures
<> 144:ef7eb2e8f9f7 199 * @{
<> 144:ef7eb2e8f9f7 200 */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /**
<> 144:ef7eb2e8f9f7 203 * @brief Analog to Digital Converter
<> 144:ef7eb2e8f9f7 204 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 typedef struct
<> 144:ef7eb2e8f9f7 207 {
<> 144:ef7eb2e8f9f7 208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 167:e84263d55307 209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 144:ef7eb2e8f9f7 223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 228 } ADC_TypeDef;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 typedef struct
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 144:ef7eb2e8f9f7 233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 144:ef7eb2e8f9f7 234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 144:ef7eb2e8f9f7 235 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 144:ef7eb2e8f9f7 236 } ADC_Common_TypeDef;
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /**
<> 144:ef7eb2e8f9f7 240 * @brief Controller Area Network TxMailBox
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 typedef struct
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 144:ef7eb2e8f9f7 246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 144:ef7eb2e8f9f7 248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 144:ef7eb2e8f9f7 249 } CAN_TxMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @brief Controller Area Network FIFOMailBox
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 typedef struct
<> 144:ef7eb2e8f9f7 256 {
<> 144:ef7eb2e8f9f7 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 144:ef7eb2e8f9f7 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 144:ef7eb2e8f9f7 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 144:ef7eb2e8f9f7 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 144:ef7eb2e8f9f7 261 } CAN_FIFOMailBox_TypeDef;
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief Controller Area Network FilterRegister
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 typedef struct
<> 144:ef7eb2e8f9f7 268 {
<> 144:ef7eb2e8f9f7 269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 144:ef7eb2e8f9f7 271 } CAN_FilterRegister_TypeDef;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @brief Controller Area Network
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 typedef struct
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 144:ef7eb2e8f9f7 288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 144:ef7eb2e8f9f7 289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 144:ef7eb2e8f9f7 290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 144:ef7eb2e8f9f7 291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 144:ef7eb2e8f9f7 292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 144:ef7eb2e8f9f7 293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 144:ef7eb2e8f9f7 294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 144:ef7eb2e8f9f7 295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 144:ef7eb2e8f9f7 296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 144:ef7eb2e8f9f7 297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 144:ef7eb2e8f9f7 298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 144:ef7eb2e8f9f7 299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 144:ef7eb2e8f9f7 300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 144:ef7eb2e8f9f7 301 } CAN_TypeDef;
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief CRC calculation unit
<> 144:ef7eb2e8f9f7 305 */
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 typedef struct
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 310 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 311 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 144:ef7eb2e8f9f7 312 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 144:ef7eb2e8f9f7 313 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 314 } CRC_TypeDef;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /**
<> 144:ef7eb2e8f9f7 317 * @brief Digital to Analog Converter
<> 144:ef7eb2e8f9f7 318 */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 typedef struct
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 324 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 325 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 327 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 328 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 329 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 330 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 331 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 332 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 333 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 334 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 335 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 336 } DAC_TypeDef;
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @brief Debug MCU
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 typedef struct
<> 144:ef7eb2e8f9f7 343 {
<> 144:ef7eb2e8f9f7 344 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 345 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 346 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 347 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 348 }DBGMCU_TypeDef;
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /**
<> 144:ef7eb2e8f9f7 351 * @brief DCMI
<> 144:ef7eb2e8f9f7 352 */
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 typedef struct
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 357 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 358 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 359 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 364 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 365 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 366 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 367 } DCMI_TypeDef;
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /**
<> 144:ef7eb2e8f9f7 370 * @brief DMA Controller
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 typedef struct
<> 144:ef7eb2e8f9f7 374 {
<> 144:ef7eb2e8f9f7 375 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 144:ef7eb2e8f9f7 376 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 144:ef7eb2e8f9f7 379 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 144:ef7eb2e8f9f7 380 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 144:ef7eb2e8f9f7 381 } DMA_Stream_TypeDef;
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 typedef struct
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 386 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 389 } DMA_TypeDef;
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @brief DMA2D Controller
<> 144:ef7eb2e8f9f7 393 */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 typedef struct
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 398 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 399 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 400 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 401 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 402 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 403 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 404 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 405 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 406 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 408 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 409 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 410 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 411 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 412 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 414 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 415 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 416 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 417 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
<> 144:ef7eb2e8f9f7 418 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
<> 144:ef7eb2e8f9f7 419 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
<> 144:ef7eb2e8f9f7 420 } DMA2D_TypeDef;
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /**
<> 144:ef7eb2e8f9f7 423 * @brief Ethernet MAC
<> 144:ef7eb2e8f9f7 424 */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 typedef struct
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 __IO uint32_t MACCR;
<> 144:ef7eb2e8f9f7 429 __IO uint32_t MACFFR;
<> 144:ef7eb2e8f9f7 430 __IO uint32_t MACHTHR;
<> 144:ef7eb2e8f9f7 431 __IO uint32_t MACHTLR;
<> 144:ef7eb2e8f9f7 432 __IO uint32_t MACMIIAR;
<> 144:ef7eb2e8f9f7 433 __IO uint32_t MACMIIDR;
<> 144:ef7eb2e8f9f7 434 __IO uint32_t MACFCR;
<> 144:ef7eb2e8f9f7 435 __IO uint32_t MACVLANTR; /* 8 */
<> 144:ef7eb2e8f9f7 436 uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 437 __IO uint32_t MACRWUFFR; /* 11 */
<> 144:ef7eb2e8f9f7 438 __IO uint32_t MACPMTCSR;
AnnaBridge 167:e84263d55307 439 uint32_t RESERVED1;
AnnaBridge 167:e84263d55307 440 __IO uint32_t MACDBGR;
<> 144:ef7eb2e8f9f7 441 __IO uint32_t MACSR; /* 15 */
<> 144:ef7eb2e8f9f7 442 __IO uint32_t MACIMR;
<> 144:ef7eb2e8f9f7 443 __IO uint32_t MACA0HR;
<> 144:ef7eb2e8f9f7 444 __IO uint32_t MACA0LR;
<> 144:ef7eb2e8f9f7 445 __IO uint32_t MACA1HR;
<> 144:ef7eb2e8f9f7 446 __IO uint32_t MACA1LR;
<> 144:ef7eb2e8f9f7 447 __IO uint32_t MACA2HR;
<> 144:ef7eb2e8f9f7 448 __IO uint32_t MACA2LR;
<> 144:ef7eb2e8f9f7 449 __IO uint32_t MACA3HR;
<> 144:ef7eb2e8f9f7 450 __IO uint32_t MACA3LR; /* 24 */
<> 144:ef7eb2e8f9f7 451 uint32_t RESERVED2[40];
<> 144:ef7eb2e8f9f7 452 __IO uint32_t MMCCR; /* 65 */
<> 144:ef7eb2e8f9f7 453 __IO uint32_t MMCRIR;
<> 144:ef7eb2e8f9f7 454 __IO uint32_t MMCTIR;
<> 144:ef7eb2e8f9f7 455 __IO uint32_t MMCRIMR;
<> 144:ef7eb2e8f9f7 456 __IO uint32_t MMCTIMR; /* 69 */
<> 144:ef7eb2e8f9f7 457 uint32_t RESERVED3[14];
<> 144:ef7eb2e8f9f7 458 __IO uint32_t MMCTGFSCCR; /* 84 */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t MMCTGFMSCCR;
<> 144:ef7eb2e8f9f7 460 uint32_t RESERVED4[5];
<> 144:ef7eb2e8f9f7 461 __IO uint32_t MMCTGFCR;
<> 144:ef7eb2e8f9f7 462 uint32_t RESERVED5[10];
<> 144:ef7eb2e8f9f7 463 __IO uint32_t MMCRFCECR;
<> 144:ef7eb2e8f9f7 464 __IO uint32_t MMCRFAECR;
<> 144:ef7eb2e8f9f7 465 uint32_t RESERVED6[10];
<> 144:ef7eb2e8f9f7 466 __IO uint32_t MMCRGUFCR;
<> 144:ef7eb2e8f9f7 467 uint32_t RESERVED7[334];
<> 144:ef7eb2e8f9f7 468 __IO uint32_t PTPTSCR;
<> 144:ef7eb2e8f9f7 469 __IO uint32_t PTPSSIR;
<> 144:ef7eb2e8f9f7 470 __IO uint32_t PTPTSHR;
<> 144:ef7eb2e8f9f7 471 __IO uint32_t PTPTSLR;
<> 144:ef7eb2e8f9f7 472 __IO uint32_t PTPTSHUR;
<> 144:ef7eb2e8f9f7 473 __IO uint32_t PTPTSLUR;
<> 144:ef7eb2e8f9f7 474 __IO uint32_t PTPTSAR;
<> 144:ef7eb2e8f9f7 475 __IO uint32_t PTPTTHR;
<> 144:ef7eb2e8f9f7 476 __IO uint32_t PTPTTLR;
<> 144:ef7eb2e8f9f7 477 __IO uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 478 __IO uint32_t PTPTSSR;
<> 144:ef7eb2e8f9f7 479 uint32_t RESERVED9[565];
<> 144:ef7eb2e8f9f7 480 __IO uint32_t DMABMR;
<> 144:ef7eb2e8f9f7 481 __IO uint32_t DMATPDR;
<> 144:ef7eb2e8f9f7 482 __IO uint32_t DMARPDR;
<> 144:ef7eb2e8f9f7 483 __IO uint32_t DMARDLAR;
<> 144:ef7eb2e8f9f7 484 __IO uint32_t DMATDLAR;
<> 144:ef7eb2e8f9f7 485 __IO uint32_t DMASR;
<> 144:ef7eb2e8f9f7 486 __IO uint32_t DMAOMR;
<> 144:ef7eb2e8f9f7 487 __IO uint32_t DMAIER;
<> 144:ef7eb2e8f9f7 488 __IO uint32_t DMAMFBOCR;
<> 144:ef7eb2e8f9f7 489 __IO uint32_t DMARSWTR;
<> 144:ef7eb2e8f9f7 490 uint32_t RESERVED10[8];
<> 144:ef7eb2e8f9f7 491 __IO uint32_t DMACHTDR;
<> 144:ef7eb2e8f9f7 492 __IO uint32_t DMACHRDR;
<> 144:ef7eb2e8f9f7 493 __IO uint32_t DMACHTBAR;
<> 144:ef7eb2e8f9f7 494 __IO uint32_t DMACHRBAR;
<> 144:ef7eb2e8f9f7 495 } ETH_TypeDef;
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /**
<> 144:ef7eb2e8f9f7 498 * @brief External Interrupt/Event Controller
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 typedef struct
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 509 } EXTI_TypeDef;
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @brief FLASH Registers
<> 144:ef7eb2e8f9f7 513 */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 typedef struct
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 518 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 519 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 520 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 521 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 522 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 523 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 524 } FLASH_TypeDef;
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /**
<> 144:ef7eb2e8f9f7 527 * @brief Flexible Memory Controller
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 typedef struct
<> 144:ef7eb2e8f9f7 531 {
AnnaBridge 167:e84263d55307 532 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 144:ef7eb2e8f9f7 533 } FMC_Bank1_TypeDef;
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /**
<> 144:ef7eb2e8f9f7 536 * @brief Flexible Memory Controller Bank1E
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 typedef struct
<> 144:ef7eb2e8f9f7 540 {
<> 144:ef7eb2e8f9f7 541 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 144:ef7eb2e8f9f7 542 } FMC_Bank1E_TypeDef;
<> 144:ef7eb2e8f9f7 543 /**
<> 144:ef7eb2e8f9f7 544 * @brief Flexible Memory Controller Bank2
<> 144:ef7eb2e8f9f7 545 */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 typedef struct
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 550 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 551 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 552 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 553 uint32_t RESERVED0; /*!< Reserved, 0x70 */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 555 uint32_t RESERVED1; /*!< Reserved, 0x78 */
<> 144:ef7eb2e8f9f7 556 uint32_t RESERVED2; /*!< Reserved, 0x7C */
<> 144:ef7eb2e8f9f7 557 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 558 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 559 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 560 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 561 uint32_t RESERVED3; /*!< Reserved, 0x90 */
<> 144:ef7eb2e8f9f7 562 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 563 } FMC_Bank2_3_TypeDef;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /**
<> 144:ef7eb2e8f9f7 566 * @brief Flexible Memory Controller Bank4
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 typedef struct
<> 144:ef7eb2e8f9f7 570 {
<> 144:ef7eb2e8f9f7 571 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
<> 144:ef7eb2e8f9f7 572 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
<> 144:ef7eb2e8f9f7 573 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
<> 144:ef7eb2e8f9f7 574 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
<> 144:ef7eb2e8f9f7 575 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
AnnaBridge 167:e84263d55307 576 } FMC_Bank4_TypeDef;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @brief Flexible Memory Controller Bank5_6
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 typedef struct
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
AnnaBridge 167:e84263d55307 586 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
AnnaBridge 167:e84263d55307 587 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
AnnaBridge 167:e84263d55307 588 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
AnnaBridge 167:e84263d55307 589 } FMC_Bank5_6_TypeDef;
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @brief General Purpose I/O
<> 144:ef7eb2e8f9f7 593 */
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 typedef struct
<> 144:ef7eb2e8f9f7 596 {
<> 144:ef7eb2e8f9f7 597 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 599 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 601 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 602 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 603 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 604 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 605 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 144:ef7eb2e8f9f7 606 } GPIO_TypeDef;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @brief System configuration controller
<> 144:ef7eb2e8f9f7 610 */
AnnaBridge 167:e84263d55307 611
<> 144:ef7eb2e8f9f7 612 typedef struct
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 615 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 616 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 167:e84263d55307 617 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
<> 144:ef7eb2e8f9f7 618 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 619 } SYSCFG_TypeDef;
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @brief Inter-integrated Circuit Interface
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 typedef struct
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 628 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 630 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 633 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 634 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 635 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 636 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 637 } I2C_TypeDef;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @brief Independent WATCHDOG
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 typedef struct
<> 144:ef7eb2e8f9f7 644 {
<> 144:ef7eb2e8f9f7 645 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 647 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 648 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 649 } IWDG_TypeDef;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651 /**
<> 144:ef7eb2e8f9f7 652 * @brief LCD-TFT Display Controller
<> 144:ef7eb2e8f9f7 653 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 typedef struct
<> 144:ef7eb2e8f9f7 656 {
AnnaBridge 167:e84263d55307 657 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
<> 144:ef7eb2e8f9f7 658 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 659 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 660 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 661 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 662 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
AnnaBridge 167:e84263d55307 663 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
<> 144:ef7eb2e8f9f7 664 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
AnnaBridge 167:e84263d55307 665 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
<> 144:ef7eb2e8f9f7 666 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
AnnaBridge 167:e84263d55307 667 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
<> 144:ef7eb2e8f9f7 668 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 669 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 670 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 671 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 672 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
AnnaBridge 167:e84263d55307 673 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
AnnaBridge 167:e84263d55307 674 } LTDC_TypeDef;
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /**
<> 144:ef7eb2e8f9f7 677 * @brief LCD-TFT Display layer x Controller
<> 144:ef7eb2e8f9f7 678 */
AnnaBridge 167:e84263d55307 679
<> 144:ef7eb2e8f9f7 680 typedef struct
AnnaBridge 167:e84263d55307 681 {
<> 144:ef7eb2e8f9f7 682 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 683 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 684 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 685 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 686 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 687 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 688 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 689 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
AnnaBridge 167:e84263d55307 690 uint32_t RESERVED0[2]; /*!< Reserved */
<> 144:ef7eb2e8f9f7 691 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
<> 144:ef7eb2e8f9f7 692 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
<> 144:ef7eb2e8f9f7 693 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
AnnaBridge 167:e84263d55307 694 uint32_t RESERVED1[3]; /*!< Reserved */
AnnaBridge 167:e84263d55307 695 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
<> 144:ef7eb2e8f9f7 696 } LTDC_Layer_TypeDef;
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Power Control
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 typedef struct
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 705 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 706 } PWR_TypeDef;
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @brief Reset and Clock Control
<> 144:ef7eb2e8f9f7 710 */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 typedef struct
<> 144:ef7eb2e8f9f7 713 {
<> 144:ef7eb2e8f9f7 714 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 715 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 716 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 717 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 718 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 719 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 720 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 721 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 144:ef7eb2e8f9f7 722 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 723 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 724 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 144:ef7eb2e8f9f7 725 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 726 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 727 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 728 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 144:ef7eb2e8f9f7 729 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 730 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 731 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 144:ef7eb2e8f9f7 732 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 733 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 734 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 735 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 144:ef7eb2e8f9f7 736 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 737 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 738 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 144:ef7eb2e8f9f7 739 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 740 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 741 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 144:ef7eb2e8f9f7 742 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 743 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 744 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 745 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 746 } RCC_TypeDef;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /**
<> 144:ef7eb2e8f9f7 749 * @brief Real-Time Clock
<> 144:ef7eb2e8f9f7 750 */
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 typedef struct
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 755 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 756 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 757 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 758 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 759 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 760 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 761 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 762 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 763 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 764 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 765 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 766 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 767 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 768 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 769 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 770 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 771 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 772 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 773 uint32_t RESERVED7; /*!< Reserved, 0x4C */
<> 144:ef7eb2e8f9f7 774 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 775 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 144:ef7eb2e8f9f7 776 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 144:ef7eb2e8f9f7 777 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 144:ef7eb2e8f9f7 778 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 144:ef7eb2e8f9f7 779 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 144:ef7eb2e8f9f7 780 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 144:ef7eb2e8f9f7 781 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 144:ef7eb2e8f9f7 782 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 144:ef7eb2e8f9f7 783 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 144:ef7eb2e8f9f7 784 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 144:ef7eb2e8f9f7 785 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 144:ef7eb2e8f9f7 786 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 787 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 144:ef7eb2e8f9f7 788 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 144:ef7eb2e8f9f7 789 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 144:ef7eb2e8f9f7 790 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 144:ef7eb2e8f9f7 791 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 144:ef7eb2e8f9f7 792 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 144:ef7eb2e8f9f7 793 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 144:ef7eb2e8f9f7 794 } RTC_TypeDef;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Serial Audio Interface
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 typedef struct
<> 144:ef7eb2e8f9f7 801 {
<> 144:ef7eb2e8f9f7 802 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 803 } SAI_TypeDef;
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 typedef struct
<> 144:ef7eb2e8f9f7 806 {
<> 144:ef7eb2e8f9f7 807 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 808 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 809 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 810 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 811 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 812 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 813 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 814 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 815 } SAI_Block_TypeDef;
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 /**
<> 144:ef7eb2e8f9f7 818 * @brief SD host Interface
<> 144:ef7eb2e8f9f7 819 */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 typedef struct
<> 144:ef7eb2e8f9f7 822 {
AnnaBridge 167:e84263d55307 823 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
AnnaBridge 167:e84263d55307 824 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
AnnaBridge 167:e84263d55307 825 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
AnnaBridge 167:e84263d55307 826 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
AnnaBridge 167:e84263d55307 827 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
AnnaBridge 167:e84263d55307 828 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
AnnaBridge 167:e84263d55307 829 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
AnnaBridge 167:e84263d55307 830 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
AnnaBridge 167:e84263d55307 831 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
AnnaBridge 167:e84263d55307 832 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
AnnaBridge 167:e84263d55307 833 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
AnnaBridge 167:e84263d55307 834 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
AnnaBridge 167:e84263d55307 835 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
AnnaBridge 167:e84263d55307 836 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
AnnaBridge 167:e84263d55307 837 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
AnnaBridge 167:e84263d55307 838 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
AnnaBridge 167:e84263d55307 839 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
AnnaBridge 167:e84263d55307 840 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
AnnaBridge 167:e84263d55307 841 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
AnnaBridge 167:e84263d55307 842 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
<> 144:ef7eb2e8f9f7 843 } SDIO_TypeDef;
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /**
<> 144:ef7eb2e8f9f7 846 * @brief Serial Peripheral Interface
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 typedef struct
<> 144:ef7eb2e8f9f7 850 {
<> 144:ef7eb2e8f9f7 851 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 852 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 853 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 854 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 855 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 856 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 857 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 858 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 859 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 860 } SPI_TypeDef;
<> 144:ef7eb2e8f9f7 861
AnnaBridge 167:e84263d55307 862
<> 144:ef7eb2e8f9f7 863 /**
<> 144:ef7eb2e8f9f7 864 * @brief TIM
<> 144:ef7eb2e8f9f7 865 */
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 typedef struct
<> 144:ef7eb2e8f9f7 868 {
<> 144:ef7eb2e8f9f7 869 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 870 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 871 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 872 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 873 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 874 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 875 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 876 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 144:ef7eb2e8f9f7 877 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 144:ef7eb2e8f9f7 878 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 144:ef7eb2e8f9f7 879 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 144:ef7eb2e8f9f7 880 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 144:ef7eb2e8f9f7 881 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 144:ef7eb2e8f9f7 882 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 144:ef7eb2e8f9f7 883 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 144:ef7eb2e8f9f7 884 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 144:ef7eb2e8f9f7 885 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 144:ef7eb2e8f9f7 886 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 144:ef7eb2e8f9f7 887 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 144:ef7eb2e8f9f7 888 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 144:ef7eb2e8f9f7 889 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 144:ef7eb2e8f9f7 890 } TIM_TypeDef;
<> 144:ef7eb2e8f9f7 891
<> 144:ef7eb2e8f9f7 892 /**
<> 144:ef7eb2e8f9f7 893 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 144:ef7eb2e8f9f7 894 */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 typedef struct
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 899 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 900 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 901 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
<> 144:ef7eb2e8f9f7 902 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
<> 144:ef7eb2e8f9f7 903 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
<> 144:ef7eb2e8f9f7 904 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
<> 144:ef7eb2e8f9f7 905 } USART_TypeDef;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 * @brief Window WATCHDOG
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 typedef struct
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 914 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 915 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 916 } WWDG_TypeDef;
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /**
<> 144:ef7eb2e8f9f7 919 * @brief RNG
<> 144:ef7eb2e8f9f7 920 */
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 typedef struct
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
<> 144:ef7eb2e8f9f7 925 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
<> 144:ef7eb2e8f9f7 926 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
<> 144:ef7eb2e8f9f7 927 } RNG_TypeDef;
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
AnnaBridge 167:e84263d55307 930 * @brief USB_OTG_Core_Registers
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932 typedef struct
<> 144:ef7eb2e8f9f7 933 {
AnnaBridge 167:e84263d55307 934 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
AnnaBridge 167:e84263d55307 935 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
AnnaBridge 167:e84263d55307 936 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
AnnaBridge 167:e84263d55307 937 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
AnnaBridge 167:e84263d55307 938 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
AnnaBridge 167:e84263d55307 939 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
AnnaBridge 167:e84263d55307 940 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
AnnaBridge 167:e84263d55307 941 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
AnnaBridge 167:e84263d55307 942 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
AnnaBridge 167:e84263d55307 943 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
AnnaBridge 167:e84263d55307 944 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
AnnaBridge 167:e84263d55307 945 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
AnnaBridge 167:e84263d55307 946 uint32_t Reserved30[2]; /*!< Reserved 030h */
AnnaBridge 167:e84263d55307 947 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
AnnaBridge 167:e84263d55307 948 __IO uint32_t CID; /*!< User ID Register 03Ch */
AnnaBridge 167:e84263d55307 949 uint32_t Reserved40[48]; /*!< Reserved 0x40-0xFF */
AnnaBridge 167:e84263d55307 950 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
AnnaBridge 167:e84263d55307 951 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
AnnaBridge 167:e84263d55307 952 } USB_OTG_GlobalTypeDef;
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /**
AnnaBridge 167:e84263d55307 955 * @brief USB_OTG_device_Registers
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 typedef struct
<> 144:ef7eb2e8f9f7 958 {
AnnaBridge 167:e84263d55307 959 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
AnnaBridge 167:e84263d55307 960 __IO uint32_t DCTL; /*!< dev Control Register 804h */
AnnaBridge 167:e84263d55307 961 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
AnnaBridge 167:e84263d55307 962 uint32_t Reserved0C; /*!< Reserved 80Ch */
AnnaBridge 167:e84263d55307 963 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
AnnaBridge 167:e84263d55307 964 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
AnnaBridge 167:e84263d55307 965 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
AnnaBridge 167:e84263d55307 966 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
AnnaBridge 167:e84263d55307 967 uint32_t Reserved20; /*!< Reserved 820h */
AnnaBridge 167:e84263d55307 968 uint32_t Reserved9; /*!< Reserved 824h */
AnnaBridge 167:e84263d55307 969 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
AnnaBridge 167:e84263d55307 970 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
AnnaBridge 167:e84263d55307 971 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
AnnaBridge 167:e84263d55307 972 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
AnnaBridge 167:e84263d55307 973 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
AnnaBridge 167:e84263d55307 974 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
AnnaBridge 167:e84263d55307 975 uint32_t Reserved40; /*!< dedicated EP mask 840h */
AnnaBridge 167:e84263d55307 976 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
AnnaBridge 167:e84263d55307 977 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
AnnaBridge 167:e84263d55307 978 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
AnnaBridge 167:e84263d55307 979 } USB_OTG_DeviceTypeDef;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /**
AnnaBridge 167:e84263d55307 982 * @brief USB_OTG_IN_Endpoint-Specific_Register
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 typedef struct
<> 144:ef7eb2e8f9f7 985 {
AnnaBridge 167:e84263d55307 986 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
AnnaBridge 167:e84263d55307 987 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
AnnaBridge 167:e84263d55307 988 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
AnnaBridge 167:e84263d55307 989 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
AnnaBridge 167:e84263d55307 990 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
AnnaBridge 167:e84263d55307 991 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
AnnaBridge 167:e84263d55307 992 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
AnnaBridge 167:e84263d55307 993 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
AnnaBridge 167:e84263d55307 994 } USB_OTG_INEndpointTypeDef;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /**
AnnaBridge 167:e84263d55307 997 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
<> 144:ef7eb2e8f9f7 998 */
<> 144:ef7eb2e8f9f7 999 typedef struct
<> 144:ef7eb2e8f9f7 1000 {
AnnaBridge 167:e84263d55307 1001 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
AnnaBridge 167:e84263d55307 1002 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
AnnaBridge 167:e84263d55307 1003 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
AnnaBridge 167:e84263d55307 1004 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
AnnaBridge 167:e84263d55307 1005 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
AnnaBridge 167:e84263d55307 1006 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
AnnaBridge 167:e84263d55307 1007 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
AnnaBridge 167:e84263d55307 1008 } USB_OTG_OUTEndpointTypeDef;
<> 144:ef7eb2e8f9f7 1009
<> 144:ef7eb2e8f9f7 1010 /**
AnnaBridge 167:e84263d55307 1011 * @brief USB_OTG_Host_Mode_Register_Structures
<> 144:ef7eb2e8f9f7 1012 */
<> 144:ef7eb2e8f9f7 1013 typedef struct
<> 144:ef7eb2e8f9f7 1014 {
AnnaBridge 167:e84263d55307 1015 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
AnnaBridge 167:e84263d55307 1016 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
AnnaBridge 167:e84263d55307 1017 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
AnnaBridge 167:e84263d55307 1018 uint32_t Reserved40C; /*!< Reserved 40Ch */
AnnaBridge 167:e84263d55307 1019 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
AnnaBridge 167:e84263d55307 1020 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
AnnaBridge 167:e84263d55307 1021 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
AnnaBridge 167:e84263d55307 1022 } USB_OTG_HostTypeDef;
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /**
AnnaBridge 167:e84263d55307 1025 * @brief USB_OTG_Host_Channel_Specific_Registers
<> 144:ef7eb2e8f9f7 1026 */
<> 144:ef7eb2e8f9f7 1027 typedef struct
<> 144:ef7eb2e8f9f7 1028 {
AnnaBridge 167:e84263d55307 1029 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
AnnaBridge 167:e84263d55307 1030 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
AnnaBridge 167:e84263d55307 1031 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
AnnaBridge 167:e84263d55307 1032 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
AnnaBridge 167:e84263d55307 1033 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
AnnaBridge 167:e84263d55307 1034 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
AnnaBridge 167:e84263d55307 1035 uint32_t Reserved[2]; /*!< Reserved */
AnnaBridge 167:e84263d55307 1036 } USB_OTG_HostChannelTypeDef;
AnnaBridge 167:e84263d55307 1037
<> 144:ef7eb2e8f9f7 1038 /**
<> 144:ef7eb2e8f9f7 1039 * @}
<> 144:ef7eb2e8f9f7 1040 */
AnnaBridge 167:e84263d55307 1041
<> 144:ef7eb2e8f9f7 1042 /** @addtogroup Peripheral_memory_map
<> 144:ef7eb2e8f9f7 1043 * @{
<> 144:ef7eb2e8f9f7 1044 */
<> 144:ef7eb2e8f9f7 1045 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 2 MB) base address in the alias region */
<> 144:ef7eb2e8f9f7 1046 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
AnnaBridge 167:e84263d55307 1047 #define SRAM1_BASE 0x20000000U /*!< SRAM1(112 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 1048 #define SRAM2_BASE 0x2001C000U /*!< SRAM2(16 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 1049 #define SRAM3_BASE 0x20020000U /*!< SRAM3(64 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 1050 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
<> 144:ef7eb2e8f9f7 1051 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
<> 144:ef7eb2e8f9f7 1052 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
AnnaBridge 167:e84263d55307 1053 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
AnnaBridge 167:e84263d55307 1054 #define SRAM2_BB_BASE 0x22380000U /*!< SRAM2(16 KB) base address in the bit-band region */
AnnaBridge 167:e84263d55307 1055 #define SRAM3_BB_BASE 0x22400000U /*!< SRAM3(64 KB) base address in the bit-band region */
AnnaBridge 167:e84263d55307 1056 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
AnnaBridge 167:e84263d55307 1057 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
AnnaBridge 167:e84263d55307 1058 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
AnnaBridge 167:e84263d55307 1059 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 167:e84263d55307 1060 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
AnnaBridge 167:e84263d55307 1061 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
<> 144:ef7eb2e8f9f7 1062
<> 144:ef7eb2e8f9f7 1063 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1064 #define SRAM_BASE SRAM1_BASE
<> 144:ef7eb2e8f9f7 1065 #define SRAM_BB_BASE SRAM1_BB_BASE
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /*!< Peripheral memory map */
<> 144:ef7eb2e8f9f7 1068 #define APB1PERIPH_BASE PERIPH_BASE
<> 144:ef7eb2e8f9f7 1069 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 144:ef7eb2e8f9f7 1070 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 144:ef7eb2e8f9f7 1071 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 1074 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1075 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1076 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1077 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1078 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1079 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1080 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1081 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1082 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1083 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1084 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1085 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1086 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 1087 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1088 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1089 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1090 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1091 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1092 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 144:ef7eb2e8f9f7 1093 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1094 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1095 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1096 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 144:ef7eb2e8f9f7 1097 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1098 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1099 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 144:ef7eb2e8f9f7 1100 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 144:ef7eb2e8f9f7 1101 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
<> 144:ef7eb2e8f9f7 1102 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 1105 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1106 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1107 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1108 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1109 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1110 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
<> 144:ef7eb2e8f9f7 1111 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
AnnaBridge 167:e84263d55307 1112 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
AnnaBridge 167:e84263d55307 1113 /* Legacy define */
AnnaBridge 167:e84263d55307 1114 #define ADC_BASE ADC123_COMMON_BASE
<> 144:ef7eb2e8f9f7 1115 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 144:ef7eb2e8f9f7 1116 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1117 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 144:ef7eb2e8f9f7 1118 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1119 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1120 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 144:ef7eb2e8f9f7 1121 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 144:ef7eb2e8f9f7 1122 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 144:ef7eb2e8f9f7 1123 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
<> 144:ef7eb2e8f9f7 1124 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
<> 144:ef7eb2e8f9f7 1125 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
<> 144:ef7eb2e8f9f7 1126 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
<> 144:ef7eb2e8f9f7 1127 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
<> 144:ef7eb2e8f9f7 1128 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
<> 144:ef7eb2e8f9f7 1129 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
AnnaBridge 167:e84263d55307 1130 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 /*!< AHB1 peripherals */
<> 144:ef7eb2e8f9f7 1133 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1134 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 144:ef7eb2e8f9f7 1135 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 144:ef7eb2e8f9f7 1136 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 144:ef7eb2e8f9f7 1137 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1138 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
<> 144:ef7eb2e8f9f7 1139 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
<> 144:ef7eb2e8f9f7 1140 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 144:ef7eb2e8f9f7 1141 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 144:ef7eb2e8f9f7 1142 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
<> 144:ef7eb2e8f9f7 1143 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
<> 144:ef7eb2e8f9f7 1144 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 144:ef7eb2e8f9f7 1145 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 144:ef7eb2e8f9f7 1146 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 144:ef7eb2e8f9f7 1147 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 144:ef7eb2e8f9f7 1148 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1149 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1150 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1151 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1152 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1153 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1154 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1155 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1156 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 144:ef7eb2e8f9f7 1157 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 144:ef7eb2e8f9f7 1158 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 144:ef7eb2e8f9f7 1159 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 144:ef7eb2e8f9f7 1160 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 144:ef7eb2e8f9f7 1161 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 144:ef7eb2e8f9f7 1162 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 144:ef7eb2e8f9f7 1163 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 144:ef7eb2e8f9f7 1164 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 144:ef7eb2e8f9f7 1165 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
<> 144:ef7eb2e8f9f7 1166 #define ETH_MAC_BASE (ETH_BASE)
<> 144:ef7eb2e8f9f7 1167 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
<> 144:ef7eb2e8f9f7 1168 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
<> 144:ef7eb2e8f9f7 1169 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
<> 144:ef7eb2e8f9f7 1170 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /*!< AHB2 peripherals */
<> 144:ef7eb2e8f9f7 1173 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
<> 144:ef7eb2e8f9f7 1174 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /*!< FMC Bankx registers base address */
<> 144:ef7eb2e8f9f7 1177 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 144:ef7eb2e8f9f7 1178 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 144:ef7eb2e8f9f7 1179 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060U)
<> 144:ef7eb2e8f9f7 1180 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0U)
<> 144:ef7eb2e8f9f7 1181 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
<> 144:ef7eb2e8f9f7 1182
AnnaBridge 167:e84263d55307 1183
AnnaBridge 167:e84263d55307 1184 /*!< Debug MCU registers base address */
<> 144:ef7eb2e8f9f7 1185 #define DBGMCU_BASE 0xE0042000U
<> 144:ef7eb2e8f9f7 1186 /*!< USB registers base address */
<> 144:ef7eb2e8f9f7 1187 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
<> 144:ef7eb2e8f9f7 1188 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 #define USB_OTG_GLOBAL_BASE 0x000U
<> 144:ef7eb2e8f9f7 1191 #define USB_OTG_DEVICE_BASE 0x800U
<> 144:ef7eb2e8f9f7 1192 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 144:ef7eb2e8f9f7 1193 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 144:ef7eb2e8f9f7 1194 #define USB_OTG_EP_REG_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1195 #define USB_OTG_HOST_BASE 0x400U
<> 144:ef7eb2e8f9f7 1196 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 144:ef7eb2e8f9f7 1197 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 144:ef7eb2e8f9f7 1198 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 144:ef7eb2e8f9f7 1199 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 144:ef7eb2e8f9f7 1200 #define USB_OTG_FIFO_BASE 0x1000U
<> 144:ef7eb2e8f9f7 1201 #define USB_OTG_FIFO_SIZE 0x1000U
<> 144:ef7eb2e8f9f7 1202
AnnaBridge 167:e84263d55307 1203 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
AnnaBridge 167:e84263d55307 1204 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
AnnaBridge 167:e84263d55307 1205 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
<> 144:ef7eb2e8f9f7 1206 /**
<> 144:ef7eb2e8f9f7 1207 * @}
<> 144:ef7eb2e8f9f7 1208 */
AnnaBridge 167:e84263d55307 1209
<> 144:ef7eb2e8f9f7 1210 /** @addtogroup Peripheral_declaration
<> 144:ef7eb2e8f9f7 1211 * @{
<> 144:ef7eb2e8f9f7 1212 */
<> 144:ef7eb2e8f9f7 1213 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 144:ef7eb2e8f9f7 1214 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 144:ef7eb2e8f9f7 1215 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 144:ef7eb2e8f9f7 1216 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 144:ef7eb2e8f9f7 1217 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 144:ef7eb2e8f9f7 1218 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 144:ef7eb2e8f9f7 1219 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
<> 144:ef7eb2e8f9f7 1220 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
<> 144:ef7eb2e8f9f7 1221 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
<> 144:ef7eb2e8f9f7 1222 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 144:ef7eb2e8f9f7 1223 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 144:ef7eb2e8f9f7 1224 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 144:ef7eb2e8f9f7 1225 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
<> 144:ef7eb2e8f9f7 1226 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 1227 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 144:ef7eb2e8f9f7 1228 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
<> 144:ef7eb2e8f9f7 1229 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 144:ef7eb2e8f9f7 1230 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 144:ef7eb2e8f9f7 1231 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 144:ef7eb2e8f9f7 1232 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 144:ef7eb2e8f9f7 1233 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 1234 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 1235 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 144:ef7eb2e8f9f7 1236 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
<> 144:ef7eb2e8f9f7 1237 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
<> 144:ef7eb2e8f9f7 1238 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 167:e84263d55307 1239 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 167:e84263d55307 1240 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
<> 144:ef7eb2e8f9f7 1241 #define UART7 ((USART_TypeDef *) UART7_BASE)
<> 144:ef7eb2e8f9f7 1242 #define UART8 ((USART_TypeDef *) UART8_BASE)
<> 144:ef7eb2e8f9f7 1243 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 144:ef7eb2e8f9f7 1244 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 144:ef7eb2e8f9f7 1245 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 144:ef7eb2e8f9f7 1246 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 144:ef7eb2e8f9f7 1247 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 144:ef7eb2e8f9f7 1248 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 144:ef7eb2e8f9f7 1249 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
AnnaBridge 167:e84263d55307 1250 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
AnnaBridge 167:e84263d55307 1251 /* Legacy define */
AnnaBridge 167:e84263d55307 1252 #define ADC ADC123_COMMON
<> 144:ef7eb2e8f9f7 1253 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
AnnaBridge 167:e84263d55307 1254 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 1255 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 144:ef7eb2e8f9f7 1256 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 144:ef7eb2e8f9f7 1257 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 144:ef7eb2e8f9f7 1258 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 144:ef7eb2e8f9f7 1259 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 144:ef7eb2e8f9f7 1260 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 144:ef7eb2e8f9f7 1261 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
<> 144:ef7eb2e8f9f7 1262 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
<> 144:ef7eb2e8f9f7 1263 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
<> 144:ef7eb2e8f9f7 1264 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
<> 144:ef7eb2e8f9f7 1265 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
<> 144:ef7eb2e8f9f7 1266 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
<> 144:ef7eb2e8f9f7 1267 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
<> 144:ef7eb2e8f9f7 1268 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
<> 144:ef7eb2e8f9f7 1269 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 1270 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 1271 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 1272 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 1273 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 1274 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 1275 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 144:ef7eb2e8f9f7 1276 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 1277 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
<> 144:ef7eb2e8f9f7 1278 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
<> 144:ef7eb2e8f9f7 1279 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
<> 144:ef7eb2e8f9f7 1280 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 144:ef7eb2e8f9f7 1281 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 144:ef7eb2e8f9f7 1282 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 144:ef7eb2e8f9f7 1283 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 144:ef7eb2e8f9f7 1284 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1285 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1286 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1287 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1288 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1289 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1290 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1291 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 144:ef7eb2e8f9f7 1292 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 144:ef7eb2e8f9f7 1293 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 144:ef7eb2e8f9f7 1294 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 144:ef7eb2e8f9f7 1295 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 144:ef7eb2e8f9f7 1296 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 144:ef7eb2e8f9f7 1297 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 144:ef7eb2e8f9f7 1298 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 144:ef7eb2e8f9f7 1299 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 144:ef7eb2e8f9f7 1300 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 144:ef7eb2e8f9f7 1301 #define ETH ((ETH_TypeDef *) ETH_BASE)
<> 144:ef7eb2e8f9f7 1302 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
<> 144:ef7eb2e8f9f7 1303 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
<> 144:ef7eb2e8f9f7 1304 #define RNG ((RNG_TypeDef *) RNG_BASE)
<> 144:ef7eb2e8f9f7 1305 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<> 144:ef7eb2e8f9f7 1306 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<> 144:ef7eb2e8f9f7 1307 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
<> 144:ef7eb2e8f9f7 1308 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
<> 144:ef7eb2e8f9f7 1309 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
<> 144:ef7eb2e8f9f7 1310 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 144:ef7eb2e8f9f7 1311 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1312 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @}
<> 144:ef7eb2e8f9f7 1316 */
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /** @addtogroup Exported_constants
<> 144:ef7eb2e8f9f7 1319 * @{
<> 144:ef7eb2e8f9f7 1320 */
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 144:ef7eb2e8f9f7 1323 * @{
<> 144:ef7eb2e8f9f7 1324 */
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1327 /* Peripheral Registers_Bits_Definition */
<> 144:ef7eb2e8f9f7 1328 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1331 /* */
<> 144:ef7eb2e8f9f7 1332 /* Analog to Digital Converter */
<> 144:ef7eb2e8f9f7 1333 /* */
<> 144:ef7eb2e8f9f7 1334 /******************************************************************************/
AnnaBridge 167:e84263d55307 1335 /*
AnnaBridge 167:e84263d55307 1336 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 1337 */
AnnaBridge 167:e84263d55307 1338 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
AnnaBridge 167:e84263d55307 1339
<> 144:ef7eb2e8f9f7 1340 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 167:e84263d55307 1341 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 167:e84263d55307 1342 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1343 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
AnnaBridge 167:e84263d55307 1344 #define ADC_SR_EOC_Pos (1U)
AnnaBridge 167:e84263d55307 1345 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1346 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
AnnaBridge 167:e84263d55307 1347 #define ADC_SR_JEOC_Pos (2U)
AnnaBridge 167:e84263d55307 1348 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1349 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
AnnaBridge 167:e84263d55307 1350 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 167:e84263d55307 1351 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1352 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
AnnaBridge 167:e84263d55307 1353 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 167:e84263d55307 1354 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1355 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
AnnaBridge 167:e84263d55307 1356 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 167:e84263d55307 1357 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1358 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 167:e84263d55307 1361 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 167:e84263d55307 1362 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1363 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
AnnaBridge 167:e84263d55307 1364 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1365 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1366 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1367 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1368 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1369 #define ADC_CR1_EOCIE_Pos (5U)
AnnaBridge 167:e84263d55307 1370 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1371 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
AnnaBridge 167:e84263d55307 1372 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 167:e84263d55307 1373 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1374 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
AnnaBridge 167:e84263d55307 1375 #define ADC_CR1_JEOCIE_Pos (7U)
AnnaBridge 167:e84263d55307 1376 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1377 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
AnnaBridge 167:e84263d55307 1378 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 167:e84263d55307 1379 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1380 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
AnnaBridge 167:e84263d55307 1381 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 167:e84263d55307 1382 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1383 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
AnnaBridge 167:e84263d55307 1384 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 167:e84263d55307 1385 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1386 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
AnnaBridge 167:e84263d55307 1387 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 167:e84263d55307 1388 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1389 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
AnnaBridge 167:e84263d55307 1390 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 167:e84263d55307 1391 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1392 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
AnnaBridge 167:e84263d55307 1393 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 167:e84263d55307 1394 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 167:e84263d55307 1395 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
AnnaBridge 167:e84263d55307 1396 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1397 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1398 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1399 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 167:e84263d55307 1400 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1401 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
AnnaBridge 167:e84263d55307 1402 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 167:e84263d55307 1403 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1404 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
AnnaBridge 167:e84263d55307 1405 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 167:e84263d55307 1406 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 1407 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
AnnaBridge 167:e84263d55307 1408 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1409 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1410 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 167:e84263d55307 1411 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 1412 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 167:e84263d55307 1415 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 167:e84263d55307 1416 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1417 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
AnnaBridge 167:e84263d55307 1418 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 167:e84263d55307 1419 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1420 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
AnnaBridge 167:e84263d55307 1421 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 167:e84263d55307 1422 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1423 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
AnnaBridge 167:e84263d55307 1424 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 167:e84263d55307 1425 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1426 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
AnnaBridge 167:e84263d55307 1427 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 167:e84263d55307 1428 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1429 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
AnnaBridge 167:e84263d55307 1430 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 167:e84263d55307 1431 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1432 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
AnnaBridge 167:e84263d55307 1433 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 167:e84263d55307 1434 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 1435 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
AnnaBridge 167:e84263d55307 1436 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1437 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1438 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1439 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1440 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 167:e84263d55307 1441 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 1442 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
AnnaBridge 167:e84263d55307 1443 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1444 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1445 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 167:e84263d55307 1446 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1447 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
AnnaBridge 167:e84263d55307 1448 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 167:e84263d55307 1449 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 1450 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
AnnaBridge 167:e84263d55307 1451 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1452 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1453 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 1454 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 1455 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 167:e84263d55307 1456 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 1457 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
AnnaBridge 167:e84263d55307 1458 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 1459 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 1460 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 167:e84263d55307 1461 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 1462 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 167:e84263d55307 1465 #define ADC_SMPR1_SMP10_Pos (0U)
AnnaBridge 167:e84263d55307 1466 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 1467 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
AnnaBridge 167:e84263d55307 1468 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1469 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1470 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1471 #define ADC_SMPR1_SMP11_Pos (3U)
AnnaBridge 167:e84263d55307 1472 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 167:e84263d55307 1473 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
AnnaBridge 167:e84263d55307 1474 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1475 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1476 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1477 #define ADC_SMPR1_SMP12_Pos (6U)
AnnaBridge 167:e84263d55307 1478 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 167:e84263d55307 1479 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
AnnaBridge 167:e84263d55307 1480 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1481 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1482 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1483 #define ADC_SMPR1_SMP13_Pos (9U)
AnnaBridge 167:e84263d55307 1484 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 167:e84263d55307 1485 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
AnnaBridge 167:e84263d55307 1486 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1487 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1488 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1489 #define ADC_SMPR1_SMP14_Pos (12U)
AnnaBridge 167:e84263d55307 1490 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 1491 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
AnnaBridge 167:e84263d55307 1492 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1493 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1494 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1495 #define ADC_SMPR1_SMP15_Pos (15U)
AnnaBridge 167:e84263d55307 1496 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 167:e84263d55307 1497 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
AnnaBridge 167:e84263d55307 1498 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1499 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1500 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1501 #define ADC_SMPR1_SMP16_Pos (18U)
AnnaBridge 167:e84263d55307 1502 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 167:e84263d55307 1503 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
AnnaBridge 167:e84263d55307 1504 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1505 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1506 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1507 #define ADC_SMPR1_SMP17_Pos (21U)
AnnaBridge 167:e84263d55307 1508 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 167:e84263d55307 1509 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
AnnaBridge 167:e84263d55307 1510 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1511 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1512 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1513 #define ADC_SMPR1_SMP18_Pos (24U)
AnnaBridge 167:e84263d55307 1514 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 167:e84263d55307 1515 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
AnnaBridge 167:e84263d55307 1516 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1517 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1518 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 167:e84263d55307 1521 #define ADC_SMPR2_SMP0_Pos (0U)
AnnaBridge 167:e84263d55307 1522 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 1523 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
AnnaBridge 167:e84263d55307 1524 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1525 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1526 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1527 #define ADC_SMPR2_SMP1_Pos (3U)
AnnaBridge 167:e84263d55307 1528 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 167:e84263d55307 1529 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
AnnaBridge 167:e84263d55307 1530 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1531 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1532 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1533 #define ADC_SMPR2_SMP2_Pos (6U)
AnnaBridge 167:e84263d55307 1534 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 167:e84263d55307 1535 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
AnnaBridge 167:e84263d55307 1536 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1537 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1538 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1539 #define ADC_SMPR2_SMP3_Pos (9U)
AnnaBridge 167:e84263d55307 1540 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 167:e84263d55307 1541 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
AnnaBridge 167:e84263d55307 1542 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1543 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1544 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1545 #define ADC_SMPR2_SMP4_Pos (12U)
AnnaBridge 167:e84263d55307 1546 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 1547 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
AnnaBridge 167:e84263d55307 1548 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1549 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1550 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1551 #define ADC_SMPR2_SMP5_Pos (15U)
AnnaBridge 167:e84263d55307 1552 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 167:e84263d55307 1553 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
AnnaBridge 167:e84263d55307 1554 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1555 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1556 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1557 #define ADC_SMPR2_SMP6_Pos (18U)
AnnaBridge 167:e84263d55307 1558 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 167:e84263d55307 1559 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
AnnaBridge 167:e84263d55307 1560 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1561 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1562 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1563 #define ADC_SMPR2_SMP7_Pos (21U)
AnnaBridge 167:e84263d55307 1564 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 167:e84263d55307 1565 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
AnnaBridge 167:e84263d55307 1566 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1567 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1568 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1569 #define ADC_SMPR2_SMP8_Pos (24U)
AnnaBridge 167:e84263d55307 1570 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 167:e84263d55307 1571 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
AnnaBridge 167:e84263d55307 1572 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1573 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1574 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 1575 #define ADC_SMPR2_SMP9_Pos (27U)
AnnaBridge 167:e84263d55307 1576 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 167:e84263d55307 1577 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
AnnaBridge 167:e84263d55307 1578 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 1579 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 1580 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 167:e84263d55307 1583 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 167:e84263d55307 1584 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1585 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 167:e84263d55307 1588 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 167:e84263d55307 1589 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1590 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 167:e84263d55307 1593 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 167:e84263d55307 1594 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1595 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 167:e84263d55307 1598 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 167:e84263d55307 1599 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1600 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 167:e84263d55307 1603 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 167:e84263d55307 1604 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1605 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 167:e84263d55307 1608 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 167:e84263d55307 1609 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 1610 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 167:e84263d55307 1613 #define ADC_SQR1_SQ13_Pos (0U)
AnnaBridge 167:e84263d55307 1614 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1615 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1616 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1617 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1618 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1619 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1620 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1621 #define ADC_SQR1_SQ14_Pos (5U)
AnnaBridge 167:e84263d55307 1622 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 167:e84263d55307 1623 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1624 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1625 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1626 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1627 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1628 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1629 #define ADC_SQR1_SQ15_Pos (10U)
AnnaBridge 167:e84263d55307 1630 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 167:e84263d55307 1631 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1632 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1633 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1634 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1635 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1636 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1637 #define ADC_SQR1_SQ16_Pos (15U)
AnnaBridge 167:e84263d55307 1638 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 167:e84263d55307 1639 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1640 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1641 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1642 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1643 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1644 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1645 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 167:e84263d55307 1646 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 1647 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
AnnaBridge 167:e84263d55307 1648 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1649 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1650 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1651 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 167:e84263d55307 1654 #define ADC_SQR2_SQ7_Pos (0U)
AnnaBridge 167:e84263d55307 1655 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1656 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1657 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1658 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1659 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1660 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1661 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1662 #define ADC_SQR2_SQ8_Pos (5U)
AnnaBridge 167:e84263d55307 1663 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 167:e84263d55307 1664 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1665 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1666 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1667 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1668 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1669 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1670 #define ADC_SQR2_SQ9_Pos (10U)
AnnaBridge 167:e84263d55307 1671 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 167:e84263d55307 1672 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1673 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1674 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1675 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1676 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1677 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1678 #define ADC_SQR2_SQ10_Pos (15U)
AnnaBridge 167:e84263d55307 1679 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 167:e84263d55307 1680 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1681 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1682 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1683 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1684 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1685 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1686 #define ADC_SQR2_SQ11_Pos (20U)
AnnaBridge 167:e84263d55307 1687 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 167:e84263d55307 1688 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1689 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1690 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1691 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1692 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1693 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1694 #define ADC_SQR2_SQ12_Pos (25U)
AnnaBridge 167:e84263d55307 1695 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 167:e84263d55307 1696 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1697 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1698 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 1699 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 1700 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 1701 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1702
<> 144:ef7eb2e8f9f7 1703 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 167:e84263d55307 1704 #define ADC_SQR3_SQ1_Pos (0U)
AnnaBridge 167:e84263d55307 1705 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1706 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1707 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1708 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1709 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1710 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1711 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1712 #define ADC_SQR3_SQ2_Pos (5U)
AnnaBridge 167:e84263d55307 1713 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 167:e84263d55307 1714 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1715 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1716 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1717 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1718 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1719 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1720 #define ADC_SQR3_SQ3_Pos (10U)
AnnaBridge 167:e84263d55307 1721 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 167:e84263d55307 1722 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1723 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1724 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1725 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1726 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1727 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1728 #define ADC_SQR3_SQ4_Pos (15U)
AnnaBridge 167:e84263d55307 1729 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 167:e84263d55307 1730 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1731 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1732 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1733 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1734 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1735 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1736 #define ADC_SQR3_SQ5_Pos (20U)
AnnaBridge 167:e84263d55307 1737 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 167:e84263d55307 1738 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1739 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1740 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1741 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1742 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1743 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 1744 #define ADC_SQR3_SQ6_Pos (25U)
AnnaBridge 167:e84263d55307 1745 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 167:e84263d55307 1746 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
AnnaBridge 167:e84263d55307 1747 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 1748 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 1749 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 1750 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 1751 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 167:e84263d55307 1754 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 167:e84263d55307 1755 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1756 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
AnnaBridge 167:e84263d55307 1757 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1758 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1759 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1760 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1761 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1762 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 167:e84263d55307 1763 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 167:e84263d55307 1764 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
AnnaBridge 167:e84263d55307 1765 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1766 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1767 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1768 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1769 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1770 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 167:e84263d55307 1771 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 167:e84263d55307 1772 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
AnnaBridge 167:e84263d55307 1773 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1774 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1775 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1776 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1777 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1778 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 167:e84263d55307 1779 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 167:e84263d55307 1780 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
AnnaBridge 167:e84263d55307 1781 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1782 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1783 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1784 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1785 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1786 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 167:e84263d55307 1787 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 1788 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
AnnaBridge 167:e84263d55307 1789 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1790 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 167:e84263d55307 1793 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 167:e84263d55307 1794 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1795 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
<> 144:ef7eb2e8f9f7 1796
<> 144:ef7eb2e8f9f7 1797 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 167:e84263d55307 1798 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 167:e84263d55307 1799 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1800 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
<> 144:ef7eb2e8f9f7 1801
<> 144:ef7eb2e8f9f7 1802 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 167:e84263d55307 1803 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 167:e84263d55307 1804 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1805 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 167:e84263d55307 1808 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 167:e84263d55307 1809 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1810 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
<> 144:ef7eb2e8f9f7 1811
<> 144:ef7eb2e8f9f7 1812 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 167:e84263d55307 1813 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 167:e84263d55307 1814 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1815 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
AnnaBridge 167:e84263d55307 1816 #define ADC_DR_ADC2DATA_Pos (16U)
AnnaBridge 167:e84263d55307 1817 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 1818 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
<> 144:ef7eb2e8f9f7 1819
<> 144:ef7eb2e8f9f7 1820 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 167:e84263d55307 1821 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 167:e84263d55307 1822 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1823 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
AnnaBridge 167:e84263d55307 1824 #define ADC_CSR_EOC1_Pos (1U)
AnnaBridge 167:e84263d55307 1825 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1826 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
AnnaBridge 167:e84263d55307 1827 #define ADC_CSR_JEOC1_Pos (2U)
AnnaBridge 167:e84263d55307 1828 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1829 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
AnnaBridge 167:e84263d55307 1830 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 167:e84263d55307 1831 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1832 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
AnnaBridge 167:e84263d55307 1833 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 167:e84263d55307 1834 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1835 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
AnnaBridge 167:e84263d55307 1836 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 167:e84263d55307 1837 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1838 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
AnnaBridge 167:e84263d55307 1839 #define ADC_CSR_AWD2_Pos (8U)
AnnaBridge 167:e84263d55307 1840 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1841 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
AnnaBridge 167:e84263d55307 1842 #define ADC_CSR_EOC2_Pos (9U)
AnnaBridge 167:e84263d55307 1843 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1844 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
AnnaBridge 167:e84263d55307 1845 #define ADC_CSR_JEOC2_Pos (10U)
AnnaBridge 167:e84263d55307 1846 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1847 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
AnnaBridge 167:e84263d55307 1848 #define ADC_CSR_JSTRT2_Pos (11U)
AnnaBridge 167:e84263d55307 1849 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1850 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
AnnaBridge 167:e84263d55307 1851 #define ADC_CSR_STRT2_Pos (12U)
AnnaBridge 167:e84263d55307 1852 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 1853 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
AnnaBridge 167:e84263d55307 1854 #define ADC_CSR_OVR2_Pos (13U)
AnnaBridge 167:e84263d55307 1855 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1856 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
AnnaBridge 167:e84263d55307 1857 #define ADC_CSR_AWD3_Pos (16U)
AnnaBridge 167:e84263d55307 1858 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1859 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
AnnaBridge 167:e84263d55307 1860 #define ADC_CSR_EOC3_Pos (17U)
AnnaBridge 167:e84263d55307 1861 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1862 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
AnnaBridge 167:e84263d55307 1863 #define ADC_CSR_JEOC3_Pos (18U)
AnnaBridge 167:e84263d55307 1864 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 1865 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
AnnaBridge 167:e84263d55307 1866 #define ADC_CSR_JSTRT3_Pos (19U)
AnnaBridge 167:e84263d55307 1867 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 1868 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
AnnaBridge 167:e84263d55307 1869 #define ADC_CSR_STRT3_Pos (20U)
AnnaBridge 167:e84263d55307 1870 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 1871 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
AnnaBridge 167:e84263d55307 1872 #define ADC_CSR_OVR3_Pos (21U)
AnnaBridge 167:e84263d55307 1873 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 1874 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876 /* Legacy defines */
<> 144:ef7eb2e8f9f7 1877 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 144:ef7eb2e8f9f7 1878 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 144:ef7eb2e8f9f7 1879 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 144:ef7eb2e8f9f7 1880
<> 144:ef7eb2e8f9f7 1881 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 167:e84263d55307 1882 #define ADC_CCR_MULTI_Pos (0U)
AnnaBridge 167:e84263d55307 1883 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 1884 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
AnnaBridge 167:e84263d55307 1885 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1886 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1887 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1888 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1889 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1890 #define ADC_CCR_DELAY_Pos (8U)
AnnaBridge 167:e84263d55307 1891 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 1892 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
AnnaBridge 167:e84263d55307 1893 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1894 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1895 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1896 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1897 #define ADC_CCR_DDS_Pos (13U)
AnnaBridge 167:e84263d55307 1898 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 1899 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
AnnaBridge 167:e84263d55307 1900 #define ADC_CCR_DMA_Pos (14U)
AnnaBridge 167:e84263d55307 1901 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 1902 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
AnnaBridge 167:e84263d55307 1903 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 1904 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1905 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 167:e84263d55307 1906 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 1907 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
AnnaBridge 167:e84263d55307 1908 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1909 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 1910 #define ADC_CCR_VBATE_Pos (22U)
AnnaBridge 167:e84263d55307 1911 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 1912 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
AnnaBridge 167:e84263d55307 1913 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 167:e84263d55307 1914 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 1915 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
<> 144:ef7eb2e8f9f7 1916
<> 144:ef7eb2e8f9f7 1917 /******************* Bit definition for ADC_CDR register ********************/
AnnaBridge 167:e84263d55307 1918 #define ADC_CDR_DATA1_Pos (0U)
AnnaBridge 167:e84263d55307 1919 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 1920 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
AnnaBridge 167:e84263d55307 1921 #define ADC_CDR_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 1922 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 1923 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
AnnaBridge 167:e84263d55307 1924
AnnaBridge 167:e84263d55307 1925 /* Legacy defines */
AnnaBridge 167:e84263d55307 1926 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
AnnaBridge 167:e84263d55307 1927 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
<> 144:ef7eb2e8f9f7 1928
<> 144:ef7eb2e8f9f7 1929 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1930 /* */
<> 144:ef7eb2e8f9f7 1931 /* Controller Area Network */
<> 144:ef7eb2e8f9f7 1932 /* */
<> 144:ef7eb2e8f9f7 1933 /******************************************************************************/
<> 144:ef7eb2e8f9f7 1934 /*!<CAN control and status registers */
<> 144:ef7eb2e8f9f7 1935 /******************* Bit definition for CAN_MCR register ********************/
AnnaBridge 167:e84263d55307 1936 #define CAN_MCR_INRQ_Pos (0U)
AnnaBridge 167:e84263d55307 1937 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1938 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
AnnaBridge 167:e84263d55307 1939 #define CAN_MCR_SLEEP_Pos (1U)
AnnaBridge 167:e84263d55307 1940 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1941 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
AnnaBridge 167:e84263d55307 1942 #define CAN_MCR_TXFP_Pos (2U)
AnnaBridge 167:e84263d55307 1943 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1944 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
AnnaBridge 167:e84263d55307 1945 #define CAN_MCR_RFLM_Pos (3U)
AnnaBridge 167:e84263d55307 1946 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1947 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
AnnaBridge 167:e84263d55307 1948 #define CAN_MCR_NART_Pos (4U)
AnnaBridge 167:e84263d55307 1949 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1950 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
AnnaBridge 167:e84263d55307 1951 #define CAN_MCR_AWUM_Pos (5U)
AnnaBridge 167:e84263d55307 1952 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 1953 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
AnnaBridge 167:e84263d55307 1954 #define CAN_MCR_ABOM_Pos (6U)
AnnaBridge 167:e84263d55307 1955 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 1956 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
AnnaBridge 167:e84263d55307 1957 #define CAN_MCR_TTCM_Pos (7U)
AnnaBridge 167:e84263d55307 1958 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 1959 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
AnnaBridge 167:e84263d55307 1960 #define CAN_MCR_RESET_Pos (15U)
AnnaBridge 167:e84263d55307 1961 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 1962 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
AnnaBridge 167:e84263d55307 1963 #define CAN_MCR_DBF_Pos (16U)
AnnaBridge 167:e84263d55307 1964 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 1965 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
<> 144:ef7eb2e8f9f7 1966 /******************* Bit definition for CAN_MSR register ********************/
AnnaBridge 167:e84263d55307 1967 #define CAN_MSR_INAK_Pos (0U)
AnnaBridge 167:e84263d55307 1968 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1969 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
AnnaBridge 167:e84263d55307 1970 #define CAN_MSR_SLAK_Pos (1U)
AnnaBridge 167:e84263d55307 1971 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 1972 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
AnnaBridge 167:e84263d55307 1973 #define CAN_MSR_ERRI_Pos (2U)
AnnaBridge 167:e84263d55307 1974 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 1975 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
AnnaBridge 167:e84263d55307 1976 #define CAN_MSR_WKUI_Pos (3U)
AnnaBridge 167:e84263d55307 1977 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 1978 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
AnnaBridge 167:e84263d55307 1979 #define CAN_MSR_SLAKI_Pos (4U)
AnnaBridge 167:e84263d55307 1980 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 1981 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
AnnaBridge 167:e84263d55307 1982 #define CAN_MSR_TXM_Pos (8U)
AnnaBridge 167:e84263d55307 1983 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 1984 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
AnnaBridge 167:e84263d55307 1985 #define CAN_MSR_RXM_Pos (9U)
AnnaBridge 167:e84263d55307 1986 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 1987 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
AnnaBridge 167:e84263d55307 1988 #define CAN_MSR_SAMP_Pos (10U)
AnnaBridge 167:e84263d55307 1989 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 1990 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
AnnaBridge 167:e84263d55307 1991 #define CAN_MSR_RX_Pos (11U)
AnnaBridge 167:e84263d55307 1992 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 1993 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
<> 144:ef7eb2e8f9f7 1994
<> 144:ef7eb2e8f9f7 1995 /******************* Bit definition for CAN_TSR register ********************/
AnnaBridge 167:e84263d55307 1996 #define CAN_TSR_RQCP0_Pos (0U)
AnnaBridge 167:e84263d55307 1997 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 1998 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
AnnaBridge 167:e84263d55307 1999 #define CAN_TSR_TXOK0_Pos (1U)
AnnaBridge 167:e84263d55307 2000 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2001 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
AnnaBridge 167:e84263d55307 2002 #define CAN_TSR_ALST0_Pos (2U)
AnnaBridge 167:e84263d55307 2003 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2004 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
AnnaBridge 167:e84263d55307 2005 #define CAN_TSR_TERR0_Pos (3U)
AnnaBridge 167:e84263d55307 2006 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2007 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
AnnaBridge 167:e84263d55307 2008 #define CAN_TSR_ABRQ0_Pos (7U)
AnnaBridge 167:e84263d55307 2009 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2010 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
AnnaBridge 167:e84263d55307 2011 #define CAN_TSR_RQCP1_Pos (8U)
AnnaBridge 167:e84263d55307 2012 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2013 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
AnnaBridge 167:e84263d55307 2014 #define CAN_TSR_TXOK1_Pos (9U)
AnnaBridge 167:e84263d55307 2015 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2016 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
AnnaBridge 167:e84263d55307 2017 #define CAN_TSR_ALST1_Pos (10U)
AnnaBridge 167:e84263d55307 2018 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2019 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
AnnaBridge 167:e84263d55307 2020 #define CAN_TSR_TERR1_Pos (11U)
AnnaBridge 167:e84263d55307 2021 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2022 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
AnnaBridge 167:e84263d55307 2023 #define CAN_TSR_ABRQ1_Pos (15U)
AnnaBridge 167:e84263d55307 2024 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2025 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
AnnaBridge 167:e84263d55307 2026 #define CAN_TSR_RQCP2_Pos (16U)
AnnaBridge 167:e84263d55307 2027 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2028 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
AnnaBridge 167:e84263d55307 2029 #define CAN_TSR_TXOK2_Pos (17U)
AnnaBridge 167:e84263d55307 2030 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2031 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
AnnaBridge 167:e84263d55307 2032 #define CAN_TSR_ALST2_Pos (18U)
AnnaBridge 167:e84263d55307 2033 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2034 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
AnnaBridge 167:e84263d55307 2035 #define CAN_TSR_TERR2_Pos (19U)
AnnaBridge 167:e84263d55307 2036 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2037 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
AnnaBridge 167:e84263d55307 2038 #define CAN_TSR_ABRQ2_Pos (23U)
AnnaBridge 167:e84263d55307 2039 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2040 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
AnnaBridge 167:e84263d55307 2041 #define CAN_TSR_CODE_Pos (24U)
AnnaBridge 167:e84263d55307 2042 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 2043 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
AnnaBridge 167:e84263d55307 2044
AnnaBridge 167:e84263d55307 2045 #define CAN_TSR_TME_Pos (26U)
AnnaBridge 167:e84263d55307 2046 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
AnnaBridge 167:e84263d55307 2047 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
AnnaBridge 167:e84263d55307 2048 #define CAN_TSR_TME0_Pos (26U)
AnnaBridge 167:e84263d55307 2049 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2050 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
AnnaBridge 167:e84263d55307 2051 #define CAN_TSR_TME1_Pos (27U)
AnnaBridge 167:e84263d55307 2052 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2053 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
AnnaBridge 167:e84263d55307 2054 #define CAN_TSR_TME2_Pos (28U)
AnnaBridge 167:e84263d55307 2055 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 2056 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
AnnaBridge 167:e84263d55307 2057
AnnaBridge 167:e84263d55307 2058 #define CAN_TSR_LOW_Pos (29U)
AnnaBridge 167:e84263d55307 2059 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
AnnaBridge 167:e84263d55307 2060 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
AnnaBridge 167:e84263d55307 2061 #define CAN_TSR_LOW0_Pos (29U)
AnnaBridge 167:e84263d55307 2062 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 2063 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
AnnaBridge 167:e84263d55307 2064 #define CAN_TSR_LOW1_Pos (30U)
AnnaBridge 167:e84263d55307 2065 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 2066 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
AnnaBridge 167:e84263d55307 2067 #define CAN_TSR_LOW2_Pos (31U)
AnnaBridge 167:e84263d55307 2068 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 2069 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
<> 144:ef7eb2e8f9f7 2070
<> 144:ef7eb2e8f9f7 2071 /******************* Bit definition for CAN_RF0R register *******************/
AnnaBridge 167:e84263d55307 2072 #define CAN_RF0R_FMP0_Pos (0U)
AnnaBridge 167:e84263d55307 2073 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 2074 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
AnnaBridge 167:e84263d55307 2075 #define CAN_RF0R_FULL0_Pos (3U)
AnnaBridge 167:e84263d55307 2076 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2077 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
AnnaBridge 167:e84263d55307 2078 #define CAN_RF0R_FOVR0_Pos (4U)
AnnaBridge 167:e84263d55307 2079 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2080 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
AnnaBridge 167:e84263d55307 2081 #define CAN_RF0R_RFOM0_Pos (5U)
AnnaBridge 167:e84263d55307 2082 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2083 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /******************* Bit definition for CAN_RF1R register *******************/
AnnaBridge 167:e84263d55307 2086 #define CAN_RF1R_FMP1_Pos (0U)
AnnaBridge 167:e84263d55307 2087 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 2088 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
AnnaBridge 167:e84263d55307 2089 #define CAN_RF1R_FULL1_Pos (3U)
AnnaBridge 167:e84263d55307 2090 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2091 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
AnnaBridge 167:e84263d55307 2092 #define CAN_RF1R_FOVR1_Pos (4U)
AnnaBridge 167:e84263d55307 2093 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2094 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
AnnaBridge 167:e84263d55307 2095 #define CAN_RF1R_RFOM1_Pos (5U)
AnnaBridge 167:e84263d55307 2096 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2097 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /******************** Bit definition for CAN_IER register *******************/
AnnaBridge 167:e84263d55307 2100 #define CAN_IER_TMEIE_Pos (0U)
AnnaBridge 167:e84263d55307 2101 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2102 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
AnnaBridge 167:e84263d55307 2103 #define CAN_IER_FMPIE0_Pos (1U)
AnnaBridge 167:e84263d55307 2104 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2105 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 167:e84263d55307 2106 #define CAN_IER_FFIE0_Pos (2U)
AnnaBridge 167:e84263d55307 2107 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2108 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 167:e84263d55307 2109 #define CAN_IER_FOVIE0_Pos (3U)
AnnaBridge 167:e84263d55307 2110 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2111 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 167:e84263d55307 2112 #define CAN_IER_FMPIE1_Pos (4U)
AnnaBridge 167:e84263d55307 2113 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2114 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
AnnaBridge 167:e84263d55307 2115 #define CAN_IER_FFIE1_Pos (5U)
AnnaBridge 167:e84263d55307 2116 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2117 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
AnnaBridge 167:e84263d55307 2118 #define CAN_IER_FOVIE1_Pos (6U)
AnnaBridge 167:e84263d55307 2119 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2120 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
AnnaBridge 167:e84263d55307 2121 #define CAN_IER_EWGIE_Pos (8U)
AnnaBridge 167:e84263d55307 2122 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2123 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
AnnaBridge 167:e84263d55307 2124 #define CAN_IER_EPVIE_Pos (9U)
AnnaBridge 167:e84263d55307 2125 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2126 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
AnnaBridge 167:e84263d55307 2127 #define CAN_IER_BOFIE_Pos (10U)
AnnaBridge 167:e84263d55307 2128 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2129 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
AnnaBridge 167:e84263d55307 2130 #define CAN_IER_LECIE_Pos (11U)
AnnaBridge 167:e84263d55307 2131 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2132 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
AnnaBridge 167:e84263d55307 2133 #define CAN_IER_ERRIE_Pos (15U)
AnnaBridge 167:e84263d55307 2134 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2135 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 167:e84263d55307 2136 #define CAN_IER_WKUIE_Pos (16U)
AnnaBridge 167:e84263d55307 2137 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2138 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
AnnaBridge 167:e84263d55307 2139 #define CAN_IER_SLKIE_Pos (17U)
AnnaBridge 167:e84263d55307 2140 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2141 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
AnnaBridge 167:e84263d55307 2142 #define CAN_IER_EWGIE_Pos (8U)
<> 144:ef7eb2e8f9f7 2143
<> 144:ef7eb2e8f9f7 2144 /******************** Bit definition for CAN_ESR register *******************/
AnnaBridge 167:e84263d55307 2145 #define CAN_ESR_EWGF_Pos (0U)
AnnaBridge 167:e84263d55307 2146 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2147 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
AnnaBridge 167:e84263d55307 2148 #define CAN_ESR_EPVF_Pos (1U)
AnnaBridge 167:e84263d55307 2149 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2150 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
AnnaBridge 167:e84263d55307 2151 #define CAN_ESR_BOFF_Pos (2U)
AnnaBridge 167:e84263d55307 2152 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2153 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
AnnaBridge 167:e84263d55307 2154
AnnaBridge 167:e84263d55307 2155 #define CAN_ESR_LEC_Pos (4U)
AnnaBridge 167:e84263d55307 2156 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 2157 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
AnnaBridge 167:e84263d55307 2158 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2159 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2160 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2161
AnnaBridge 167:e84263d55307 2162 #define CAN_ESR_TEC_Pos (16U)
AnnaBridge 167:e84263d55307 2163 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2164 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
AnnaBridge 167:e84263d55307 2165 #define CAN_ESR_REC_Pos (24U)
AnnaBridge 167:e84263d55307 2166 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2167 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
<> 144:ef7eb2e8f9f7 2168
<> 144:ef7eb2e8f9f7 2169 /******************* Bit definition for CAN_BTR register ********************/
AnnaBridge 167:e84263d55307 2170 #define CAN_BTR_BRP_Pos (0U)
AnnaBridge 167:e84263d55307 2171 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
AnnaBridge 167:e84263d55307 2172 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
AnnaBridge 167:e84263d55307 2173 #define CAN_BTR_TS1_Pos (16U)
AnnaBridge 167:e84263d55307 2174 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 2175 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
AnnaBridge 167:e84263d55307 2176 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2177 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2178 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2179 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2180 #define CAN_BTR_TS2_Pos (20U)
AnnaBridge 167:e84263d55307 2181 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
AnnaBridge 167:e84263d55307 2182 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
AnnaBridge 167:e84263d55307 2183 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2184 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2185 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2186 #define CAN_BTR_SJW_Pos (24U)
AnnaBridge 167:e84263d55307 2187 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 2188 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
AnnaBridge 167:e84263d55307 2189 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2190 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2191 #define CAN_BTR_LBKM_Pos (30U)
AnnaBridge 167:e84263d55307 2192 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 2193 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
AnnaBridge 167:e84263d55307 2194 #define CAN_BTR_SILM_Pos (31U)
AnnaBridge 167:e84263d55307 2195 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 2196 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
<> 144:ef7eb2e8f9f7 2197
<> 144:ef7eb2e8f9f7 2198
<> 144:ef7eb2e8f9f7 2199 /*!<Mailbox registers */
<> 144:ef7eb2e8f9f7 2200 /****************** Bit definition for CAN_TI0R register ********************/
AnnaBridge 167:e84263d55307 2201 #define CAN_TI0R_TXRQ_Pos (0U)
AnnaBridge 167:e84263d55307 2202 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2203 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 167:e84263d55307 2204 #define CAN_TI0R_RTR_Pos (1U)
AnnaBridge 167:e84263d55307 2205 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2206 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 167:e84263d55307 2207 #define CAN_TI0R_IDE_Pos (2U)
AnnaBridge 167:e84263d55307 2208 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2209 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 167:e84263d55307 2210 #define CAN_TI0R_EXID_Pos (3U)
AnnaBridge 167:e84263d55307 2211 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 167:e84263d55307 2212 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 167:e84263d55307 2213 #define CAN_TI0R_STID_Pos (21U)
AnnaBridge 167:e84263d55307 2214 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 167:e84263d55307 2215 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2216
<> 144:ef7eb2e8f9f7 2217 /****************** Bit definition for CAN_TDT0R register *******************/
AnnaBridge 167:e84263d55307 2218 #define CAN_TDT0R_DLC_Pos (0U)
AnnaBridge 167:e84263d55307 2219 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 2220 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 167:e84263d55307 2221 #define CAN_TDT0R_TGT_Pos (8U)
AnnaBridge 167:e84263d55307 2222 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2223 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 167:e84263d55307 2224 #define CAN_TDT0R_TIME_Pos (16U)
AnnaBridge 167:e84263d55307 2225 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 2226 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2227
<> 144:ef7eb2e8f9f7 2228 /****************** Bit definition for CAN_TDL0R register *******************/
AnnaBridge 167:e84263d55307 2229 #define CAN_TDL0R_DATA0_Pos (0U)
AnnaBridge 167:e84263d55307 2230 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2231 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 167:e84263d55307 2232 #define CAN_TDL0R_DATA1_Pos (8U)
AnnaBridge 167:e84263d55307 2233 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2234 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 167:e84263d55307 2235 #define CAN_TDL0R_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 2236 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2237 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 167:e84263d55307 2238 #define CAN_TDL0R_DATA3_Pos (24U)
AnnaBridge 167:e84263d55307 2239 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2240 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /****************** Bit definition for CAN_TDH0R register *******************/
AnnaBridge 167:e84263d55307 2243 #define CAN_TDH0R_DATA4_Pos (0U)
AnnaBridge 167:e84263d55307 2244 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2245 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 167:e84263d55307 2246 #define CAN_TDH0R_DATA5_Pos (8U)
AnnaBridge 167:e84263d55307 2247 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2248 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 167:e84263d55307 2249 #define CAN_TDH0R_DATA6_Pos (16U)
AnnaBridge 167:e84263d55307 2250 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2251 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 167:e84263d55307 2252 #define CAN_TDH0R_DATA7_Pos (24U)
AnnaBridge 167:e84263d55307 2253 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2254 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2255
<> 144:ef7eb2e8f9f7 2256 /******************* Bit definition for CAN_TI1R register *******************/
AnnaBridge 167:e84263d55307 2257 #define CAN_TI1R_TXRQ_Pos (0U)
AnnaBridge 167:e84263d55307 2258 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2259 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 167:e84263d55307 2260 #define CAN_TI1R_RTR_Pos (1U)
AnnaBridge 167:e84263d55307 2261 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2262 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 167:e84263d55307 2263 #define CAN_TI1R_IDE_Pos (2U)
AnnaBridge 167:e84263d55307 2264 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2265 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 167:e84263d55307 2266 #define CAN_TI1R_EXID_Pos (3U)
AnnaBridge 167:e84263d55307 2267 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 167:e84263d55307 2268 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 167:e84263d55307 2269 #define CAN_TI1R_STID_Pos (21U)
AnnaBridge 167:e84263d55307 2270 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 167:e84263d55307 2271 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2272
<> 144:ef7eb2e8f9f7 2273 /******************* Bit definition for CAN_TDT1R register ******************/
AnnaBridge 167:e84263d55307 2274 #define CAN_TDT1R_DLC_Pos (0U)
AnnaBridge 167:e84263d55307 2275 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 2276 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 167:e84263d55307 2277 #define CAN_TDT1R_TGT_Pos (8U)
AnnaBridge 167:e84263d55307 2278 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2279 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 167:e84263d55307 2280 #define CAN_TDT1R_TIME_Pos (16U)
AnnaBridge 167:e84263d55307 2281 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 2282 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2283
<> 144:ef7eb2e8f9f7 2284 /******************* Bit definition for CAN_TDL1R register ******************/
AnnaBridge 167:e84263d55307 2285 #define CAN_TDL1R_DATA0_Pos (0U)
AnnaBridge 167:e84263d55307 2286 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2287 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 167:e84263d55307 2288 #define CAN_TDL1R_DATA1_Pos (8U)
AnnaBridge 167:e84263d55307 2289 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2290 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 167:e84263d55307 2291 #define CAN_TDL1R_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 2292 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2293 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 167:e84263d55307 2294 #define CAN_TDL1R_DATA3_Pos (24U)
AnnaBridge 167:e84263d55307 2295 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2296 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2297
<> 144:ef7eb2e8f9f7 2298 /******************* Bit definition for CAN_TDH1R register ******************/
AnnaBridge 167:e84263d55307 2299 #define CAN_TDH1R_DATA4_Pos (0U)
AnnaBridge 167:e84263d55307 2300 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2301 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 167:e84263d55307 2302 #define CAN_TDH1R_DATA5_Pos (8U)
AnnaBridge 167:e84263d55307 2303 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2304 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 167:e84263d55307 2305 #define CAN_TDH1R_DATA6_Pos (16U)
AnnaBridge 167:e84263d55307 2306 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2307 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 167:e84263d55307 2308 #define CAN_TDH1R_DATA7_Pos (24U)
AnnaBridge 167:e84263d55307 2309 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2310 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2311
<> 144:ef7eb2e8f9f7 2312 /******************* Bit definition for CAN_TI2R register *******************/
AnnaBridge 167:e84263d55307 2313 #define CAN_TI2R_TXRQ_Pos (0U)
AnnaBridge 167:e84263d55307 2314 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2315 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
AnnaBridge 167:e84263d55307 2316 #define CAN_TI2R_RTR_Pos (1U)
AnnaBridge 167:e84263d55307 2317 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2318 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 167:e84263d55307 2319 #define CAN_TI2R_IDE_Pos (2U)
AnnaBridge 167:e84263d55307 2320 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2321 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 167:e84263d55307 2322 #define CAN_TI2R_EXID_Pos (3U)
AnnaBridge 167:e84263d55307 2323 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 167:e84263d55307 2324 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
AnnaBridge 167:e84263d55307 2325 #define CAN_TI2R_STID_Pos (21U)
AnnaBridge 167:e84263d55307 2326 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 167:e84263d55307 2327 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2328
<> 144:ef7eb2e8f9f7 2329 /******************* Bit definition for CAN_TDT2R register ******************/
AnnaBridge 167:e84263d55307 2330 #define CAN_TDT2R_DLC_Pos (0U)
AnnaBridge 167:e84263d55307 2331 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 2332 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
AnnaBridge 167:e84263d55307 2333 #define CAN_TDT2R_TGT_Pos (8U)
AnnaBridge 167:e84263d55307 2334 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2335 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
AnnaBridge 167:e84263d55307 2336 #define CAN_TDT2R_TIME_Pos (16U)
AnnaBridge 167:e84263d55307 2337 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 2338 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2339
<> 144:ef7eb2e8f9f7 2340 /******************* Bit definition for CAN_TDL2R register ******************/
AnnaBridge 167:e84263d55307 2341 #define CAN_TDL2R_DATA0_Pos (0U)
AnnaBridge 167:e84263d55307 2342 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2343 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 167:e84263d55307 2344 #define CAN_TDL2R_DATA1_Pos (8U)
AnnaBridge 167:e84263d55307 2345 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2346 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 167:e84263d55307 2347 #define CAN_TDL2R_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 2348 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2349 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 167:e84263d55307 2350 #define CAN_TDL2R_DATA3_Pos (24U)
AnnaBridge 167:e84263d55307 2351 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2352 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2353
<> 144:ef7eb2e8f9f7 2354 /******************* Bit definition for CAN_TDH2R register ******************/
AnnaBridge 167:e84263d55307 2355 #define CAN_TDH2R_DATA4_Pos (0U)
AnnaBridge 167:e84263d55307 2356 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2357 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 167:e84263d55307 2358 #define CAN_TDH2R_DATA5_Pos (8U)
AnnaBridge 167:e84263d55307 2359 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2360 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 167:e84263d55307 2361 #define CAN_TDH2R_DATA6_Pos (16U)
AnnaBridge 167:e84263d55307 2362 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2363 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 167:e84263d55307 2364 #define CAN_TDH2R_DATA7_Pos (24U)
AnnaBridge 167:e84263d55307 2365 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2366 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2367
<> 144:ef7eb2e8f9f7 2368 /******************* Bit definition for CAN_RI0R register *******************/
AnnaBridge 167:e84263d55307 2369 #define CAN_RI0R_RTR_Pos (1U)
AnnaBridge 167:e84263d55307 2370 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2371 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 167:e84263d55307 2372 #define CAN_RI0R_IDE_Pos (2U)
AnnaBridge 167:e84263d55307 2373 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2374 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 167:e84263d55307 2375 #define CAN_RI0R_EXID_Pos (3U)
AnnaBridge 167:e84263d55307 2376 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 167:e84263d55307 2377 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
AnnaBridge 167:e84263d55307 2378 #define CAN_RI0R_STID_Pos (21U)
AnnaBridge 167:e84263d55307 2379 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 167:e84263d55307 2380 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2381
<> 144:ef7eb2e8f9f7 2382 /******************* Bit definition for CAN_RDT0R register ******************/
AnnaBridge 167:e84263d55307 2383 #define CAN_RDT0R_DLC_Pos (0U)
AnnaBridge 167:e84263d55307 2384 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 2385 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
AnnaBridge 167:e84263d55307 2386 #define CAN_RDT0R_FMI_Pos (8U)
AnnaBridge 167:e84263d55307 2387 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2388 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 167:e84263d55307 2389 #define CAN_RDT0R_TIME_Pos (16U)
AnnaBridge 167:e84263d55307 2390 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 2391 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2392
<> 144:ef7eb2e8f9f7 2393 /******************* Bit definition for CAN_RDL0R register ******************/
AnnaBridge 167:e84263d55307 2394 #define CAN_RDL0R_DATA0_Pos (0U)
AnnaBridge 167:e84263d55307 2395 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2396 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 167:e84263d55307 2397 #define CAN_RDL0R_DATA1_Pos (8U)
AnnaBridge 167:e84263d55307 2398 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2399 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 167:e84263d55307 2400 #define CAN_RDL0R_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 2401 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2402 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 167:e84263d55307 2403 #define CAN_RDL0R_DATA3_Pos (24U)
AnnaBridge 167:e84263d55307 2404 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2405 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 /******************* Bit definition for CAN_RDH0R register ******************/
AnnaBridge 167:e84263d55307 2408 #define CAN_RDH0R_DATA4_Pos (0U)
AnnaBridge 167:e84263d55307 2409 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2410 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 167:e84263d55307 2411 #define CAN_RDH0R_DATA5_Pos (8U)
AnnaBridge 167:e84263d55307 2412 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2413 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 167:e84263d55307 2414 #define CAN_RDH0R_DATA6_Pos (16U)
AnnaBridge 167:e84263d55307 2415 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2416 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 167:e84263d55307 2417 #define CAN_RDH0R_DATA7_Pos (24U)
AnnaBridge 167:e84263d55307 2418 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2419 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2420
<> 144:ef7eb2e8f9f7 2421 /******************* Bit definition for CAN_RI1R register *******************/
AnnaBridge 167:e84263d55307 2422 #define CAN_RI1R_RTR_Pos (1U)
AnnaBridge 167:e84263d55307 2423 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2424 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
AnnaBridge 167:e84263d55307 2425 #define CAN_RI1R_IDE_Pos (2U)
AnnaBridge 167:e84263d55307 2426 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2427 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
AnnaBridge 167:e84263d55307 2428 #define CAN_RI1R_EXID_Pos (3U)
AnnaBridge 167:e84263d55307 2429 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
AnnaBridge 167:e84263d55307 2430 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
AnnaBridge 167:e84263d55307 2431 #define CAN_RI1R_STID_Pos (21U)
AnnaBridge 167:e84263d55307 2432 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
AnnaBridge 167:e84263d55307 2433 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
<> 144:ef7eb2e8f9f7 2434
<> 144:ef7eb2e8f9f7 2435 /******************* Bit definition for CAN_RDT1R register ******************/
AnnaBridge 167:e84263d55307 2436 #define CAN_RDT1R_DLC_Pos (0U)
AnnaBridge 167:e84263d55307 2437 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 2438 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
AnnaBridge 167:e84263d55307 2439 #define CAN_RDT1R_FMI_Pos (8U)
AnnaBridge 167:e84263d55307 2440 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2441 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
AnnaBridge 167:e84263d55307 2442 #define CAN_RDT1R_TIME_Pos (16U)
AnnaBridge 167:e84263d55307 2443 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 2444 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
<> 144:ef7eb2e8f9f7 2445
<> 144:ef7eb2e8f9f7 2446 /******************* Bit definition for CAN_RDL1R register ******************/
AnnaBridge 167:e84263d55307 2447 #define CAN_RDL1R_DATA0_Pos (0U)
AnnaBridge 167:e84263d55307 2448 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2449 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
AnnaBridge 167:e84263d55307 2450 #define CAN_RDL1R_DATA1_Pos (8U)
AnnaBridge 167:e84263d55307 2451 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2452 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
AnnaBridge 167:e84263d55307 2453 #define CAN_RDL1R_DATA2_Pos (16U)
AnnaBridge 167:e84263d55307 2454 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2455 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
AnnaBridge 167:e84263d55307 2456 #define CAN_RDL1R_DATA3_Pos (24U)
AnnaBridge 167:e84263d55307 2457 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2458 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
<> 144:ef7eb2e8f9f7 2459
<> 144:ef7eb2e8f9f7 2460 /******************* Bit definition for CAN_RDH1R register ******************/
AnnaBridge 167:e84263d55307 2461 #define CAN_RDH1R_DATA4_Pos (0U)
AnnaBridge 167:e84263d55307 2462 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 2463 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
AnnaBridge 167:e84263d55307 2464 #define CAN_RDH1R_DATA5_Pos (8U)
AnnaBridge 167:e84263d55307 2465 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 2466 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
AnnaBridge 167:e84263d55307 2467 #define CAN_RDH1R_DATA6_Pos (16U)
AnnaBridge 167:e84263d55307 2468 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 2469 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
AnnaBridge 167:e84263d55307 2470 #define CAN_RDH1R_DATA7_Pos (24U)
AnnaBridge 167:e84263d55307 2471 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 2472 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /*!<CAN filter registers */
<> 144:ef7eb2e8f9f7 2475 /******************* Bit definition for CAN_FMR register ********************/
AnnaBridge 167:e84263d55307 2476 #define CAN_FMR_FINIT_Pos (0U)
AnnaBridge 167:e84263d55307 2477 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2478 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
AnnaBridge 167:e84263d55307 2479 #define CAN_FMR_CAN2SB_Pos (8U)
AnnaBridge 167:e84263d55307 2480 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
AnnaBridge 167:e84263d55307 2481 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
<> 144:ef7eb2e8f9f7 2482
<> 144:ef7eb2e8f9f7 2483 /******************* Bit definition for CAN_FM1R register *******************/
AnnaBridge 167:e84263d55307 2484 #define CAN_FM1R_FBM_Pos (0U)
AnnaBridge 167:e84263d55307 2485 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 167:e84263d55307 2486 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
AnnaBridge 167:e84263d55307 2487 #define CAN_FM1R_FBM0_Pos (0U)
AnnaBridge 167:e84263d55307 2488 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2489 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
AnnaBridge 167:e84263d55307 2490 #define CAN_FM1R_FBM1_Pos (1U)
AnnaBridge 167:e84263d55307 2491 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2492 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
AnnaBridge 167:e84263d55307 2493 #define CAN_FM1R_FBM2_Pos (2U)
AnnaBridge 167:e84263d55307 2494 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2495 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
AnnaBridge 167:e84263d55307 2496 #define CAN_FM1R_FBM3_Pos (3U)
AnnaBridge 167:e84263d55307 2497 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2498 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
AnnaBridge 167:e84263d55307 2499 #define CAN_FM1R_FBM4_Pos (4U)
AnnaBridge 167:e84263d55307 2500 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2501 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
AnnaBridge 167:e84263d55307 2502 #define CAN_FM1R_FBM5_Pos (5U)
AnnaBridge 167:e84263d55307 2503 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2504 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
AnnaBridge 167:e84263d55307 2505 #define CAN_FM1R_FBM6_Pos (6U)
AnnaBridge 167:e84263d55307 2506 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2507 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
AnnaBridge 167:e84263d55307 2508 #define CAN_FM1R_FBM7_Pos (7U)
AnnaBridge 167:e84263d55307 2509 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2510 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
AnnaBridge 167:e84263d55307 2511 #define CAN_FM1R_FBM8_Pos (8U)
AnnaBridge 167:e84263d55307 2512 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2513 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
AnnaBridge 167:e84263d55307 2514 #define CAN_FM1R_FBM9_Pos (9U)
AnnaBridge 167:e84263d55307 2515 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2516 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
AnnaBridge 167:e84263d55307 2517 #define CAN_FM1R_FBM10_Pos (10U)
AnnaBridge 167:e84263d55307 2518 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2519 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
AnnaBridge 167:e84263d55307 2520 #define CAN_FM1R_FBM11_Pos (11U)
AnnaBridge 167:e84263d55307 2521 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2522 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
AnnaBridge 167:e84263d55307 2523 #define CAN_FM1R_FBM12_Pos (12U)
AnnaBridge 167:e84263d55307 2524 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2525 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
AnnaBridge 167:e84263d55307 2526 #define CAN_FM1R_FBM13_Pos (13U)
AnnaBridge 167:e84263d55307 2527 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2528 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
AnnaBridge 167:e84263d55307 2529 #define CAN_FM1R_FBM14_Pos (14U)
AnnaBridge 167:e84263d55307 2530 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2531 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
AnnaBridge 167:e84263d55307 2532 #define CAN_FM1R_FBM15_Pos (15U)
AnnaBridge 167:e84263d55307 2533 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2534 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
AnnaBridge 167:e84263d55307 2535 #define CAN_FM1R_FBM16_Pos (16U)
AnnaBridge 167:e84263d55307 2536 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2537 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
AnnaBridge 167:e84263d55307 2538 #define CAN_FM1R_FBM17_Pos (17U)
AnnaBridge 167:e84263d55307 2539 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2540 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
AnnaBridge 167:e84263d55307 2541 #define CAN_FM1R_FBM18_Pos (18U)
AnnaBridge 167:e84263d55307 2542 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2543 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
AnnaBridge 167:e84263d55307 2544 #define CAN_FM1R_FBM19_Pos (19U)
AnnaBridge 167:e84263d55307 2545 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2546 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
AnnaBridge 167:e84263d55307 2547 #define CAN_FM1R_FBM20_Pos (20U)
AnnaBridge 167:e84263d55307 2548 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2549 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
AnnaBridge 167:e84263d55307 2550 #define CAN_FM1R_FBM21_Pos (21U)
AnnaBridge 167:e84263d55307 2551 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2552 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
AnnaBridge 167:e84263d55307 2553 #define CAN_FM1R_FBM22_Pos (22U)
AnnaBridge 167:e84263d55307 2554 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2555 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
AnnaBridge 167:e84263d55307 2556 #define CAN_FM1R_FBM23_Pos (23U)
AnnaBridge 167:e84263d55307 2557 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2558 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
AnnaBridge 167:e84263d55307 2559 #define CAN_FM1R_FBM24_Pos (24U)
AnnaBridge 167:e84263d55307 2560 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2561 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
AnnaBridge 167:e84263d55307 2562 #define CAN_FM1R_FBM25_Pos (25U)
AnnaBridge 167:e84263d55307 2563 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2564 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
AnnaBridge 167:e84263d55307 2565 #define CAN_FM1R_FBM26_Pos (26U)
AnnaBridge 167:e84263d55307 2566 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2567 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
AnnaBridge 167:e84263d55307 2568 #define CAN_FM1R_FBM27_Pos (27U)
AnnaBridge 167:e84263d55307 2569 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2570 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
<> 144:ef7eb2e8f9f7 2571
<> 144:ef7eb2e8f9f7 2572 /******************* Bit definition for CAN_FS1R register *******************/
AnnaBridge 167:e84263d55307 2573 #define CAN_FS1R_FSC_Pos (0U)
AnnaBridge 167:e84263d55307 2574 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 167:e84263d55307 2575 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
AnnaBridge 167:e84263d55307 2576 #define CAN_FS1R_FSC0_Pos (0U)
AnnaBridge 167:e84263d55307 2577 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2578 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
AnnaBridge 167:e84263d55307 2579 #define CAN_FS1R_FSC1_Pos (1U)
AnnaBridge 167:e84263d55307 2580 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2581 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
AnnaBridge 167:e84263d55307 2582 #define CAN_FS1R_FSC2_Pos (2U)
AnnaBridge 167:e84263d55307 2583 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2584 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
AnnaBridge 167:e84263d55307 2585 #define CAN_FS1R_FSC3_Pos (3U)
AnnaBridge 167:e84263d55307 2586 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2587 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
AnnaBridge 167:e84263d55307 2588 #define CAN_FS1R_FSC4_Pos (4U)
AnnaBridge 167:e84263d55307 2589 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2590 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
AnnaBridge 167:e84263d55307 2591 #define CAN_FS1R_FSC5_Pos (5U)
AnnaBridge 167:e84263d55307 2592 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2593 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
AnnaBridge 167:e84263d55307 2594 #define CAN_FS1R_FSC6_Pos (6U)
AnnaBridge 167:e84263d55307 2595 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2596 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
AnnaBridge 167:e84263d55307 2597 #define CAN_FS1R_FSC7_Pos (7U)
AnnaBridge 167:e84263d55307 2598 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2599 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
AnnaBridge 167:e84263d55307 2600 #define CAN_FS1R_FSC8_Pos (8U)
AnnaBridge 167:e84263d55307 2601 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2602 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
AnnaBridge 167:e84263d55307 2603 #define CAN_FS1R_FSC9_Pos (9U)
AnnaBridge 167:e84263d55307 2604 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2605 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
AnnaBridge 167:e84263d55307 2606 #define CAN_FS1R_FSC10_Pos (10U)
AnnaBridge 167:e84263d55307 2607 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2608 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
AnnaBridge 167:e84263d55307 2609 #define CAN_FS1R_FSC11_Pos (11U)
AnnaBridge 167:e84263d55307 2610 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2611 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
AnnaBridge 167:e84263d55307 2612 #define CAN_FS1R_FSC12_Pos (12U)
AnnaBridge 167:e84263d55307 2613 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2614 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
AnnaBridge 167:e84263d55307 2615 #define CAN_FS1R_FSC13_Pos (13U)
AnnaBridge 167:e84263d55307 2616 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2617 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
AnnaBridge 167:e84263d55307 2618 #define CAN_FS1R_FSC14_Pos (14U)
AnnaBridge 167:e84263d55307 2619 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2620 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
AnnaBridge 167:e84263d55307 2621 #define CAN_FS1R_FSC15_Pos (15U)
AnnaBridge 167:e84263d55307 2622 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2623 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
AnnaBridge 167:e84263d55307 2624 #define CAN_FS1R_FSC16_Pos (16U)
AnnaBridge 167:e84263d55307 2625 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2626 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
AnnaBridge 167:e84263d55307 2627 #define CAN_FS1R_FSC17_Pos (17U)
AnnaBridge 167:e84263d55307 2628 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2629 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
AnnaBridge 167:e84263d55307 2630 #define CAN_FS1R_FSC18_Pos (18U)
AnnaBridge 167:e84263d55307 2631 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2632 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
AnnaBridge 167:e84263d55307 2633 #define CAN_FS1R_FSC19_Pos (19U)
AnnaBridge 167:e84263d55307 2634 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2635 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
AnnaBridge 167:e84263d55307 2636 #define CAN_FS1R_FSC20_Pos (20U)
AnnaBridge 167:e84263d55307 2637 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2638 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
AnnaBridge 167:e84263d55307 2639 #define CAN_FS1R_FSC21_Pos (21U)
AnnaBridge 167:e84263d55307 2640 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2641 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
AnnaBridge 167:e84263d55307 2642 #define CAN_FS1R_FSC22_Pos (22U)
AnnaBridge 167:e84263d55307 2643 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2644 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
AnnaBridge 167:e84263d55307 2645 #define CAN_FS1R_FSC23_Pos (23U)
AnnaBridge 167:e84263d55307 2646 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2647 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
AnnaBridge 167:e84263d55307 2648 #define CAN_FS1R_FSC24_Pos (24U)
AnnaBridge 167:e84263d55307 2649 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2650 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
AnnaBridge 167:e84263d55307 2651 #define CAN_FS1R_FSC25_Pos (25U)
AnnaBridge 167:e84263d55307 2652 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2653 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
AnnaBridge 167:e84263d55307 2654 #define CAN_FS1R_FSC26_Pos (26U)
AnnaBridge 167:e84263d55307 2655 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2656 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
AnnaBridge 167:e84263d55307 2657 #define CAN_FS1R_FSC27_Pos (27U)
AnnaBridge 167:e84263d55307 2658 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2659 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
<> 144:ef7eb2e8f9f7 2660
<> 144:ef7eb2e8f9f7 2661 /****************** Bit definition for CAN_FFA1R register *******************/
AnnaBridge 167:e84263d55307 2662 #define CAN_FFA1R_FFA_Pos (0U)
AnnaBridge 167:e84263d55307 2663 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 167:e84263d55307 2664 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
AnnaBridge 167:e84263d55307 2665 #define CAN_FFA1R_FFA0_Pos (0U)
AnnaBridge 167:e84263d55307 2666 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2667 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
AnnaBridge 167:e84263d55307 2668 #define CAN_FFA1R_FFA1_Pos (1U)
AnnaBridge 167:e84263d55307 2669 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2670 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
AnnaBridge 167:e84263d55307 2671 #define CAN_FFA1R_FFA2_Pos (2U)
AnnaBridge 167:e84263d55307 2672 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2673 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
AnnaBridge 167:e84263d55307 2674 #define CAN_FFA1R_FFA3_Pos (3U)
AnnaBridge 167:e84263d55307 2675 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2676 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
AnnaBridge 167:e84263d55307 2677 #define CAN_FFA1R_FFA4_Pos (4U)
AnnaBridge 167:e84263d55307 2678 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2679 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
AnnaBridge 167:e84263d55307 2680 #define CAN_FFA1R_FFA5_Pos (5U)
AnnaBridge 167:e84263d55307 2681 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2682 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
AnnaBridge 167:e84263d55307 2683 #define CAN_FFA1R_FFA6_Pos (6U)
AnnaBridge 167:e84263d55307 2684 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2685 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
AnnaBridge 167:e84263d55307 2686 #define CAN_FFA1R_FFA7_Pos (7U)
AnnaBridge 167:e84263d55307 2687 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2688 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
AnnaBridge 167:e84263d55307 2689 #define CAN_FFA1R_FFA8_Pos (8U)
AnnaBridge 167:e84263d55307 2690 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2691 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
AnnaBridge 167:e84263d55307 2692 #define CAN_FFA1R_FFA9_Pos (9U)
AnnaBridge 167:e84263d55307 2693 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2694 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
AnnaBridge 167:e84263d55307 2695 #define CAN_FFA1R_FFA10_Pos (10U)
AnnaBridge 167:e84263d55307 2696 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2697 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
AnnaBridge 167:e84263d55307 2698 #define CAN_FFA1R_FFA11_Pos (11U)
AnnaBridge 167:e84263d55307 2699 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2700 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
AnnaBridge 167:e84263d55307 2701 #define CAN_FFA1R_FFA12_Pos (12U)
AnnaBridge 167:e84263d55307 2702 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2703 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
AnnaBridge 167:e84263d55307 2704 #define CAN_FFA1R_FFA13_Pos (13U)
AnnaBridge 167:e84263d55307 2705 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2706 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
AnnaBridge 167:e84263d55307 2707 #define CAN_FFA1R_FFA14_Pos (14U)
AnnaBridge 167:e84263d55307 2708 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2709 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
AnnaBridge 167:e84263d55307 2710 #define CAN_FFA1R_FFA15_Pos (15U)
AnnaBridge 167:e84263d55307 2711 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2712 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
AnnaBridge 167:e84263d55307 2713 #define CAN_FFA1R_FFA16_Pos (16U)
AnnaBridge 167:e84263d55307 2714 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2715 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
AnnaBridge 167:e84263d55307 2716 #define CAN_FFA1R_FFA17_Pos (17U)
AnnaBridge 167:e84263d55307 2717 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2718 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
AnnaBridge 167:e84263d55307 2719 #define CAN_FFA1R_FFA18_Pos (18U)
AnnaBridge 167:e84263d55307 2720 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2721 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
AnnaBridge 167:e84263d55307 2722 #define CAN_FFA1R_FFA19_Pos (19U)
AnnaBridge 167:e84263d55307 2723 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2724 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
AnnaBridge 167:e84263d55307 2725 #define CAN_FFA1R_FFA20_Pos (20U)
AnnaBridge 167:e84263d55307 2726 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2727 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
AnnaBridge 167:e84263d55307 2728 #define CAN_FFA1R_FFA21_Pos (21U)
AnnaBridge 167:e84263d55307 2729 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2730 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
AnnaBridge 167:e84263d55307 2731 #define CAN_FFA1R_FFA22_Pos (22U)
AnnaBridge 167:e84263d55307 2732 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2733 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
AnnaBridge 167:e84263d55307 2734 #define CAN_FFA1R_FFA23_Pos (23U)
AnnaBridge 167:e84263d55307 2735 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2736 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
AnnaBridge 167:e84263d55307 2737 #define CAN_FFA1R_FFA24_Pos (24U)
AnnaBridge 167:e84263d55307 2738 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2739 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
AnnaBridge 167:e84263d55307 2740 #define CAN_FFA1R_FFA25_Pos (25U)
AnnaBridge 167:e84263d55307 2741 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2742 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
AnnaBridge 167:e84263d55307 2743 #define CAN_FFA1R_FFA26_Pos (26U)
AnnaBridge 167:e84263d55307 2744 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2745 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
AnnaBridge 167:e84263d55307 2746 #define CAN_FFA1R_FFA27_Pos (27U)
AnnaBridge 167:e84263d55307 2747 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2748 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
<> 144:ef7eb2e8f9f7 2749
<> 144:ef7eb2e8f9f7 2750 /******************* Bit definition for CAN_FA1R register *******************/
AnnaBridge 167:e84263d55307 2751 #define CAN_FA1R_FACT_Pos (0U)
AnnaBridge 167:e84263d55307 2752 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
AnnaBridge 167:e84263d55307 2753 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
AnnaBridge 167:e84263d55307 2754 #define CAN_FA1R_FACT0_Pos (0U)
AnnaBridge 167:e84263d55307 2755 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2756 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
AnnaBridge 167:e84263d55307 2757 #define CAN_FA1R_FACT1_Pos (1U)
AnnaBridge 167:e84263d55307 2758 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2759 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
AnnaBridge 167:e84263d55307 2760 #define CAN_FA1R_FACT2_Pos (2U)
AnnaBridge 167:e84263d55307 2761 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2762 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
AnnaBridge 167:e84263d55307 2763 #define CAN_FA1R_FACT3_Pos (3U)
AnnaBridge 167:e84263d55307 2764 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2765 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
AnnaBridge 167:e84263d55307 2766 #define CAN_FA1R_FACT4_Pos (4U)
AnnaBridge 167:e84263d55307 2767 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2768 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
AnnaBridge 167:e84263d55307 2769 #define CAN_FA1R_FACT5_Pos (5U)
AnnaBridge 167:e84263d55307 2770 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2771 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
AnnaBridge 167:e84263d55307 2772 #define CAN_FA1R_FACT6_Pos (6U)
AnnaBridge 167:e84263d55307 2773 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2774 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
AnnaBridge 167:e84263d55307 2775 #define CAN_FA1R_FACT7_Pos (7U)
AnnaBridge 167:e84263d55307 2776 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2777 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
AnnaBridge 167:e84263d55307 2778 #define CAN_FA1R_FACT8_Pos (8U)
AnnaBridge 167:e84263d55307 2779 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2780 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
AnnaBridge 167:e84263d55307 2781 #define CAN_FA1R_FACT9_Pos (9U)
AnnaBridge 167:e84263d55307 2782 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2783 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
AnnaBridge 167:e84263d55307 2784 #define CAN_FA1R_FACT10_Pos (10U)
AnnaBridge 167:e84263d55307 2785 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2786 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
AnnaBridge 167:e84263d55307 2787 #define CAN_FA1R_FACT11_Pos (11U)
AnnaBridge 167:e84263d55307 2788 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2789 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
AnnaBridge 167:e84263d55307 2790 #define CAN_FA1R_FACT12_Pos (12U)
AnnaBridge 167:e84263d55307 2791 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2792 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
AnnaBridge 167:e84263d55307 2793 #define CAN_FA1R_FACT13_Pos (13U)
AnnaBridge 167:e84263d55307 2794 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2795 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
AnnaBridge 167:e84263d55307 2796 #define CAN_FA1R_FACT14_Pos (14U)
AnnaBridge 167:e84263d55307 2797 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2798 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
AnnaBridge 167:e84263d55307 2799 #define CAN_FA1R_FACT15_Pos (15U)
AnnaBridge 167:e84263d55307 2800 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2801 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
AnnaBridge 167:e84263d55307 2802 #define CAN_FA1R_FACT16_Pos (16U)
AnnaBridge 167:e84263d55307 2803 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2804 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
AnnaBridge 167:e84263d55307 2805 #define CAN_FA1R_FACT17_Pos (17U)
AnnaBridge 167:e84263d55307 2806 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2807 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
AnnaBridge 167:e84263d55307 2808 #define CAN_FA1R_FACT18_Pos (18U)
AnnaBridge 167:e84263d55307 2809 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2810 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
AnnaBridge 167:e84263d55307 2811 #define CAN_FA1R_FACT19_Pos (19U)
AnnaBridge 167:e84263d55307 2812 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2813 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
AnnaBridge 167:e84263d55307 2814 #define CAN_FA1R_FACT20_Pos (20U)
AnnaBridge 167:e84263d55307 2815 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2816 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
AnnaBridge 167:e84263d55307 2817 #define CAN_FA1R_FACT21_Pos (21U)
AnnaBridge 167:e84263d55307 2818 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2819 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
AnnaBridge 167:e84263d55307 2820 #define CAN_FA1R_FACT22_Pos (22U)
AnnaBridge 167:e84263d55307 2821 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2822 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
AnnaBridge 167:e84263d55307 2823 #define CAN_FA1R_FACT23_Pos (23U)
AnnaBridge 167:e84263d55307 2824 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2825 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
AnnaBridge 167:e84263d55307 2826 #define CAN_FA1R_FACT24_Pos (24U)
AnnaBridge 167:e84263d55307 2827 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2828 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
AnnaBridge 167:e84263d55307 2829 #define CAN_FA1R_FACT25_Pos (25U)
AnnaBridge 167:e84263d55307 2830 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2831 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
AnnaBridge 167:e84263d55307 2832 #define CAN_FA1R_FACT26_Pos (26U)
AnnaBridge 167:e84263d55307 2833 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2834 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
AnnaBridge 167:e84263d55307 2835 #define CAN_FA1R_FACT27_Pos (27U)
AnnaBridge 167:e84263d55307 2836 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2837 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
AnnaBridge 167:e84263d55307 2838
<> 144:ef7eb2e8f9f7 2839
<> 144:ef7eb2e8f9f7 2840 /******************* Bit definition for CAN_F0R1 register *******************/
AnnaBridge 167:e84263d55307 2841 #define CAN_F0R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 2842 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2843 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 2844 #define CAN_F0R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 2845 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2846 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 2847 #define CAN_F0R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 2848 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2849 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 2850 #define CAN_F0R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 2851 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2852 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 2853 #define CAN_F0R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 2854 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2855 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 2856 #define CAN_F0R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 2857 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2858 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 2859 #define CAN_F0R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 2860 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2861 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 2862 #define CAN_F0R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 2863 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2864 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 2865 #define CAN_F0R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 2866 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2867 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 2868 #define CAN_F0R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 2869 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2870 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 2871 #define CAN_F0R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 2872 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2873 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 2874 #define CAN_F0R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 2875 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2876 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 2877 #define CAN_F0R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 2878 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2879 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 2880 #define CAN_F0R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 2881 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2882 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 2883 #define CAN_F0R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 2884 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2885 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 2886 #define CAN_F0R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 2887 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2888 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 2889 #define CAN_F0R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 2890 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2891 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 2892 #define CAN_F0R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 2893 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2894 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 2895 #define CAN_F0R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 2896 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2897 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 2898 #define CAN_F0R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 2899 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2900 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 2901 #define CAN_F0R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 2902 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 2903 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 2904 #define CAN_F0R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 2905 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 2906 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 2907 #define CAN_F0R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 2908 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 2909 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 2910 #define CAN_F0R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 2911 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 2912 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 2913 #define CAN_F0R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 2914 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 2915 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 2916 #define CAN_F0R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 2917 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 2918 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 2919 #define CAN_F0R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 2920 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 2921 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 2922 #define CAN_F0R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 2923 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 2924 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 2925 #define CAN_F0R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 2926 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 2927 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 2928 #define CAN_F0R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 2929 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 2930 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 2931 #define CAN_F0R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 2932 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 2933 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 2934 #define CAN_F0R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 2935 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 2936 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 2937
<> 144:ef7eb2e8f9f7 2938 /******************* Bit definition for CAN_F1R1 register *******************/
AnnaBridge 167:e84263d55307 2939 #define CAN_F1R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 2940 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 2941 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 2942 #define CAN_F1R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 2943 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 2944 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 2945 #define CAN_F1R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 2946 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 2947 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 2948 #define CAN_F1R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 2949 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 2950 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 2951 #define CAN_F1R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 2952 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 2953 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 2954 #define CAN_F1R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 2955 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 2956 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 2957 #define CAN_F1R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 2958 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 2959 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 2960 #define CAN_F1R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 2961 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 2962 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 2963 #define CAN_F1R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 2964 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 2965 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 2966 #define CAN_F1R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 2967 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 2968 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 2969 #define CAN_F1R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 2970 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 2971 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 2972 #define CAN_F1R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 2973 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 2974 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 2975 #define CAN_F1R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 2976 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 2977 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 2978 #define CAN_F1R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 2979 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 2980 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 2981 #define CAN_F1R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 2982 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 2983 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 2984 #define CAN_F1R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 2985 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 2986 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 2987 #define CAN_F1R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 2988 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 2989 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 2990 #define CAN_F1R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 2991 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 2992 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 2993 #define CAN_F1R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 2994 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 2995 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 2996 #define CAN_F1R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 2997 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 2998 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 2999 #define CAN_F1R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3000 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3001 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3002 #define CAN_F1R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3003 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3004 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3005 #define CAN_F1R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3006 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3007 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3008 #define CAN_F1R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3009 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3010 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3011 #define CAN_F1R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3012 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3013 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3014 #define CAN_F1R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3015 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3016 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3017 #define CAN_F1R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3018 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3019 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3020 #define CAN_F1R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3021 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3022 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3023 #define CAN_F1R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3024 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3025 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3026 #define CAN_F1R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3027 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3028 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3029 #define CAN_F1R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3030 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3031 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3032 #define CAN_F1R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3033 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3034 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3035
<> 144:ef7eb2e8f9f7 3036 /******************* Bit definition for CAN_F2R1 register *******************/
AnnaBridge 167:e84263d55307 3037 #define CAN_F2R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3038 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3039 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3040 #define CAN_F2R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3041 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3042 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3043 #define CAN_F2R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3044 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3045 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3046 #define CAN_F2R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3047 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3048 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3049 #define CAN_F2R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3050 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3051 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3052 #define CAN_F2R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3053 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3054 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3055 #define CAN_F2R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3056 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3057 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3058 #define CAN_F2R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3059 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3060 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3061 #define CAN_F2R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3062 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3063 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3064 #define CAN_F2R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3065 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3066 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3067 #define CAN_F2R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3068 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3069 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3070 #define CAN_F2R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3071 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3072 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3073 #define CAN_F2R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3074 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3075 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3076 #define CAN_F2R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3077 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3078 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3079 #define CAN_F2R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3080 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3081 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3082 #define CAN_F2R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3083 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3084 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3085 #define CAN_F2R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3086 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3087 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3088 #define CAN_F2R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3089 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3090 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3091 #define CAN_F2R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3092 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3093 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3094 #define CAN_F2R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3095 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3096 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3097 #define CAN_F2R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3098 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3099 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3100 #define CAN_F2R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3101 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3102 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3103 #define CAN_F2R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3104 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3105 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3106 #define CAN_F2R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3107 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3108 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3109 #define CAN_F2R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3110 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3111 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3112 #define CAN_F2R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3113 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3114 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3115 #define CAN_F2R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3116 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3117 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3118 #define CAN_F2R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3119 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3120 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3121 #define CAN_F2R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3122 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3123 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3124 #define CAN_F2R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3125 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3126 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3127 #define CAN_F2R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3128 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3129 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3130 #define CAN_F2R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3131 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3132 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3133
<> 144:ef7eb2e8f9f7 3134 /******************* Bit definition for CAN_F3R1 register *******************/
AnnaBridge 167:e84263d55307 3135 #define CAN_F3R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3136 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3137 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3138 #define CAN_F3R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3139 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3140 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3141 #define CAN_F3R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3142 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3143 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3144 #define CAN_F3R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3145 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3146 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3147 #define CAN_F3R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3148 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3149 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3150 #define CAN_F3R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3151 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3152 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3153 #define CAN_F3R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3154 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3155 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3156 #define CAN_F3R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3157 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3158 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3159 #define CAN_F3R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3160 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3161 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3162 #define CAN_F3R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3163 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3164 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3165 #define CAN_F3R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3166 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3167 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3168 #define CAN_F3R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3169 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3170 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3171 #define CAN_F3R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3172 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3173 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3174 #define CAN_F3R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3175 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3176 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3177 #define CAN_F3R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3178 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3179 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3180 #define CAN_F3R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3181 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3182 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3183 #define CAN_F3R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3184 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3185 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3186 #define CAN_F3R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3187 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3188 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3189 #define CAN_F3R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3190 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3191 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3192 #define CAN_F3R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3193 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3194 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3195 #define CAN_F3R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3196 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3197 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3198 #define CAN_F3R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3199 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3200 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3201 #define CAN_F3R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3202 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3203 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3204 #define CAN_F3R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3205 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3206 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3207 #define CAN_F3R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3208 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3209 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3210 #define CAN_F3R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3211 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3212 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3213 #define CAN_F3R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3214 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3215 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3216 #define CAN_F3R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3217 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3218 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3219 #define CAN_F3R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3220 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3221 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3222 #define CAN_F3R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3223 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3224 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3225 #define CAN_F3R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3226 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3227 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3228 #define CAN_F3R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3229 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3230 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3231
<> 144:ef7eb2e8f9f7 3232 /******************* Bit definition for CAN_F4R1 register *******************/
AnnaBridge 167:e84263d55307 3233 #define CAN_F4R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3234 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3235 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3236 #define CAN_F4R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3237 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3238 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3239 #define CAN_F4R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3240 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3241 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3242 #define CAN_F4R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3243 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3244 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3245 #define CAN_F4R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3246 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3247 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3248 #define CAN_F4R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3249 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3250 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3251 #define CAN_F4R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3252 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3253 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3254 #define CAN_F4R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3255 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3256 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3257 #define CAN_F4R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3258 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3259 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3260 #define CAN_F4R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3261 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3262 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3263 #define CAN_F4R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3264 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3265 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3266 #define CAN_F4R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3267 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3268 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3269 #define CAN_F4R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3270 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3271 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3272 #define CAN_F4R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3273 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3274 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3275 #define CAN_F4R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3276 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3277 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3278 #define CAN_F4R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3279 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3280 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3281 #define CAN_F4R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3282 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3283 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3284 #define CAN_F4R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3285 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3286 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3287 #define CAN_F4R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3288 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3289 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3290 #define CAN_F4R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3291 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3292 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3293 #define CAN_F4R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3294 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3295 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3296 #define CAN_F4R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3297 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3298 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3299 #define CAN_F4R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3300 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3301 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3302 #define CAN_F4R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3303 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3304 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3305 #define CAN_F4R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3306 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3307 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3308 #define CAN_F4R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3309 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3310 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3311 #define CAN_F4R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3312 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3313 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3314 #define CAN_F4R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3315 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3316 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3317 #define CAN_F4R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3318 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3319 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3320 #define CAN_F4R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3321 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3322 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3323 #define CAN_F4R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3324 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3325 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3326 #define CAN_F4R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3327 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3328 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3329
<> 144:ef7eb2e8f9f7 3330 /******************* Bit definition for CAN_F5R1 register *******************/
AnnaBridge 167:e84263d55307 3331 #define CAN_F5R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3332 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3333 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3334 #define CAN_F5R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3335 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3336 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3337 #define CAN_F5R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3338 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3339 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3340 #define CAN_F5R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3341 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3342 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3343 #define CAN_F5R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3344 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3345 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3346 #define CAN_F5R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3347 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3348 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3349 #define CAN_F5R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3350 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3351 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3352 #define CAN_F5R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3353 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3354 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3355 #define CAN_F5R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3356 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3357 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3358 #define CAN_F5R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3359 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3360 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3361 #define CAN_F5R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3362 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3363 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3364 #define CAN_F5R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3365 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3366 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3367 #define CAN_F5R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3368 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3369 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3370 #define CAN_F5R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3371 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3372 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3373 #define CAN_F5R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3374 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3375 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3376 #define CAN_F5R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3377 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3378 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3379 #define CAN_F5R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3380 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3381 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3382 #define CAN_F5R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3383 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3384 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3385 #define CAN_F5R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3386 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3387 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3388 #define CAN_F5R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3389 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3390 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3391 #define CAN_F5R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3392 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3393 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3394 #define CAN_F5R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3395 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3396 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3397 #define CAN_F5R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3398 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3399 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3400 #define CAN_F5R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3401 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3402 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3403 #define CAN_F5R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3404 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3405 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3406 #define CAN_F5R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3407 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3408 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3409 #define CAN_F5R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3410 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3411 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3412 #define CAN_F5R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3413 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3414 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3415 #define CAN_F5R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3416 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3417 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3418 #define CAN_F5R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3419 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3420 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3421 #define CAN_F5R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3422 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3423 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3424 #define CAN_F5R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3425 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3426 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3427
<> 144:ef7eb2e8f9f7 3428 /******************* Bit definition for CAN_F6R1 register *******************/
AnnaBridge 167:e84263d55307 3429 #define CAN_F6R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3430 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3431 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3432 #define CAN_F6R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3433 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3434 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3435 #define CAN_F6R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3436 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3437 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3438 #define CAN_F6R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3439 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3440 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3441 #define CAN_F6R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3442 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3443 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3444 #define CAN_F6R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3445 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3446 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3447 #define CAN_F6R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3448 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3449 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3450 #define CAN_F6R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3451 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3452 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3453 #define CAN_F6R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3454 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3455 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3456 #define CAN_F6R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3457 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3458 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3459 #define CAN_F6R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3460 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3461 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3462 #define CAN_F6R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3463 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3464 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3465 #define CAN_F6R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3466 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3467 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3468 #define CAN_F6R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3469 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3470 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3471 #define CAN_F6R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3472 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3473 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3474 #define CAN_F6R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3475 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3476 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3477 #define CAN_F6R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3478 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3479 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3480 #define CAN_F6R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3481 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3482 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3483 #define CAN_F6R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3484 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3485 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3486 #define CAN_F6R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3487 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3488 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3489 #define CAN_F6R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3490 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3491 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3492 #define CAN_F6R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3493 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3494 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3495 #define CAN_F6R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3496 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3497 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3498 #define CAN_F6R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3499 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3500 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3501 #define CAN_F6R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3502 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3503 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3504 #define CAN_F6R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3505 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3506 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3507 #define CAN_F6R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3508 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3509 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3510 #define CAN_F6R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3511 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3512 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3513 #define CAN_F6R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3514 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3515 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3516 #define CAN_F6R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3517 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3518 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3519 #define CAN_F6R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3520 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3521 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3522 #define CAN_F6R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3523 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3524 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3525
<> 144:ef7eb2e8f9f7 3526 /******************* Bit definition for CAN_F7R1 register *******************/
AnnaBridge 167:e84263d55307 3527 #define CAN_F7R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3528 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3529 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3530 #define CAN_F7R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3531 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3532 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3533 #define CAN_F7R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3534 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3535 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3536 #define CAN_F7R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3537 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3538 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3539 #define CAN_F7R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3540 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3541 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3542 #define CAN_F7R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3543 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3544 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3545 #define CAN_F7R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3546 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3547 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3548 #define CAN_F7R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3549 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3550 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3551 #define CAN_F7R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3552 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3553 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3554 #define CAN_F7R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3555 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3556 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3557 #define CAN_F7R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3558 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3559 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3560 #define CAN_F7R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3561 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3562 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3563 #define CAN_F7R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3564 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3565 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3566 #define CAN_F7R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3567 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3568 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3569 #define CAN_F7R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3570 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3571 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3572 #define CAN_F7R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3573 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3574 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3575 #define CAN_F7R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3576 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3577 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3578 #define CAN_F7R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3579 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3580 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3581 #define CAN_F7R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3582 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3583 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3584 #define CAN_F7R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3585 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3586 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3587 #define CAN_F7R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3588 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3589 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3590 #define CAN_F7R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3591 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3592 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3593 #define CAN_F7R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3594 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3595 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3596 #define CAN_F7R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3597 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3598 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3599 #define CAN_F7R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3600 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3601 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3602 #define CAN_F7R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3603 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3604 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3605 #define CAN_F7R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3606 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3607 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3608 #define CAN_F7R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3609 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3610 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3611 #define CAN_F7R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3612 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3613 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3614 #define CAN_F7R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3615 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3616 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3617 #define CAN_F7R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3618 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3619 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3620 #define CAN_F7R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3621 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3622 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3623
<> 144:ef7eb2e8f9f7 3624 /******************* Bit definition for CAN_F8R1 register *******************/
AnnaBridge 167:e84263d55307 3625 #define CAN_F8R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3626 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3627 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3628 #define CAN_F8R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3629 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3630 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3631 #define CAN_F8R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3632 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3633 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3634 #define CAN_F8R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3635 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3636 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3637 #define CAN_F8R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3638 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3639 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3640 #define CAN_F8R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3641 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3642 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3643 #define CAN_F8R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3644 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3645 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3646 #define CAN_F8R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3647 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3648 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3649 #define CAN_F8R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3650 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3651 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3652 #define CAN_F8R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3653 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3654 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3655 #define CAN_F8R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3656 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3657 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3658 #define CAN_F8R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3659 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3660 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3661 #define CAN_F8R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3662 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3663 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3664 #define CAN_F8R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3665 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3666 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3667 #define CAN_F8R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3668 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3669 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3670 #define CAN_F8R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3671 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3672 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3673 #define CAN_F8R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3674 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3675 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3676 #define CAN_F8R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3677 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3678 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3679 #define CAN_F8R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3680 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3681 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3682 #define CAN_F8R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3683 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3684 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3685 #define CAN_F8R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3686 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3687 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3688 #define CAN_F8R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3689 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3690 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3691 #define CAN_F8R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3692 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3693 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3694 #define CAN_F8R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3695 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3696 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3697 #define CAN_F8R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3698 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3699 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3700 #define CAN_F8R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3701 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3702 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3703 #define CAN_F8R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3704 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3705 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3706 #define CAN_F8R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3707 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3708 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3709 #define CAN_F8R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3710 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3711 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3712 #define CAN_F8R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3713 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3714 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3715 #define CAN_F8R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3716 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3717 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3718 #define CAN_F8R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3719 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3720 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3721
<> 144:ef7eb2e8f9f7 3722 /******************* Bit definition for CAN_F9R1 register *******************/
AnnaBridge 167:e84263d55307 3723 #define CAN_F9R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3724 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3725 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3726 #define CAN_F9R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3727 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3728 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3729 #define CAN_F9R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3730 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3731 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3732 #define CAN_F9R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3733 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3734 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3735 #define CAN_F9R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3736 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3737 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3738 #define CAN_F9R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3739 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3740 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3741 #define CAN_F9R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3742 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3743 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3744 #define CAN_F9R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3745 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3746 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3747 #define CAN_F9R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3748 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3749 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3750 #define CAN_F9R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3751 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3752 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3753 #define CAN_F9R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3754 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3755 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3756 #define CAN_F9R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3757 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3758 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3759 #define CAN_F9R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3760 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3761 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3762 #define CAN_F9R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3763 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3764 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3765 #define CAN_F9R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3766 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3767 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3768 #define CAN_F9R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3769 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3770 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3771 #define CAN_F9R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3772 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3773 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3774 #define CAN_F9R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3775 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3776 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3777 #define CAN_F9R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3778 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3779 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3780 #define CAN_F9R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3781 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3782 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3783 #define CAN_F9R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3784 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3785 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3786 #define CAN_F9R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3787 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3788 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3789 #define CAN_F9R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3790 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3791 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3792 #define CAN_F9R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3793 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3794 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3795 #define CAN_F9R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3796 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3797 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3798 #define CAN_F9R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3799 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3800 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3801 #define CAN_F9R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3802 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3803 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3804 #define CAN_F9R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3805 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3806 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3807 #define CAN_F9R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3808 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3809 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3810 #define CAN_F9R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3811 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3812 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3813 #define CAN_F9R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3814 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3815 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3816 #define CAN_F9R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3817 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3818 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3819
<> 144:ef7eb2e8f9f7 3820 /******************* Bit definition for CAN_F10R1 register ******************/
AnnaBridge 167:e84263d55307 3821 #define CAN_F10R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3822 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3823 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3824 #define CAN_F10R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3825 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3826 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3827 #define CAN_F10R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3828 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3829 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3830 #define CAN_F10R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3831 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3832 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3833 #define CAN_F10R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3834 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3835 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3836 #define CAN_F10R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3837 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3838 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3839 #define CAN_F10R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3840 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3841 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3842 #define CAN_F10R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3843 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3844 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3845 #define CAN_F10R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3846 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3847 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3848 #define CAN_F10R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3849 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3850 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3851 #define CAN_F10R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3852 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3853 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3854 #define CAN_F10R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3855 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3856 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3857 #define CAN_F10R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3858 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3859 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3860 #define CAN_F10R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3861 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3862 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3863 #define CAN_F10R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3864 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3865 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3866 #define CAN_F10R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3867 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3868 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3869 #define CAN_F10R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3870 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3871 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3872 #define CAN_F10R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3873 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3874 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3875 #define CAN_F10R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3876 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3877 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3878 #define CAN_F10R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3879 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3880 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3881 #define CAN_F10R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3882 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3883 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3884 #define CAN_F10R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3885 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3886 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3887 #define CAN_F10R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3888 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3889 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3890 #define CAN_F10R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3891 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3892 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3893 #define CAN_F10R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3894 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3895 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3896 #define CAN_F10R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3897 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3898 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3899 #define CAN_F10R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3900 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3901 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 3902 #define CAN_F10R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 3903 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 3904 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 3905 #define CAN_F10R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 3906 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 3907 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 3908 #define CAN_F10R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 3909 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 3910 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 3911 #define CAN_F10R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 3912 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 3913 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 3914 #define CAN_F10R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 3915 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 3916 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 3917
<> 144:ef7eb2e8f9f7 3918 /******************* Bit definition for CAN_F11R1 register ******************/
AnnaBridge 167:e84263d55307 3919 #define CAN_F11R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 3920 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 3921 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 3922 #define CAN_F11R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 3923 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 3924 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 3925 #define CAN_F11R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 3926 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 3927 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 3928 #define CAN_F11R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 3929 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 3930 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 3931 #define CAN_F11R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 3932 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 3933 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 3934 #define CAN_F11R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 3935 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 3936 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 3937 #define CAN_F11R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 3938 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 3939 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 3940 #define CAN_F11R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 3941 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 3942 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 3943 #define CAN_F11R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 3944 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 3945 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 3946 #define CAN_F11R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 3947 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 3948 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 3949 #define CAN_F11R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 3950 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 3951 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 3952 #define CAN_F11R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 3953 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 3954 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 3955 #define CAN_F11R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 3956 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 3957 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 3958 #define CAN_F11R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 3959 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 3960 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 3961 #define CAN_F11R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 3962 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 3963 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 3964 #define CAN_F11R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 3965 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 3966 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 3967 #define CAN_F11R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 3968 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 3969 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 3970 #define CAN_F11R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 3971 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 3972 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 3973 #define CAN_F11R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 3974 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 3975 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 3976 #define CAN_F11R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 3977 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 3978 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 3979 #define CAN_F11R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 3980 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 3981 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 3982 #define CAN_F11R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 3983 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 3984 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 3985 #define CAN_F11R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 3986 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 3987 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 3988 #define CAN_F11R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 3989 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 3990 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 3991 #define CAN_F11R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 3992 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 3993 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 3994 #define CAN_F11R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 3995 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 3996 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 3997 #define CAN_F11R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 3998 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 3999 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4000 #define CAN_F11R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4001 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4002 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4003 #define CAN_F11R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4004 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4005 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4006 #define CAN_F11R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4007 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4008 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4009 #define CAN_F11R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4010 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4011 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4012 #define CAN_F11R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4013 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4014 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4015
<> 144:ef7eb2e8f9f7 4016 /******************* Bit definition for CAN_F12R1 register ******************/
AnnaBridge 167:e84263d55307 4017 #define CAN_F12R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4018 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4019 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4020 #define CAN_F12R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4021 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4022 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4023 #define CAN_F12R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4024 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4025 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4026 #define CAN_F12R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4027 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4028 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4029 #define CAN_F12R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4030 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4031 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4032 #define CAN_F12R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4033 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4034 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4035 #define CAN_F12R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4036 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4037 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4038 #define CAN_F12R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4039 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4040 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4041 #define CAN_F12R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4042 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4043 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4044 #define CAN_F12R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4045 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4046 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4047 #define CAN_F12R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4048 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4049 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4050 #define CAN_F12R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4051 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4052 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4053 #define CAN_F12R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4054 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4055 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4056 #define CAN_F12R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4057 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4058 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4059 #define CAN_F12R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4060 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4061 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4062 #define CAN_F12R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4063 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4064 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4065 #define CAN_F12R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4066 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4067 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4068 #define CAN_F12R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4069 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4070 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4071 #define CAN_F12R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4072 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4073 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4074 #define CAN_F12R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4075 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4076 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4077 #define CAN_F12R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4078 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4079 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4080 #define CAN_F12R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4081 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4082 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4083 #define CAN_F12R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4084 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4085 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4086 #define CAN_F12R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4087 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4088 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4089 #define CAN_F12R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4090 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4091 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4092 #define CAN_F12R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4093 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4094 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4095 #define CAN_F12R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4096 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4097 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4098 #define CAN_F12R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4099 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4100 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4101 #define CAN_F12R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4102 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4103 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4104 #define CAN_F12R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4105 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4106 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4107 #define CAN_F12R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4108 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4109 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4110 #define CAN_F12R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4111 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4112 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4113
<> 144:ef7eb2e8f9f7 4114 /******************* Bit definition for CAN_F13R1 register ******************/
AnnaBridge 167:e84263d55307 4115 #define CAN_F13R1_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4116 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4117 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4118 #define CAN_F13R1_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4119 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4120 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4121 #define CAN_F13R1_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4122 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4123 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4124 #define CAN_F13R1_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4125 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4126 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4127 #define CAN_F13R1_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4128 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4129 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4130 #define CAN_F13R1_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4131 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4132 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4133 #define CAN_F13R1_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4134 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4135 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4136 #define CAN_F13R1_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4137 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4138 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4139 #define CAN_F13R1_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4140 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4141 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4142 #define CAN_F13R1_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4143 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4144 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4145 #define CAN_F13R1_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4146 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4147 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4148 #define CAN_F13R1_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4149 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4150 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4151 #define CAN_F13R1_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4152 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4153 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4154 #define CAN_F13R1_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4155 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4156 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4157 #define CAN_F13R1_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4158 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4159 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4160 #define CAN_F13R1_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4161 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4162 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4163 #define CAN_F13R1_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4164 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4165 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4166 #define CAN_F13R1_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4167 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4168 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4169 #define CAN_F13R1_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4170 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4171 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4172 #define CAN_F13R1_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4173 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4174 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4175 #define CAN_F13R1_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4176 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4177 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4178 #define CAN_F13R1_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4179 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4180 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4181 #define CAN_F13R1_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4182 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4183 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4184 #define CAN_F13R1_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4185 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4186 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4187 #define CAN_F13R1_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4188 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4189 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4190 #define CAN_F13R1_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4191 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4192 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4193 #define CAN_F13R1_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4194 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4195 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4196 #define CAN_F13R1_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4197 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4198 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4199 #define CAN_F13R1_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4200 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4201 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4202 #define CAN_F13R1_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4203 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4204 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4205 #define CAN_F13R1_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4206 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4207 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4208 #define CAN_F13R1_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4209 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4210 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4211
<> 144:ef7eb2e8f9f7 4212 /******************* Bit definition for CAN_F0R2 register *******************/
AnnaBridge 167:e84263d55307 4213 #define CAN_F0R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4214 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4215 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4216 #define CAN_F0R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4217 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4218 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4219 #define CAN_F0R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4220 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4221 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4222 #define CAN_F0R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4223 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4224 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4225 #define CAN_F0R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4226 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4227 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4228 #define CAN_F0R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4229 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4230 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4231 #define CAN_F0R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4232 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4233 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4234 #define CAN_F0R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4235 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4236 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4237 #define CAN_F0R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4238 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4239 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4240 #define CAN_F0R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4241 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4242 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4243 #define CAN_F0R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4244 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4245 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4246 #define CAN_F0R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4247 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4248 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4249 #define CAN_F0R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4250 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4251 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4252 #define CAN_F0R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4253 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4254 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4255 #define CAN_F0R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4256 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4257 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4258 #define CAN_F0R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4259 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4260 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4261 #define CAN_F0R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4262 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4263 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4264 #define CAN_F0R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4265 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4266 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4267 #define CAN_F0R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4268 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4269 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4270 #define CAN_F0R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4271 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4272 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4273 #define CAN_F0R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4274 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4275 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4276 #define CAN_F0R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4277 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4278 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4279 #define CAN_F0R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4280 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4281 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4282 #define CAN_F0R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4283 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4284 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4285 #define CAN_F0R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4286 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4287 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4288 #define CAN_F0R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4289 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4290 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4291 #define CAN_F0R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4292 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4293 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4294 #define CAN_F0R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4295 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4296 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4297 #define CAN_F0R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4298 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4299 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4300 #define CAN_F0R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4301 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4302 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4303 #define CAN_F0R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4304 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4305 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4306 #define CAN_F0R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4307 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4308 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4309
<> 144:ef7eb2e8f9f7 4310 /******************* Bit definition for CAN_F1R2 register *******************/
AnnaBridge 167:e84263d55307 4311 #define CAN_F1R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4312 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4313 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4314 #define CAN_F1R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4315 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4316 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4317 #define CAN_F1R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4318 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4319 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4320 #define CAN_F1R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4321 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4322 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4323 #define CAN_F1R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4324 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4325 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4326 #define CAN_F1R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4327 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4328 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4329 #define CAN_F1R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4330 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4331 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4332 #define CAN_F1R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4333 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4334 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4335 #define CAN_F1R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4336 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4337 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4338 #define CAN_F1R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4339 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4340 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4341 #define CAN_F1R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4342 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4343 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4344 #define CAN_F1R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4345 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4346 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4347 #define CAN_F1R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4348 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4349 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4350 #define CAN_F1R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4351 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4352 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4353 #define CAN_F1R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4354 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4355 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4356 #define CAN_F1R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4357 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4358 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4359 #define CAN_F1R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4360 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4361 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4362 #define CAN_F1R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4363 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4364 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4365 #define CAN_F1R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4366 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4367 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4368 #define CAN_F1R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4369 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4370 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4371 #define CAN_F1R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4372 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4373 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4374 #define CAN_F1R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4375 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4376 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4377 #define CAN_F1R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4378 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4379 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4380 #define CAN_F1R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4381 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4382 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4383 #define CAN_F1R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4384 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4385 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4386 #define CAN_F1R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4387 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4388 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4389 #define CAN_F1R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4390 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4391 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4392 #define CAN_F1R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4393 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4394 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4395 #define CAN_F1R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4396 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4397 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4398 #define CAN_F1R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4399 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4400 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4401 #define CAN_F1R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4402 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4403 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4404 #define CAN_F1R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4405 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4406 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4407
<> 144:ef7eb2e8f9f7 4408 /******************* Bit definition for CAN_F2R2 register *******************/
AnnaBridge 167:e84263d55307 4409 #define CAN_F2R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4410 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4411 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4412 #define CAN_F2R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4413 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4414 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4415 #define CAN_F2R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4416 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4417 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4418 #define CAN_F2R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4419 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4420 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4421 #define CAN_F2R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4422 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4423 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4424 #define CAN_F2R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4425 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4426 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4427 #define CAN_F2R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4428 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4429 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4430 #define CAN_F2R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4431 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4432 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4433 #define CAN_F2R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4434 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4435 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4436 #define CAN_F2R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4437 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4438 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4439 #define CAN_F2R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4440 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4441 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4442 #define CAN_F2R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4443 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4444 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4445 #define CAN_F2R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4446 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4447 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4448 #define CAN_F2R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4449 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4450 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4451 #define CAN_F2R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4452 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4453 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4454 #define CAN_F2R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4455 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4456 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4457 #define CAN_F2R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4458 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4459 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4460 #define CAN_F2R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4461 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4462 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4463 #define CAN_F2R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4464 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4465 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4466 #define CAN_F2R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4467 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4468 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4469 #define CAN_F2R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4470 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4471 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4472 #define CAN_F2R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4473 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4474 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4475 #define CAN_F2R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4476 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4477 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4478 #define CAN_F2R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4479 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4480 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4481 #define CAN_F2R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4482 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4483 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4484 #define CAN_F2R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4485 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4486 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4487 #define CAN_F2R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4488 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4489 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4490 #define CAN_F2R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4491 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4492 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4493 #define CAN_F2R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4494 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4495 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4496 #define CAN_F2R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4497 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4498 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4499 #define CAN_F2R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4500 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4501 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4502 #define CAN_F2R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4503 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4504 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4505
<> 144:ef7eb2e8f9f7 4506 /******************* Bit definition for CAN_F3R2 register *******************/
AnnaBridge 167:e84263d55307 4507 #define CAN_F3R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4508 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4509 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4510 #define CAN_F3R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4511 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4512 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4513 #define CAN_F3R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4514 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4515 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4516 #define CAN_F3R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4517 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4518 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4519 #define CAN_F3R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4520 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4521 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4522 #define CAN_F3R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4523 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4524 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4525 #define CAN_F3R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4526 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4527 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4528 #define CAN_F3R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4529 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4530 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4531 #define CAN_F3R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4532 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4533 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4534 #define CAN_F3R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4535 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4536 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4537 #define CAN_F3R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4538 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4539 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4540 #define CAN_F3R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4541 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4542 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4543 #define CAN_F3R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4544 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4545 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4546 #define CAN_F3R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4547 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4548 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4549 #define CAN_F3R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4550 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4551 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4552 #define CAN_F3R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4553 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4554 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4555 #define CAN_F3R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4556 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4557 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4558 #define CAN_F3R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4559 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4560 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4561 #define CAN_F3R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4562 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4563 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4564 #define CAN_F3R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4565 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4566 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4567 #define CAN_F3R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4568 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4569 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4570 #define CAN_F3R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4571 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4572 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4573 #define CAN_F3R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4574 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4575 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4576 #define CAN_F3R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4577 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4578 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4579 #define CAN_F3R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4580 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4581 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4582 #define CAN_F3R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4583 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4584 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4585 #define CAN_F3R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4586 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4587 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4588 #define CAN_F3R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4589 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4590 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4591 #define CAN_F3R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4592 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4593 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4594 #define CAN_F3R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4595 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4596 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4597 #define CAN_F3R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4598 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4599 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4600 #define CAN_F3R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4601 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4602 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4603
<> 144:ef7eb2e8f9f7 4604 /******************* Bit definition for CAN_F4R2 register *******************/
AnnaBridge 167:e84263d55307 4605 #define CAN_F4R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4606 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4607 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4608 #define CAN_F4R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4609 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4610 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4611 #define CAN_F4R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4612 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4613 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4614 #define CAN_F4R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4615 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4616 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4617 #define CAN_F4R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4618 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4619 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4620 #define CAN_F4R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4621 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4622 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4623 #define CAN_F4R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4624 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4625 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4626 #define CAN_F4R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4627 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4628 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4629 #define CAN_F4R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4630 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4631 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4632 #define CAN_F4R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4633 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4634 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4635 #define CAN_F4R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4636 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4637 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4638 #define CAN_F4R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4639 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4640 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4641 #define CAN_F4R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4642 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4643 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4644 #define CAN_F4R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4645 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4646 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4647 #define CAN_F4R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4648 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4649 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4650 #define CAN_F4R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4651 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4652 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4653 #define CAN_F4R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4654 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4655 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4656 #define CAN_F4R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4657 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4658 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4659 #define CAN_F4R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4660 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4661 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4662 #define CAN_F4R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4663 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4664 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4665 #define CAN_F4R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4666 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4667 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4668 #define CAN_F4R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4669 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4670 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4671 #define CAN_F4R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4672 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4673 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4674 #define CAN_F4R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4675 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4676 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4677 #define CAN_F4R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4678 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4679 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4680 #define CAN_F4R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4681 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4682 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4683 #define CAN_F4R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4684 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4685 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4686 #define CAN_F4R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4687 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4688 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4689 #define CAN_F4R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4690 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4691 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4692 #define CAN_F4R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4693 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4694 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4695 #define CAN_F4R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4696 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4697 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4698 #define CAN_F4R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4699 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4700 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4701
<> 144:ef7eb2e8f9f7 4702 /******************* Bit definition for CAN_F5R2 register *******************/
AnnaBridge 167:e84263d55307 4703 #define CAN_F5R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4704 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4705 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4706 #define CAN_F5R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4707 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4708 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4709 #define CAN_F5R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4710 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4711 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4712 #define CAN_F5R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4713 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4714 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4715 #define CAN_F5R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4716 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4717 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4718 #define CAN_F5R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4719 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4720 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4721 #define CAN_F5R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4722 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4723 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4724 #define CAN_F5R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4725 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4726 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4727 #define CAN_F5R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4728 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4729 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4730 #define CAN_F5R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4731 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4732 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4733 #define CAN_F5R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4734 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4735 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4736 #define CAN_F5R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4737 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4738 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4739 #define CAN_F5R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4740 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4741 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4742 #define CAN_F5R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4743 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4744 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4745 #define CAN_F5R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4746 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4747 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4748 #define CAN_F5R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4749 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4750 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4751 #define CAN_F5R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4752 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4753 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4754 #define CAN_F5R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4755 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4756 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4757 #define CAN_F5R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4758 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4759 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4760 #define CAN_F5R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4761 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4762 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4763 #define CAN_F5R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4764 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4765 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4766 #define CAN_F5R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4767 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4768 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4769 #define CAN_F5R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4770 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4771 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4772 #define CAN_F5R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4773 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4774 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4775 #define CAN_F5R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4776 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4777 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4778 #define CAN_F5R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4779 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4780 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4781 #define CAN_F5R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4782 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4783 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4784 #define CAN_F5R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4785 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4786 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4787 #define CAN_F5R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4788 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4789 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4790 #define CAN_F5R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4791 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4792 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4793 #define CAN_F5R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4794 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4795 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4796 #define CAN_F5R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4797 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4798 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4799
<> 144:ef7eb2e8f9f7 4800 /******************* Bit definition for CAN_F6R2 register *******************/
AnnaBridge 167:e84263d55307 4801 #define CAN_F6R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4802 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4803 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4804 #define CAN_F6R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4805 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4806 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4807 #define CAN_F6R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4808 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4809 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4810 #define CAN_F6R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4811 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4812 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4813 #define CAN_F6R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4814 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4815 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4816 #define CAN_F6R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4817 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4818 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4819 #define CAN_F6R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4820 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4821 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4822 #define CAN_F6R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4823 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4824 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4825 #define CAN_F6R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4826 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4827 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4828 #define CAN_F6R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4829 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4830 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4831 #define CAN_F6R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4832 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4833 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4834 #define CAN_F6R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4835 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4836 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4837 #define CAN_F6R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4838 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4839 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4840 #define CAN_F6R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4841 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4842 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4843 #define CAN_F6R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4844 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4845 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4846 #define CAN_F6R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4847 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4848 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4849 #define CAN_F6R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4850 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4851 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4852 #define CAN_F6R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4853 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4854 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4855 #define CAN_F6R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4856 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4857 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4858 #define CAN_F6R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4859 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4860 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4861 #define CAN_F6R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4862 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4863 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4864 #define CAN_F6R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4865 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4866 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4867 #define CAN_F6R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4868 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4869 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4870 #define CAN_F6R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4871 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4872 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4873 #define CAN_F6R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4874 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4875 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4876 #define CAN_F6R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4877 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4878 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4879 #define CAN_F6R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4880 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4881 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4882 #define CAN_F6R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4883 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4884 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4885 #define CAN_F6R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4886 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4887 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4888 #define CAN_F6R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4889 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4890 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4891 #define CAN_F6R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4892 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4893 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4894 #define CAN_F6R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4895 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4896 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4897
<> 144:ef7eb2e8f9f7 4898 /******************* Bit definition for CAN_F7R2 register *******************/
AnnaBridge 167:e84263d55307 4899 #define CAN_F7R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4900 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4901 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 4902 #define CAN_F7R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 4903 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 4904 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 4905 #define CAN_F7R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 4906 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 4907 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 4908 #define CAN_F7R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 4909 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 4910 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 4911 #define CAN_F7R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 4912 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 4913 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 4914 #define CAN_F7R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 4915 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 4916 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 4917 #define CAN_F7R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 4918 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 4919 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 4920 #define CAN_F7R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 4921 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 4922 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 4923 #define CAN_F7R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 4924 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 4925 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 4926 #define CAN_F7R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 4927 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 4928 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 4929 #define CAN_F7R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 4930 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 4931 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 4932 #define CAN_F7R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 4933 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 4934 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 4935 #define CAN_F7R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 4936 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 4937 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 4938 #define CAN_F7R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 4939 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 4940 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 4941 #define CAN_F7R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 4942 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 4943 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 4944 #define CAN_F7R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 4945 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 4946 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 4947 #define CAN_F7R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 4948 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 4949 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 4950 #define CAN_F7R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 4951 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 4952 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 4953 #define CAN_F7R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 4954 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 4955 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 4956 #define CAN_F7R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 4957 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 4958 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 4959 #define CAN_F7R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 4960 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 4961 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 4962 #define CAN_F7R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 4963 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 4964 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 4965 #define CAN_F7R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 4966 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 4967 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 4968 #define CAN_F7R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 4969 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 4970 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 4971 #define CAN_F7R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 4972 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 4973 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 4974 #define CAN_F7R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 4975 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 4976 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 4977 #define CAN_F7R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 4978 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 4979 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 4980 #define CAN_F7R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 4981 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 4982 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 4983 #define CAN_F7R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 4984 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 4985 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 4986 #define CAN_F7R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 4987 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 4988 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 4989 #define CAN_F7R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 4990 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 4991 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 4992 #define CAN_F7R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 4993 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 4994 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 4995
<> 144:ef7eb2e8f9f7 4996 /******************* Bit definition for CAN_F8R2 register *******************/
AnnaBridge 167:e84263d55307 4997 #define CAN_F8R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 4998 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 4999 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5000 #define CAN_F8R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5001 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5002 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5003 #define CAN_F8R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5004 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5005 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5006 #define CAN_F8R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5007 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5008 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5009 #define CAN_F8R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5010 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5011 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5012 #define CAN_F8R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5013 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5014 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5015 #define CAN_F8R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5016 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5017 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5018 #define CAN_F8R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5019 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5020 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5021 #define CAN_F8R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5022 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5023 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5024 #define CAN_F8R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5025 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5026 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5027 #define CAN_F8R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5028 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5029 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5030 #define CAN_F8R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5031 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5032 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5033 #define CAN_F8R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5034 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5035 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5036 #define CAN_F8R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5037 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5038 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5039 #define CAN_F8R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5040 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5041 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5042 #define CAN_F8R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5043 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5044 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5045 #define CAN_F8R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5046 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5047 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5048 #define CAN_F8R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5049 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5050 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5051 #define CAN_F8R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5052 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5053 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5054 #define CAN_F8R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5055 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5056 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5057 #define CAN_F8R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5058 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5059 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5060 #define CAN_F8R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5061 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5062 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5063 #define CAN_F8R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5064 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5065 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5066 #define CAN_F8R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5067 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5068 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5069 #define CAN_F8R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5070 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5071 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5072 #define CAN_F8R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5073 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5074 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5075 #define CAN_F8R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5076 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5077 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5078 #define CAN_F8R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5079 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5080 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5081 #define CAN_F8R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5082 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5083 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5084 #define CAN_F8R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5085 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5086 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5087 #define CAN_F8R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5088 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5089 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5090 #define CAN_F8R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5091 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5092 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5093
<> 144:ef7eb2e8f9f7 5094 /******************* Bit definition for CAN_F9R2 register *******************/
AnnaBridge 167:e84263d55307 5095 #define CAN_F9R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 5096 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5097 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5098 #define CAN_F9R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5099 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5100 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5101 #define CAN_F9R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5102 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5103 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5104 #define CAN_F9R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5105 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5106 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5107 #define CAN_F9R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5108 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5109 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5110 #define CAN_F9R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5111 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5112 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5113 #define CAN_F9R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5114 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5115 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5116 #define CAN_F9R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5117 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5118 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5119 #define CAN_F9R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5120 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5121 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5122 #define CAN_F9R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5123 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5124 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5125 #define CAN_F9R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5126 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5127 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5128 #define CAN_F9R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5129 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5130 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5131 #define CAN_F9R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5132 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5133 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5134 #define CAN_F9R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5135 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5136 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5137 #define CAN_F9R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5138 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5139 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5140 #define CAN_F9R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5141 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5142 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5143 #define CAN_F9R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5144 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5145 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5146 #define CAN_F9R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5147 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5148 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5149 #define CAN_F9R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5150 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5151 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5152 #define CAN_F9R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5153 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5154 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5155 #define CAN_F9R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5156 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5157 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5158 #define CAN_F9R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5159 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5160 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5161 #define CAN_F9R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5162 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5163 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5164 #define CAN_F9R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5165 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5166 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5167 #define CAN_F9R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5168 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5169 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5170 #define CAN_F9R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5171 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5172 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5173 #define CAN_F9R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5174 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5175 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5176 #define CAN_F9R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5177 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5178 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5179 #define CAN_F9R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5180 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5181 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5182 #define CAN_F9R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5183 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5184 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5185 #define CAN_F9R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5186 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5187 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5188 #define CAN_F9R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5189 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5190 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5191
<> 144:ef7eb2e8f9f7 5192 /******************* Bit definition for CAN_F10R2 register ******************/
AnnaBridge 167:e84263d55307 5193 #define CAN_F10R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 5194 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5195 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5196 #define CAN_F10R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5197 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5198 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5199 #define CAN_F10R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5200 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5201 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5202 #define CAN_F10R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5203 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5204 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5205 #define CAN_F10R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5206 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5207 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5208 #define CAN_F10R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5209 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5210 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5211 #define CAN_F10R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5212 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5213 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5214 #define CAN_F10R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5215 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5216 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5217 #define CAN_F10R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5218 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5219 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5220 #define CAN_F10R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5221 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5222 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5223 #define CAN_F10R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5224 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5225 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5226 #define CAN_F10R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5227 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5228 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5229 #define CAN_F10R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5230 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5231 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5232 #define CAN_F10R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5233 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5234 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5235 #define CAN_F10R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5236 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5237 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5238 #define CAN_F10R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5239 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5240 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5241 #define CAN_F10R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5242 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5243 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5244 #define CAN_F10R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5245 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5246 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5247 #define CAN_F10R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5248 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5249 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5250 #define CAN_F10R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5251 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5252 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5253 #define CAN_F10R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5254 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5255 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5256 #define CAN_F10R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5257 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5258 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5259 #define CAN_F10R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5260 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5261 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5262 #define CAN_F10R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5263 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5264 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5265 #define CAN_F10R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5266 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5267 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5268 #define CAN_F10R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5269 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5270 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5271 #define CAN_F10R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5272 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5273 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5274 #define CAN_F10R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5275 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5276 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5277 #define CAN_F10R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5278 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5279 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5280 #define CAN_F10R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5281 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5282 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5283 #define CAN_F10R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5284 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5285 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5286 #define CAN_F10R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5287 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5288 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5289
<> 144:ef7eb2e8f9f7 5290 /******************* Bit definition for CAN_F11R2 register ******************/
AnnaBridge 167:e84263d55307 5291 #define CAN_F11R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 5292 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5293 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5294 #define CAN_F11R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5295 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5296 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5297 #define CAN_F11R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5298 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5299 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5300 #define CAN_F11R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5301 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5302 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5303 #define CAN_F11R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5304 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5305 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5306 #define CAN_F11R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5307 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5308 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5309 #define CAN_F11R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5310 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5311 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5312 #define CAN_F11R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5313 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5314 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5315 #define CAN_F11R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5316 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5317 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5318 #define CAN_F11R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5319 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5320 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5321 #define CAN_F11R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5322 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5323 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5324 #define CAN_F11R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5325 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5326 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5327 #define CAN_F11R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5328 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5329 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5330 #define CAN_F11R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5331 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5332 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5333 #define CAN_F11R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5334 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5335 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5336 #define CAN_F11R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5337 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5338 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5339 #define CAN_F11R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5340 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5341 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5342 #define CAN_F11R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5343 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5344 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5345 #define CAN_F11R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5346 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5347 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5348 #define CAN_F11R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5349 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5350 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5351 #define CAN_F11R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5352 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5353 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5354 #define CAN_F11R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5355 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5356 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5357 #define CAN_F11R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5358 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5359 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5360 #define CAN_F11R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5361 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5362 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5363 #define CAN_F11R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5364 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5365 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5366 #define CAN_F11R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5367 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5368 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5369 #define CAN_F11R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5370 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5371 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5372 #define CAN_F11R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5373 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5374 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5375 #define CAN_F11R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5376 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5377 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5378 #define CAN_F11R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5379 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5380 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5381 #define CAN_F11R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5382 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5383 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5384 #define CAN_F11R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5385 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5386 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5387
<> 144:ef7eb2e8f9f7 5388 /******************* Bit definition for CAN_F12R2 register ******************/
AnnaBridge 167:e84263d55307 5389 #define CAN_F12R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 5390 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5391 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5392 #define CAN_F12R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5393 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5394 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5395 #define CAN_F12R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5396 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5397 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5398 #define CAN_F12R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5399 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5400 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5401 #define CAN_F12R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5402 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5403 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5404 #define CAN_F12R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5405 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5406 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5407 #define CAN_F12R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5408 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5409 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5410 #define CAN_F12R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5411 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5412 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5413 #define CAN_F12R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5414 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5415 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5416 #define CAN_F12R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5417 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5418 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5419 #define CAN_F12R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5420 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5421 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5422 #define CAN_F12R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5423 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5424 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5425 #define CAN_F12R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5426 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5427 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5428 #define CAN_F12R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5429 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5430 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5431 #define CAN_F12R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5432 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5433 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5434 #define CAN_F12R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5435 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5436 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5437 #define CAN_F12R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5438 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5439 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5440 #define CAN_F12R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5441 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5442 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5443 #define CAN_F12R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5444 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5445 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5446 #define CAN_F12R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5447 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5448 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5449 #define CAN_F12R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5450 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5451 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5452 #define CAN_F12R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5453 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5454 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5455 #define CAN_F12R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5456 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5457 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5458 #define CAN_F12R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5459 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5460 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5461 #define CAN_F12R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5462 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5463 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5464 #define CAN_F12R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5465 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5466 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5467 #define CAN_F12R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5468 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5469 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5470 #define CAN_F12R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5471 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5472 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5473 #define CAN_F12R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5474 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5475 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5476 #define CAN_F12R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5477 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5478 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5479 #define CAN_F12R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5480 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5481 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5482 #define CAN_F12R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5483 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5484 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5485
<> 144:ef7eb2e8f9f7 5486 /******************* Bit definition for CAN_F13R2 register ******************/
AnnaBridge 167:e84263d55307 5487 #define CAN_F13R2_FB0_Pos (0U)
AnnaBridge 167:e84263d55307 5488 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5489 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
AnnaBridge 167:e84263d55307 5490 #define CAN_F13R2_FB1_Pos (1U)
AnnaBridge 167:e84263d55307 5491 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5492 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
AnnaBridge 167:e84263d55307 5493 #define CAN_F13R2_FB2_Pos (2U)
AnnaBridge 167:e84263d55307 5494 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5495 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
AnnaBridge 167:e84263d55307 5496 #define CAN_F13R2_FB3_Pos (3U)
AnnaBridge 167:e84263d55307 5497 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5498 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
AnnaBridge 167:e84263d55307 5499 #define CAN_F13R2_FB4_Pos (4U)
AnnaBridge 167:e84263d55307 5500 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5501 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
AnnaBridge 167:e84263d55307 5502 #define CAN_F13R2_FB5_Pos (5U)
AnnaBridge 167:e84263d55307 5503 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5504 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
AnnaBridge 167:e84263d55307 5505 #define CAN_F13R2_FB6_Pos (6U)
AnnaBridge 167:e84263d55307 5506 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5507 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
AnnaBridge 167:e84263d55307 5508 #define CAN_F13R2_FB7_Pos (7U)
AnnaBridge 167:e84263d55307 5509 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5510 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
AnnaBridge 167:e84263d55307 5511 #define CAN_F13R2_FB8_Pos (8U)
AnnaBridge 167:e84263d55307 5512 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5513 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
AnnaBridge 167:e84263d55307 5514 #define CAN_F13R2_FB9_Pos (9U)
AnnaBridge 167:e84263d55307 5515 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5516 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
AnnaBridge 167:e84263d55307 5517 #define CAN_F13R2_FB10_Pos (10U)
AnnaBridge 167:e84263d55307 5518 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5519 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
AnnaBridge 167:e84263d55307 5520 #define CAN_F13R2_FB11_Pos (11U)
AnnaBridge 167:e84263d55307 5521 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5522 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
AnnaBridge 167:e84263d55307 5523 #define CAN_F13R2_FB12_Pos (12U)
AnnaBridge 167:e84263d55307 5524 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5525 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
AnnaBridge 167:e84263d55307 5526 #define CAN_F13R2_FB13_Pos (13U)
AnnaBridge 167:e84263d55307 5527 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5528 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
AnnaBridge 167:e84263d55307 5529 #define CAN_F13R2_FB14_Pos (14U)
AnnaBridge 167:e84263d55307 5530 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5531 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
AnnaBridge 167:e84263d55307 5532 #define CAN_F13R2_FB15_Pos (15U)
AnnaBridge 167:e84263d55307 5533 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 5534 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
AnnaBridge 167:e84263d55307 5535 #define CAN_F13R2_FB16_Pos (16U)
AnnaBridge 167:e84263d55307 5536 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5537 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
AnnaBridge 167:e84263d55307 5538 #define CAN_F13R2_FB17_Pos (17U)
AnnaBridge 167:e84263d55307 5539 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5540 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
AnnaBridge 167:e84263d55307 5541 #define CAN_F13R2_FB18_Pos (18U)
AnnaBridge 167:e84263d55307 5542 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5543 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
AnnaBridge 167:e84263d55307 5544 #define CAN_F13R2_FB19_Pos (19U)
AnnaBridge 167:e84263d55307 5545 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5546 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
AnnaBridge 167:e84263d55307 5547 #define CAN_F13R2_FB20_Pos (20U)
AnnaBridge 167:e84263d55307 5548 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5549 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
AnnaBridge 167:e84263d55307 5550 #define CAN_F13R2_FB21_Pos (21U)
AnnaBridge 167:e84263d55307 5551 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5552 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
AnnaBridge 167:e84263d55307 5553 #define CAN_F13R2_FB22_Pos (22U)
AnnaBridge 167:e84263d55307 5554 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5555 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
AnnaBridge 167:e84263d55307 5556 #define CAN_F13R2_FB23_Pos (23U)
AnnaBridge 167:e84263d55307 5557 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5558 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
AnnaBridge 167:e84263d55307 5559 #define CAN_F13R2_FB24_Pos (24U)
AnnaBridge 167:e84263d55307 5560 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5561 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
AnnaBridge 167:e84263d55307 5562 #define CAN_F13R2_FB25_Pos (25U)
AnnaBridge 167:e84263d55307 5563 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5564 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
AnnaBridge 167:e84263d55307 5565 #define CAN_F13R2_FB26_Pos (26U)
AnnaBridge 167:e84263d55307 5566 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5567 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
AnnaBridge 167:e84263d55307 5568 #define CAN_F13R2_FB27_Pos (27U)
AnnaBridge 167:e84263d55307 5569 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5570 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
AnnaBridge 167:e84263d55307 5571 #define CAN_F13R2_FB28_Pos (28U)
AnnaBridge 167:e84263d55307 5572 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5573 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
AnnaBridge 167:e84263d55307 5574 #define CAN_F13R2_FB29_Pos (29U)
AnnaBridge 167:e84263d55307 5575 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5576 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
AnnaBridge 167:e84263d55307 5577 #define CAN_F13R2_FB30_Pos (30U)
AnnaBridge 167:e84263d55307 5578 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 5579 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
AnnaBridge 167:e84263d55307 5580 #define CAN_F13R2_FB31_Pos (31U)
AnnaBridge 167:e84263d55307 5581 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 5582 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
<> 144:ef7eb2e8f9f7 5583
<> 144:ef7eb2e8f9f7 5584 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5585 /* */
<> 144:ef7eb2e8f9f7 5586 /* CRC calculation unit */
<> 144:ef7eb2e8f9f7 5587 /* */
<> 144:ef7eb2e8f9f7 5588 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5589 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 167:e84263d55307 5590 #define CRC_DR_DR_Pos (0U)
AnnaBridge 167:e84263d55307 5591 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 5592 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
<> 144:ef7eb2e8f9f7 5593
<> 144:ef7eb2e8f9f7 5594
<> 144:ef7eb2e8f9f7 5595 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 167:e84263d55307 5596 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 167:e84263d55307 5597 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5598 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
<> 144:ef7eb2e8f9f7 5599
<> 144:ef7eb2e8f9f7 5600
<> 144:ef7eb2e8f9f7 5601 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 167:e84263d55307 5602 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 167:e84263d55307 5603 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5604 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
<> 144:ef7eb2e8f9f7 5605
<> 144:ef7eb2e8f9f7 5606 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5607 /* */
<> 144:ef7eb2e8f9f7 5608 /* Digital to Analog Converter */
<> 144:ef7eb2e8f9f7 5609 /* */
<> 144:ef7eb2e8f9f7 5610 /******************************************************************************/
AnnaBridge 167:e84263d55307 5611 /*
AnnaBridge 167:e84263d55307 5612 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 5613 */
AnnaBridge 167:e84263d55307 5614 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
<> 144:ef7eb2e8f9f7 5615 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 167:e84263d55307 5616 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 167:e84263d55307 5617 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5618 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 167:e84263d55307 5619 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 167:e84263d55307 5620 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5621 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 167:e84263d55307 5622 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 167:e84263d55307 5623 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5624 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 167:e84263d55307 5625
AnnaBridge 167:e84263d55307 5626 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 167:e84263d55307 5627 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 167:e84263d55307 5628 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 167:e84263d55307 5629 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5630 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5631 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5632
AnnaBridge 167:e84263d55307 5633 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 167:e84263d55307 5634 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 5635 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 167:e84263d55307 5636 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5637 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5638
AnnaBridge 167:e84263d55307 5639 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 167:e84263d55307 5640 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 5641 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 167:e84263d55307 5642 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 5643 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 5644 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 5645 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 5646
AnnaBridge 167:e84263d55307 5647 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 167:e84263d55307 5648 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5649 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 167:e84263d55307 5650 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 167:e84263d55307 5651 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5652 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
AnnaBridge 167:e84263d55307 5653 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 167:e84263d55307 5654 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 5655 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 167:e84263d55307 5656 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 167:e84263d55307 5657 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 5658 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 167:e84263d55307 5659 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 167:e84263d55307 5660 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5661 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 167:e84263d55307 5662
AnnaBridge 167:e84263d55307 5663 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 167:e84263d55307 5664 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 167:e84263d55307 5665 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 167:e84263d55307 5666 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5667 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 5668 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5669
AnnaBridge 167:e84263d55307 5670 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 167:e84263d55307 5671 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 5672 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 167:e84263d55307 5673 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5674 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5675
AnnaBridge 167:e84263d55307 5676 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 167:e84263d55307 5677 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 5678 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 167:e84263d55307 5679 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5680 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 5681 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 5682 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 5683
AnnaBridge 167:e84263d55307 5684 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 167:e84263d55307 5685 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 5686 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 167:e84263d55307 5687 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 167:e84263d55307 5688 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5689 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
<> 144:ef7eb2e8f9f7 5690
<> 144:ef7eb2e8f9f7 5691 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 167:e84263d55307 5692 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 167:e84263d55307 5693 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5694 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 167:e84263d55307 5695 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 167:e84263d55307 5696 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5697 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
<> 144:ef7eb2e8f9f7 5698
<> 144:ef7eb2e8f9f7 5699 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 167:e84263d55307 5700 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5701 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 5702 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5703
<> 144:ef7eb2e8f9f7 5704 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 167:e84263d55307 5705 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 167:e84263d55307 5706 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 167:e84263d55307 5707 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5708
<> 144:ef7eb2e8f9f7 5709 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 167:e84263d55307 5710 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5711 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5712 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5713
<> 144:ef7eb2e8f9f7 5714 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 167:e84263d55307 5715 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5716 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 5717 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5718
<> 144:ef7eb2e8f9f7 5719 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 167:e84263d55307 5720 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 167:e84263d55307 5721 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 167:e84263d55307 5722 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5723
<> 144:ef7eb2e8f9f7 5724 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 167:e84263d55307 5725 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5726 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5727 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5728
<> 144:ef7eb2e8f9f7 5729 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 167:e84263d55307 5730 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5731 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 5732 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 167:e84263d55307 5733 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 167:e84263d55307 5734 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 5735 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5736
<> 144:ef7eb2e8f9f7 5737 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 167:e84263d55307 5738 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 167:e84263d55307 5739 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 167:e84263d55307 5740 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 167:e84263d55307 5741 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 167:e84263d55307 5742 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 167:e84263d55307 5743 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
<> 144:ef7eb2e8f9f7 5744
<> 144:ef7eb2e8f9f7 5745 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 167:e84263d55307 5746 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 167:e84263d55307 5747 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5748 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 167:e84263d55307 5749 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 167:e84263d55307 5750 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 5751 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
<> 144:ef7eb2e8f9f7 5752
<> 144:ef7eb2e8f9f7 5753 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 167:e84263d55307 5754 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 167:e84263d55307 5755 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 5756 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
<> 144:ef7eb2e8f9f7 5757
<> 144:ef7eb2e8f9f7 5758 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 167:e84263d55307 5759 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 167:e84263d55307 5760 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 5761 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
<> 144:ef7eb2e8f9f7 5762
<> 144:ef7eb2e8f9f7 5763 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 167:e84263d55307 5764 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 167:e84263d55307 5765 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 5766 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 167:e84263d55307 5767 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 167:e84263d55307 5768 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 5769 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
<> 144:ef7eb2e8f9f7 5770
<> 144:ef7eb2e8f9f7 5771 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5772 /* */
<> 144:ef7eb2e8f9f7 5773 /* DCMI */
<> 144:ef7eb2e8f9f7 5774 /* */
<> 144:ef7eb2e8f9f7 5775 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5776 /******************** Bits definition for DCMI_CR register ******************/
AnnaBridge 167:e84263d55307 5777 #define DCMI_CR_CAPTURE_Pos (0U)
AnnaBridge 167:e84263d55307 5778 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5779 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
AnnaBridge 167:e84263d55307 5780 #define DCMI_CR_CM_Pos (1U)
AnnaBridge 167:e84263d55307 5781 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5782 #define DCMI_CR_CM DCMI_CR_CM_Msk
AnnaBridge 167:e84263d55307 5783 #define DCMI_CR_CROP_Pos (2U)
AnnaBridge 167:e84263d55307 5784 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5785 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
AnnaBridge 167:e84263d55307 5786 #define DCMI_CR_JPEG_Pos (3U)
AnnaBridge 167:e84263d55307 5787 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5788 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
AnnaBridge 167:e84263d55307 5789 #define DCMI_CR_ESS_Pos (4U)
AnnaBridge 167:e84263d55307 5790 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5791 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
AnnaBridge 167:e84263d55307 5792 #define DCMI_CR_PCKPOL_Pos (5U)
AnnaBridge 167:e84263d55307 5793 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 5794 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
AnnaBridge 167:e84263d55307 5795 #define DCMI_CR_HSPOL_Pos (6U)
AnnaBridge 167:e84263d55307 5796 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 5797 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
AnnaBridge 167:e84263d55307 5798 #define DCMI_CR_VSPOL_Pos (7U)
AnnaBridge 167:e84263d55307 5799 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 5800 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
AnnaBridge 167:e84263d55307 5801 #define DCMI_CR_FCRC_0 0x00000100U
AnnaBridge 167:e84263d55307 5802 #define DCMI_CR_FCRC_1 0x00000200U
AnnaBridge 167:e84263d55307 5803 #define DCMI_CR_EDM_0 0x00000400U
AnnaBridge 167:e84263d55307 5804 #define DCMI_CR_EDM_1 0x00000800U
AnnaBridge 167:e84263d55307 5805 #define DCMI_CR_CRE_Pos (12U)
AnnaBridge 167:e84263d55307 5806 #define DCMI_CR_CRE_Msk (0x1U << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 5807 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
AnnaBridge 167:e84263d55307 5808 #define DCMI_CR_ENABLE_Pos (14U)
AnnaBridge 167:e84263d55307 5809 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 5810 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
<> 144:ef7eb2e8f9f7 5811
<> 144:ef7eb2e8f9f7 5812 /******************** Bits definition for DCMI_SR register ******************/
AnnaBridge 167:e84263d55307 5813 #define DCMI_SR_HSYNC_Pos (0U)
AnnaBridge 167:e84263d55307 5814 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5815 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
AnnaBridge 167:e84263d55307 5816 #define DCMI_SR_VSYNC_Pos (1U)
AnnaBridge 167:e84263d55307 5817 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5818 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
AnnaBridge 167:e84263d55307 5819 #define DCMI_SR_FNE_Pos (2U)
AnnaBridge 167:e84263d55307 5820 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5821 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
<> 144:ef7eb2e8f9f7 5822
<> 144:ef7eb2e8f9f7 5823 /******************** Bits definition for DCMI_RIS register *****************/
AnnaBridge 167:e84263d55307 5824 #define DCMI_RIS_FRAME_RIS_Pos (0U)
AnnaBridge 167:e84263d55307 5825 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5826 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
AnnaBridge 167:e84263d55307 5827 #define DCMI_RIS_OVR_RIS_Pos (1U)
AnnaBridge 167:e84263d55307 5828 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5829 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
AnnaBridge 167:e84263d55307 5830 #define DCMI_RIS_ERR_RIS_Pos (2U)
AnnaBridge 167:e84263d55307 5831 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5832 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
AnnaBridge 167:e84263d55307 5833 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
AnnaBridge 167:e84263d55307 5834 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5835 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
AnnaBridge 167:e84263d55307 5836 #define DCMI_RIS_LINE_RIS_Pos (4U)
AnnaBridge 167:e84263d55307 5837 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5838 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
<> 144:ef7eb2e8f9f7 5839 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5840 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
<> 144:ef7eb2e8f9f7 5841 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
<> 144:ef7eb2e8f9f7 5842 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
<> 144:ef7eb2e8f9f7 5843 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
<> 144:ef7eb2e8f9f7 5844 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
<> 144:ef7eb2e8f9f7 5845 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
<> 144:ef7eb2e8f9f7 5846
<> 144:ef7eb2e8f9f7 5847 /******************** Bits definition for DCMI_IER register *****************/
AnnaBridge 167:e84263d55307 5848 #define DCMI_IER_FRAME_IE_Pos (0U)
AnnaBridge 167:e84263d55307 5849 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5850 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
AnnaBridge 167:e84263d55307 5851 #define DCMI_IER_OVR_IE_Pos (1U)
AnnaBridge 167:e84263d55307 5852 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5853 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
AnnaBridge 167:e84263d55307 5854 #define DCMI_IER_ERR_IE_Pos (2U)
AnnaBridge 167:e84263d55307 5855 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5856 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
AnnaBridge 167:e84263d55307 5857 #define DCMI_IER_VSYNC_IE_Pos (3U)
AnnaBridge 167:e84263d55307 5858 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5859 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
AnnaBridge 167:e84263d55307 5860 #define DCMI_IER_LINE_IE_Pos (4U)
AnnaBridge 167:e84263d55307 5861 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5862 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
<> 144:ef7eb2e8f9f7 5863 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5864 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
<> 144:ef7eb2e8f9f7 5865
<> 144:ef7eb2e8f9f7 5866 /******************** Bits definition for DCMI_MIS register *****************/
AnnaBridge 167:e84263d55307 5867 #define DCMI_MIS_FRAME_MIS_Pos (0U)
AnnaBridge 167:e84263d55307 5868 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5869 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
AnnaBridge 167:e84263d55307 5870 #define DCMI_MIS_OVR_MIS_Pos (1U)
AnnaBridge 167:e84263d55307 5871 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5872 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
AnnaBridge 167:e84263d55307 5873 #define DCMI_MIS_ERR_MIS_Pos (2U)
AnnaBridge 167:e84263d55307 5874 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5875 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
AnnaBridge 167:e84263d55307 5876 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
AnnaBridge 167:e84263d55307 5877 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5878 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
AnnaBridge 167:e84263d55307 5879 #define DCMI_MIS_LINE_MIS_Pos (4U)
AnnaBridge 167:e84263d55307 5880 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5881 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
<> 144:ef7eb2e8f9f7 5882
<> 144:ef7eb2e8f9f7 5883 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5884 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
<> 144:ef7eb2e8f9f7 5885 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
<> 144:ef7eb2e8f9f7 5886 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
<> 144:ef7eb2e8f9f7 5887 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
<> 144:ef7eb2e8f9f7 5888 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
<> 144:ef7eb2e8f9f7 5889
<> 144:ef7eb2e8f9f7 5890 /******************** Bits definition for DCMI_ICR register *****************/
AnnaBridge 167:e84263d55307 5891 #define DCMI_ICR_FRAME_ISC_Pos (0U)
AnnaBridge 167:e84263d55307 5892 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 5893 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
AnnaBridge 167:e84263d55307 5894 #define DCMI_ICR_OVR_ISC_Pos (1U)
AnnaBridge 167:e84263d55307 5895 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 5896 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
AnnaBridge 167:e84263d55307 5897 #define DCMI_ICR_ERR_ISC_Pos (2U)
AnnaBridge 167:e84263d55307 5898 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 5899 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
AnnaBridge 167:e84263d55307 5900 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
AnnaBridge 167:e84263d55307 5901 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 5902 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
AnnaBridge 167:e84263d55307 5903 #define DCMI_ICR_LINE_ISC_Pos (4U)
AnnaBridge 167:e84263d55307 5904 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 5905 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
<> 144:ef7eb2e8f9f7 5906
<> 144:ef7eb2e8f9f7 5907 /* Legacy defines */
<> 144:ef7eb2e8f9f7 5908 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
<> 144:ef7eb2e8f9f7 5909
<> 144:ef7eb2e8f9f7 5910 /******************** Bits definition for DCMI_ESCR register ******************/
AnnaBridge 167:e84263d55307 5911 #define DCMI_ESCR_FSC_Pos (0U)
AnnaBridge 167:e84263d55307 5912 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5913 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
AnnaBridge 167:e84263d55307 5914 #define DCMI_ESCR_LSC_Pos (8U)
AnnaBridge 167:e84263d55307 5915 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 5916 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
AnnaBridge 167:e84263d55307 5917 #define DCMI_ESCR_LEC_Pos (16U)
AnnaBridge 167:e84263d55307 5918 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 5919 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
AnnaBridge 167:e84263d55307 5920 #define DCMI_ESCR_FEC_Pos (24U)
AnnaBridge 167:e84263d55307 5921 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 5922 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
<> 144:ef7eb2e8f9f7 5923
<> 144:ef7eb2e8f9f7 5924 /******************** Bits definition for DCMI_ESUR register ******************/
AnnaBridge 167:e84263d55307 5925 #define DCMI_ESUR_FSU_Pos (0U)
AnnaBridge 167:e84263d55307 5926 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5927 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
AnnaBridge 167:e84263d55307 5928 #define DCMI_ESUR_LSU_Pos (8U)
AnnaBridge 167:e84263d55307 5929 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 5930 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
AnnaBridge 167:e84263d55307 5931 #define DCMI_ESUR_LEU_Pos (16U)
AnnaBridge 167:e84263d55307 5932 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 5933 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
AnnaBridge 167:e84263d55307 5934 #define DCMI_ESUR_FEU_Pos (24U)
AnnaBridge 167:e84263d55307 5935 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 5936 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
<> 144:ef7eb2e8f9f7 5937
<> 144:ef7eb2e8f9f7 5938 /******************** Bits definition for DCMI_CWSTRT register ******************/
AnnaBridge 167:e84263d55307 5939 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
AnnaBridge 167:e84263d55307 5940 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 167:e84263d55307 5941 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
AnnaBridge 167:e84263d55307 5942 #define DCMI_CWSTRT_VST_Pos (16U)
AnnaBridge 167:e84263d55307 5943 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
AnnaBridge 167:e84263d55307 5944 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
<> 144:ef7eb2e8f9f7 5945
<> 144:ef7eb2e8f9f7 5946 /******************** Bits definition for DCMI_CWSIZE register ******************/
AnnaBridge 167:e84263d55307 5947 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
AnnaBridge 167:e84263d55307 5948 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
AnnaBridge 167:e84263d55307 5949 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
AnnaBridge 167:e84263d55307 5950 #define DCMI_CWSIZE_VLINE_Pos (16U)
AnnaBridge 167:e84263d55307 5951 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
AnnaBridge 167:e84263d55307 5952 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
AnnaBridge 167:e84263d55307 5953
AnnaBridge 167:e84263d55307 5954 /******************** Bits definition for DCMI_DR register *********************/
AnnaBridge 167:e84263d55307 5955 #define DCMI_DR_BYTE0_Pos (0U)
AnnaBridge 167:e84263d55307 5956 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 5957 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
AnnaBridge 167:e84263d55307 5958 #define DCMI_DR_BYTE1_Pos (8U)
AnnaBridge 167:e84263d55307 5959 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 5960 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
AnnaBridge 167:e84263d55307 5961 #define DCMI_DR_BYTE2_Pos (16U)
AnnaBridge 167:e84263d55307 5962 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 5963 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
AnnaBridge 167:e84263d55307 5964 #define DCMI_DR_BYTE3_Pos (24U)
AnnaBridge 167:e84263d55307 5965 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 5966 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
<> 144:ef7eb2e8f9f7 5967
<> 144:ef7eb2e8f9f7 5968 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5969 /* */
<> 144:ef7eb2e8f9f7 5970 /* DMA Controller */
<> 144:ef7eb2e8f9f7 5971 /* */
<> 144:ef7eb2e8f9f7 5972 /******************************************************************************/
<> 144:ef7eb2e8f9f7 5973 /******************** Bits definition for DMA_SxCR register *****************/
AnnaBridge 167:e84263d55307 5974 #define DMA_SxCR_CHSEL_Pos (25U)
AnnaBridge 167:e84263d55307 5975 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
AnnaBridge 167:e84263d55307 5976 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
AnnaBridge 167:e84263d55307 5977 #define DMA_SxCR_CHSEL_0 0x02000000U
AnnaBridge 167:e84263d55307 5978 #define DMA_SxCR_CHSEL_1 0x04000000U
AnnaBridge 167:e84263d55307 5979 #define DMA_SxCR_CHSEL_2 0x08000000U
AnnaBridge 167:e84263d55307 5980 #define DMA_SxCR_MBURST_Pos (23U)
AnnaBridge 167:e84263d55307 5981 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
AnnaBridge 167:e84263d55307 5982 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
AnnaBridge 167:e84263d55307 5983 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 5984 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 5985 #define DMA_SxCR_PBURST_Pos (21U)
AnnaBridge 167:e84263d55307 5986 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
AnnaBridge 167:e84263d55307 5987 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
AnnaBridge 167:e84263d55307 5988 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 5989 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 5990 #define DMA_SxCR_CT_Pos (19U)
AnnaBridge 167:e84263d55307 5991 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 5992 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
AnnaBridge 167:e84263d55307 5993 #define DMA_SxCR_DBM_Pos (18U)
AnnaBridge 167:e84263d55307 5994 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 5995 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
AnnaBridge 167:e84263d55307 5996 #define DMA_SxCR_PL_Pos (16U)
AnnaBridge 167:e84263d55307 5997 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 5998 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
AnnaBridge 167:e84263d55307 5999 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6000 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6001 #define DMA_SxCR_PINCOS_Pos (15U)
AnnaBridge 167:e84263d55307 6002 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 6003 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
AnnaBridge 167:e84263d55307 6004 #define DMA_SxCR_MSIZE_Pos (13U)
AnnaBridge 167:e84263d55307 6005 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
AnnaBridge 167:e84263d55307 6006 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
AnnaBridge 167:e84263d55307 6007 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6008 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6009 #define DMA_SxCR_PSIZE_Pos (11U)
AnnaBridge 167:e84263d55307 6010 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
AnnaBridge 167:e84263d55307 6011 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
AnnaBridge 167:e84263d55307 6012 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6013 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6014 #define DMA_SxCR_MINC_Pos (10U)
AnnaBridge 167:e84263d55307 6015 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6016 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
AnnaBridge 167:e84263d55307 6017 #define DMA_SxCR_PINC_Pos (9U)
AnnaBridge 167:e84263d55307 6018 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6019 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
AnnaBridge 167:e84263d55307 6020 #define DMA_SxCR_CIRC_Pos (8U)
AnnaBridge 167:e84263d55307 6021 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6022 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
AnnaBridge 167:e84263d55307 6023 #define DMA_SxCR_DIR_Pos (6U)
AnnaBridge 167:e84263d55307 6024 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 6025 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
AnnaBridge 167:e84263d55307 6026 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6027 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6028 #define DMA_SxCR_PFCTRL_Pos (5U)
AnnaBridge 167:e84263d55307 6029 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6030 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
AnnaBridge 167:e84263d55307 6031 #define DMA_SxCR_TCIE_Pos (4U)
AnnaBridge 167:e84263d55307 6032 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6033 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
AnnaBridge 167:e84263d55307 6034 #define DMA_SxCR_HTIE_Pos (3U)
AnnaBridge 167:e84263d55307 6035 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6036 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
AnnaBridge 167:e84263d55307 6037 #define DMA_SxCR_TEIE_Pos (2U)
AnnaBridge 167:e84263d55307 6038 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6039 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
AnnaBridge 167:e84263d55307 6040 #define DMA_SxCR_DMEIE_Pos (1U)
AnnaBridge 167:e84263d55307 6041 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6042 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
AnnaBridge 167:e84263d55307 6043 #define DMA_SxCR_EN_Pos (0U)
AnnaBridge 167:e84263d55307 6044 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6045 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
<> 144:ef7eb2e8f9f7 6046
<> 144:ef7eb2e8f9f7 6047 /* Legacy defines */
AnnaBridge 167:e84263d55307 6048 #define DMA_SxCR_ACK_Pos (20U)
AnnaBridge 167:e84263d55307 6049 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6050 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
<> 144:ef7eb2e8f9f7 6051
<> 144:ef7eb2e8f9f7 6052 /******************** Bits definition for DMA_SxCNDTR register **************/
AnnaBridge 167:e84263d55307 6053 #define DMA_SxNDT_Pos (0U)
AnnaBridge 167:e84263d55307 6054 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 6055 #define DMA_SxNDT DMA_SxNDT_Msk
AnnaBridge 167:e84263d55307 6056 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6057 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6058 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6059 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6060 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6061 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6062 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6063 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6064 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6065 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6066 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6067 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6068 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6069 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6070 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6071 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 6072
<> 144:ef7eb2e8f9f7 6073 /******************** Bits definition for DMA_SxFCR register ****************/
AnnaBridge 167:e84263d55307 6074 #define DMA_SxFCR_FEIE_Pos (7U)
AnnaBridge 167:e84263d55307 6075 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6076 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
AnnaBridge 167:e84263d55307 6077 #define DMA_SxFCR_FS_Pos (3U)
AnnaBridge 167:e84263d55307 6078 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
AnnaBridge 167:e84263d55307 6079 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
AnnaBridge 167:e84263d55307 6080 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6081 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6082 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6083 #define DMA_SxFCR_DMDIS_Pos (2U)
AnnaBridge 167:e84263d55307 6084 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6085 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
AnnaBridge 167:e84263d55307 6086 #define DMA_SxFCR_FTH_Pos (0U)
AnnaBridge 167:e84263d55307 6087 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 6088 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
AnnaBridge 167:e84263d55307 6089 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6090 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
<> 144:ef7eb2e8f9f7 6091
<> 144:ef7eb2e8f9f7 6092 /******************** Bits definition for DMA_LISR register *****************/
AnnaBridge 167:e84263d55307 6093 #define DMA_LISR_TCIF3_Pos (27U)
AnnaBridge 167:e84263d55307 6094 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 6095 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
AnnaBridge 167:e84263d55307 6096 #define DMA_LISR_HTIF3_Pos (26U)
AnnaBridge 167:e84263d55307 6097 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 6098 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
AnnaBridge 167:e84263d55307 6099 #define DMA_LISR_TEIF3_Pos (25U)
AnnaBridge 167:e84263d55307 6100 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 6101 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
AnnaBridge 167:e84263d55307 6102 #define DMA_LISR_DMEIF3_Pos (24U)
AnnaBridge 167:e84263d55307 6103 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 6104 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
AnnaBridge 167:e84263d55307 6105 #define DMA_LISR_FEIF3_Pos (22U)
AnnaBridge 167:e84263d55307 6106 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6107 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
AnnaBridge 167:e84263d55307 6108 #define DMA_LISR_TCIF2_Pos (21U)
AnnaBridge 167:e84263d55307 6109 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6110 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
AnnaBridge 167:e84263d55307 6111 #define DMA_LISR_HTIF2_Pos (20U)
AnnaBridge 167:e84263d55307 6112 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6113 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
AnnaBridge 167:e84263d55307 6114 #define DMA_LISR_TEIF2_Pos (19U)
AnnaBridge 167:e84263d55307 6115 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6116 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
AnnaBridge 167:e84263d55307 6117 #define DMA_LISR_DMEIF2_Pos (18U)
AnnaBridge 167:e84263d55307 6118 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6119 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
AnnaBridge 167:e84263d55307 6120 #define DMA_LISR_FEIF2_Pos (16U)
AnnaBridge 167:e84263d55307 6121 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6122 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
AnnaBridge 167:e84263d55307 6123 #define DMA_LISR_TCIF1_Pos (11U)
AnnaBridge 167:e84263d55307 6124 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6125 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
AnnaBridge 167:e84263d55307 6126 #define DMA_LISR_HTIF1_Pos (10U)
AnnaBridge 167:e84263d55307 6127 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6128 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
AnnaBridge 167:e84263d55307 6129 #define DMA_LISR_TEIF1_Pos (9U)
AnnaBridge 167:e84263d55307 6130 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6131 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
AnnaBridge 167:e84263d55307 6132 #define DMA_LISR_DMEIF1_Pos (8U)
AnnaBridge 167:e84263d55307 6133 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6134 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
AnnaBridge 167:e84263d55307 6135 #define DMA_LISR_FEIF1_Pos (6U)
AnnaBridge 167:e84263d55307 6136 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6137 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
AnnaBridge 167:e84263d55307 6138 #define DMA_LISR_TCIF0_Pos (5U)
AnnaBridge 167:e84263d55307 6139 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6140 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
AnnaBridge 167:e84263d55307 6141 #define DMA_LISR_HTIF0_Pos (4U)
AnnaBridge 167:e84263d55307 6142 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6143 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
AnnaBridge 167:e84263d55307 6144 #define DMA_LISR_TEIF0_Pos (3U)
AnnaBridge 167:e84263d55307 6145 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6146 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
AnnaBridge 167:e84263d55307 6147 #define DMA_LISR_DMEIF0_Pos (2U)
AnnaBridge 167:e84263d55307 6148 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6149 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
AnnaBridge 167:e84263d55307 6150 #define DMA_LISR_FEIF0_Pos (0U)
AnnaBridge 167:e84263d55307 6151 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6152 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
<> 144:ef7eb2e8f9f7 6153
<> 144:ef7eb2e8f9f7 6154 /******************** Bits definition for DMA_HISR register *****************/
AnnaBridge 167:e84263d55307 6155 #define DMA_HISR_TCIF7_Pos (27U)
AnnaBridge 167:e84263d55307 6156 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 6157 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
AnnaBridge 167:e84263d55307 6158 #define DMA_HISR_HTIF7_Pos (26U)
AnnaBridge 167:e84263d55307 6159 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 6160 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
AnnaBridge 167:e84263d55307 6161 #define DMA_HISR_TEIF7_Pos (25U)
AnnaBridge 167:e84263d55307 6162 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 6163 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
AnnaBridge 167:e84263d55307 6164 #define DMA_HISR_DMEIF7_Pos (24U)
AnnaBridge 167:e84263d55307 6165 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 6166 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
AnnaBridge 167:e84263d55307 6167 #define DMA_HISR_FEIF7_Pos (22U)
AnnaBridge 167:e84263d55307 6168 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6169 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
AnnaBridge 167:e84263d55307 6170 #define DMA_HISR_TCIF6_Pos (21U)
AnnaBridge 167:e84263d55307 6171 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6172 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
AnnaBridge 167:e84263d55307 6173 #define DMA_HISR_HTIF6_Pos (20U)
AnnaBridge 167:e84263d55307 6174 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6175 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
AnnaBridge 167:e84263d55307 6176 #define DMA_HISR_TEIF6_Pos (19U)
AnnaBridge 167:e84263d55307 6177 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6178 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
AnnaBridge 167:e84263d55307 6179 #define DMA_HISR_DMEIF6_Pos (18U)
AnnaBridge 167:e84263d55307 6180 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6181 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
AnnaBridge 167:e84263d55307 6182 #define DMA_HISR_FEIF6_Pos (16U)
AnnaBridge 167:e84263d55307 6183 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6184 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
AnnaBridge 167:e84263d55307 6185 #define DMA_HISR_TCIF5_Pos (11U)
AnnaBridge 167:e84263d55307 6186 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6187 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
AnnaBridge 167:e84263d55307 6188 #define DMA_HISR_HTIF5_Pos (10U)
AnnaBridge 167:e84263d55307 6189 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6190 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
AnnaBridge 167:e84263d55307 6191 #define DMA_HISR_TEIF5_Pos (9U)
AnnaBridge 167:e84263d55307 6192 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6193 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
AnnaBridge 167:e84263d55307 6194 #define DMA_HISR_DMEIF5_Pos (8U)
AnnaBridge 167:e84263d55307 6195 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6196 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
AnnaBridge 167:e84263d55307 6197 #define DMA_HISR_FEIF5_Pos (6U)
AnnaBridge 167:e84263d55307 6198 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6199 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
AnnaBridge 167:e84263d55307 6200 #define DMA_HISR_TCIF4_Pos (5U)
AnnaBridge 167:e84263d55307 6201 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6202 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
AnnaBridge 167:e84263d55307 6203 #define DMA_HISR_HTIF4_Pos (4U)
AnnaBridge 167:e84263d55307 6204 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6205 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
AnnaBridge 167:e84263d55307 6206 #define DMA_HISR_TEIF4_Pos (3U)
AnnaBridge 167:e84263d55307 6207 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6208 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
AnnaBridge 167:e84263d55307 6209 #define DMA_HISR_DMEIF4_Pos (2U)
AnnaBridge 167:e84263d55307 6210 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6211 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
AnnaBridge 167:e84263d55307 6212 #define DMA_HISR_FEIF4_Pos (0U)
AnnaBridge 167:e84263d55307 6213 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6214 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
<> 144:ef7eb2e8f9f7 6215
<> 144:ef7eb2e8f9f7 6216 /******************** Bits definition for DMA_LIFCR register ****************/
AnnaBridge 167:e84263d55307 6217 #define DMA_LIFCR_CTCIF3_Pos (27U)
AnnaBridge 167:e84263d55307 6218 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 6219 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
AnnaBridge 167:e84263d55307 6220 #define DMA_LIFCR_CHTIF3_Pos (26U)
AnnaBridge 167:e84263d55307 6221 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 6222 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
AnnaBridge 167:e84263d55307 6223 #define DMA_LIFCR_CTEIF3_Pos (25U)
AnnaBridge 167:e84263d55307 6224 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 6225 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
AnnaBridge 167:e84263d55307 6226 #define DMA_LIFCR_CDMEIF3_Pos (24U)
AnnaBridge 167:e84263d55307 6227 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 6228 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
AnnaBridge 167:e84263d55307 6229 #define DMA_LIFCR_CFEIF3_Pos (22U)
AnnaBridge 167:e84263d55307 6230 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6231 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
AnnaBridge 167:e84263d55307 6232 #define DMA_LIFCR_CTCIF2_Pos (21U)
AnnaBridge 167:e84263d55307 6233 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6234 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
AnnaBridge 167:e84263d55307 6235 #define DMA_LIFCR_CHTIF2_Pos (20U)
AnnaBridge 167:e84263d55307 6236 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6237 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
AnnaBridge 167:e84263d55307 6238 #define DMA_LIFCR_CTEIF2_Pos (19U)
AnnaBridge 167:e84263d55307 6239 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6240 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
AnnaBridge 167:e84263d55307 6241 #define DMA_LIFCR_CDMEIF2_Pos (18U)
AnnaBridge 167:e84263d55307 6242 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6243 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
AnnaBridge 167:e84263d55307 6244 #define DMA_LIFCR_CFEIF2_Pos (16U)
AnnaBridge 167:e84263d55307 6245 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6246 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
AnnaBridge 167:e84263d55307 6247 #define DMA_LIFCR_CTCIF1_Pos (11U)
AnnaBridge 167:e84263d55307 6248 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6249 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
AnnaBridge 167:e84263d55307 6250 #define DMA_LIFCR_CHTIF1_Pos (10U)
AnnaBridge 167:e84263d55307 6251 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6252 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
AnnaBridge 167:e84263d55307 6253 #define DMA_LIFCR_CTEIF1_Pos (9U)
AnnaBridge 167:e84263d55307 6254 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6255 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
AnnaBridge 167:e84263d55307 6256 #define DMA_LIFCR_CDMEIF1_Pos (8U)
AnnaBridge 167:e84263d55307 6257 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6258 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
AnnaBridge 167:e84263d55307 6259 #define DMA_LIFCR_CFEIF1_Pos (6U)
AnnaBridge 167:e84263d55307 6260 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6261 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
AnnaBridge 167:e84263d55307 6262 #define DMA_LIFCR_CTCIF0_Pos (5U)
AnnaBridge 167:e84263d55307 6263 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6264 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
AnnaBridge 167:e84263d55307 6265 #define DMA_LIFCR_CHTIF0_Pos (4U)
AnnaBridge 167:e84263d55307 6266 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6267 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
AnnaBridge 167:e84263d55307 6268 #define DMA_LIFCR_CTEIF0_Pos (3U)
AnnaBridge 167:e84263d55307 6269 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6270 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
AnnaBridge 167:e84263d55307 6271 #define DMA_LIFCR_CDMEIF0_Pos (2U)
AnnaBridge 167:e84263d55307 6272 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6273 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
AnnaBridge 167:e84263d55307 6274 #define DMA_LIFCR_CFEIF0_Pos (0U)
AnnaBridge 167:e84263d55307 6275 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6276 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
<> 144:ef7eb2e8f9f7 6277
<> 144:ef7eb2e8f9f7 6278 /******************** Bits definition for DMA_HIFCR register ****************/
AnnaBridge 167:e84263d55307 6279 #define DMA_HIFCR_CTCIF7_Pos (27U)
AnnaBridge 167:e84263d55307 6280 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 6281 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
AnnaBridge 167:e84263d55307 6282 #define DMA_HIFCR_CHTIF7_Pos (26U)
AnnaBridge 167:e84263d55307 6283 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 6284 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
AnnaBridge 167:e84263d55307 6285 #define DMA_HIFCR_CTEIF7_Pos (25U)
AnnaBridge 167:e84263d55307 6286 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 6287 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
AnnaBridge 167:e84263d55307 6288 #define DMA_HIFCR_CDMEIF7_Pos (24U)
AnnaBridge 167:e84263d55307 6289 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 6290 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
AnnaBridge 167:e84263d55307 6291 #define DMA_HIFCR_CFEIF7_Pos (22U)
AnnaBridge 167:e84263d55307 6292 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6293 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
AnnaBridge 167:e84263d55307 6294 #define DMA_HIFCR_CTCIF6_Pos (21U)
AnnaBridge 167:e84263d55307 6295 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6296 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
AnnaBridge 167:e84263d55307 6297 #define DMA_HIFCR_CHTIF6_Pos (20U)
AnnaBridge 167:e84263d55307 6298 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6299 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
AnnaBridge 167:e84263d55307 6300 #define DMA_HIFCR_CTEIF6_Pos (19U)
AnnaBridge 167:e84263d55307 6301 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6302 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
AnnaBridge 167:e84263d55307 6303 #define DMA_HIFCR_CDMEIF6_Pos (18U)
AnnaBridge 167:e84263d55307 6304 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6305 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
AnnaBridge 167:e84263d55307 6306 #define DMA_HIFCR_CFEIF6_Pos (16U)
AnnaBridge 167:e84263d55307 6307 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6308 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
AnnaBridge 167:e84263d55307 6309 #define DMA_HIFCR_CTCIF5_Pos (11U)
AnnaBridge 167:e84263d55307 6310 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6311 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
AnnaBridge 167:e84263d55307 6312 #define DMA_HIFCR_CHTIF5_Pos (10U)
AnnaBridge 167:e84263d55307 6313 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6314 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
AnnaBridge 167:e84263d55307 6315 #define DMA_HIFCR_CTEIF5_Pos (9U)
AnnaBridge 167:e84263d55307 6316 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6317 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
AnnaBridge 167:e84263d55307 6318 #define DMA_HIFCR_CDMEIF5_Pos (8U)
AnnaBridge 167:e84263d55307 6319 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6320 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
AnnaBridge 167:e84263d55307 6321 #define DMA_HIFCR_CFEIF5_Pos (6U)
AnnaBridge 167:e84263d55307 6322 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6323 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
AnnaBridge 167:e84263d55307 6324 #define DMA_HIFCR_CTCIF4_Pos (5U)
AnnaBridge 167:e84263d55307 6325 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6326 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
AnnaBridge 167:e84263d55307 6327 #define DMA_HIFCR_CHTIF4_Pos (4U)
AnnaBridge 167:e84263d55307 6328 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6329 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
AnnaBridge 167:e84263d55307 6330 #define DMA_HIFCR_CTEIF4_Pos (3U)
AnnaBridge 167:e84263d55307 6331 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6332 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
AnnaBridge 167:e84263d55307 6333 #define DMA_HIFCR_CDMEIF4_Pos (2U)
AnnaBridge 167:e84263d55307 6334 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6335 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
AnnaBridge 167:e84263d55307 6336 #define DMA_HIFCR_CFEIF4_Pos (0U)
AnnaBridge 167:e84263d55307 6337 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6338 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
AnnaBridge 167:e84263d55307 6339
AnnaBridge 167:e84263d55307 6340 /****************** Bit definition for DMA_SxPAR register ********************/
AnnaBridge 167:e84263d55307 6341 #define DMA_SxPAR_PA_Pos (0U)
AnnaBridge 167:e84263d55307 6342 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6343 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 167:e84263d55307 6344
AnnaBridge 167:e84263d55307 6345 /****************** Bit definition for DMA_SxM0AR register ********************/
AnnaBridge 167:e84263d55307 6346 #define DMA_SxM0AR_M0A_Pos (0U)
AnnaBridge 167:e84263d55307 6347 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6348 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
AnnaBridge 167:e84263d55307 6349
AnnaBridge 167:e84263d55307 6350 /****************** Bit definition for DMA_SxM1AR register ********************/
AnnaBridge 167:e84263d55307 6351 #define DMA_SxM1AR_M1A_Pos (0U)
AnnaBridge 167:e84263d55307 6352 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6353 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6354
<> 144:ef7eb2e8f9f7 6355
<> 144:ef7eb2e8f9f7 6356 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6357 /* */
<> 144:ef7eb2e8f9f7 6358 /* AHB Master DMA2D Controller (DMA2D) */
<> 144:ef7eb2e8f9f7 6359 /* */
<> 144:ef7eb2e8f9f7 6360 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6361
<> 144:ef7eb2e8f9f7 6362 /******************** Bit definition for DMA2D_CR register ******************/
<> 144:ef7eb2e8f9f7 6363
AnnaBridge 167:e84263d55307 6364 #define DMA2D_CR_START_Pos (0U)
AnnaBridge 167:e84263d55307 6365 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6366 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
AnnaBridge 167:e84263d55307 6367 #define DMA2D_CR_SUSP_Pos (1U)
AnnaBridge 167:e84263d55307 6368 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6369 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
AnnaBridge 167:e84263d55307 6370 #define DMA2D_CR_ABORT_Pos (2U)
AnnaBridge 167:e84263d55307 6371 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6372 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
AnnaBridge 167:e84263d55307 6373 #define DMA2D_CR_TEIE_Pos (8U)
AnnaBridge 167:e84263d55307 6374 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6375 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 167:e84263d55307 6376 #define DMA2D_CR_TCIE_Pos (9U)
AnnaBridge 167:e84263d55307 6377 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6378 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
AnnaBridge 167:e84263d55307 6379 #define DMA2D_CR_TWIE_Pos (10U)
AnnaBridge 167:e84263d55307 6380 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6381 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
AnnaBridge 167:e84263d55307 6382 #define DMA2D_CR_CAEIE_Pos (11U)
AnnaBridge 167:e84263d55307 6383 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6384 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
AnnaBridge 167:e84263d55307 6385 #define DMA2D_CR_CTCIE_Pos (12U)
AnnaBridge 167:e84263d55307 6386 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6387 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
AnnaBridge 167:e84263d55307 6388 #define DMA2D_CR_CEIE_Pos (13U)
AnnaBridge 167:e84263d55307 6389 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6390 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
AnnaBridge 167:e84263d55307 6391 #define DMA2D_CR_MODE_Pos (16U)
AnnaBridge 167:e84263d55307 6392 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 6393 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
AnnaBridge 167:e84263d55307 6394 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6395 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
<> 144:ef7eb2e8f9f7 6396
<> 144:ef7eb2e8f9f7 6397 /******************** Bit definition for DMA2D_ISR register *****************/
<> 144:ef7eb2e8f9f7 6398
AnnaBridge 167:e84263d55307 6399 #define DMA2D_ISR_TEIF_Pos (0U)
AnnaBridge 167:e84263d55307 6400 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6401 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 167:e84263d55307 6402 #define DMA2D_ISR_TCIF_Pos (1U)
AnnaBridge 167:e84263d55307 6403 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6404 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
AnnaBridge 167:e84263d55307 6405 #define DMA2D_ISR_TWIF_Pos (2U)
AnnaBridge 167:e84263d55307 6406 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6407 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
AnnaBridge 167:e84263d55307 6408 #define DMA2D_ISR_CAEIF_Pos (3U)
AnnaBridge 167:e84263d55307 6409 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6410 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
AnnaBridge 167:e84263d55307 6411 #define DMA2D_ISR_CTCIF_Pos (4U)
AnnaBridge 167:e84263d55307 6412 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6413 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
AnnaBridge 167:e84263d55307 6414 #define DMA2D_ISR_CEIF_Pos (5U)
AnnaBridge 167:e84263d55307 6415 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6416 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6417
<> 144:ef7eb2e8f9f7 6418 /******************** Bit definition for DMA2D_IFCR register ****************/
<> 144:ef7eb2e8f9f7 6419
AnnaBridge 167:e84263d55307 6420 #define DMA2D_IFCR_CTEIF_Pos (0U)
AnnaBridge 167:e84263d55307 6421 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6422 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
AnnaBridge 167:e84263d55307 6423 #define DMA2D_IFCR_CTCIF_Pos (1U)
AnnaBridge 167:e84263d55307 6424 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6425 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
AnnaBridge 167:e84263d55307 6426 #define DMA2D_IFCR_CTWIF_Pos (2U)
AnnaBridge 167:e84263d55307 6427 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6428 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
AnnaBridge 167:e84263d55307 6429 #define DMA2D_IFCR_CAECIF_Pos (3U)
AnnaBridge 167:e84263d55307 6430 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6431 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
AnnaBridge 167:e84263d55307 6432 #define DMA2D_IFCR_CCTCIF_Pos (4U)
AnnaBridge 167:e84263d55307 6433 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6434 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
AnnaBridge 167:e84263d55307 6435 #define DMA2D_IFCR_CCEIF_Pos (5U)
AnnaBridge 167:e84263d55307 6436 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6437 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6438
<> 144:ef7eb2e8f9f7 6439 /* Legacy defines */
<> 144:ef7eb2e8f9f7 6440 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6441 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 6442 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
<> 144:ef7eb2e8f9f7 6443 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6444 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 144:ef7eb2e8f9f7 6445 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
<> 144:ef7eb2e8f9f7 6446
<> 144:ef7eb2e8f9f7 6447 /******************** Bit definition for DMA2D_FGMAR register ***************/
<> 144:ef7eb2e8f9f7 6448
AnnaBridge 167:e84263d55307 6449 #define DMA2D_FGMAR_MA_Pos (0U)
AnnaBridge 167:e84263d55307 6450 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6451 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6452
<> 144:ef7eb2e8f9f7 6453 /******************** Bit definition for DMA2D_FGOR register ****************/
<> 144:ef7eb2e8f9f7 6454
AnnaBridge 167:e84263d55307 6455 #define DMA2D_FGOR_LO_Pos (0U)
AnnaBridge 167:e84263d55307 6456 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 167:e84263d55307 6457 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 6458
<> 144:ef7eb2e8f9f7 6459 /******************** Bit definition for DMA2D_BGMAR register ***************/
<> 144:ef7eb2e8f9f7 6460
AnnaBridge 167:e84263d55307 6461 #define DMA2D_BGMAR_MA_Pos (0U)
AnnaBridge 167:e84263d55307 6462 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6463 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6464
<> 144:ef7eb2e8f9f7 6465 /******************** Bit definition for DMA2D_BGOR register ****************/
<> 144:ef7eb2e8f9f7 6466
AnnaBridge 167:e84263d55307 6467 #define DMA2D_BGOR_LO_Pos (0U)
AnnaBridge 167:e84263d55307 6468 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 167:e84263d55307 6469 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 6470
<> 144:ef7eb2e8f9f7 6471 /******************** Bit definition for DMA2D_FGPFCCR register *************/
<> 144:ef7eb2e8f9f7 6472
AnnaBridge 167:e84263d55307 6473 #define DMA2D_FGPFCCR_CM_Pos (0U)
AnnaBridge 167:e84263d55307 6474 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 6475 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 167:e84263d55307 6476 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6477 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6478 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6479 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6480 #define DMA2D_FGPFCCR_CCM_Pos (4U)
AnnaBridge 167:e84263d55307 6481 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6482 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 167:e84263d55307 6483 #define DMA2D_FGPFCCR_START_Pos (5U)
AnnaBridge 167:e84263d55307 6484 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6485 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
AnnaBridge 167:e84263d55307 6486 #define DMA2D_FGPFCCR_CS_Pos (8U)
AnnaBridge 167:e84263d55307 6487 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 6488 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 167:e84263d55307 6489 #define DMA2D_FGPFCCR_AM_Pos (16U)
AnnaBridge 167:e84263d55307 6490 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 6491 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 167:e84263d55307 6492 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6493 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6494 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
AnnaBridge 167:e84263d55307 6495 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 6496 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
<> 144:ef7eb2e8f9f7 6497
<> 144:ef7eb2e8f9f7 6498 /******************** Bit definition for DMA2D_FGCOLR register **************/
<> 144:ef7eb2e8f9f7 6499
AnnaBridge 167:e84263d55307 6500 #define DMA2D_FGCOLR_BLUE_Pos (0U)
AnnaBridge 167:e84263d55307 6501 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 6502 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 167:e84263d55307 6503 #define DMA2D_FGCOLR_GREEN_Pos (8U)
AnnaBridge 167:e84263d55307 6504 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 6505 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 167:e84263d55307 6506 #define DMA2D_FGCOLR_RED_Pos (16U)
AnnaBridge 167:e84263d55307 6507 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 6508 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
<> 144:ef7eb2e8f9f7 6509
<> 144:ef7eb2e8f9f7 6510 /******************** Bit definition for DMA2D_BGPFCCR register *************/
<> 144:ef7eb2e8f9f7 6511
AnnaBridge 167:e84263d55307 6512 #define DMA2D_BGPFCCR_CM_Pos (0U)
AnnaBridge 167:e84263d55307 6513 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 6514 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
AnnaBridge 167:e84263d55307 6515 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6516 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6517 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6518 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
AnnaBridge 167:e84263d55307 6519 #define DMA2D_BGPFCCR_CCM_Pos (4U)
AnnaBridge 167:e84263d55307 6520 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6521 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
AnnaBridge 167:e84263d55307 6522 #define DMA2D_BGPFCCR_START_Pos (5U)
AnnaBridge 167:e84263d55307 6523 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6524 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
AnnaBridge 167:e84263d55307 6525 #define DMA2D_BGPFCCR_CS_Pos (8U)
AnnaBridge 167:e84263d55307 6526 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 6527 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
AnnaBridge 167:e84263d55307 6528 #define DMA2D_BGPFCCR_AM_Pos (16U)
AnnaBridge 167:e84263d55307 6529 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 6530 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
AnnaBridge 167:e84263d55307 6531 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6532 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6533 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
AnnaBridge 167:e84263d55307 6534 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 6535 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
<> 144:ef7eb2e8f9f7 6536
<> 144:ef7eb2e8f9f7 6537 /******************** Bit definition for DMA2D_BGCOLR register **************/
<> 144:ef7eb2e8f9f7 6538
AnnaBridge 167:e84263d55307 6539 #define DMA2D_BGCOLR_BLUE_Pos (0U)
AnnaBridge 167:e84263d55307 6540 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 6541 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
AnnaBridge 167:e84263d55307 6542 #define DMA2D_BGCOLR_GREEN_Pos (8U)
AnnaBridge 167:e84263d55307 6543 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 6544 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
AnnaBridge 167:e84263d55307 6545 #define DMA2D_BGCOLR_RED_Pos (16U)
AnnaBridge 167:e84263d55307 6546 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 6547 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
<> 144:ef7eb2e8f9f7 6548
<> 144:ef7eb2e8f9f7 6549 /******************** Bit definition for DMA2D_FGCMAR register **************/
<> 144:ef7eb2e8f9f7 6550
AnnaBridge 167:e84263d55307 6551 #define DMA2D_FGCMAR_MA_Pos (0U)
AnnaBridge 167:e84263d55307 6552 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6553 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6554
<> 144:ef7eb2e8f9f7 6555 /******************** Bit definition for DMA2D_BGCMAR register **************/
<> 144:ef7eb2e8f9f7 6556
AnnaBridge 167:e84263d55307 6557 #define DMA2D_BGCMAR_MA_Pos (0U)
AnnaBridge 167:e84263d55307 6558 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6559 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6560
<> 144:ef7eb2e8f9f7 6561 /******************** Bit definition for DMA2D_OPFCCR register **************/
<> 144:ef7eb2e8f9f7 6562
AnnaBridge 167:e84263d55307 6563 #define DMA2D_OPFCCR_CM_Pos (0U)
AnnaBridge 167:e84263d55307 6564 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 6565 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
AnnaBridge 167:e84263d55307 6566 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6567 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6568 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 6569
<> 144:ef7eb2e8f9f7 6570 /******************** Bit definition for DMA2D_OCOLR register ***************/
<> 144:ef7eb2e8f9f7 6571
<> 144:ef7eb2e8f9f7 6572 /*!<Mode_ARGB8888/RGB888 */
<> 144:ef7eb2e8f9f7 6573
AnnaBridge 167:e84263d55307 6574 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
AnnaBridge 167:e84263d55307 6575 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
AnnaBridge 167:e84263d55307 6576 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
AnnaBridge 167:e84263d55307 6577 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 6578
<> 144:ef7eb2e8f9f7 6579 /*!<Mode_RGB565 */
AnnaBridge 167:e84263d55307 6580 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
AnnaBridge 167:e84263d55307 6581 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
AnnaBridge 167:e84263d55307 6582 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
<> 144:ef7eb2e8f9f7 6583
<> 144:ef7eb2e8f9f7 6584 /*!<Mode_ARGB1555 */
AnnaBridge 167:e84263d55307 6585 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
AnnaBridge 167:e84263d55307 6586 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
AnnaBridge 167:e84263d55307 6587 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
AnnaBridge 167:e84263d55307 6588 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 6589
<> 144:ef7eb2e8f9f7 6590 /*!<Mode_ARGB4444 */
AnnaBridge 167:e84263d55307 6591 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
AnnaBridge 167:e84263d55307 6592 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
AnnaBridge 167:e84263d55307 6593 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
AnnaBridge 167:e84263d55307 6594 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
<> 144:ef7eb2e8f9f7 6595
<> 144:ef7eb2e8f9f7 6596 /******************** Bit definition for DMA2D_OMAR register ****************/
<> 144:ef7eb2e8f9f7 6597
AnnaBridge 167:e84263d55307 6598 #define DMA2D_OMAR_MA_Pos (0U)
AnnaBridge 167:e84263d55307 6599 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 6600 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
<> 144:ef7eb2e8f9f7 6601
<> 144:ef7eb2e8f9f7 6602 /******************** Bit definition for DMA2D_OOR register *****************/
<> 144:ef7eb2e8f9f7 6603
AnnaBridge 167:e84263d55307 6604 #define DMA2D_OOR_LO_Pos (0U)
AnnaBridge 167:e84263d55307 6605 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
AnnaBridge 167:e84263d55307 6606 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
<> 144:ef7eb2e8f9f7 6607
<> 144:ef7eb2e8f9f7 6608 /******************** Bit definition for DMA2D_NLR register *****************/
<> 144:ef7eb2e8f9f7 6609
AnnaBridge 167:e84263d55307 6610 #define DMA2D_NLR_NL_Pos (0U)
AnnaBridge 167:e84263d55307 6611 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 6612 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
AnnaBridge 167:e84263d55307 6613 #define DMA2D_NLR_PL_Pos (16U)
AnnaBridge 167:e84263d55307 6614 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
AnnaBridge 167:e84263d55307 6615 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
<> 144:ef7eb2e8f9f7 6616
<> 144:ef7eb2e8f9f7 6617 /******************** Bit definition for DMA2D_LWR register *****************/
<> 144:ef7eb2e8f9f7 6618
AnnaBridge 167:e84263d55307 6619 #define DMA2D_LWR_LW_Pos (0U)
AnnaBridge 167:e84263d55307 6620 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 6621 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
<> 144:ef7eb2e8f9f7 6622
<> 144:ef7eb2e8f9f7 6623 /******************** Bit definition for DMA2D_AMTCR register ***************/
<> 144:ef7eb2e8f9f7 6624
AnnaBridge 167:e84263d55307 6625 #define DMA2D_AMTCR_EN_Pos (0U)
AnnaBridge 167:e84263d55307 6626 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6627 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
AnnaBridge 167:e84263d55307 6628 #define DMA2D_AMTCR_DT_Pos (8U)
AnnaBridge 167:e84263d55307 6629 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 6630 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
<> 144:ef7eb2e8f9f7 6631
<> 144:ef7eb2e8f9f7 6632 /******************** Bit definition for DMA2D_FGCLUT register **************/
<> 144:ef7eb2e8f9f7 6633
<> 144:ef7eb2e8f9f7 6634 /******************** Bit definition for DMA2D_BGCLUT register **************/
<> 144:ef7eb2e8f9f7 6635
<> 144:ef7eb2e8f9f7 6636
<> 144:ef7eb2e8f9f7 6637 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6638 /* */
<> 144:ef7eb2e8f9f7 6639 /* External Interrupt/Event Controller */
<> 144:ef7eb2e8f9f7 6640 /* */
<> 144:ef7eb2e8f9f7 6641 /******************************************************************************/
<> 144:ef7eb2e8f9f7 6642 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 167:e84263d55307 6643 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 167:e84263d55307 6644 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6645 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 167:e84263d55307 6646 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 167:e84263d55307 6647 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6648 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 167:e84263d55307 6649 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 167:e84263d55307 6650 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6651 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 167:e84263d55307 6652 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 167:e84263d55307 6653 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6654 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 167:e84263d55307 6655 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 167:e84263d55307 6656 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6657 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 167:e84263d55307 6658 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 167:e84263d55307 6659 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6660 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 167:e84263d55307 6661 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 167:e84263d55307 6662 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6663 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 167:e84263d55307 6664 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 167:e84263d55307 6665 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6666 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 167:e84263d55307 6667 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 167:e84263d55307 6668 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6669 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 167:e84263d55307 6670 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 167:e84263d55307 6671 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6672 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 167:e84263d55307 6673 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 167:e84263d55307 6674 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6675 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 167:e84263d55307 6676 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 167:e84263d55307 6677 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6678 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 167:e84263d55307 6679 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 167:e84263d55307 6680 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6681 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 167:e84263d55307 6682 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 167:e84263d55307 6683 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6684 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 167:e84263d55307 6685 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 167:e84263d55307 6686 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6687 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 167:e84263d55307 6688 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 167:e84263d55307 6689 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 6690 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 167:e84263d55307 6691 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 167:e84263d55307 6692 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6693 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 167:e84263d55307 6694 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 167:e84263d55307 6695 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6696 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 167:e84263d55307 6697 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 167:e84263d55307 6698 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6699 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 167:e84263d55307 6700 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 167:e84263d55307 6701 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6702 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 167:e84263d55307 6703 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 167:e84263d55307 6704 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6705 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 167:e84263d55307 6706 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 167:e84263d55307 6707 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6708 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 167:e84263d55307 6709 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 167:e84263d55307 6710 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6711 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 167:e84263d55307 6712
AnnaBridge 167:e84263d55307 6713 /* Reference Defines */
AnnaBridge 167:e84263d55307 6714 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 167:e84263d55307 6715 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 167:e84263d55307 6716 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 167:e84263d55307 6717 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 167:e84263d55307 6718 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 167:e84263d55307 6719 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 167:e84263d55307 6720 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 167:e84263d55307 6721 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 167:e84263d55307 6722 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 167:e84263d55307 6723 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 167:e84263d55307 6724 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 167:e84263d55307 6725 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 167:e84263d55307 6726 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 167:e84263d55307 6727 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 167:e84263d55307 6728 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 167:e84263d55307 6729 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 167:e84263d55307 6730 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 167:e84263d55307 6731 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 167:e84263d55307 6732 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 167:e84263d55307 6733 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 167:e84263d55307 6734 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 167:e84263d55307 6735 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 167:e84263d55307 6736 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 167:e84263d55307 6737 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 167:e84263d55307 6738 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
AnnaBridge 167:e84263d55307 6739 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
<> 144:ef7eb2e8f9f7 6740
<> 144:ef7eb2e8f9f7 6741 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 167:e84263d55307 6742 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 167:e84263d55307 6743 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6744 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 167:e84263d55307 6745 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 167:e84263d55307 6746 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6747 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 167:e84263d55307 6748 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 167:e84263d55307 6749 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6750 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 167:e84263d55307 6751 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 167:e84263d55307 6752 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6753 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 167:e84263d55307 6754 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 167:e84263d55307 6755 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6756 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 167:e84263d55307 6757 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 167:e84263d55307 6758 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6759 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 167:e84263d55307 6760 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 167:e84263d55307 6761 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6762 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 167:e84263d55307 6763 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 167:e84263d55307 6764 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6765 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 167:e84263d55307 6766 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 167:e84263d55307 6767 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6768 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 167:e84263d55307 6769 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 167:e84263d55307 6770 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6771 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 167:e84263d55307 6772 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 167:e84263d55307 6773 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6774 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 167:e84263d55307 6775 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 167:e84263d55307 6776 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6777 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 167:e84263d55307 6778 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 167:e84263d55307 6779 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6780 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 167:e84263d55307 6781 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 167:e84263d55307 6782 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6783 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 167:e84263d55307 6784 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 167:e84263d55307 6785 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6786 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 167:e84263d55307 6787 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 167:e84263d55307 6788 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 6789 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 167:e84263d55307 6790 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 167:e84263d55307 6791 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6792 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 167:e84263d55307 6793 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 167:e84263d55307 6794 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6795 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 167:e84263d55307 6796 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 167:e84263d55307 6797 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6798 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 167:e84263d55307 6799 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 167:e84263d55307 6800 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6801 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 167:e84263d55307 6802 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 167:e84263d55307 6803 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6804 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 167:e84263d55307 6805 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 167:e84263d55307 6806 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6807 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 167:e84263d55307 6808 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 167:e84263d55307 6809 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6810 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 167:e84263d55307 6811
AnnaBridge 167:e84263d55307 6812 /* Reference Defines */
AnnaBridge 167:e84263d55307 6813 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 167:e84263d55307 6814 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 167:e84263d55307 6815 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 167:e84263d55307 6816 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 167:e84263d55307 6817 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 167:e84263d55307 6818 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 167:e84263d55307 6819 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 167:e84263d55307 6820 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 167:e84263d55307 6821 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 167:e84263d55307 6822 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 167:e84263d55307 6823 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 167:e84263d55307 6824 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 167:e84263d55307 6825 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 167:e84263d55307 6826 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 167:e84263d55307 6827 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 167:e84263d55307 6828 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 167:e84263d55307 6829 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 167:e84263d55307 6830 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 167:e84263d55307 6831 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 167:e84263d55307 6832 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 167:e84263d55307 6833 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 167:e84263d55307 6834 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 167:e84263d55307 6835 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 144:ef7eb2e8f9f7 6836
<> 144:ef7eb2e8f9f7 6837 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 167:e84263d55307 6838 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 167:e84263d55307 6839 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6840 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 167:e84263d55307 6841 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 167:e84263d55307 6842 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6843 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 167:e84263d55307 6844 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 167:e84263d55307 6845 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6846 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 167:e84263d55307 6847 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 167:e84263d55307 6848 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6849 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 167:e84263d55307 6850 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 167:e84263d55307 6851 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6852 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 167:e84263d55307 6853 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 167:e84263d55307 6854 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6855 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 167:e84263d55307 6856 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 167:e84263d55307 6857 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6858 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 167:e84263d55307 6859 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 167:e84263d55307 6860 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6861 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 167:e84263d55307 6862 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 167:e84263d55307 6863 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6864 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 167:e84263d55307 6865 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 167:e84263d55307 6866 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6867 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 167:e84263d55307 6868 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 167:e84263d55307 6869 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6870 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 167:e84263d55307 6871 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 167:e84263d55307 6872 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6873 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 167:e84263d55307 6874 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 167:e84263d55307 6875 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6876 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 167:e84263d55307 6877 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 167:e84263d55307 6878 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6879 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 167:e84263d55307 6880 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 167:e84263d55307 6881 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6882 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 167:e84263d55307 6883 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 167:e84263d55307 6884 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 6885 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 167:e84263d55307 6886 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 167:e84263d55307 6887 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6888 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 167:e84263d55307 6889 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 167:e84263d55307 6890 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6891 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 167:e84263d55307 6892 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 167:e84263d55307 6893 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6894 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 167:e84263d55307 6895 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 167:e84263d55307 6896 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6897 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 167:e84263d55307 6898 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 167:e84263d55307 6899 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6900 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 167:e84263d55307 6901 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 167:e84263d55307 6902 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6903 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 167:e84263d55307 6904 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 167:e84263d55307 6905 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6906 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 6907
<> 144:ef7eb2e8f9f7 6908 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 167:e84263d55307 6909 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 167:e84263d55307 6910 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6911 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 167:e84263d55307 6912 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 167:e84263d55307 6913 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6914 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 167:e84263d55307 6915 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 167:e84263d55307 6916 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6917 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 167:e84263d55307 6918 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 167:e84263d55307 6919 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6920 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 167:e84263d55307 6921 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 167:e84263d55307 6922 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6923 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 167:e84263d55307 6924 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 167:e84263d55307 6925 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6926 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 167:e84263d55307 6927 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 167:e84263d55307 6928 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 6929 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 167:e84263d55307 6930 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 167:e84263d55307 6931 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 6932 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 167:e84263d55307 6933 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 167:e84263d55307 6934 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 6935 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 167:e84263d55307 6936 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 167:e84263d55307 6937 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 6938 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 167:e84263d55307 6939 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 167:e84263d55307 6940 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 6941 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 167:e84263d55307 6942 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 167:e84263d55307 6943 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 6944 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 167:e84263d55307 6945 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 167:e84263d55307 6946 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 6947 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 167:e84263d55307 6948 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 167:e84263d55307 6949 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 6950 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 167:e84263d55307 6951 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 167:e84263d55307 6952 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 6953 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 167:e84263d55307 6954 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 167:e84263d55307 6955 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 6956 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 167:e84263d55307 6957 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 167:e84263d55307 6958 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 6959 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 167:e84263d55307 6960 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 167:e84263d55307 6961 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 6962 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 167:e84263d55307 6963 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 167:e84263d55307 6964 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 6965 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 167:e84263d55307 6966 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 167:e84263d55307 6967 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 6968 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 167:e84263d55307 6969 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 167:e84263d55307 6970 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 6971 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 167:e84263d55307 6972 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 167:e84263d55307 6973 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 6974 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 167:e84263d55307 6975 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 167:e84263d55307 6976 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 6977 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
<> 144:ef7eb2e8f9f7 6978
<> 144:ef7eb2e8f9f7 6979 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 167:e84263d55307 6980 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 167:e84263d55307 6981 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 6982 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 167:e84263d55307 6983 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 167:e84263d55307 6984 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 6985 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 167:e84263d55307 6986 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 167:e84263d55307 6987 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 6988 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 167:e84263d55307 6989 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 167:e84263d55307 6990 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 6991 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 167:e84263d55307 6992 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 167:e84263d55307 6993 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 6994 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 167:e84263d55307 6995 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 167:e84263d55307 6996 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 6997 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 167:e84263d55307 6998 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 167:e84263d55307 6999 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7000 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 167:e84263d55307 7001 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 167:e84263d55307 7002 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7003 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 167:e84263d55307 7004 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 167:e84263d55307 7005 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7006 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 167:e84263d55307 7007 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 167:e84263d55307 7008 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7009 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 167:e84263d55307 7010 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 167:e84263d55307 7011 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7012 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 167:e84263d55307 7013 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 167:e84263d55307 7014 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7015 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 167:e84263d55307 7016 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 167:e84263d55307 7017 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7018 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 167:e84263d55307 7019 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 167:e84263d55307 7020 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7021 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 167:e84263d55307 7022 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 167:e84263d55307 7023 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7024 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 167:e84263d55307 7025 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 167:e84263d55307 7026 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7027 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 167:e84263d55307 7028 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 167:e84263d55307 7029 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7030 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 167:e84263d55307 7031 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 167:e84263d55307 7032 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7033 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 167:e84263d55307 7034 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 167:e84263d55307 7035 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7036 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 167:e84263d55307 7037 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 167:e84263d55307 7038 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7039 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 167:e84263d55307 7040 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 167:e84263d55307 7041 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7042 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 167:e84263d55307 7043 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 167:e84263d55307 7044 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7045 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 167:e84263d55307 7046 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 167:e84263d55307 7047 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7048 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
<> 144:ef7eb2e8f9f7 7049
<> 144:ef7eb2e8f9f7 7050 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 167:e84263d55307 7051 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 167:e84263d55307 7052 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7053 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 167:e84263d55307 7054 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 167:e84263d55307 7055 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7056 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 167:e84263d55307 7057 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 167:e84263d55307 7058 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7059 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 167:e84263d55307 7060 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 167:e84263d55307 7061 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7062 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 167:e84263d55307 7063 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 167:e84263d55307 7064 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7065 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 167:e84263d55307 7066 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 167:e84263d55307 7067 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7068 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 167:e84263d55307 7069 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 167:e84263d55307 7070 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7071 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 167:e84263d55307 7072 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 167:e84263d55307 7073 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7074 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 167:e84263d55307 7075 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 167:e84263d55307 7076 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7077 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 167:e84263d55307 7078 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 167:e84263d55307 7079 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7080 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 167:e84263d55307 7081 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 167:e84263d55307 7082 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7083 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 167:e84263d55307 7084 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 167:e84263d55307 7085 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7086 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 167:e84263d55307 7087 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 167:e84263d55307 7088 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7089 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 167:e84263d55307 7090 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 167:e84263d55307 7091 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7092 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 167:e84263d55307 7093 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 167:e84263d55307 7094 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7095 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 167:e84263d55307 7096 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 167:e84263d55307 7097 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7098 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 167:e84263d55307 7099 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 167:e84263d55307 7100 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7101 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 167:e84263d55307 7102 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 167:e84263d55307 7103 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7104 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 167:e84263d55307 7105 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 167:e84263d55307 7106 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7107 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 167:e84263d55307 7108 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 167:e84263d55307 7109 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7110 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 167:e84263d55307 7111 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 167:e84263d55307 7112 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7113 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 167:e84263d55307 7114 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 167:e84263d55307 7115 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7116 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 167:e84263d55307 7117 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 167:e84263d55307 7118 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7119 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
<> 144:ef7eb2e8f9f7 7120
<> 144:ef7eb2e8f9f7 7121 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7122 /* */
<> 144:ef7eb2e8f9f7 7123 /* FLASH */
<> 144:ef7eb2e8f9f7 7124 /* */
<> 144:ef7eb2e8f9f7 7125 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7126 /******************* Bits definition for FLASH_ACR register *****************/
AnnaBridge 167:e84263d55307 7127 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 167:e84263d55307 7128 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7129 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
AnnaBridge 167:e84263d55307 7130 #define FLASH_ACR_LATENCY_0WS 0x00000000U
AnnaBridge 167:e84263d55307 7131 #define FLASH_ACR_LATENCY_1WS 0x00000001U
AnnaBridge 167:e84263d55307 7132 #define FLASH_ACR_LATENCY_2WS 0x00000002U
AnnaBridge 167:e84263d55307 7133 #define FLASH_ACR_LATENCY_3WS 0x00000003U
AnnaBridge 167:e84263d55307 7134 #define FLASH_ACR_LATENCY_4WS 0x00000004U
AnnaBridge 167:e84263d55307 7135 #define FLASH_ACR_LATENCY_5WS 0x00000005U
AnnaBridge 167:e84263d55307 7136 #define FLASH_ACR_LATENCY_6WS 0x00000006U
AnnaBridge 167:e84263d55307 7137 #define FLASH_ACR_LATENCY_7WS 0x00000007U
AnnaBridge 167:e84263d55307 7138
AnnaBridge 167:e84263d55307 7139 #define FLASH_ACR_LATENCY_8WS 0x00000008U
AnnaBridge 167:e84263d55307 7140 #define FLASH_ACR_LATENCY_9WS 0x00000009U
AnnaBridge 167:e84263d55307 7141 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
AnnaBridge 167:e84263d55307 7142 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
AnnaBridge 167:e84263d55307 7143 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
AnnaBridge 167:e84263d55307 7144 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
AnnaBridge 167:e84263d55307 7145 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
AnnaBridge 167:e84263d55307 7146 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
AnnaBridge 167:e84263d55307 7147 #define FLASH_ACR_PRFTEN_Pos (8U)
AnnaBridge 167:e84263d55307 7148 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7149 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
AnnaBridge 167:e84263d55307 7150 #define FLASH_ACR_ICEN_Pos (9U)
AnnaBridge 167:e84263d55307 7151 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7152 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
AnnaBridge 167:e84263d55307 7153 #define FLASH_ACR_DCEN_Pos (10U)
AnnaBridge 167:e84263d55307 7154 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7155 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
AnnaBridge 167:e84263d55307 7156 #define FLASH_ACR_ICRST_Pos (11U)
AnnaBridge 167:e84263d55307 7157 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7158 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
AnnaBridge 167:e84263d55307 7159 #define FLASH_ACR_DCRST_Pos (12U)
AnnaBridge 167:e84263d55307 7160 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7161 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
AnnaBridge 167:e84263d55307 7162 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
AnnaBridge 167:e84263d55307 7163 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
AnnaBridge 167:e84263d55307 7164 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
AnnaBridge 167:e84263d55307 7165 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
AnnaBridge 167:e84263d55307 7166 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
AnnaBridge 167:e84263d55307 7167 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
<> 144:ef7eb2e8f9f7 7168
<> 144:ef7eb2e8f9f7 7169 /******************* Bits definition for FLASH_SR register ******************/
AnnaBridge 167:e84263d55307 7170 #define FLASH_SR_EOP_Pos (0U)
AnnaBridge 167:e84263d55307 7171 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7172 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
AnnaBridge 167:e84263d55307 7173 #define FLASH_SR_SOP_Pos (1U)
AnnaBridge 167:e84263d55307 7174 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7175 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
AnnaBridge 167:e84263d55307 7176 #define FLASH_SR_WRPERR_Pos (4U)
AnnaBridge 167:e84263d55307 7177 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7178 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
AnnaBridge 167:e84263d55307 7179 #define FLASH_SR_PGAERR_Pos (5U)
AnnaBridge 167:e84263d55307 7180 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7181 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
AnnaBridge 167:e84263d55307 7182 #define FLASH_SR_PGPERR_Pos (6U)
AnnaBridge 167:e84263d55307 7183 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7184 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
AnnaBridge 167:e84263d55307 7185 #define FLASH_SR_PGSERR_Pos (7U)
AnnaBridge 167:e84263d55307 7186 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7187 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
AnnaBridge 167:e84263d55307 7188 #define FLASH_SR_RDERR_Pos (8U)
AnnaBridge 167:e84263d55307 7189 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7190 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
AnnaBridge 167:e84263d55307 7191 #define FLASH_SR_BSY_Pos (16U)
AnnaBridge 167:e84263d55307 7192 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7193 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
<> 144:ef7eb2e8f9f7 7194
<> 144:ef7eb2e8f9f7 7195 /******************* Bits definition for FLASH_CR register ******************/
AnnaBridge 167:e84263d55307 7196 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 167:e84263d55307 7197 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7198 #define FLASH_CR_PG FLASH_CR_PG_Msk
AnnaBridge 167:e84263d55307 7199 #define FLASH_CR_SER_Pos (1U)
AnnaBridge 167:e84263d55307 7200 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7201 #define FLASH_CR_SER FLASH_CR_SER_Msk
AnnaBridge 167:e84263d55307 7202 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 167:e84263d55307 7203 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7204 #define FLASH_CR_MER FLASH_CR_MER_Msk
<> 144:ef7eb2e8f9f7 7205 #define FLASH_CR_MER1 FLASH_CR_MER
AnnaBridge 167:e84263d55307 7206 #define FLASH_CR_SNB_Pos (3U)
AnnaBridge 167:e84263d55307 7207 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
AnnaBridge 167:e84263d55307 7208 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
AnnaBridge 167:e84263d55307 7209 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7210 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7211 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7212 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7213 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7214 #define FLASH_CR_PSIZE_Pos (8U)
AnnaBridge 167:e84263d55307 7215 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 7216 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
AnnaBridge 167:e84263d55307 7217 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7218 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7219 #define FLASH_CR_MER2_Pos (15U)
AnnaBridge 167:e84263d55307 7220 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7221 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
AnnaBridge 167:e84263d55307 7222 #define FLASH_CR_STRT_Pos (16U)
AnnaBridge 167:e84263d55307 7223 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7224 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
AnnaBridge 167:e84263d55307 7225 #define FLASH_CR_EOPIE_Pos (24U)
AnnaBridge 167:e84263d55307 7226 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7227 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
AnnaBridge 167:e84263d55307 7228 #define FLASH_CR_LOCK_Pos (31U)
AnnaBridge 167:e84263d55307 7229 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 7230 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
<> 144:ef7eb2e8f9f7 7231
<> 144:ef7eb2e8f9f7 7232 /******************* Bits definition for FLASH_OPTCR register ***************/
AnnaBridge 167:e84263d55307 7233 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
AnnaBridge 167:e84263d55307 7234 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7235 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
AnnaBridge 167:e84263d55307 7236 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
AnnaBridge 167:e84263d55307 7237 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7238 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
AnnaBridge 167:e84263d55307 7239
AnnaBridge 167:e84263d55307 7240 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
AnnaBridge 167:e84263d55307 7241 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
AnnaBridge 167:e84263d55307 7242 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
AnnaBridge 167:e84263d55307 7243 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 7244 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
AnnaBridge 167:e84263d55307 7245 #define FLASH_OPTCR_BFB2_Pos (4U)
AnnaBridge 167:e84263d55307 7246 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7247 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
AnnaBridge 167:e84263d55307 7248 #define FLASH_OPTCR_WDG_SW_Pos (5U)
AnnaBridge 167:e84263d55307 7249 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7250 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
AnnaBridge 167:e84263d55307 7251 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
AnnaBridge 167:e84263d55307 7252 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7253 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
AnnaBridge 167:e84263d55307 7254 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
AnnaBridge 167:e84263d55307 7255 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7256 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
AnnaBridge 167:e84263d55307 7257 #define FLASH_OPTCR_RDP_Pos (8U)
AnnaBridge 167:e84263d55307 7258 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7259 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
AnnaBridge 167:e84263d55307 7260 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7261 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7262 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7263 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7264 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7265 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7266 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7267 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7268 #define FLASH_OPTCR_nWRP_Pos (16U)
AnnaBridge 167:e84263d55307 7269 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 7270 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
AnnaBridge 167:e84263d55307 7271 #define FLASH_OPTCR_nWRP_0 0x00010000U
AnnaBridge 167:e84263d55307 7272 #define FLASH_OPTCR_nWRP_1 0x00020000U
AnnaBridge 167:e84263d55307 7273 #define FLASH_OPTCR_nWRP_2 0x00040000U
AnnaBridge 167:e84263d55307 7274 #define FLASH_OPTCR_nWRP_3 0x00080000U
AnnaBridge 167:e84263d55307 7275 #define FLASH_OPTCR_nWRP_4 0x00100000U
AnnaBridge 167:e84263d55307 7276 #define FLASH_OPTCR_nWRP_5 0x00200000U
AnnaBridge 167:e84263d55307 7277 #define FLASH_OPTCR_nWRP_6 0x00400000U
AnnaBridge 167:e84263d55307 7278 #define FLASH_OPTCR_nWRP_7 0x00800000U
AnnaBridge 167:e84263d55307 7279 #define FLASH_OPTCR_nWRP_8 0x01000000U
AnnaBridge 167:e84263d55307 7280 #define FLASH_OPTCR_nWRP_9 0x02000000U
AnnaBridge 167:e84263d55307 7281 #define FLASH_OPTCR_nWRP_10 0x04000000U
AnnaBridge 167:e84263d55307 7282 #define FLASH_OPTCR_nWRP_11 0x08000000U
AnnaBridge 167:e84263d55307 7283 #define FLASH_OPTCR_DB1M_Pos (30U)
AnnaBridge 167:e84263d55307 7284 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 7285 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
AnnaBridge 167:e84263d55307 7286 #define FLASH_OPTCR_SPRMOD_Pos (31U)
AnnaBridge 167:e84263d55307 7287 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 7288 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
<> 144:ef7eb2e8f9f7 7289
<> 144:ef7eb2e8f9f7 7290 /****************** Bits definition for FLASH_OPTCR1 register ***************/
AnnaBridge 167:e84263d55307 7291 #define FLASH_OPTCR1_nWRP_Pos (16U)
AnnaBridge 167:e84263d55307 7292 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 7293 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
AnnaBridge 167:e84263d55307 7294 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7295 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7296 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7297 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7298 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7299 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7300 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7301 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 7302 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7303 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 7304 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 7305 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
<> 144:ef7eb2e8f9f7 7306
<> 144:ef7eb2e8f9f7 7307 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7308 /* */
<> 144:ef7eb2e8f9f7 7309 /* Flexible Memory Controller */
<> 144:ef7eb2e8f9f7 7310 /* */
<> 144:ef7eb2e8f9f7 7311 /******************************************************************************/
<> 144:ef7eb2e8f9f7 7312 /****************** Bit definition for FMC_BCR1 register *******************/
AnnaBridge 167:e84263d55307 7313 #define FMC_BCR1_MBKEN_Pos (0U)
AnnaBridge 167:e84263d55307 7314 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7315 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 167:e84263d55307 7316 #define FMC_BCR1_MUXEN_Pos (1U)
AnnaBridge 167:e84263d55307 7317 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7318 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 167:e84263d55307 7319
AnnaBridge 167:e84263d55307 7320 #define FMC_BCR1_MTYP_Pos (2U)
AnnaBridge 167:e84263d55307 7321 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 7322 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 167:e84263d55307 7323 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7324 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7325
AnnaBridge 167:e84263d55307 7326 #define FMC_BCR1_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 7327 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 7328 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 167:e84263d55307 7329 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7330 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7331
AnnaBridge 167:e84263d55307 7332 #define FMC_BCR1_FACCEN_Pos (6U)
AnnaBridge 167:e84263d55307 7333 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7334 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 167:e84263d55307 7335 #define FMC_BCR1_BURSTEN_Pos (8U)
AnnaBridge 167:e84263d55307 7336 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7337 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 167:e84263d55307 7338 #define FMC_BCR1_WAITPOL_Pos (9U)
AnnaBridge 167:e84263d55307 7339 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7340 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 167:e84263d55307 7341 #define FMC_BCR1_WRAPMOD_Pos (10U)
AnnaBridge 167:e84263d55307 7342 #define FMC_BCR1_WRAPMOD_Msk (0x1U << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7343 #define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 167:e84263d55307 7344 #define FMC_BCR1_WAITCFG_Pos (11U)
AnnaBridge 167:e84263d55307 7345 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7346 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 167:e84263d55307 7347 #define FMC_BCR1_WREN_Pos (12U)
AnnaBridge 167:e84263d55307 7348 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7349 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
AnnaBridge 167:e84263d55307 7350 #define FMC_BCR1_WAITEN_Pos (13U)
AnnaBridge 167:e84263d55307 7351 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7352 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 167:e84263d55307 7353 #define FMC_BCR1_EXTMOD_Pos (14U)
AnnaBridge 167:e84263d55307 7354 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7355 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 167:e84263d55307 7356 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
AnnaBridge 167:e84263d55307 7357 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7358 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 167:e84263d55307 7359 #define FMC_BCR1_CPSIZE_Pos (16U)
AnnaBridge 167:e84263d55307 7360 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 7361 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 167:e84263d55307 7362 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7363 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7364 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7365 #define FMC_BCR1_CBURSTRW_Pos (19U)
AnnaBridge 167:e84263d55307 7366 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7367 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
AnnaBridge 167:e84263d55307 7368 #define FMC_BCR1_CCLKEN_Pos (20U)
AnnaBridge 167:e84263d55307 7369 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7370 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
<> 144:ef7eb2e8f9f7 7371
<> 144:ef7eb2e8f9f7 7372 /****************** Bit definition for FMC_BCR2 register *******************/
AnnaBridge 167:e84263d55307 7373 #define FMC_BCR2_MBKEN_Pos (0U)
AnnaBridge 167:e84263d55307 7374 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7375 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 167:e84263d55307 7376 #define FMC_BCR2_MUXEN_Pos (1U)
AnnaBridge 167:e84263d55307 7377 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7378 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 167:e84263d55307 7379
AnnaBridge 167:e84263d55307 7380 #define FMC_BCR2_MTYP_Pos (2U)
AnnaBridge 167:e84263d55307 7381 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 7382 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 167:e84263d55307 7383 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7384 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7385
AnnaBridge 167:e84263d55307 7386 #define FMC_BCR2_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 7387 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 7388 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 167:e84263d55307 7389 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7390 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7391
AnnaBridge 167:e84263d55307 7392 #define FMC_BCR2_FACCEN_Pos (6U)
AnnaBridge 167:e84263d55307 7393 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7394 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 167:e84263d55307 7395 #define FMC_BCR2_BURSTEN_Pos (8U)
AnnaBridge 167:e84263d55307 7396 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7397 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 167:e84263d55307 7398 #define FMC_BCR2_WAITPOL_Pos (9U)
AnnaBridge 167:e84263d55307 7399 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7400 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 167:e84263d55307 7401 #define FMC_BCR2_WRAPMOD_Pos (10U)
AnnaBridge 167:e84263d55307 7402 #define FMC_BCR2_WRAPMOD_Msk (0x1U << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7403 #define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 167:e84263d55307 7404 #define FMC_BCR2_WAITCFG_Pos (11U)
AnnaBridge 167:e84263d55307 7405 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7406 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 167:e84263d55307 7407 #define FMC_BCR2_WREN_Pos (12U)
AnnaBridge 167:e84263d55307 7408 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7409 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
AnnaBridge 167:e84263d55307 7410 #define FMC_BCR2_WAITEN_Pos (13U)
AnnaBridge 167:e84263d55307 7411 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7412 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 167:e84263d55307 7413 #define FMC_BCR2_EXTMOD_Pos (14U)
AnnaBridge 167:e84263d55307 7414 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7415 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 167:e84263d55307 7416 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
AnnaBridge 167:e84263d55307 7417 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7418 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 167:e84263d55307 7419 #define FMC_BCR2_CPSIZE_Pos (16U)
AnnaBridge 167:e84263d55307 7420 #define FMC_BCR2_CPSIZE_Msk (0x7U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 7421 #define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 167:e84263d55307 7422 #define FMC_BCR2_CPSIZE_0 (0x1U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7423 #define FMC_BCR2_CPSIZE_1 (0x2U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7424 #define FMC_BCR2_CPSIZE_2 (0x4U << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7425 #define FMC_BCR2_CBURSTRW_Pos (19U)
AnnaBridge 167:e84263d55307 7426 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7427 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 7428
<> 144:ef7eb2e8f9f7 7429 /****************** Bit definition for FMC_BCR3 register *******************/
AnnaBridge 167:e84263d55307 7430 #define FMC_BCR3_MBKEN_Pos (0U)
AnnaBridge 167:e84263d55307 7431 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7432 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 167:e84263d55307 7433 #define FMC_BCR3_MUXEN_Pos (1U)
AnnaBridge 167:e84263d55307 7434 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7435 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 167:e84263d55307 7436
AnnaBridge 167:e84263d55307 7437 #define FMC_BCR3_MTYP_Pos (2U)
AnnaBridge 167:e84263d55307 7438 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 7439 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 167:e84263d55307 7440 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7441 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7442
AnnaBridge 167:e84263d55307 7443 #define FMC_BCR3_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 7444 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 7445 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 167:e84263d55307 7446 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7447 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7448
AnnaBridge 167:e84263d55307 7449 #define FMC_BCR3_FACCEN_Pos (6U)
AnnaBridge 167:e84263d55307 7450 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7451 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 167:e84263d55307 7452 #define FMC_BCR3_BURSTEN_Pos (8U)
AnnaBridge 167:e84263d55307 7453 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7454 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 167:e84263d55307 7455 #define FMC_BCR3_WAITPOL_Pos (9U)
AnnaBridge 167:e84263d55307 7456 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7457 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 167:e84263d55307 7458 #define FMC_BCR3_WRAPMOD_Pos (10U)
AnnaBridge 167:e84263d55307 7459 #define FMC_BCR3_WRAPMOD_Msk (0x1U << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7460 #define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 167:e84263d55307 7461 #define FMC_BCR3_WAITCFG_Pos (11U)
AnnaBridge 167:e84263d55307 7462 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7463 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 167:e84263d55307 7464 #define FMC_BCR3_WREN_Pos (12U)
AnnaBridge 167:e84263d55307 7465 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7466 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
AnnaBridge 167:e84263d55307 7467 #define FMC_BCR3_WAITEN_Pos (13U)
AnnaBridge 167:e84263d55307 7468 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7469 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 167:e84263d55307 7470 #define FMC_BCR3_EXTMOD_Pos (14U)
AnnaBridge 167:e84263d55307 7471 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7472 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 167:e84263d55307 7473 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
AnnaBridge 167:e84263d55307 7474 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7475 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 167:e84263d55307 7476 #define FMC_BCR3_CPSIZE_Pos (16U)
AnnaBridge 167:e84263d55307 7477 #define FMC_BCR3_CPSIZE_Msk (0x7U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 7478 #define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 167:e84263d55307 7479 #define FMC_BCR3_CPSIZE_0 (0x1U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7480 #define FMC_BCR3_CPSIZE_1 (0x2U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7481 #define FMC_BCR3_CPSIZE_2 (0x4U << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7482 #define FMC_BCR3_CBURSTRW_Pos (19U)
AnnaBridge 167:e84263d55307 7483 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7484 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 7485
<> 144:ef7eb2e8f9f7 7486 /****************** Bit definition for FMC_BCR4 register *******************/
AnnaBridge 167:e84263d55307 7487 #define FMC_BCR4_MBKEN_Pos (0U)
AnnaBridge 167:e84263d55307 7488 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7489 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
AnnaBridge 167:e84263d55307 7490 #define FMC_BCR4_MUXEN_Pos (1U)
AnnaBridge 167:e84263d55307 7491 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7492 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
AnnaBridge 167:e84263d55307 7493
AnnaBridge 167:e84263d55307 7494 #define FMC_BCR4_MTYP_Pos (2U)
AnnaBridge 167:e84263d55307 7495 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 7496 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
AnnaBridge 167:e84263d55307 7497 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7498 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7499
AnnaBridge 167:e84263d55307 7500 #define FMC_BCR4_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 7501 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 7502 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
AnnaBridge 167:e84263d55307 7503 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7504 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7505
AnnaBridge 167:e84263d55307 7506 #define FMC_BCR4_FACCEN_Pos (6U)
AnnaBridge 167:e84263d55307 7507 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7508 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
AnnaBridge 167:e84263d55307 7509 #define FMC_BCR4_BURSTEN_Pos (8U)
AnnaBridge 167:e84263d55307 7510 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7511 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
AnnaBridge 167:e84263d55307 7512 #define FMC_BCR4_WAITPOL_Pos (9U)
AnnaBridge 167:e84263d55307 7513 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7514 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
AnnaBridge 167:e84263d55307 7515 #define FMC_BCR4_WRAPMOD_Pos (10U)
AnnaBridge 167:e84263d55307 7516 #define FMC_BCR4_WRAPMOD_Msk (0x1U << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7517 #define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */
AnnaBridge 167:e84263d55307 7518 #define FMC_BCR4_WAITCFG_Pos (11U)
AnnaBridge 167:e84263d55307 7519 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7520 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
AnnaBridge 167:e84263d55307 7521 #define FMC_BCR4_WREN_Pos (12U)
AnnaBridge 167:e84263d55307 7522 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7523 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
AnnaBridge 167:e84263d55307 7524 #define FMC_BCR4_WAITEN_Pos (13U)
AnnaBridge 167:e84263d55307 7525 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7526 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
AnnaBridge 167:e84263d55307 7527 #define FMC_BCR4_EXTMOD_Pos (14U)
AnnaBridge 167:e84263d55307 7528 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7529 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
AnnaBridge 167:e84263d55307 7530 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
AnnaBridge 167:e84263d55307 7531 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7532 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
AnnaBridge 167:e84263d55307 7533 #define FMC_BCR4_CPSIZE_Pos (16U)
AnnaBridge 167:e84263d55307 7534 #define FMC_BCR4_CPSIZE_Msk (0x7U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 7535 #define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */
AnnaBridge 167:e84263d55307 7536 #define FMC_BCR4_CPSIZE_0 (0x1U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7537 #define FMC_BCR4_CPSIZE_1 (0x2U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7538 #define FMC_BCR4_CPSIZE_2 (0x4U << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7539 #define FMC_BCR4_CBURSTRW_Pos (19U)
AnnaBridge 167:e84263d55307 7540 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7541 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
<> 144:ef7eb2e8f9f7 7542
<> 144:ef7eb2e8f9f7 7543 /****************** Bit definition for FMC_BTR1 register ******************/
AnnaBridge 167:e84263d55307 7544 #define FMC_BTR1_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7545 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7546 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7547 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7548 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7549 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7550 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7551
AnnaBridge 167:e84263d55307 7552 #define FMC_BTR1_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7553 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7554 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7555 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7556 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7557 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7558 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7559
AnnaBridge 167:e84263d55307 7560 #define FMC_BTR1_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7561 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7562 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7563 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7564 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7565 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7566 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7567 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7568 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7569 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7570 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7571
AnnaBridge 167:e84263d55307 7572 #define FMC_BTR1_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7573 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7574 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 167:e84263d55307 7575 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7576 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7577 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7578 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7579
AnnaBridge 167:e84263d55307 7580 #define FMC_BTR1_CLKDIV_Pos (20U)
AnnaBridge 167:e84263d55307 7581 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 7582 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 167:e84263d55307 7583 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7584 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7585 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7586 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 7587
AnnaBridge 167:e84263d55307 7588 #define FMC_BTR1_DATLAT_Pos (24U)
AnnaBridge 167:e84263d55307 7589 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 7590 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 167:e84263d55307 7591 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7592 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 7593 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 7594 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 7595
AnnaBridge 167:e84263d55307 7596 #define FMC_BTR1_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7597 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7598 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7599 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7600 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7601
<> 144:ef7eb2e8f9f7 7602 /****************** Bit definition for FMC_BTR2 register *******************/
AnnaBridge 167:e84263d55307 7603 #define FMC_BTR2_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7604 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7605 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7606 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7607 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7608 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7609 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7610
AnnaBridge 167:e84263d55307 7611 #define FMC_BTR2_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7612 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7613 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7614 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7615 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7616 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7617 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7618
AnnaBridge 167:e84263d55307 7619 #define FMC_BTR2_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7620 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7621 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7622 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7623 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7624 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7625 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7626 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7627 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7628 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7629 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7630
AnnaBridge 167:e84263d55307 7631 #define FMC_BTR2_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7632 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7633 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 167:e84263d55307 7634 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7635 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7636 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7637 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7638
AnnaBridge 167:e84263d55307 7639 #define FMC_BTR2_CLKDIV_Pos (20U)
AnnaBridge 167:e84263d55307 7640 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 7641 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 167:e84263d55307 7642 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7643 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7644 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7645 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 7646
AnnaBridge 167:e84263d55307 7647 #define FMC_BTR2_DATLAT_Pos (24U)
AnnaBridge 167:e84263d55307 7648 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 7649 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 167:e84263d55307 7650 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7651 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 7652 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 7653 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 7654
AnnaBridge 167:e84263d55307 7655 #define FMC_BTR2_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7656 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7657 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7658 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7659 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7660
<> 144:ef7eb2e8f9f7 7661 /******************* Bit definition for FMC_BTR3 register *******************/
AnnaBridge 167:e84263d55307 7662 #define FMC_BTR3_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7663 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7664 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7665 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7666 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7667 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7668 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7669
AnnaBridge 167:e84263d55307 7670 #define FMC_BTR3_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7671 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7672 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7673 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7674 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7675 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7676 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7677
AnnaBridge 167:e84263d55307 7678 #define FMC_BTR3_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7679 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7680 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7681 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7682 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7683 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7684 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7685 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7686 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7687 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7688 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7689
AnnaBridge 167:e84263d55307 7690 #define FMC_BTR3_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7691 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7692 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 167:e84263d55307 7693 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7694 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7695 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7696 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7697
AnnaBridge 167:e84263d55307 7698 #define FMC_BTR3_CLKDIV_Pos (20U)
AnnaBridge 167:e84263d55307 7699 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 7700 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 167:e84263d55307 7701 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7702 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7703 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7704 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 7705
AnnaBridge 167:e84263d55307 7706 #define FMC_BTR3_DATLAT_Pos (24U)
AnnaBridge 167:e84263d55307 7707 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 7708 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 167:e84263d55307 7709 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7710 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 7711 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 7712 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 7713
AnnaBridge 167:e84263d55307 7714 #define FMC_BTR3_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7715 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7716 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7717 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7718 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7719
<> 144:ef7eb2e8f9f7 7720 /****************** Bit definition for FMC_BTR4 register *******************/
AnnaBridge 167:e84263d55307 7721 #define FMC_BTR4_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7722 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7723 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7724 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7725 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7726 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7727 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7728
AnnaBridge 167:e84263d55307 7729 #define FMC_BTR4_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7730 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7731 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7732 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7733 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7734 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7735 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7736
AnnaBridge 167:e84263d55307 7737 #define FMC_BTR4_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7738 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7739 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7740 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7741 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7742 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7743 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7744 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7745 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7746 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7747 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7748
AnnaBridge 167:e84263d55307 7749 #define FMC_BTR4_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7750 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7751 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
AnnaBridge 167:e84263d55307 7752 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7753 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7754 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7755 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7756
AnnaBridge 167:e84263d55307 7757 #define FMC_BTR4_CLKDIV_Pos (20U)
AnnaBridge 167:e84263d55307 7758 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 7759 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
AnnaBridge 167:e84263d55307 7760 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 7761 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 7762 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 7763 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 7764
AnnaBridge 167:e84263d55307 7765 #define FMC_BTR4_DATLAT_Pos (24U)
AnnaBridge 167:e84263d55307 7766 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 7767 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
AnnaBridge 167:e84263d55307 7768 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 7769 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 7770 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 7771 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 7772
AnnaBridge 167:e84263d55307 7773 #define FMC_BTR4_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7774 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7775 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7776 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7777 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7778
<> 144:ef7eb2e8f9f7 7779 /****************** Bit definition for FMC_BWTR1 register ******************/
AnnaBridge 167:e84263d55307 7780 #define FMC_BWTR1_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7781 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7782 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7783 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7784 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7785 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7786 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7787
AnnaBridge 167:e84263d55307 7788 #define FMC_BWTR1_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7789 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7790 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7791 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7792 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7793 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7794 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7795
AnnaBridge 167:e84263d55307 7796 #define FMC_BWTR1_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7797 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7798 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7799 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7800 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7801 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7802 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7803 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7804 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7805 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7806 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7807
AnnaBridge 167:e84263d55307 7808 #define FMC_BWTR1_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7809 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7810 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 167:e84263d55307 7811 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7812 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7813 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7814 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7815
AnnaBridge 167:e84263d55307 7816 #define FMC_BWTR1_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7817 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7818 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7819 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7820 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7821
<> 144:ef7eb2e8f9f7 7822 /****************** Bit definition for FMC_BWTR2 register ******************/
AnnaBridge 167:e84263d55307 7823 #define FMC_BWTR2_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7824 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7825 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7826 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7827 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7828 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7829 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7830
AnnaBridge 167:e84263d55307 7831 #define FMC_BWTR2_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7832 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7833 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7834 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7835 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7836 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7837 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7838
AnnaBridge 167:e84263d55307 7839 #define FMC_BWTR2_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7840 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7841 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7842 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7843 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7844 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7845 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7846 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7847 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7848 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7849 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7850
AnnaBridge 167:e84263d55307 7851 #define FMC_BWTR2_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7852 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7853 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 167:e84263d55307 7854 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7855 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7856 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7857 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7858
AnnaBridge 167:e84263d55307 7859 #define FMC_BWTR2_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7860 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7861 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7862 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7863 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7864
<> 144:ef7eb2e8f9f7 7865 /****************** Bit definition for FMC_BWTR3 register ******************/
AnnaBridge 167:e84263d55307 7866 #define FMC_BWTR3_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7867 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7868 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7869 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7870 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7871 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7872 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7873
AnnaBridge 167:e84263d55307 7874 #define FMC_BWTR3_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7875 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7876 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7877 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7878 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7879 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7880 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7881
AnnaBridge 167:e84263d55307 7882 #define FMC_BWTR3_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7883 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7884 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7885 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7886 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7887 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7888 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7889 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7890 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7891 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7892 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7893
AnnaBridge 167:e84263d55307 7894 #define FMC_BWTR3_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7895 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7896 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 167:e84263d55307 7897 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7898 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7899 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7900 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7901
AnnaBridge 167:e84263d55307 7902 #define FMC_BWTR3_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7903 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7904 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7905 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7906 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7907
<> 144:ef7eb2e8f9f7 7908 /****************** Bit definition for FMC_BWTR4 register ******************/
AnnaBridge 167:e84263d55307 7909 #define FMC_BWTR4_ADDSET_Pos (0U)
AnnaBridge 167:e84263d55307 7910 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 7911 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
AnnaBridge 167:e84263d55307 7912 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 7913 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7914 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7915 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7916
AnnaBridge 167:e84263d55307 7917 #define FMC_BWTR4_ADDHLD_Pos (4U)
AnnaBridge 167:e84263d55307 7918 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 7919 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
AnnaBridge 167:e84263d55307 7920 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7921 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7922 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7923 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 7924
AnnaBridge 167:e84263d55307 7925 #define FMC_BWTR4_DATAST_Pos (8U)
AnnaBridge 167:e84263d55307 7926 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 7927 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
AnnaBridge 167:e84263d55307 7928 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 7929 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7930 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7931 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7932 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7933 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7934 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7935 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7936
AnnaBridge 167:e84263d55307 7937 #define FMC_BWTR4_BUSTURN_Pos (16U)
AnnaBridge 167:e84263d55307 7938 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 7939 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
AnnaBridge 167:e84263d55307 7940 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7941 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7942 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7943 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 7944
AnnaBridge 167:e84263d55307 7945 #define FMC_BWTR4_ACCMOD_Pos (28U)
AnnaBridge 167:e84263d55307 7946 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 7947 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
AnnaBridge 167:e84263d55307 7948 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 7949 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
<> 144:ef7eb2e8f9f7 7950
<> 144:ef7eb2e8f9f7 7951 /****************** Bit definition for FMC_PCR2 register *******************/
AnnaBridge 167:e84263d55307 7952
AnnaBridge 167:e84263d55307 7953 #define FMC_PCR2_PWAITEN_Pos (1U)
AnnaBridge 167:e84263d55307 7954 #define FMC_PCR2_PWAITEN_Msk (0x1U << FMC_PCR2_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7955 #define FMC_PCR2_PWAITEN FMC_PCR2_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 167:e84263d55307 7956 #define FMC_PCR2_PBKEN_Pos (2U)
AnnaBridge 167:e84263d55307 7957 #define FMC_PCR2_PBKEN_Msk (0x1U << FMC_PCR2_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 7958 #define FMC_PCR2_PBKEN FMC_PCR2_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 167:e84263d55307 7959 #define FMC_PCR2_PTYP_Pos (3U)
AnnaBridge 167:e84263d55307 7960 #define FMC_PCR2_PTYP_Msk (0x1U << FMC_PCR2_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 7961 #define FMC_PCR2_PTYP FMC_PCR2_PTYP_Msk /*!<Memory type */
AnnaBridge 167:e84263d55307 7962
AnnaBridge 167:e84263d55307 7963 #define FMC_PCR2_PWID_Pos (4U)
AnnaBridge 167:e84263d55307 7964 #define FMC_PCR2_PWID_Msk (0x3U << FMC_PCR2_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 7965 #define FMC_PCR2_PWID FMC_PCR2_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 167:e84263d55307 7966 #define FMC_PCR2_PWID_0 (0x1U << FMC_PCR2_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 7967 #define FMC_PCR2_PWID_1 (0x2U << FMC_PCR2_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 7968
AnnaBridge 167:e84263d55307 7969 #define FMC_PCR2_ECCEN_Pos (6U)
AnnaBridge 167:e84263d55307 7970 #define FMC_PCR2_ECCEN_Msk (0x1U << FMC_PCR2_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 7971 #define FMC_PCR2_ECCEN FMC_PCR2_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 167:e84263d55307 7972
AnnaBridge 167:e84263d55307 7973 #define FMC_PCR2_TCLR_Pos (9U)
AnnaBridge 167:e84263d55307 7974 #define FMC_PCR2_TCLR_Msk (0xFU << FMC_PCR2_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 167:e84263d55307 7975 #define FMC_PCR2_TCLR FMC_PCR2_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 167:e84263d55307 7976 #define FMC_PCR2_TCLR_0 (0x1U << FMC_PCR2_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 7977 #define FMC_PCR2_TCLR_1 (0x2U << FMC_PCR2_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 7978 #define FMC_PCR2_TCLR_2 (0x4U << FMC_PCR2_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 7979 #define FMC_PCR2_TCLR_3 (0x8U << FMC_PCR2_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 7980
AnnaBridge 167:e84263d55307 7981 #define FMC_PCR2_TAR_Pos (13U)
AnnaBridge 167:e84263d55307 7982 #define FMC_PCR2_TAR_Msk (0xFU << FMC_PCR2_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 167:e84263d55307 7983 #define FMC_PCR2_TAR FMC_PCR2_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 167:e84263d55307 7984 #define FMC_PCR2_TAR_0 (0x1U << FMC_PCR2_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 7985 #define FMC_PCR2_TAR_1 (0x2U << FMC_PCR2_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 7986 #define FMC_PCR2_TAR_2 (0x4U << FMC_PCR2_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 7987 #define FMC_PCR2_TAR_3 (0x8U << FMC_PCR2_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 7988
AnnaBridge 167:e84263d55307 7989 #define FMC_PCR2_ECCPS_Pos (17U)
AnnaBridge 167:e84263d55307 7990 #define FMC_PCR2_ECCPS_Msk (0x7U << FMC_PCR2_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 7991 #define FMC_PCR2_ECCPS FMC_PCR2_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
AnnaBridge 167:e84263d55307 7992 #define FMC_PCR2_ECCPS_0 (0x1U << FMC_PCR2_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 7993 #define FMC_PCR2_ECCPS_1 (0x2U << FMC_PCR2_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 7994 #define FMC_PCR2_ECCPS_2 (0x4U << FMC_PCR2_ECCPS_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 7995
<> 144:ef7eb2e8f9f7 7996 /****************** Bit definition for FMC_PCR3 register *******************/
AnnaBridge 167:e84263d55307 7997 #define FMC_PCR3_PWAITEN_Pos (1U)
AnnaBridge 167:e84263d55307 7998 #define FMC_PCR3_PWAITEN_Msk (0x1U << FMC_PCR3_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 7999 #define FMC_PCR3_PWAITEN FMC_PCR3_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 167:e84263d55307 8000 #define FMC_PCR3_PBKEN_Pos (2U)
AnnaBridge 167:e84263d55307 8001 #define FMC_PCR3_PBKEN_Msk (0x1U << FMC_PCR3_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8002 #define FMC_PCR3_PBKEN FMC_PCR3_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 167:e84263d55307 8003 #define FMC_PCR3_PTYP_Pos (3U)
AnnaBridge 167:e84263d55307 8004 #define FMC_PCR3_PTYP_Msk (0x1U << FMC_PCR3_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8005 #define FMC_PCR3_PTYP FMC_PCR3_PTYP_Msk /*!<Memory type */
AnnaBridge 167:e84263d55307 8006
AnnaBridge 167:e84263d55307 8007 #define FMC_PCR3_PWID_Pos (4U)
AnnaBridge 167:e84263d55307 8008 #define FMC_PCR3_PWID_Msk (0x3U << FMC_PCR3_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8009 #define FMC_PCR3_PWID FMC_PCR3_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 167:e84263d55307 8010 #define FMC_PCR3_PWID_0 (0x1U << FMC_PCR3_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8011 #define FMC_PCR3_PWID_1 (0x2U << FMC_PCR3_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8012
AnnaBridge 167:e84263d55307 8013 #define FMC_PCR3_ECCEN_Pos (6U)
AnnaBridge 167:e84263d55307 8014 #define FMC_PCR3_ECCEN_Msk (0x1U << FMC_PCR3_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8015 #define FMC_PCR3_ECCEN FMC_PCR3_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 167:e84263d55307 8016
AnnaBridge 167:e84263d55307 8017 #define FMC_PCR3_TCLR_Pos (9U)
AnnaBridge 167:e84263d55307 8018 #define FMC_PCR3_TCLR_Msk (0xFU << FMC_PCR3_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 167:e84263d55307 8019 #define FMC_PCR3_TCLR FMC_PCR3_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 167:e84263d55307 8020 #define FMC_PCR3_TCLR_0 (0x1U << FMC_PCR3_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8021 #define FMC_PCR3_TCLR_1 (0x2U << FMC_PCR3_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8022 #define FMC_PCR3_TCLR_2 (0x4U << FMC_PCR3_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8023 #define FMC_PCR3_TCLR_3 (0x8U << FMC_PCR3_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8024
AnnaBridge 167:e84263d55307 8025 #define FMC_PCR3_TAR_Pos (13U)
AnnaBridge 167:e84263d55307 8026 #define FMC_PCR3_TAR_Msk (0xFU << FMC_PCR3_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 167:e84263d55307 8027 #define FMC_PCR3_TAR FMC_PCR3_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 167:e84263d55307 8028 #define FMC_PCR3_TAR_0 (0x1U << FMC_PCR3_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8029 #define FMC_PCR3_TAR_1 (0x2U << FMC_PCR3_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8030 #define FMC_PCR3_TAR_2 (0x4U << FMC_PCR3_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8031 #define FMC_PCR3_TAR_3 (0x8U << FMC_PCR3_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8032
AnnaBridge 167:e84263d55307 8033 #define FMC_PCR3_ECCPS_Pos (17U)
AnnaBridge 167:e84263d55307 8034 #define FMC_PCR3_ECCPS_Msk (0x7U << FMC_PCR3_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 8035 #define FMC_PCR3_ECCPS FMC_PCR3_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 167:e84263d55307 8036 #define FMC_PCR3_ECCPS_0 (0x1U << FMC_PCR3_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8037 #define FMC_PCR3_ECCPS_1 (0x2U << FMC_PCR3_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8038 #define FMC_PCR3_ECCPS_2 (0x4U << FMC_PCR3_ECCPS_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8039
<> 144:ef7eb2e8f9f7 8040 /****************** Bit definition for FMC_PCR4 register *******************/
AnnaBridge 167:e84263d55307 8041 #define FMC_PCR4_PWAITEN_Pos (1U)
AnnaBridge 167:e84263d55307 8042 #define FMC_PCR4_PWAITEN_Msk (0x1U << FMC_PCR4_PWAITEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8043 #define FMC_PCR4_PWAITEN FMC_PCR4_PWAITEN_Msk /*!<Wait feature enable bit */
AnnaBridge 167:e84263d55307 8044 #define FMC_PCR4_PBKEN_Pos (2U)
AnnaBridge 167:e84263d55307 8045 #define FMC_PCR4_PBKEN_Msk (0x1U << FMC_PCR4_PBKEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8046 #define FMC_PCR4_PBKEN FMC_PCR4_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
AnnaBridge 167:e84263d55307 8047 #define FMC_PCR4_PTYP_Pos (3U)
AnnaBridge 167:e84263d55307 8048 #define FMC_PCR4_PTYP_Msk (0x1U << FMC_PCR4_PTYP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8049 #define FMC_PCR4_PTYP FMC_PCR4_PTYP_Msk /*!<Memory type */
AnnaBridge 167:e84263d55307 8050
AnnaBridge 167:e84263d55307 8051 #define FMC_PCR4_PWID_Pos (4U)
AnnaBridge 167:e84263d55307 8052 #define FMC_PCR4_PWID_Msk (0x3U << FMC_PCR4_PWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8053 #define FMC_PCR4_PWID FMC_PCR4_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
AnnaBridge 167:e84263d55307 8054 #define FMC_PCR4_PWID_0 (0x1U << FMC_PCR4_PWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8055 #define FMC_PCR4_PWID_1 (0x2U << FMC_PCR4_PWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8056
AnnaBridge 167:e84263d55307 8057 #define FMC_PCR4_ECCEN_Pos (6U)
AnnaBridge 167:e84263d55307 8058 #define FMC_PCR4_ECCEN_Msk (0x1U << FMC_PCR4_ECCEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8059 #define FMC_PCR4_ECCEN FMC_PCR4_ECCEN_Msk /*!<ECC computation logic enable bit */
AnnaBridge 167:e84263d55307 8060
AnnaBridge 167:e84263d55307 8061 #define FMC_PCR4_TCLR_Pos (9U)
AnnaBridge 167:e84263d55307 8062 #define FMC_PCR4_TCLR_Msk (0xFU << FMC_PCR4_TCLR_Pos) /*!< 0x00001E00 */
AnnaBridge 167:e84263d55307 8063 #define FMC_PCR4_TCLR FMC_PCR4_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
AnnaBridge 167:e84263d55307 8064 #define FMC_PCR4_TCLR_0 (0x1U << FMC_PCR4_TCLR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8065 #define FMC_PCR4_TCLR_1 (0x2U << FMC_PCR4_TCLR_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8066 #define FMC_PCR4_TCLR_2 (0x4U << FMC_PCR4_TCLR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8067 #define FMC_PCR4_TCLR_3 (0x8U << FMC_PCR4_TCLR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8068
AnnaBridge 167:e84263d55307 8069 #define FMC_PCR4_TAR_Pos (13U)
AnnaBridge 167:e84263d55307 8070 #define FMC_PCR4_TAR_Msk (0xFU << FMC_PCR4_TAR_Pos) /*!< 0x0001E000 */
AnnaBridge 167:e84263d55307 8071 #define FMC_PCR4_TAR FMC_PCR4_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
AnnaBridge 167:e84263d55307 8072 #define FMC_PCR4_TAR_0 (0x1U << FMC_PCR4_TAR_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8073 #define FMC_PCR4_TAR_1 (0x2U << FMC_PCR4_TAR_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8074 #define FMC_PCR4_TAR_2 (0x4U << FMC_PCR4_TAR_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8075 #define FMC_PCR4_TAR_3 (0x8U << FMC_PCR4_TAR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8076
AnnaBridge 167:e84263d55307 8077 #define FMC_PCR4_ECCPS_Pos (17U)
AnnaBridge 167:e84263d55307 8078 #define FMC_PCR4_ECCPS_Msk (0x7U << FMC_PCR4_ECCPS_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 8079 #define FMC_PCR4_ECCPS FMC_PCR4_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */
AnnaBridge 167:e84263d55307 8080 #define FMC_PCR4_ECCPS_0 (0x1U << FMC_PCR4_ECCPS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8081 #define FMC_PCR4_ECCPS_1 (0x2U << FMC_PCR4_ECCPS_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8082 #define FMC_PCR4_ECCPS_2 (0x4U << FMC_PCR4_ECCPS_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 8083
<> 144:ef7eb2e8f9f7 8084 /******************* Bit definition for FMC_SR2 register *******************/
AnnaBridge 167:e84263d55307 8085 #define FMC_SR2_IRS_Pos (0U)
AnnaBridge 167:e84263d55307 8086 #define FMC_SR2_IRS_Msk (0x1U << FMC_SR2_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8087 #define FMC_SR2_IRS FMC_SR2_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 167:e84263d55307 8088 #define FMC_SR2_ILS_Pos (1U)
AnnaBridge 167:e84263d55307 8089 #define FMC_SR2_ILS_Msk (0x1U << FMC_SR2_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8090 #define FMC_SR2_ILS FMC_SR2_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 167:e84263d55307 8091 #define FMC_SR2_IFS_Pos (2U)
AnnaBridge 167:e84263d55307 8092 #define FMC_SR2_IFS_Msk (0x1U << FMC_SR2_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8093 #define FMC_SR2_IFS FMC_SR2_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 167:e84263d55307 8094 #define FMC_SR2_IREN_Pos (3U)
AnnaBridge 167:e84263d55307 8095 #define FMC_SR2_IREN_Msk (0x1U << FMC_SR2_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8096 #define FMC_SR2_IREN FMC_SR2_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8097 #define FMC_SR2_ILEN_Pos (4U)
AnnaBridge 167:e84263d55307 8098 #define FMC_SR2_ILEN_Msk (0x1U << FMC_SR2_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8099 #define FMC_SR2_ILEN FMC_SR2_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 167:e84263d55307 8100 #define FMC_SR2_IFEN_Pos (5U)
AnnaBridge 167:e84263d55307 8101 #define FMC_SR2_IFEN_Msk (0x1U << FMC_SR2_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8102 #define FMC_SR2_IFEN FMC_SR2_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8103 #define FMC_SR2_FEMPT_Pos (6U)
AnnaBridge 167:e84263d55307 8104 #define FMC_SR2_FEMPT_Msk (0x1U << FMC_SR2_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8105 #define FMC_SR2_FEMPT FMC_SR2_FEMPT_Msk /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 8106
<> 144:ef7eb2e8f9f7 8107 /******************* Bit definition for FMC_SR3 register *******************/
AnnaBridge 167:e84263d55307 8108 #define FMC_SR3_IRS_Pos (0U)
AnnaBridge 167:e84263d55307 8109 #define FMC_SR3_IRS_Msk (0x1U << FMC_SR3_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8110 #define FMC_SR3_IRS FMC_SR3_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 167:e84263d55307 8111 #define FMC_SR3_ILS_Pos (1U)
AnnaBridge 167:e84263d55307 8112 #define FMC_SR3_ILS_Msk (0x1U << FMC_SR3_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8113 #define FMC_SR3_ILS FMC_SR3_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 167:e84263d55307 8114 #define FMC_SR3_IFS_Pos (2U)
AnnaBridge 167:e84263d55307 8115 #define FMC_SR3_IFS_Msk (0x1U << FMC_SR3_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8116 #define FMC_SR3_IFS FMC_SR3_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 167:e84263d55307 8117 #define FMC_SR3_IREN_Pos (3U)
AnnaBridge 167:e84263d55307 8118 #define FMC_SR3_IREN_Msk (0x1U << FMC_SR3_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8119 #define FMC_SR3_IREN FMC_SR3_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8120 #define FMC_SR3_ILEN_Pos (4U)
AnnaBridge 167:e84263d55307 8121 #define FMC_SR3_ILEN_Msk (0x1U << FMC_SR3_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8122 #define FMC_SR3_ILEN FMC_SR3_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 167:e84263d55307 8123 #define FMC_SR3_IFEN_Pos (5U)
AnnaBridge 167:e84263d55307 8124 #define FMC_SR3_IFEN_Msk (0x1U << FMC_SR3_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8125 #define FMC_SR3_IFEN FMC_SR3_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8126 #define FMC_SR3_FEMPT_Pos (6U)
AnnaBridge 167:e84263d55307 8127 #define FMC_SR3_FEMPT_Msk (0x1U << FMC_SR3_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8128 #define FMC_SR3_FEMPT FMC_SR3_FEMPT_Msk /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 8129
<> 144:ef7eb2e8f9f7 8130 /******************* Bit definition for FMC_SR4 register *******************/
AnnaBridge 167:e84263d55307 8131 #define FMC_SR4_IRS_Pos (0U)
AnnaBridge 167:e84263d55307 8132 #define FMC_SR4_IRS_Msk (0x1U << FMC_SR4_IRS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8133 #define FMC_SR4_IRS FMC_SR4_IRS_Msk /*!<Interrupt Rising Edge status */
AnnaBridge 167:e84263d55307 8134 #define FMC_SR4_ILS_Pos (1U)
AnnaBridge 167:e84263d55307 8135 #define FMC_SR4_ILS_Msk (0x1U << FMC_SR4_ILS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8136 #define FMC_SR4_ILS FMC_SR4_ILS_Msk /*!<Interrupt Level status */
AnnaBridge 167:e84263d55307 8137 #define FMC_SR4_IFS_Pos (2U)
AnnaBridge 167:e84263d55307 8138 #define FMC_SR4_IFS_Msk (0x1U << FMC_SR4_IFS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8139 #define FMC_SR4_IFS FMC_SR4_IFS_Msk /*!<Interrupt Falling Edge status */
AnnaBridge 167:e84263d55307 8140 #define FMC_SR4_IREN_Pos (3U)
AnnaBridge 167:e84263d55307 8141 #define FMC_SR4_IREN_Msk (0x1U << FMC_SR4_IREN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8142 #define FMC_SR4_IREN FMC_SR4_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8143 #define FMC_SR4_ILEN_Pos (4U)
AnnaBridge 167:e84263d55307 8144 #define FMC_SR4_ILEN_Msk (0x1U << FMC_SR4_ILEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8145 #define FMC_SR4_ILEN FMC_SR4_ILEN_Msk /*!<Interrupt Level detection Enable bit */
AnnaBridge 167:e84263d55307 8146 #define FMC_SR4_IFEN_Pos (5U)
AnnaBridge 167:e84263d55307 8147 #define FMC_SR4_IFEN_Msk (0x1U << FMC_SR4_IFEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8148 #define FMC_SR4_IFEN FMC_SR4_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
AnnaBridge 167:e84263d55307 8149 #define FMC_SR4_FEMPT_Pos (6U)
AnnaBridge 167:e84263d55307 8150 #define FMC_SR4_FEMPT_Msk (0x1U << FMC_SR4_FEMPT_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8151 #define FMC_SR4_FEMPT FMC_SR4_FEMPT_Msk /*!<FIFO empty */
<> 144:ef7eb2e8f9f7 8152
<> 144:ef7eb2e8f9f7 8153 /****************** Bit definition for FMC_PMEM2 register ******************/
AnnaBridge 167:e84263d55307 8154 #define FMC_PMEM2_MEMSET2_Pos (0U)
AnnaBridge 167:e84263d55307 8155 #define FMC_PMEM2_MEMSET2_Msk (0xFFU << FMC_PMEM2_MEMSET2_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8156 #define FMC_PMEM2_MEMSET2 FMC_PMEM2_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
AnnaBridge 167:e84263d55307 8157 #define FMC_PMEM2_MEMSET2_0 (0x01U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8158 #define FMC_PMEM2_MEMSET2_1 (0x02U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8159 #define FMC_PMEM2_MEMSET2_2 (0x04U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8160 #define FMC_PMEM2_MEMSET2_3 (0x08U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8161 #define FMC_PMEM2_MEMSET2_4 (0x10U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8162 #define FMC_PMEM2_MEMSET2_5 (0x20U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8163 #define FMC_PMEM2_MEMSET2_6 (0x40U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8164 #define FMC_PMEM2_MEMSET2_7 (0x80U << FMC_PMEM2_MEMSET2_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8165
AnnaBridge 167:e84263d55307 8166 #define FMC_PMEM2_MEMWAIT2_Pos (8U)
AnnaBridge 167:e84263d55307 8167 #define FMC_PMEM2_MEMWAIT2_Msk (0xFFU << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8168 #define FMC_PMEM2_MEMWAIT2 FMC_PMEM2_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
AnnaBridge 167:e84263d55307 8169 #define FMC_PMEM2_MEMWAIT2_0 (0x01U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8170 #define FMC_PMEM2_MEMWAIT2_1 (0x02U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8171 #define FMC_PMEM2_MEMWAIT2_2 (0x04U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8172 #define FMC_PMEM2_MEMWAIT2_3 (0x08U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8173 #define FMC_PMEM2_MEMWAIT2_4 (0x10U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8174 #define FMC_PMEM2_MEMWAIT2_5 (0x20U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8175 #define FMC_PMEM2_MEMWAIT2_6 (0x40U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8176 #define FMC_PMEM2_MEMWAIT2_7 (0x80U << FMC_PMEM2_MEMWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8177
AnnaBridge 167:e84263d55307 8178 #define FMC_PMEM2_MEMHOLD2_Pos (16U)
AnnaBridge 167:e84263d55307 8179 #define FMC_PMEM2_MEMHOLD2_Msk (0xFFU << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8180 #define FMC_PMEM2_MEMHOLD2 FMC_PMEM2_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
AnnaBridge 167:e84263d55307 8181 #define FMC_PMEM2_MEMHOLD2_0 (0x01U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8182 #define FMC_PMEM2_MEMHOLD2_1 (0x02U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8183 #define FMC_PMEM2_MEMHOLD2_2 (0x04U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8184 #define FMC_PMEM2_MEMHOLD2_3 (0x08U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8185 #define FMC_PMEM2_MEMHOLD2_4 (0x10U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8186 #define FMC_PMEM2_MEMHOLD2_5 (0x20U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8187 #define FMC_PMEM2_MEMHOLD2_6 (0x40U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8188 #define FMC_PMEM2_MEMHOLD2_7 (0x80U << FMC_PMEM2_MEMHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8189
AnnaBridge 167:e84263d55307 8190 #define FMC_PMEM2_MEMHIZ2_Pos (24U)
AnnaBridge 167:e84263d55307 8191 #define FMC_PMEM2_MEMHIZ2_Msk (0xFFU << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8192 #define FMC_PMEM2_MEMHIZ2 FMC_PMEM2_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
AnnaBridge 167:e84263d55307 8193 #define FMC_PMEM2_MEMHIZ2_0 (0x01U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8194 #define FMC_PMEM2_MEMHIZ2_1 (0x02U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8195 #define FMC_PMEM2_MEMHIZ2_2 (0x04U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8196 #define FMC_PMEM2_MEMHIZ2_3 (0x08U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8197 #define FMC_PMEM2_MEMHIZ2_4 (0x10U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8198 #define FMC_PMEM2_MEMHIZ2_5 (0x20U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8199 #define FMC_PMEM2_MEMHIZ2_6 (0x40U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8200 #define FMC_PMEM2_MEMHIZ2_7 (0x80U << FMC_PMEM2_MEMHIZ2_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8201
<> 144:ef7eb2e8f9f7 8202 /****************** Bit definition for FMC_PMEM3 register ******************/
AnnaBridge 167:e84263d55307 8203 #define FMC_PMEM3_MEMSET3_Pos (0U)
AnnaBridge 167:e84263d55307 8204 #define FMC_PMEM3_MEMSET3_Msk (0xFFU << FMC_PMEM3_MEMSET3_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8205 #define FMC_PMEM3_MEMSET3 FMC_PMEM3_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
AnnaBridge 167:e84263d55307 8206 #define FMC_PMEM3_MEMSET3_0 (0x01U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8207 #define FMC_PMEM3_MEMSET3_1 (0x02U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8208 #define FMC_PMEM3_MEMSET3_2 (0x04U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8209 #define FMC_PMEM3_MEMSET3_3 (0x08U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8210 #define FMC_PMEM3_MEMSET3_4 (0x10U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8211 #define FMC_PMEM3_MEMSET3_5 (0x20U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8212 #define FMC_PMEM3_MEMSET3_6 (0x40U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8213 #define FMC_PMEM3_MEMSET3_7 (0x80U << FMC_PMEM3_MEMSET3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8214
AnnaBridge 167:e84263d55307 8215 #define FMC_PMEM3_MEMWAIT3_Pos (8U)
AnnaBridge 167:e84263d55307 8216 #define FMC_PMEM3_MEMWAIT3_Msk (0xFFU << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8217 #define FMC_PMEM3_MEMWAIT3 FMC_PMEM3_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
AnnaBridge 167:e84263d55307 8218 #define FMC_PMEM3_MEMWAIT3_0 (0x01U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8219 #define FMC_PMEM3_MEMWAIT3_1 (0x02U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8220 #define FMC_PMEM3_MEMWAIT3_2 (0x04U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8221 #define FMC_PMEM3_MEMWAIT3_3 (0x08U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8222 #define FMC_PMEM3_MEMWAIT3_4 (0x10U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8223 #define FMC_PMEM3_MEMWAIT3_5 (0x20U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8224 #define FMC_PMEM3_MEMWAIT3_6 (0x40U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8225 #define FMC_PMEM3_MEMWAIT3_7 (0x80U << FMC_PMEM3_MEMWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8226
AnnaBridge 167:e84263d55307 8227 #define FMC_PMEM3_MEMHOLD3_Pos (16U)
AnnaBridge 167:e84263d55307 8228 #define FMC_PMEM3_MEMHOLD3_Msk (0xFFU << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8229 #define FMC_PMEM3_MEMHOLD3 FMC_PMEM3_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
AnnaBridge 167:e84263d55307 8230 #define FMC_PMEM3_MEMHOLD3_0 (0x01U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8231 #define FMC_PMEM3_MEMHOLD3_1 (0x02U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8232 #define FMC_PMEM3_MEMHOLD3_2 (0x04U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8233 #define FMC_PMEM3_MEMHOLD3_3 (0x08U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8234 #define FMC_PMEM3_MEMHOLD3_4 (0x10U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8235 #define FMC_PMEM3_MEMHOLD3_5 (0x20U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8236 #define FMC_PMEM3_MEMHOLD3_6 (0x40U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8237 #define FMC_PMEM3_MEMHOLD3_7 (0x80U << FMC_PMEM3_MEMHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8238
AnnaBridge 167:e84263d55307 8239 #define FMC_PMEM3_MEMHIZ3_Pos (24U)
AnnaBridge 167:e84263d55307 8240 #define FMC_PMEM3_MEMHIZ3_Msk (0xFFU << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8241 #define FMC_PMEM3_MEMHIZ3 FMC_PMEM3_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
AnnaBridge 167:e84263d55307 8242 #define FMC_PMEM3_MEMHIZ3_0 (0x01U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8243 #define FMC_PMEM3_MEMHIZ3_1 (0x02U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8244 #define FMC_PMEM3_MEMHIZ3_2 (0x04U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8245 #define FMC_PMEM3_MEMHIZ3_3 (0x08U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8246 #define FMC_PMEM3_MEMHIZ3_4 (0x10U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8247 #define FMC_PMEM3_MEMHIZ3_5 (0x20U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8248 #define FMC_PMEM3_MEMHIZ3_6 (0x40U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8249 #define FMC_PMEM3_MEMHIZ3_7 (0x80U << FMC_PMEM3_MEMHIZ3_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8250
<> 144:ef7eb2e8f9f7 8251 /****************** Bit definition for FMC_PMEM4 register ******************/
AnnaBridge 167:e84263d55307 8252 #define FMC_PMEM4_MEMSET4_Pos (0U)
AnnaBridge 167:e84263d55307 8253 #define FMC_PMEM4_MEMSET4_Msk (0xFFU << FMC_PMEM4_MEMSET4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8254 #define FMC_PMEM4_MEMSET4 FMC_PMEM4_MEMSET4_Msk /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
AnnaBridge 167:e84263d55307 8255 #define FMC_PMEM4_MEMSET4_0 (0x01U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8256 #define FMC_PMEM4_MEMSET4_1 (0x02U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8257 #define FMC_PMEM4_MEMSET4_2 (0x04U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8258 #define FMC_PMEM4_MEMSET4_3 (0x08U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8259 #define FMC_PMEM4_MEMSET4_4 (0x10U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8260 #define FMC_PMEM4_MEMSET4_5 (0x20U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8261 #define FMC_PMEM4_MEMSET4_6 (0x40U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8262 #define FMC_PMEM4_MEMSET4_7 (0x80U << FMC_PMEM4_MEMSET4_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8263
AnnaBridge 167:e84263d55307 8264 #define FMC_PMEM4_MEMWAIT4_Pos (8U)
AnnaBridge 167:e84263d55307 8265 #define FMC_PMEM4_MEMWAIT4_Msk (0xFFU << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8266 #define FMC_PMEM4_MEMWAIT4 FMC_PMEM4_MEMWAIT4_Msk /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
AnnaBridge 167:e84263d55307 8267 #define FMC_PMEM4_MEMWAIT4_0 (0x01U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8268 #define FMC_PMEM4_MEMWAIT4_1 (0x02U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8269 #define FMC_PMEM4_MEMWAIT4_2 (0x04U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8270 #define FMC_PMEM4_MEMWAIT4_3 (0x08U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8271 #define FMC_PMEM4_MEMWAIT4_4 (0x10U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8272 #define FMC_PMEM4_MEMWAIT4_5 (0x20U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8273 #define FMC_PMEM4_MEMWAIT4_6 (0x40U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8274 #define FMC_PMEM4_MEMWAIT4_7 (0x80U << FMC_PMEM4_MEMWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8275
AnnaBridge 167:e84263d55307 8276 #define FMC_PMEM4_MEMHOLD4_Pos (16U)
AnnaBridge 167:e84263d55307 8277 #define FMC_PMEM4_MEMHOLD4_Msk (0xFFU << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8278 #define FMC_PMEM4_MEMHOLD4 FMC_PMEM4_MEMHOLD4_Msk /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
AnnaBridge 167:e84263d55307 8279 #define FMC_PMEM4_MEMHOLD4_0 (0x01U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8280 #define FMC_PMEM4_MEMHOLD4_1 (0x02U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8281 #define FMC_PMEM4_MEMHOLD4_2 (0x04U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8282 #define FMC_PMEM4_MEMHOLD4_3 (0x08U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8283 #define FMC_PMEM4_MEMHOLD4_4 (0x10U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8284 #define FMC_PMEM4_MEMHOLD4_5 (0x20U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8285 #define FMC_PMEM4_MEMHOLD4_6 (0x40U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8286 #define FMC_PMEM4_MEMHOLD4_7 (0x80U << FMC_PMEM4_MEMHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8287
AnnaBridge 167:e84263d55307 8288 #define FMC_PMEM4_MEMHIZ4_Pos (24U)
AnnaBridge 167:e84263d55307 8289 #define FMC_PMEM4_MEMHIZ4_Msk (0xFFU << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8290 #define FMC_PMEM4_MEMHIZ4 FMC_PMEM4_MEMHIZ4_Msk /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
AnnaBridge 167:e84263d55307 8291 #define FMC_PMEM4_MEMHIZ4_0 (0x01U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8292 #define FMC_PMEM4_MEMHIZ4_1 (0x02U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8293 #define FMC_PMEM4_MEMHIZ4_2 (0x04U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8294 #define FMC_PMEM4_MEMHIZ4_3 (0x08U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8295 #define FMC_PMEM4_MEMHIZ4_4 (0x10U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8296 #define FMC_PMEM4_MEMHIZ4_5 (0x20U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8297 #define FMC_PMEM4_MEMHIZ4_6 (0x40U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8298 #define FMC_PMEM4_MEMHIZ4_7 (0x80U << FMC_PMEM4_MEMHIZ4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8299
<> 144:ef7eb2e8f9f7 8300 /****************** Bit definition for FMC_PATT2 register ******************/
AnnaBridge 167:e84263d55307 8301 #define FMC_PATT2_ATTSET2_Pos (0U)
AnnaBridge 167:e84263d55307 8302 #define FMC_PATT2_ATTSET2_Msk (0xFFU << FMC_PATT2_ATTSET2_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8303 #define FMC_PATT2_ATTSET2 FMC_PATT2_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
AnnaBridge 167:e84263d55307 8304 #define FMC_PATT2_ATTSET2_0 (0x01U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8305 #define FMC_PATT2_ATTSET2_1 (0x02U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8306 #define FMC_PATT2_ATTSET2_2 (0x04U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8307 #define FMC_PATT2_ATTSET2_3 (0x08U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8308 #define FMC_PATT2_ATTSET2_4 (0x10U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8309 #define FMC_PATT2_ATTSET2_5 (0x20U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8310 #define FMC_PATT2_ATTSET2_6 (0x40U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8311 #define FMC_PATT2_ATTSET2_7 (0x80U << FMC_PATT2_ATTSET2_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8312
AnnaBridge 167:e84263d55307 8313 #define FMC_PATT2_ATTWAIT2_Pos (8U)
AnnaBridge 167:e84263d55307 8314 #define FMC_PATT2_ATTWAIT2_Msk (0xFFU << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8315 #define FMC_PATT2_ATTWAIT2 FMC_PATT2_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
AnnaBridge 167:e84263d55307 8316 #define FMC_PATT2_ATTWAIT2_0 (0x01U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8317 #define FMC_PATT2_ATTWAIT2_1 (0x02U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8318 #define FMC_PATT2_ATTWAIT2_2 (0x04U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8319 #define FMC_PATT2_ATTWAIT2_3 (0x08U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8320 #define FMC_PATT2_ATTWAIT2_4 (0x10U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8321 #define FMC_PATT2_ATTWAIT2_5 (0x20U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8322 #define FMC_PATT2_ATTWAIT2_6 (0x40U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8323 #define FMC_PATT2_ATTWAIT2_7 (0x80U << FMC_PATT2_ATTWAIT2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8324
AnnaBridge 167:e84263d55307 8325 #define FMC_PATT2_ATTHOLD2_Pos (16U)
AnnaBridge 167:e84263d55307 8326 #define FMC_PATT2_ATTHOLD2_Msk (0xFFU << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8327 #define FMC_PATT2_ATTHOLD2 FMC_PATT2_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
AnnaBridge 167:e84263d55307 8328 #define FMC_PATT2_ATTHOLD2_0 (0x01U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8329 #define FMC_PATT2_ATTHOLD2_1 (0x02U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8330 #define FMC_PATT2_ATTHOLD2_2 (0x04U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8331 #define FMC_PATT2_ATTHOLD2_3 (0x08U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8332 #define FMC_PATT2_ATTHOLD2_4 (0x10U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8333 #define FMC_PATT2_ATTHOLD2_5 (0x20U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8334 #define FMC_PATT2_ATTHOLD2_6 (0x40U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8335 #define FMC_PATT2_ATTHOLD2_7 (0x80U << FMC_PATT2_ATTHOLD2_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8336
AnnaBridge 167:e84263d55307 8337 #define FMC_PATT2_ATTHIZ2_Pos (24U)
AnnaBridge 167:e84263d55307 8338 #define FMC_PATT2_ATTHIZ2_Msk (0xFFU << FMC_PATT2_ATTHIZ2_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8339 #define FMC_PATT2_ATTHIZ2 FMC_PATT2_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
AnnaBridge 167:e84263d55307 8340 #define FMC_PATT2_ATTHIZ2_0 (0x01U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8341 #define FMC_PATT2_ATTHIZ2_1 (0x02U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8342 #define FMC_PATT2_ATTHIZ2_2 (0x04U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8343 #define FMC_PATT2_ATTHIZ2_3 (0x08U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8344 #define FMC_PATT2_ATTHIZ2_4 (0x10U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8345 #define FMC_PATT2_ATTHIZ2_5 (0x20U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8346 #define FMC_PATT2_ATTHIZ2_6 (0x40U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8347 #define FMC_PATT2_ATTHIZ2_7 (0x80U << FMC_PATT2_ATTHIZ2_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8348
<> 144:ef7eb2e8f9f7 8349 /****************** Bit definition for FMC_PATT3 register ******************/
AnnaBridge 167:e84263d55307 8350 #define FMC_PATT3_ATTSET3_Pos (0U)
AnnaBridge 167:e84263d55307 8351 #define FMC_PATT3_ATTSET3_Msk (0xFFU << FMC_PATT3_ATTSET3_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8352 #define FMC_PATT3_ATTSET3 FMC_PATT3_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
AnnaBridge 167:e84263d55307 8353 #define FMC_PATT3_ATTSET3_0 (0x01U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8354 #define FMC_PATT3_ATTSET3_1 (0x02U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8355 #define FMC_PATT3_ATTSET3_2 (0x04U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8356 #define FMC_PATT3_ATTSET3_3 (0x08U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8357 #define FMC_PATT3_ATTSET3_4 (0x10U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8358 #define FMC_PATT3_ATTSET3_5 (0x20U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8359 #define FMC_PATT3_ATTSET3_6 (0x40U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8360 #define FMC_PATT3_ATTSET3_7 (0x80U << FMC_PATT3_ATTSET3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8361
AnnaBridge 167:e84263d55307 8362 #define FMC_PATT3_ATTWAIT3_Pos (8U)
AnnaBridge 167:e84263d55307 8363 #define FMC_PATT3_ATTWAIT3_Msk (0xFFU << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8364 #define FMC_PATT3_ATTWAIT3 FMC_PATT3_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
AnnaBridge 167:e84263d55307 8365 #define FMC_PATT3_ATTWAIT3_0 (0x01U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8366 #define FMC_PATT3_ATTWAIT3_1 (0x02U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8367 #define FMC_PATT3_ATTWAIT3_2 (0x04U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8368 #define FMC_PATT3_ATTWAIT3_3 (0x08U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8369 #define FMC_PATT3_ATTWAIT3_4 (0x10U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8370 #define FMC_PATT3_ATTWAIT3_5 (0x20U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8371 #define FMC_PATT3_ATTWAIT3_6 (0x40U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8372 #define FMC_PATT3_ATTWAIT3_7 (0x80U << FMC_PATT3_ATTWAIT3_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8373
AnnaBridge 167:e84263d55307 8374 #define FMC_PATT3_ATTHOLD3_Pos (16U)
AnnaBridge 167:e84263d55307 8375 #define FMC_PATT3_ATTHOLD3_Msk (0xFFU << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8376 #define FMC_PATT3_ATTHOLD3 FMC_PATT3_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
AnnaBridge 167:e84263d55307 8377 #define FMC_PATT3_ATTHOLD3_0 (0x01U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8378 #define FMC_PATT3_ATTHOLD3_1 (0x02U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8379 #define FMC_PATT3_ATTHOLD3_2 (0x04U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8380 #define FMC_PATT3_ATTHOLD3_3 (0x08U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8381 #define FMC_PATT3_ATTHOLD3_4 (0x10U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8382 #define FMC_PATT3_ATTHOLD3_5 (0x20U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8383 #define FMC_PATT3_ATTHOLD3_6 (0x40U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8384 #define FMC_PATT3_ATTHOLD3_7 (0x80U << FMC_PATT3_ATTHOLD3_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8385
AnnaBridge 167:e84263d55307 8386 #define FMC_PATT3_ATTHIZ3_Pos (24U)
AnnaBridge 167:e84263d55307 8387 #define FMC_PATT3_ATTHIZ3_Msk (0xFFU << FMC_PATT3_ATTHIZ3_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8388 #define FMC_PATT3_ATTHIZ3 FMC_PATT3_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
AnnaBridge 167:e84263d55307 8389 #define FMC_PATT3_ATTHIZ3_0 (0x01U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8390 #define FMC_PATT3_ATTHIZ3_1 (0x02U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8391 #define FMC_PATT3_ATTHIZ3_2 (0x04U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8392 #define FMC_PATT3_ATTHIZ3_3 (0x08U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8393 #define FMC_PATT3_ATTHIZ3_4 (0x10U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8394 #define FMC_PATT3_ATTHIZ3_5 (0x20U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8395 #define FMC_PATT3_ATTHIZ3_6 (0x40U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8396 #define FMC_PATT3_ATTHIZ3_7 (0x80U << FMC_PATT3_ATTHIZ3_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8397
<> 144:ef7eb2e8f9f7 8398 /****************** Bit definition for FMC_PATT4 register ******************/
AnnaBridge 167:e84263d55307 8399 #define FMC_PATT4_ATTSET4_Pos (0U)
AnnaBridge 167:e84263d55307 8400 #define FMC_PATT4_ATTSET4_Msk (0xFFU << FMC_PATT4_ATTSET4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8401 #define FMC_PATT4_ATTSET4 FMC_PATT4_ATTSET4_Msk /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
AnnaBridge 167:e84263d55307 8402 #define FMC_PATT4_ATTSET4_0 (0x01U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8403 #define FMC_PATT4_ATTSET4_1 (0x02U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8404 #define FMC_PATT4_ATTSET4_2 (0x04U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8405 #define FMC_PATT4_ATTSET4_3 (0x08U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8406 #define FMC_PATT4_ATTSET4_4 (0x10U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8407 #define FMC_PATT4_ATTSET4_5 (0x20U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8408 #define FMC_PATT4_ATTSET4_6 (0x40U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8409 #define FMC_PATT4_ATTSET4_7 (0x80U << FMC_PATT4_ATTSET4_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8410
AnnaBridge 167:e84263d55307 8411 #define FMC_PATT4_ATTWAIT4_Pos (8U)
AnnaBridge 167:e84263d55307 8412 #define FMC_PATT4_ATTWAIT4_Msk (0xFFU << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8413 #define FMC_PATT4_ATTWAIT4 FMC_PATT4_ATTWAIT4_Msk /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
AnnaBridge 167:e84263d55307 8414 #define FMC_PATT4_ATTWAIT4_0 (0x01U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8415 #define FMC_PATT4_ATTWAIT4_1 (0x02U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8416 #define FMC_PATT4_ATTWAIT4_2 (0x04U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8417 #define FMC_PATT4_ATTWAIT4_3 (0x08U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8418 #define FMC_PATT4_ATTWAIT4_4 (0x10U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8419 #define FMC_PATT4_ATTWAIT4_5 (0x20U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8420 #define FMC_PATT4_ATTWAIT4_6 (0x40U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8421 #define FMC_PATT4_ATTWAIT4_7 (0x80U << FMC_PATT4_ATTWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8422
AnnaBridge 167:e84263d55307 8423 #define FMC_PATT4_ATTHOLD4_Pos (16U)
AnnaBridge 167:e84263d55307 8424 #define FMC_PATT4_ATTHOLD4_Msk (0xFFU << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8425 #define FMC_PATT4_ATTHOLD4 FMC_PATT4_ATTHOLD4_Msk /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
AnnaBridge 167:e84263d55307 8426 #define FMC_PATT4_ATTHOLD4_0 (0x01U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8427 #define FMC_PATT4_ATTHOLD4_1 (0x02U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8428 #define FMC_PATT4_ATTHOLD4_2 (0x04U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8429 #define FMC_PATT4_ATTHOLD4_3 (0x08U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8430 #define FMC_PATT4_ATTHOLD4_4 (0x10U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8431 #define FMC_PATT4_ATTHOLD4_5 (0x20U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8432 #define FMC_PATT4_ATTHOLD4_6 (0x40U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8433 #define FMC_PATT4_ATTHOLD4_7 (0x80U << FMC_PATT4_ATTHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8434
AnnaBridge 167:e84263d55307 8435 #define FMC_PATT4_ATTHIZ4_Pos (24U)
AnnaBridge 167:e84263d55307 8436 #define FMC_PATT4_ATTHIZ4_Msk (0xFFU << FMC_PATT4_ATTHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8437 #define FMC_PATT4_ATTHIZ4 FMC_PATT4_ATTHIZ4_Msk /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
AnnaBridge 167:e84263d55307 8438 #define FMC_PATT4_ATTHIZ4_0 (0x01U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8439 #define FMC_PATT4_ATTHIZ4_1 (0x02U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8440 #define FMC_PATT4_ATTHIZ4_2 (0x04U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8441 #define FMC_PATT4_ATTHIZ4_3 (0x08U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8442 #define FMC_PATT4_ATTHIZ4_4 (0x10U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8443 #define FMC_PATT4_ATTHIZ4_5 (0x20U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8444 #define FMC_PATT4_ATTHIZ4_6 (0x40U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8445 #define FMC_PATT4_ATTHIZ4_7 (0x80U << FMC_PATT4_ATTHIZ4_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8446
<> 144:ef7eb2e8f9f7 8447 /****************** Bit definition for FMC_PIO4 register *******************/
AnnaBridge 167:e84263d55307 8448 #define FMC_PIO4_IOSET4_Pos (0U)
AnnaBridge 167:e84263d55307 8449 #define FMC_PIO4_IOSET4_Msk (0xFFU << FMC_PIO4_IOSET4_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 8450 #define FMC_PIO4_IOSET4 FMC_PIO4_IOSET4_Msk /*!<IOSET4[7:0] bits (I/O 4 setup time) */
AnnaBridge 167:e84263d55307 8451 #define FMC_PIO4_IOSET4_0 (0x01U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8452 #define FMC_PIO4_IOSET4_1 (0x02U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8453 #define FMC_PIO4_IOSET4_2 (0x04U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8454 #define FMC_PIO4_IOSET4_3 (0x08U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8455 #define FMC_PIO4_IOSET4_4 (0x10U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8456 #define FMC_PIO4_IOSET4_5 (0x20U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8457 #define FMC_PIO4_IOSET4_6 (0x40U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8458 #define FMC_PIO4_IOSET4_7 (0x80U << FMC_PIO4_IOSET4_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8459
AnnaBridge 167:e84263d55307 8460 #define FMC_PIO4_IOWAIT4_Pos (8U)
AnnaBridge 167:e84263d55307 8461 #define FMC_PIO4_IOWAIT4_Msk (0xFFU << FMC_PIO4_IOWAIT4_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 8462 #define FMC_PIO4_IOWAIT4 FMC_PIO4_IOWAIT4_Msk /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
AnnaBridge 167:e84263d55307 8463 #define FMC_PIO4_IOWAIT4_0 (0x01U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8464 #define FMC_PIO4_IOWAIT4_1 (0x02U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8465 #define FMC_PIO4_IOWAIT4_2 (0x04U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8466 #define FMC_PIO4_IOWAIT4_3 (0x08U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8467 #define FMC_PIO4_IOWAIT4_4 (0x10U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8468 #define FMC_PIO4_IOWAIT4_5 (0x20U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8469 #define FMC_PIO4_IOWAIT4_6 (0x40U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8470 #define FMC_PIO4_IOWAIT4_7 (0x80U << FMC_PIO4_IOWAIT4_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8471
AnnaBridge 167:e84263d55307 8472 #define FMC_PIO4_IOHOLD4_Pos (16U)
AnnaBridge 167:e84263d55307 8473 #define FMC_PIO4_IOHOLD4_Msk (0xFFU << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 8474 #define FMC_PIO4_IOHOLD4 FMC_PIO4_IOHOLD4_Msk /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
AnnaBridge 167:e84263d55307 8475 #define FMC_PIO4_IOHOLD4_0 (0x01U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8476 #define FMC_PIO4_IOHOLD4_1 (0x02U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8477 #define FMC_PIO4_IOHOLD4_2 (0x04U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8478 #define FMC_PIO4_IOHOLD4_3 (0x08U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8479 #define FMC_PIO4_IOHOLD4_4 (0x10U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8480 #define FMC_PIO4_IOHOLD4_5 (0x20U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8481 #define FMC_PIO4_IOHOLD4_6 (0x40U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8482 #define FMC_PIO4_IOHOLD4_7 (0x80U << FMC_PIO4_IOHOLD4_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8483
AnnaBridge 167:e84263d55307 8484 #define FMC_PIO4_IOHIZ4_Pos (24U)
AnnaBridge 167:e84263d55307 8485 #define FMC_PIO4_IOHIZ4_Msk (0xFFU << FMC_PIO4_IOHIZ4_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 8486 #define FMC_PIO4_IOHIZ4 FMC_PIO4_IOHIZ4_Msk /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
AnnaBridge 167:e84263d55307 8487 #define FMC_PIO4_IOHIZ4_0 (0x01U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8488 #define FMC_PIO4_IOHIZ4_1 (0x02U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8489 #define FMC_PIO4_IOHIZ4_2 (0x04U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8490 #define FMC_PIO4_IOHIZ4_3 (0x08U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8491 #define FMC_PIO4_IOHIZ4_4 (0x10U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8492 #define FMC_PIO4_IOHIZ4_5 (0x20U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8493 #define FMC_PIO4_IOHIZ4_6 (0x40U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8494 #define FMC_PIO4_IOHIZ4_7 (0x80U << FMC_PIO4_IOHIZ4_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 8495
<> 144:ef7eb2e8f9f7 8496
<> 144:ef7eb2e8f9f7 8497 /****************** Bit definition for FMC_ECCR2 register ******************/
AnnaBridge 167:e84263d55307 8498 #define FMC_ECCR2_ECC2_Pos (0U)
AnnaBridge 167:e84263d55307 8499 #define FMC_ECCR2_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR2_ECC2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 8500 #define FMC_ECCR2_ECC2 FMC_ECCR2_ECC2_Msk /*!<ECC result */
<> 144:ef7eb2e8f9f7 8501
<> 144:ef7eb2e8f9f7 8502 /****************** Bit definition for FMC_ECCR3 register ******************/
AnnaBridge 167:e84263d55307 8503 #define FMC_ECCR3_ECC3_Pos (0U)
AnnaBridge 167:e84263d55307 8504 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFU << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 8505 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
<> 144:ef7eb2e8f9f7 8506
<> 144:ef7eb2e8f9f7 8507 /****************** Bit definition for FMC_SDCR1 register ******************/
AnnaBridge 167:e84263d55307 8508 #define FMC_SDCR1_NC_Pos (0U)
AnnaBridge 167:e84263d55307 8509 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 8510 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 167:e84263d55307 8511 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8512 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8513
AnnaBridge 167:e84263d55307 8514 #define FMC_SDCR1_NR_Pos (2U)
AnnaBridge 167:e84263d55307 8515 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 8516 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 167:e84263d55307 8517 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8518 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8519
AnnaBridge 167:e84263d55307 8520 #define FMC_SDCR1_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 8521 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8522 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 167:e84263d55307 8523 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8524 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8525
AnnaBridge 167:e84263d55307 8526 #define FMC_SDCR1_NB_Pos (6U)
AnnaBridge 167:e84263d55307 8527 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8528 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
AnnaBridge 167:e84263d55307 8529
AnnaBridge 167:e84263d55307 8530 #define FMC_SDCR1_CAS_Pos (7U)
AnnaBridge 167:e84263d55307 8531 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 167:e84263d55307 8532 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 167:e84263d55307 8533 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8534 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8535
AnnaBridge 167:e84263d55307 8536 #define FMC_SDCR1_WP_Pos (9U)
AnnaBridge 167:e84263d55307 8537 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8538 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
AnnaBridge 167:e84263d55307 8539
AnnaBridge 167:e84263d55307 8540 #define FMC_SDCR1_SDCLK_Pos (10U)
AnnaBridge 167:e84263d55307 8541 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 8542 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
AnnaBridge 167:e84263d55307 8543 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8544 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8545
AnnaBridge 167:e84263d55307 8546 #define FMC_SDCR1_RBURST_Pos (12U)
AnnaBridge 167:e84263d55307 8547 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8548 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
AnnaBridge 167:e84263d55307 8549
AnnaBridge 167:e84263d55307 8550 #define FMC_SDCR1_RPIPE_Pos (13U)
AnnaBridge 167:e84263d55307 8551 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 167:e84263d55307 8552 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
AnnaBridge 167:e84263d55307 8553 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8554 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8555
<> 144:ef7eb2e8f9f7 8556 /****************** Bit definition for FMC_SDCR2 register ******************/
AnnaBridge 167:e84263d55307 8557 #define FMC_SDCR2_NC_Pos (0U)
AnnaBridge 167:e84263d55307 8558 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 8559 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
AnnaBridge 167:e84263d55307 8560 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8561 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8562
AnnaBridge 167:e84263d55307 8563 #define FMC_SDCR2_NR_Pos (2U)
AnnaBridge 167:e84263d55307 8564 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 8565 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 167:e84263d55307 8566 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8567 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8568
AnnaBridge 167:e84263d55307 8569 #define FMC_SDCR2_MWID_Pos (4U)
AnnaBridge 167:e84263d55307 8570 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8571 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
AnnaBridge 167:e84263d55307 8572 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8573 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8574
AnnaBridge 167:e84263d55307 8575 #define FMC_SDCR2_NB_Pos (6U)
AnnaBridge 167:e84263d55307 8576 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8577 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
AnnaBridge 167:e84263d55307 8578
AnnaBridge 167:e84263d55307 8579 #define FMC_SDCR2_CAS_Pos (7U)
AnnaBridge 167:e84263d55307 8580 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
AnnaBridge 167:e84263d55307 8581 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
AnnaBridge 167:e84263d55307 8582 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8583 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8584
AnnaBridge 167:e84263d55307 8585 #define FMC_SDCR2_WP_Pos (9U)
AnnaBridge 167:e84263d55307 8586 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8587 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
AnnaBridge 167:e84263d55307 8588
AnnaBridge 167:e84263d55307 8589 #define FMC_SDCR2_SDCLK_Pos (10U)
AnnaBridge 167:e84263d55307 8590 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 8591 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
AnnaBridge 167:e84263d55307 8592 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8593 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8594
AnnaBridge 167:e84263d55307 8595 #define FMC_SDCR2_RBURST_Pos (12U)
AnnaBridge 167:e84263d55307 8596 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8597 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
AnnaBridge 167:e84263d55307 8598
AnnaBridge 167:e84263d55307 8599 #define FMC_SDCR2_RPIPE_Pos (13U)
AnnaBridge 167:e84263d55307 8600 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
AnnaBridge 167:e84263d55307 8601 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
AnnaBridge 167:e84263d55307 8602 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8603 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
<> 144:ef7eb2e8f9f7 8604
<> 144:ef7eb2e8f9f7 8605 /****************** Bit definition for FMC_SDTR1 register ******************/
AnnaBridge 167:e84263d55307 8606 #define FMC_SDTR1_TMRD_Pos (0U)
AnnaBridge 167:e84263d55307 8607 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 8608 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 167:e84263d55307 8609 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8610 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8611 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8612 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8613
AnnaBridge 167:e84263d55307 8614 #define FMC_SDTR1_TXSR_Pos (4U)
AnnaBridge 167:e84263d55307 8615 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 8616 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 167:e84263d55307 8617 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8618 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8619 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8620 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8621
AnnaBridge 167:e84263d55307 8622 #define FMC_SDTR1_TRAS_Pos (8U)
AnnaBridge 167:e84263d55307 8623 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 8624 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 167:e84263d55307 8625 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8626 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8627 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8628 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8629
AnnaBridge 167:e84263d55307 8630 #define FMC_SDTR1_TRC_Pos (12U)
AnnaBridge 167:e84263d55307 8631 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 8632 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 167:e84263d55307 8633 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8634 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8635 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8636
AnnaBridge 167:e84263d55307 8637 #define FMC_SDTR1_TWR_Pos (16U)
AnnaBridge 167:e84263d55307 8638 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 8639 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 167:e84263d55307 8640 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8641 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8642 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8643
AnnaBridge 167:e84263d55307 8644 #define FMC_SDTR1_TRP_Pos (20U)
AnnaBridge 167:e84263d55307 8645 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 8646 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 167:e84263d55307 8647 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8648 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8649 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8650
AnnaBridge 167:e84263d55307 8651 #define FMC_SDTR1_TRCD_Pos (24U)
AnnaBridge 167:e84263d55307 8652 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 8653 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 167:e84263d55307 8654 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8655 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8656 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8657
<> 144:ef7eb2e8f9f7 8658 /****************** Bit definition for FMC_SDTR2 register ******************/
AnnaBridge 167:e84263d55307 8659 #define FMC_SDTR2_TMRD_Pos (0U)
AnnaBridge 167:e84263d55307 8660 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 8661 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
AnnaBridge 167:e84263d55307 8662 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8663 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8664 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8665 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 8666
AnnaBridge 167:e84263d55307 8667 #define FMC_SDTR2_TXSR_Pos (4U)
AnnaBridge 167:e84263d55307 8668 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 8669 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
AnnaBridge 167:e84263d55307 8670 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8671 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8672 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8673 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8674
AnnaBridge 167:e84263d55307 8675 #define FMC_SDTR2_TRAS_Pos (8U)
AnnaBridge 167:e84263d55307 8676 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 8677 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
AnnaBridge 167:e84263d55307 8678 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8679 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8680 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8681 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8682
AnnaBridge 167:e84263d55307 8683 #define FMC_SDTR2_TRC_Pos (12U)
AnnaBridge 167:e84263d55307 8684 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 8685 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
AnnaBridge 167:e84263d55307 8686 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8687 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8688 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8689
AnnaBridge 167:e84263d55307 8690 #define FMC_SDTR2_TWR_Pos (16U)
AnnaBridge 167:e84263d55307 8691 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 8692 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
AnnaBridge 167:e84263d55307 8693 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8694 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8695 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8696
AnnaBridge 167:e84263d55307 8697 #define FMC_SDTR2_TRP_Pos (20U)
AnnaBridge 167:e84263d55307 8698 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 8699 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
AnnaBridge 167:e84263d55307 8700 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8701 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8702 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8703
AnnaBridge 167:e84263d55307 8704 #define FMC_SDTR2_TRCD_Pos (24U)
AnnaBridge 167:e84263d55307 8705 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 8706 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
AnnaBridge 167:e84263d55307 8707 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8708 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8709 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
<> 144:ef7eb2e8f9f7 8710
<> 144:ef7eb2e8f9f7 8711 /****************** Bit definition for FMC_SDCMR register ******************/
AnnaBridge 167:e84263d55307 8712 #define FMC_SDCMR_MODE_Pos (0U)
AnnaBridge 167:e84263d55307 8713 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 8714 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
AnnaBridge 167:e84263d55307 8715 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8716 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8717 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
<> 144:ef7eb2e8f9f7 8718
AnnaBridge 167:e84263d55307 8719 #define FMC_SDCMR_CTB2_Pos (3U)
AnnaBridge 167:e84263d55307 8720 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8721 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
AnnaBridge 167:e84263d55307 8722
AnnaBridge 167:e84263d55307 8723 #define FMC_SDCMR_CTB1_Pos (4U)
AnnaBridge 167:e84263d55307 8724 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8725 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
AnnaBridge 167:e84263d55307 8726
AnnaBridge 167:e84263d55307 8727 #define FMC_SDCMR_NRFS_Pos (5U)
AnnaBridge 167:e84263d55307 8728 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
AnnaBridge 167:e84263d55307 8729 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
AnnaBridge 167:e84263d55307 8730 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8731 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8732 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8733 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8734
AnnaBridge 167:e84263d55307 8735 #define FMC_SDCMR_MRD_Pos (9U)
AnnaBridge 167:e84263d55307 8736 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
AnnaBridge 167:e84263d55307 8737 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
<> 144:ef7eb2e8f9f7 8738
<> 144:ef7eb2e8f9f7 8739 /****************** Bit definition for FMC_SDRTR register ******************/
AnnaBridge 167:e84263d55307 8740 #define FMC_SDRTR_CRE_Pos (0U)
AnnaBridge 167:e84263d55307 8741 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8742 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
AnnaBridge 167:e84263d55307 8743
AnnaBridge 167:e84263d55307 8744 #define FMC_SDRTR_COUNT_Pos (1U)
AnnaBridge 167:e84263d55307 8745 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
AnnaBridge 167:e84263d55307 8746 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
AnnaBridge 167:e84263d55307 8747
AnnaBridge 167:e84263d55307 8748 #define FMC_SDRTR_REIE_Pos (14U)
AnnaBridge 167:e84263d55307 8749 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8750 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
<> 144:ef7eb2e8f9f7 8751
<> 144:ef7eb2e8f9f7 8752 /****************** Bit definition for FMC_SDSR register ******************/
AnnaBridge 167:e84263d55307 8753 #define FMC_SDSR_RE_Pos (0U)
AnnaBridge 167:e84263d55307 8754 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8755 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
AnnaBridge 167:e84263d55307 8756
AnnaBridge 167:e84263d55307 8757 #define FMC_SDSR_MODES1_Pos (1U)
AnnaBridge 167:e84263d55307 8758 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
AnnaBridge 167:e84263d55307 8759 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
AnnaBridge 167:e84263d55307 8760 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8761 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8762
AnnaBridge 167:e84263d55307 8763 #define FMC_SDSR_MODES2_Pos (3U)
AnnaBridge 167:e84263d55307 8764 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
AnnaBridge 167:e84263d55307 8765 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
AnnaBridge 167:e84263d55307 8766 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8767 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8768 #define FMC_SDSR_BUSY_Pos (5U)
AnnaBridge 167:e84263d55307 8769 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8770 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
<> 144:ef7eb2e8f9f7 8771
<> 144:ef7eb2e8f9f7 8772 /******************************************************************************/
<> 144:ef7eb2e8f9f7 8773 /* */
<> 144:ef7eb2e8f9f7 8774 /* General Purpose I/O */
<> 144:ef7eb2e8f9f7 8775 /* */
<> 144:ef7eb2e8f9f7 8776 /******************************************************************************/
<> 144:ef7eb2e8f9f7 8777 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 167:e84263d55307 8778 #define GPIO_MODER_MODE0_Pos (0U)
AnnaBridge 167:e84263d55307 8779 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 8780 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
AnnaBridge 167:e84263d55307 8781 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8782 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8783 #define GPIO_MODER_MODE1_Pos (2U)
AnnaBridge 167:e84263d55307 8784 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 8785 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
AnnaBridge 167:e84263d55307 8786 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8787 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8788 #define GPIO_MODER_MODE2_Pos (4U)
AnnaBridge 167:e84263d55307 8789 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8790 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
AnnaBridge 167:e84263d55307 8791 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8792 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8793 #define GPIO_MODER_MODE3_Pos (6U)
AnnaBridge 167:e84263d55307 8794 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 8795 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
AnnaBridge 167:e84263d55307 8796 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8797 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8798 #define GPIO_MODER_MODE4_Pos (8U)
AnnaBridge 167:e84263d55307 8799 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 8800 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
AnnaBridge 167:e84263d55307 8801 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8802 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8803 #define GPIO_MODER_MODE5_Pos (10U)
AnnaBridge 167:e84263d55307 8804 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 8805 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
AnnaBridge 167:e84263d55307 8806 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8807 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8808 #define GPIO_MODER_MODE6_Pos (12U)
AnnaBridge 167:e84263d55307 8809 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 8810 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
AnnaBridge 167:e84263d55307 8811 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8812 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8813 #define GPIO_MODER_MODE7_Pos (14U)
AnnaBridge 167:e84263d55307 8814 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 8815 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
AnnaBridge 167:e84263d55307 8816 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8817 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8818 #define GPIO_MODER_MODE8_Pos (16U)
AnnaBridge 167:e84263d55307 8819 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 8820 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
AnnaBridge 167:e84263d55307 8821 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8822 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8823 #define GPIO_MODER_MODE9_Pos (18U)
AnnaBridge 167:e84263d55307 8824 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 8825 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
AnnaBridge 167:e84263d55307 8826 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8827 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8828 #define GPIO_MODER_MODE10_Pos (20U)
AnnaBridge 167:e84263d55307 8829 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 8830 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
AnnaBridge 167:e84263d55307 8831 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8832 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8833 #define GPIO_MODER_MODE11_Pos (22U)
AnnaBridge 167:e84263d55307 8834 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 8835 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
AnnaBridge 167:e84263d55307 8836 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8837 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8838 #define GPIO_MODER_MODE12_Pos (24U)
AnnaBridge 167:e84263d55307 8839 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 8840 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
AnnaBridge 167:e84263d55307 8841 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8842 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8843 #define GPIO_MODER_MODE13_Pos (26U)
AnnaBridge 167:e84263d55307 8844 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
AnnaBridge 167:e84263d55307 8845 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
AnnaBridge 167:e84263d55307 8846 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8847 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8848 #define GPIO_MODER_MODE14_Pos (28U)
AnnaBridge 167:e84263d55307 8849 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 8850 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
AnnaBridge 167:e84263d55307 8851 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8852 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8853 #define GPIO_MODER_MODE15_Pos (30U)
AnnaBridge 167:e84263d55307 8854 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
AnnaBridge 167:e84263d55307 8855 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
AnnaBridge 167:e84263d55307 8856 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8857 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 8858
AnnaBridge 167:e84263d55307 8859 /* Legacy defines */
AnnaBridge 167:e84263d55307 8860 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 167:e84263d55307 8861 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 8862 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 167:e84263d55307 8863 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8864 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8865 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 167:e84263d55307 8866 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 8867 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 167:e84263d55307 8868 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8869 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8870 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 167:e84263d55307 8871 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 8872 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 167:e84263d55307 8873 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8874 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8875 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 167:e84263d55307 8876 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 8877 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 167:e84263d55307 8878 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8879 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8880 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 167:e84263d55307 8881 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 8882 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 167:e84263d55307 8883 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8884 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8885 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 167:e84263d55307 8886 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 8887 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 167:e84263d55307 8888 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8889 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8890 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 167:e84263d55307 8891 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 8892 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 167:e84263d55307 8893 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8894 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8895 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 167:e84263d55307 8896 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 8897 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 167:e84263d55307 8898 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8899 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8900 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 167:e84263d55307 8901 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 8902 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 167:e84263d55307 8903 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 8904 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 8905 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 167:e84263d55307 8906 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 8907 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 167:e84263d55307 8908 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 8909 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 8910 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 167:e84263d55307 8911 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 8912 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 167:e84263d55307 8913 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 8914 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 8915 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 167:e84263d55307 8916 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 8917 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 167:e84263d55307 8918 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 8919 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 8920 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 167:e84263d55307 8921 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 8922 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 167:e84263d55307 8923 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 8924 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 8925 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 167:e84263d55307 8926 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 167:e84263d55307 8927 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 167:e84263d55307 8928 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 8929 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 8930 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 167:e84263d55307 8931 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 8932 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 167:e84263d55307 8933 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 8934 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 8935 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 167:e84263d55307 8936 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 167:e84263d55307 8937 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 167:e84263d55307 8938 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 8939 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 8940
<> 144:ef7eb2e8f9f7 8941 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 167:e84263d55307 8942 #define GPIO_OTYPER_OT0_Pos (0U)
AnnaBridge 167:e84263d55307 8943 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 8944 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
AnnaBridge 167:e84263d55307 8945 #define GPIO_OTYPER_OT1_Pos (1U)
AnnaBridge 167:e84263d55307 8946 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 8947 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
AnnaBridge 167:e84263d55307 8948 #define GPIO_OTYPER_OT2_Pos (2U)
AnnaBridge 167:e84263d55307 8949 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 8950 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
AnnaBridge 167:e84263d55307 8951 #define GPIO_OTYPER_OT3_Pos (3U)
AnnaBridge 167:e84263d55307 8952 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 8953 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
AnnaBridge 167:e84263d55307 8954 #define GPIO_OTYPER_OT4_Pos (4U)
AnnaBridge 167:e84263d55307 8955 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 8956 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
AnnaBridge 167:e84263d55307 8957 #define GPIO_OTYPER_OT5_Pos (5U)
AnnaBridge 167:e84263d55307 8958 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 8959 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
AnnaBridge 167:e84263d55307 8960 #define GPIO_OTYPER_OT6_Pos (6U)
AnnaBridge 167:e84263d55307 8961 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 8962 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
AnnaBridge 167:e84263d55307 8963 #define GPIO_OTYPER_OT7_Pos (7U)
AnnaBridge 167:e84263d55307 8964 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 8965 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
AnnaBridge 167:e84263d55307 8966 #define GPIO_OTYPER_OT8_Pos (8U)
AnnaBridge 167:e84263d55307 8967 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 8968 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
AnnaBridge 167:e84263d55307 8969 #define GPIO_OTYPER_OT9_Pos (9U)
AnnaBridge 167:e84263d55307 8970 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 8971 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
AnnaBridge 167:e84263d55307 8972 #define GPIO_OTYPER_OT10_Pos (10U)
AnnaBridge 167:e84263d55307 8973 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 8974 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
AnnaBridge 167:e84263d55307 8975 #define GPIO_OTYPER_OT11_Pos (11U)
AnnaBridge 167:e84263d55307 8976 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 8977 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
AnnaBridge 167:e84263d55307 8978 #define GPIO_OTYPER_OT12_Pos (12U)
AnnaBridge 167:e84263d55307 8979 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 8980 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
AnnaBridge 167:e84263d55307 8981 #define GPIO_OTYPER_OT13_Pos (13U)
AnnaBridge 167:e84263d55307 8982 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 8983 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
AnnaBridge 167:e84263d55307 8984 #define GPIO_OTYPER_OT14_Pos (14U)
AnnaBridge 167:e84263d55307 8985 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 8986 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
AnnaBridge 167:e84263d55307 8987 #define GPIO_OTYPER_OT15_Pos (15U)
AnnaBridge 167:e84263d55307 8988 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 8989 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
AnnaBridge 167:e84263d55307 8990
AnnaBridge 167:e84263d55307 8991 /* Legacy defines */
AnnaBridge 167:e84263d55307 8992 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
AnnaBridge 167:e84263d55307 8993 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
AnnaBridge 167:e84263d55307 8994 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
AnnaBridge 167:e84263d55307 8995 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
AnnaBridge 167:e84263d55307 8996 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
AnnaBridge 167:e84263d55307 8997 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
AnnaBridge 167:e84263d55307 8998 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
AnnaBridge 167:e84263d55307 8999 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
AnnaBridge 167:e84263d55307 9000 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
AnnaBridge 167:e84263d55307 9001 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
AnnaBridge 167:e84263d55307 9002 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
AnnaBridge 167:e84263d55307 9003 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
AnnaBridge 167:e84263d55307 9004 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
AnnaBridge 167:e84263d55307 9005 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
AnnaBridge 167:e84263d55307 9006 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
AnnaBridge 167:e84263d55307 9007 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
<> 144:ef7eb2e8f9f7 9008
<> 144:ef7eb2e8f9f7 9009 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 167:e84263d55307 9010 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
AnnaBridge 167:e84263d55307 9011 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 9012 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
AnnaBridge 167:e84263d55307 9013 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9014 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9015 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
AnnaBridge 167:e84263d55307 9016 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 9017 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
AnnaBridge 167:e84263d55307 9018 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9019 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9020 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
AnnaBridge 167:e84263d55307 9021 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 9022 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
AnnaBridge 167:e84263d55307 9023 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9024 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9025 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
AnnaBridge 167:e84263d55307 9026 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 9027 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
AnnaBridge 167:e84263d55307 9028 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9029 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9030 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
AnnaBridge 167:e84263d55307 9031 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 9032 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
AnnaBridge 167:e84263d55307 9033 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9034 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9035 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
AnnaBridge 167:e84263d55307 9036 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 9037 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
AnnaBridge 167:e84263d55307 9038 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9039 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9040 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
AnnaBridge 167:e84263d55307 9041 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 9042 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
AnnaBridge 167:e84263d55307 9043 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9044 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9045 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
AnnaBridge 167:e84263d55307 9046 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 9047 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
AnnaBridge 167:e84263d55307 9048 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9049 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9050 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
AnnaBridge 167:e84263d55307 9051 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 9052 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
AnnaBridge 167:e84263d55307 9053 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9054 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 9055 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
AnnaBridge 167:e84263d55307 9056 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 9057 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
AnnaBridge 167:e84263d55307 9058 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 9059 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 9060 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
AnnaBridge 167:e84263d55307 9061 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 9062 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
AnnaBridge 167:e84263d55307 9063 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 9064 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 9065 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
AnnaBridge 167:e84263d55307 9066 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 9067 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
AnnaBridge 167:e84263d55307 9068 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 9069 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 9070 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
AnnaBridge 167:e84263d55307 9071 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 9072 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
AnnaBridge 167:e84263d55307 9073 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 9074 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 9075 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
AnnaBridge 167:e84263d55307 9076 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
AnnaBridge 167:e84263d55307 9077 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
AnnaBridge 167:e84263d55307 9078 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 9079 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 9080 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
AnnaBridge 167:e84263d55307 9081 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 9082 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
AnnaBridge 167:e84263d55307 9083 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 9084 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 9085 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
AnnaBridge 167:e84263d55307 9086 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
AnnaBridge 167:e84263d55307 9087 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
AnnaBridge 167:e84263d55307 9088 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 9089 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 9090
AnnaBridge 167:e84263d55307 9091 /* Legacy defines */
AnnaBridge 167:e84263d55307 9092 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
AnnaBridge 167:e84263d55307 9093 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
AnnaBridge 167:e84263d55307 9094 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
AnnaBridge 167:e84263d55307 9095 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
AnnaBridge 167:e84263d55307 9096 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
AnnaBridge 167:e84263d55307 9097 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
AnnaBridge 167:e84263d55307 9098 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
AnnaBridge 167:e84263d55307 9099 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
AnnaBridge 167:e84263d55307 9100 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
AnnaBridge 167:e84263d55307 9101 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
AnnaBridge 167:e84263d55307 9102 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
AnnaBridge 167:e84263d55307 9103 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
AnnaBridge 167:e84263d55307 9104 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
AnnaBridge 167:e84263d55307 9105 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
AnnaBridge 167:e84263d55307 9106 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
AnnaBridge 167:e84263d55307 9107 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
AnnaBridge 167:e84263d55307 9108 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
AnnaBridge 167:e84263d55307 9109 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
AnnaBridge 167:e84263d55307 9110 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
AnnaBridge 167:e84263d55307 9111 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
AnnaBridge 167:e84263d55307 9112 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
AnnaBridge 167:e84263d55307 9113 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
AnnaBridge 167:e84263d55307 9114 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
AnnaBridge 167:e84263d55307 9115 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
AnnaBridge 167:e84263d55307 9116 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
AnnaBridge 167:e84263d55307 9117 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
AnnaBridge 167:e84263d55307 9118 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
AnnaBridge 167:e84263d55307 9119 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
AnnaBridge 167:e84263d55307 9120 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
AnnaBridge 167:e84263d55307 9121 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
AnnaBridge 167:e84263d55307 9122 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
AnnaBridge 167:e84263d55307 9123 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
AnnaBridge 167:e84263d55307 9124 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
AnnaBridge 167:e84263d55307 9125 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
AnnaBridge 167:e84263d55307 9126 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
AnnaBridge 167:e84263d55307 9127 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
AnnaBridge 167:e84263d55307 9128 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
AnnaBridge 167:e84263d55307 9129 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
AnnaBridge 167:e84263d55307 9130 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
AnnaBridge 167:e84263d55307 9131 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
AnnaBridge 167:e84263d55307 9132 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
AnnaBridge 167:e84263d55307 9133 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
AnnaBridge 167:e84263d55307 9134 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
AnnaBridge 167:e84263d55307 9135 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
AnnaBridge 167:e84263d55307 9136 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
AnnaBridge 167:e84263d55307 9137 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
AnnaBridge 167:e84263d55307 9138 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
AnnaBridge 167:e84263d55307 9139 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
<> 144:ef7eb2e8f9f7 9140
<> 144:ef7eb2e8f9f7 9141 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 167:e84263d55307 9142 #define GPIO_PUPDR_PUPD0_Pos (0U)
AnnaBridge 167:e84263d55307 9143 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 9144 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
AnnaBridge 167:e84263d55307 9145 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9146 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9147 #define GPIO_PUPDR_PUPD1_Pos (2U)
AnnaBridge 167:e84263d55307 9148 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 9149 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
AnnaBridge 167:e84263d55307 9150 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9151 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9152 #define GPIO_PUPDR_PUPD2_Pos (4U)
AnnaBridge 167:e84263d55307 9153 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 9154 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
AnnaBridge 167:e84263d55307 9155 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9156 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9157 #define GPIO_PUPDR_PUPD3_Pos (6U)
AnnaBridge 167:e84263d55307 9158 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 9159 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
AnnaBridge 167:e84263d55307 9160 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9161 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9162 #define GPIO_PUPDR_PUPD4_Pos (8U)
AnnaBridge 167:e84263d55307 9163 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 9164 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
AnnaBridge 167:e84263d55307 9165 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9166 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9167 #define GPIO_PUPDR_PUPD5_Pos (10U)
AnnaBridge 167:e84263d55307 9168 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 9169 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
AnnaBridge 167:e84263d55307 9170 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9171 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9172 #define GPIO_PUPDR_PUPD6_Pos (12U)
AnnaBridge 167:e84263d55307 9173 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 9174 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
AnnaBridge 167:e84263d55307 9175 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9176 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9177 #define GPIO_PUPDR_PUPD7_Pos (14U)
AnnaBridge 167:e84263d55307 9178 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 9179 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
AnnaBridge 167:e84263d55307 9180 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9181 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9182 #define GPIO_PUPDR_PUPD8_Pos (16U)
AnnaBridge 167:e84263d55307 9183 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 9184 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
AnnaBridge 167:e84263d55307 9185 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9186 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 9187 #define GPIO_PUPDR_PUPD9_Pos (18U)
AnnaBridge 167:e84263d55307 9188 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 9189 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
AnnaBridge 167:e84263d55307 9190 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 9191 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 9192 #define GPIO_PUPDR_PUPD10_Pos (20U)
AnnaBridge 167:e84263d55307 9193 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 9194 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
AnnaBridge 167:e84263d55307 9195 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 9196 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 9197 #define GPIO_PUPDR_PUPD11_Pos (22U)
AnnaBridge 167:e84263d55307 9198 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 9199 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
AnnaBridge 167:e84263d55307 9200 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 9201 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 9202 #define GPIO_PUPDR_PUPD12_Pos (24U)
AnnaBridge 167:e84263d55307 9203 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 9204 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
AnnaBridge 167:e84263d55307 9205 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 9206 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 9207 #define GPIO_PUPDR_PUPD13_Pos (26U)
AnnaBridge 167:e84263d55307 9208 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
AnnaBridge 167:e84263d55307 9209 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
AnnaBridge 167:e84263d55307 9210 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 9211 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 9212 #define GPIO_PUPDR_PUPD14_Pos (28U)
AnnaBridge 167:e84263d55307 9213 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 9214 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
AnnaBridge 167:e84263d55307 9215 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 9216 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 9217 #define GPIO_PUPDR_PUPD15_Pos (30U)
AnnaBridge 167:e84263d55307 9218 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
AnnaBridge 167:e84263d55307 9219 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
AnnaBridge 167:e84263d55307 9220 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 9221 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 9222
AnnaBridge 167:e84263d55307 9223 /* Legacy defines */
AnnaBridge 167:e84263d55307 9224 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
AnnaBridge 167:e84263d55307 9225 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
AnnaBridge 167:e84263d55307 9226 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
AnnaBridge 167:e84263d55307 9227 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
AnnaBridge 167:e84263d55307 9228 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
AnnaBridge 167:e84263d55307 9229 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
AnnaBridge 167:e84263d55307 9230 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
AnnaBridge 167:e84263d55307 9231 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
AnnaBridge 167:e84263d55307 9232 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
AnnaBridge 167:e84263d55307 9233 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
AnnaBridge 167:e84263d55307 9234 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
AnnaBridge 167:e84263d55307 9235 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
AnnaBridge 167:e84263d55307 9236 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
AnnaBridge 167:e84263d55307 9237 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
AnnaBridge 167:e84263d55307 9238 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
AnnaBridge 167:e84263d55307 9239 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
AnnaBridge 167:e84263d55307 9240 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
AnnaBridge 167:e84263d55307 9241 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
AnnaBridge 167:e84263d55307 9242 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
AnnaBridge 167:e84263d55307 9243 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
AnnaBridge 167:e84263d55307 9244 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
AnnaBridge 167:e84263d55307 9245 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
AnnaBridge 167:e84263d55307 9246 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
AnnaBridge 167:e84263d55307 9247 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
AnnaBridge 167:e84263d55307 9248 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
AnnaBridge 167:e84263d55307 9249 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
AnnaBridge 167:e84263d55307 9250 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
AnnaBridge 167:e84263d55307 9251 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
AnnaBridge 167:e84263d55307 9252 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
AnnaBridge 167:e84263d55307 9253 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
AnnaBridge 167:e84263d55307 9254 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
AnnaBridge 167:e84263d55307 9255 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
AnnaBridge 167:e84263d55307 9256 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
AnnaBridge 167:e84263d55307 9257 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
AnnaBridge 167:e84263d55307 9258 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
AnnaBridge 167:e84263d55307 9259 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
AnnaBridge 167:e84263d55307 9260 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
AnnaBridge 167:e84263d55307 9261 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
AnnaBridge 167:e84263d55307 9262 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
AnnaBridge 167:e84263d55307 9263 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
AnnaBridge 167:e84263d55307 9264 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
AnnaBridge 167:e84263d55307 9265 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
AnnaBridge 167:e84263d55307 9266 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
AnnaBridge 167:e84263d55307 9267 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
AnnaBridge 167:e84263d55307 9268 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
AnnaBridge 167:e84263d55307 9269 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
AnnaBridge 167:e84263d55307 9270 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
AnnaBridge 167:e84263d55307 9271 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
<> 144:ef7eb2e8f9f7 9272
<> 144:ef7eb2e8f9f7 9273 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 167:e84263d55307 9274 #define GPIO_IDR_ID0_Pos (0U)
AnnaBridge 167:e84263d55307 9275 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9276 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
AnnaBridge 167:e84263d55307 9277 #define GPIO_IDR_ID1_Pos (1U)
AnnaBridge 167:e84263d55307 9278 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9279 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
AnnaBridge 167:e84263d55307 9280 #define GPIO_IDR_ID2_Pos (2U)
AnnaBridge 167:e84263d55307 9281 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9282 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
AnnaBridge 167:e84263d55307 9283 #define GPIO_IDR_ID3_Pos (3U)
AnnaBridge 167:e84263d55307 9284 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9285 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
AnnaBridge 167:e84263d55307 9286 #define GPIO_IDR_ID4_Pos (4U)
AnnaBridge 167:e84263d55307 9287 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9288 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
AnnaBridge 167:e84263d55307 9289 #define GPIO_IDR_ID5_Pos (5U)
AnnaBridge 167:e84263d55307 9290 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9291 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
AnnaBridge 167:e84263d55307 9292 #define GPIO_IDR_ID6_Pos (6U)
AnnaBridge 167:e84263d55307 9293 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9294 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
AnnaBridge 167:e84263d55307 9295 #define GPIO_IDR_ID7_Pos (7U)
AnnaBridge 167:e84263d55307 9296 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9297 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
AnnaBridge 167:e84263d55307 9298 #define GPIO_IDR_ID8_Pos (8U)
AnnaBridge 167:e84263d55307 9299 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9300 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
AnnaBridge 167:e84263d55307 9301 #define GPIO_IDR_ID9_Pos (9U)
AnnaBridge 167:e84263d55307 9302 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9303 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
AnnaBridge 167:e84263d55307 9304 #define GPIO_IDR_ID10_Pos (10U)
AnnaBridge 167:e84263d55307 9305 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9306 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
AnnaBridge 167:e84263d55307 9307 #define GPIO_IDR_ID11_Pos (11U)
AnnaBridge 167:e84263d55307 9308 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9309 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
AnnaBridge 167:e84263d55307 9310 #define GPIO_IDR_ID12_Pos (12U)
AnnaBridge 167:e84263d55307 9311 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9312 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
AnnaBridge 167:e84263d55307 9313 #define GPIO_IDR_ID13_Pos (13U)
AnnaBridge 167:e84263d55307 9314 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9315 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
AnnaBridge 167:e84263d55307 9316 #define GPIO_IDR_ID14_Pos (14U)
AnnaBridge 167:e84263d55307 9317 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9318 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
AnnaBridge 167:e84263d55307 9319 #define GPIO_IDR_ID15_Pos (15U)
AnnaBridge 167:e84263d55307 9320 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9321 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
AnnaBridge 167:e84263d55307 9322
AnnaBridge 167:e84263d55307 9323 /* Legacy defines */
AnnaBridge 167:e84263d55307 9324 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
AnnaBridge 167:e84263d55307 9325 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
AnnaBridge 167:e84263d55307 9326 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
AnnaBridge 167:e84263d55307 9327 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
AnnaBridge 167:e84263d55307 9328 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
AnnaBridge 167:e84263d55307 9329 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
AnnaBridge 167:e84263d55307 9330 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
AnnaBridge 167:e84263d55307 9331 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
AnnaBridge 167:e84263d55307 9332 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
AnnaBridge 167:e84263d55307 9333 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
AnnaBridge 167:e84263d55307 9334 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
AnnaBridge 167:e84263d55307 9335 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
AnnaBridge 167:e84263d55307 9336 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
AnnaBridge 167:e84263d55307 9337 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
AnnaBridge 167:e84263d55307 9338 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
AnnaBridge 167:e84263d55307 9339 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
<> 144:ef7eb2e8f9f7 9340
<> 144:ef7eb2e8f9f7 9341 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 167:e84263d55307 9342 #define GPIO_ODR_OD0_Pos (0U)
AnnaBridge 167:e84263d55307 9343 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9344 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
AnnaBridge 167:e84263d55307 9345 #define GPIO_ODR_OD1_Pos (1U)
AnnaBridge 167:e84263d55307 9346 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9347 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
AnnaBridge 167:e84263d55307 9348 #define GPIO_ODR_OD2_Pos (2U)
AnnaBridge 167:e84263d55307 9349 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9350 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
AnnaBridge 167:e84263d55307 9351 #define GPIO_ODR_OD3_Pos (3U)
AnnaBridge 167:e84263d55307 9352 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9353 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
AnnaBridge 167:e84263d55307 9354 #define GPIO_ODR_OD4_Pos (4U)
AnnaBridge 167:e84263d55307 9355 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9356 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
AnnaBridge 167:e84263d55307 9357 #define GPIO_ODR_OD5_Pos (5U)
AnnaBridge 167:e84263d55307 9358 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9359 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
AnnaBridge 167:e84263d55307 9360 #define GPIO_ODR_OD6_Pos (6U)
AnnaBridge 167:e84263d55307 9361 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9362 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
AnnaBridge 167:e84263d55307 9363 #define GPIO_ODR_OD7_Pos (7U)
AnnaBridge 167:e84263d55307 9364 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9365 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
AnnaBridge 167:e84263d55307 9366 #define GPIO_ODR_OD8_Pos (8U)
AnnaBridge 167:e84263d55307 9367 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9368 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
AnnaBridge 167:e84263d55307 9369 #define GPIO_ODR_OD9_Pos (9U)
AnnaBridge 167:e84263d55307 9370 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9371 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
AnnaBridge 167:e84263d55307 9372 #define GPIO_ODR_OD10_Pos (10U)
AnnaBridge 167:e84263d55307 9373 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9374 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
AnnaBridge 167:e84263d55307 9375 #define GPIO_ODR_OD11_Pos (11U)
AnnaBridge 167:e84263d55307 9376 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9377 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
AnnaBridge 167:e84263d55307 9378 #define GPIO_ODR_OD12_Pos (12U)
AnnaBridge 167:e84263d55307 9379 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9380 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
AnnaBridge 167:e84263d55307 9381 #define GPIO_ODR_OD13_Pos (13U)
AnnaBridge 167:e84263d55307 9382 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9383 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
AnnaBridge 167:e84263d55307 9384 #define GPIO_ODR_OD14_Pos (14U)
AnnaBridge 167:e84263d55307 9385 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9386 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
AnnaBridge 167:e84263d55307 9387 #define GPIO_ODR_OD15_Pos (15U)
AnnaBridge 167:e84263d55307 9388 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9389 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
AnnaBridge 167:e84263d55307 9390 /* Legacy defines */
AnnaBridge 167:e84263d55307 9391 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
AnnaBridge 167:e84263d55307 9392 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
AnnaBridge 167:e84263d55307 9393 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
AnnaBridge 167:e84263d55307 9394 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
AnnaBridge 167:e84263d55307 9395 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
AnnaBridge 167:e84263d55307 9396 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
AnnaBridge 167:e84263d55307 9397 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
AnnaBridge 167:e84263d55307 9398 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
AnnaBridge 167:e84263d55307 9399 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
AnnaBridge 167:e84263d55307 9400 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
AnnaBridge 167:e84263d55307 9401 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
AnnaBridge 167:e84263d55307 9402 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
AnnaBridge 167:e84263d55307 9403 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
AnnaBridge 167:e84263d55307 9404 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
AnnaBridge 167:e84263d55307 9405 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
AnnaBridge 167:e84263d55307 9406 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
<> 144:ef7eb2e8f9f7 9407
<> 144:ef7eb2e8f9f7 9408 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 167:e84263d55307 9409 #define GPIO_BSRR_BS0_Pos (0U)
AnnaBridge 167:e84263d55307 9410 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9411 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
AnnaBridge 167:e84263d55307 9412 #define GPIO_BSRR_BS1_Pos (1U)
AnnaBridge 167:e84263d55307 9413 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9414 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
AnnaBridge 167:e84263d55307 9415 #define GPIO_BSRR_BS2_Pos (2U)
AnnaBridge 167:e84263d55307 9416 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9417 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
AnnaBridge 167:e84263d55307 9418 #define GPIO_BSRR_BS3_Pos (3U)
AnnaBridge 167:e84263d55307 9419 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9420 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
AnnaBridge 167:e84263d55307 9421 #define GPIO_BSRR_BS4_Pos (4U)
AnnaBridge 167:e84263d55307 9422 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9423 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
AnnaBridge 167:e84263d55307 9424 #define GPIO_BSRR_BS5_Pos (5U)
AnnaBridge 167:e84263d55307 9425 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9426 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
AnnaBridge 167:e84263d55307 9427 #define GPIO_BSRR_BS6_Pos (6U)
AnnaBridge 167:e84263d55307 9428 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9429 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
AnnaBridge 167:e84263d55307 9430 #define GPIO_BSRR_BS7_Pos (7U)
AnnaBridge 167:e84263d55307 9431 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9432 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
AnnaBridge 167:e84263d55307 9433 #define GPIO_BSRR_BS8_Pos (8U)
AnnaBridge 167:e84263d55307 9434 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9435 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
AnnaBridge 167:e84263d55307 9436 #define GPIO_BSRR_BS9_Pos (9U)
AnnaBridge 167:e84263d55307 9437 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9438 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
AnnaBridge 167:e84263d55307 9439 #define GPIO_BSRR_BS10_Pos (10U)
AnnaBridge 167:e84263d55307 9440 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9441 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
AnnaBridge 167:e84263d55307 9442 #define GPIO_BSRR_BS11_Pos (11U)
AnnaBridge 167:e84263d55307 9443 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9444 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
AnnaBridge 167:e84263d55307 9445 #define GPIO_BSRR_BS12_Pos (12U)
AnnaBridge 167:e84263d55307 9446 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9447 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
AnnaBridge 167:e84263d55307 9448 #define GPIO_BSRR_BS13_Pos (13U)
AnnaBridge 167:e84263d55307 9449 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9450 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
AnnaBridge 167:e84263d55307 9451 #define GPIO_BSRR_BS14_Pos (14U)
AnnaBridge 167:e84263d55307 9452 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9453 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
AnnaBridge 167:e84263d55307 9454 #define GPIO_BSRR_BS15_Pos (15U)
AnnaBridge 167:e84263d55307 9455 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9456 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
AnnaBridge 167:e84263d55307 9457 #define GPIO_BSRR_BR0_Pos (16U)
AnnaBridge 167:e84263d55307 9458 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9459 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
AnnaBridge 167:e84263d55307 9460 #define GPIO_BSRR_BR1_Pos (17U)
AnnaBridge 167:e84263d55307 9461 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 9462 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
AnnaBridge 167:e84263d55307 9463 #define GPIO_BSRR_BR2_Pos (18U)
AnnaBridge 167:e84263d55307 9464 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 9465 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
AnnaBridge 167:e84263d55307 9466 #define GPIO_BSRR_BR3_Pos (19U)
AnnaBridge 167:e84263d55307 9467 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 9468 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
AnnaBridge 167:e84263d55307 9469 #define GPIO_BSRR_BR4_Pos (20U)
AnnaBridge 167:e84263d55307 9470 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 9471 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
AnnaBridge 167:e84263d55307 9472 #define GPIO_BSRR_BR5_Pos (21U)
AnnaBridge 167:e84263d55307 9473 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 9474 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
AnnaBridge 167:e84263d55307 9475 #define GPIO_BSRR_BR6_Pos (22U)
AnnaBridge 167:e84263d55307 9476 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 9477 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
AnnaBridge 167:e84263d55307 9478 #define GPIO_BSRR_BR7_Pos (23U)
AnnaBridge 167:e84263d55307 9479 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 9480 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
AnnaBridge 167:e84263d55307 9481 #define GPIO_BSRR_BR8_Pos (24U)
AnnaBridge 167:e84263d55307 9482 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 9483 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
AnnaBridge 167:e84263d55307 9484 #define GPIO_BSRR_BR9_Pos (25U)
AnnaBridge 167:e84263d55307 9485 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 9486 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
AnnaBridge 167:e84263d55307 9487 #define GPIO_BSRR_BR10_Pos (26U)
AnnaBridge 167:e84263d55307 9488 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 9489 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
AnnaBridge 167:e84263d55307 9490 #define GPIO_BSRR_BR11_Pos (27U)
AnnaBridge 167:e84263d55307 9491 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 9492 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
AnnaBridge 167:e84263d55307 9493 #define GPIO_BSRR_BR12_Pos (28U)
AnnaBridge 167:e84263d55307 9494 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 9495 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
AnnaBridge 167:e84263d55307 9496 #define GPIO_BSRR_BR13_Pos (29U)
AnnaBridge 167:e84263d55307 9497 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 9498 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
AnnaBridge 167:e84263d55307 9499 #define GPIO_BSRR_BR14_Pos (30U)
AnnaBridge 167:e84263d55307 9500 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 9501 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
AnnaBridge 167:e84263d55307 9502 #define GPIO_BSRR_BR15_Pos (31U)
AnnaBridge 167:e84263d55307 9503 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 9504 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
AnnaBridge 167:e84263d55307 9505
AnnaBridge 167:e84263d55307 9506 /* Legacy defines */
AnnaBridge 167:e84263d55307 9507 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
AnnaBridge 167:e84263d55307 9508 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
AnnaBridge 167:e84263d55307 9509 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
AnnaBridge 167:e84263d55307 9510 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
AnnaBridge 167:e84263d55307 9511 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
AnnaBridge 167:e84263d55307 9512 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
AnnaBridge 167:e84263d55307 9513 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
AnnaBridge 167:e84263d55307 9514 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
AnnaBridge 167:e84263d55307 9515 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
AnnaBridge 167:e84263d55307 9516 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
AnnaBridge 167:e84263d55307 9517 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
AnnaBridge 167:e84263d55307 9518 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
AnnaBridge 167:e84263d55307 9519 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
AnnaBridge 167:e84263d55307 9520 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
AnnaBridge 167:e84263d55307 9521 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
AnnaBridge 167:e84263d55307 9522 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
AnnaBridge 167:e84263d55307 9523 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
AnnaBridge 167:e84263d55307 9524 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
AnnaBridge 167:e84263d55307 9525 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
AnnaBridge 167:e84263d55307 9526 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
AnnaBridge 167:e84263d55307 9527 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
AnnaBridge 167:e84263d55307 9528 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
AnnaBridge 167:e84263d55307 9529 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
AnnaBridge 167:e84263d55307 9530 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
AnnaBridge 167:e84263d55307 9531 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
AnnaBridge 167:e84263d55307 9532 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
AnnaBridge 167:e84263d55307 9533 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
AnnaBridge 167:e84263d55307 9534 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
AnnaBridge 167:e84263d55307 9535 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
AnnaBridge 167:e84263d55307 9536 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
AnnaBridge 167:e84263d55307 9537 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
AnnaBridge 167:e84263d55307 9538 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
<> 144:ef7eb2e8f9f7 9539 /****************** Bit definition for GPIO_LCKR register *********************/
AnnaBridge 167:e84263d55307 9540 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 167:e84263d55307 9541 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9542 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 167:e84263d55307 9543 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 167:e84263d55307 9544 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9545 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 167:e84263d55307 9546 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 167:e84263d55307 9547 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9548 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 167:e84263d55307 9549 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 167:e84263d55307 9550 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9551 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 167:e84263d55307 9552 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 167:e84263d55307 9553 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9554 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 167:e84263d55307 9555 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 167:e84263d55307 9556 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9557 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 167:e84263d55307 9558 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 167:e84263d55307 9559 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9560 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 167:e84263d55307 9561 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 167:e84263d55307 9562 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9563 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 167:e84263d55307 9564 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 167:e84263d55307 9565 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9566 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 167:e84263d55307 9567 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 167:e84263d55307 9568 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9569 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 167:e84263d55307 9570 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 167:e84263d55307 9571 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9572 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 167:e84263d55307 9573 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 167:e84263d55307 9574 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9575 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 167:e84263d55307 9576 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 167:e84263d55307 9577 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9578 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 167:e84263d55307 9579 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 167:e84263d55307 9580 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9581 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 167:e84263d55307 9582 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 167:e84263d55307 9583 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9584 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 167:e84263d55307 9585 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 167:e84263d55307 9586 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9587 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 167:e84263d55307 9588 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 167:e84263d55307 9589 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9590 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 167:e84263d55307 9591 /****************** Bit definition for GPIO_AFRL register *********************/
AnnaBridge 167:e84263d55307 9592 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 167:e84263d55307 9593 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 9594 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 167:e84263d55307 9595 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9596 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9597 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9598 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9599 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 167:e84263d55307 9600 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 9601 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 167:e84263d55307 9602 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9603 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9604 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9605 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9606 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 167:e84263d55307 9607 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 9608 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 167:e84263d55307 9609 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9610 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9611 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9612 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9613 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 167:e84263d55307 9614 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 9615 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 167:e84263d55307 9616 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9617 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9618 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9619 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9620 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 167:e84263d55307 9621 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 9622 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 167:e84263d55307 9623 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9624 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 9625 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 9626 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 9627 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 167:e84263d55307 9628 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 9629 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 167:e84263d55307 9630 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 9631 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 9632 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 9633 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 9634 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 167:e84263d55307 9635 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 9636 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 167:e84263d55307 9637 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 9638 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 9639 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 9640 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 9641 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 167:e84263d55307 9642 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 167:e84263d55307 9643 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 167:e84263d55307 9644 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 9645 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 9646 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 9647 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 9648
AnnaBridge 167:e84263d55307 9649 /* Legacy defines */
AnnaBridge 167:e84263d55307 9650 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 167:e84263d55307 9651 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
AnnaBridge 167:e84263d55307 9652 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
AnnaBridge 167:e84263d55307 9653 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
AnnaBridge 167:e84263d55307 9654 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
AnnaBridge 167:e84263d55307 9655 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 167:e84263d55307 9656 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
AnnaBridge 167:e84263d55307 9657 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
AnnaBridge 167:e84263d55307 9658 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
AnnaBridge 167:e84263d55307 9659 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
AnnaBridge 167:e84263d55307 9660 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 167:e84263d55307 9661 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
AnnaBridge 167:e84263d55307 9662 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
AnnaBridge 167:e84263d55307 9663 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
AnnaBridge 167:e84263d55307 9664 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
AnnaBridge 167:e84263d55307 9665 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 167:e84263d55307 9666 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
AnnaBridge 167:e84263d55307 9667 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
AnnaBridge 167:e84263d55307 9668 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
AnnaBridge 167:e84263d55307 9669 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
AnnaBridge 167:e84263d55307 9670 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 167:e84263d55307 9671 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
AnnaBridge 167:e84263d55307 9672 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
AnnaBridge 167:e84263d55307 9673 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
AnnaBridge 167:e84263d55307 9674 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
AnnaBridge 167:e84263d55307 9675 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 167:e84263d55307 9676 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
AnnaBridge 167:e84263d55307 9677 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
AnnaBridge 167:e84263d55307 9678 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
AnnaBridge 167:e84263d55307 9679 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
AnnaBridge 167:e84263d55307 9680 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 167:e84263d55307 9681 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
AnnaBridge 167:e84263d55307 9682 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
AnnaBridge 167:e84263d55307 9683 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
AnnaBridge 167:e84263d55307 9684 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
AnnaBridge 167:e84263d55307 9685 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 167:e84263d55307 9686 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
AnnaBridge 167:e84263d55307 9687 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
AnnaBridge 167:e84263d55307 9688 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
AnnaBridge 167:e84263d55307 9689 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
AnnaBridge 167:e84263d55307 9690
AnnaBridge 167:e84263d55307 9691 /****************** Bit definition for GPIO_AFRH register *********************/
AnnaBridge 167:e84263d55307 9692 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 167:e84263d55307 9693 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 9694 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 167:e84263d55307 9695 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9696 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9697 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9698 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9699 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 167:e84263d55307 9700 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 9701 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 167:e84263d55307 9702 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9703 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9704 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9705 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9706 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 167:e84263d55307 9707 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 9708 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 167:e84263d55307 9709 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9710 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9711 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9712 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9713 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 167:e84263d55307 9714 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 9715 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 167:e84263d55307 9716 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9717 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9718 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9719 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9720 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 167:e84263d55307 9721 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 9722 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 167:e84263d55307 9723 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 9724 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 9725 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 9726 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 9727 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 167:e84263d55307 9728 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 9729 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 167:e84263d55307 9730 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 9731 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 9732 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 9733 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 9734 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 167:e84263d55307 9735 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 9736 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 167:e84263d55307 9737 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 9738 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 9739 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 9740 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 9741 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 167:e84263d55307 9742 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 167:e84263d55307 9743 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 167:e84263d55307 9744 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 9745 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 9746 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 9747 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 9748
AnnaBridge 167:e84263d55307 9749 /* Legacy defines */
AnnaBridge 167:e84263d55307 9750 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 167:e84263d55307 9751 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
AnnaBridge 167:e84263d55307 9752 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
AnnaBridge 167:e84263d55307 9753 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
AnnaBridge 167:e84263d55307 9754 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
AnnaBridge 167:e84263d55307 9755 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 167:e84263d55307 9756 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
AnnaBridge 167:e84263d55307 9757 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
AnnaBridge 167:e84263d55307 9758 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
AnnaBridge 167:e84263d55307 9759 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
AnnaBridge 167:e84263d55307 9760 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 167:e84263d55307 9761 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
AnnaBridge 167:e84263d55307 9762 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
AnnaBridge 167:e84263d55307 9763 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
AnnaBridge 167:e84263d55307 9764 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
AnnaBridge 167:e84263d55307 9765 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 167:e84263d55307 9766 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
AnnaBridge 167:e84263d55307 9767 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
AnnaBridge 167:e84263d55307 9768 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
AnnaBridge 167:e84263d55307 9769 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
AnnaBridge 167:e84263d55307 9770 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 167:e84263d55307 9771 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
AnnaBridge 167:e84263d55307 9772 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
AnnaBridge 167:e84263d55307 9773 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
AnnaBridge 167:e84263d55307 9774 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
AnnaBridge 167:e84263d55307 9775 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 167:e84263d55307 9776 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
AnnaBridge 167:e84263d55307 9777 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
AnnaBridge 167:e84263d55307 9778 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
AnnaBridge 167:e84263d55307 9779 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
AnnaBridge 167:e84263d55307 9780 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 167:e84263d55307 9781 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
AnnaBridge 167:e84263d55307 9782 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
AnnaBridge 167:e84263d55307 9783 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
AnnaBridge 167:e84263d55307 9784 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
AnnaBridge 167:e84263d55307 9785 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 167:e84263d55307 9786 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
AnnaBridge 167:e84263d55307 9787 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
AnnaBridge 167:e84263d55307 9788 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
AnnaBridge 167:e84263d55307 9789 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
AnnaBridge 167:e84263d55307 9790
AnnaBridge 167:e84263d55307 9791 /****************** Bits definition for GPIO_BRR register ******************/
AnnaBridge 167:e84263d55307 9792 #define GPIO_BRR_BR0_Pos (0U)
AnnaBridge 167:e84263d55307 9793 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9794 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
AnnaBridge 167:e84263d55307 9795 #define GPIO_BRR_BR1_Pos (1U)
AnnaBridge 167:e84263d55307 9796 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9797 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
AnnaBridge 167:e84263d55307 9798 #define GPIO_BRR_BR2_Pos (2U)
AnnaBridge 167:e84263d55307 9799 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9800 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
AnnaBridge 167:e84263d55307 9801 #define GPIO_BRR_BR3_Pos (3U)
AnnaBridge 167:e84263d55307 9802 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9803 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
AnnaBridge 167:e84263d55307 9804 #define GPIO_BRR_BR4_Pos (4U)
AnnaBridge 167:e84263d55307 9805 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9806 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
AnnaBridge 167:e84263d55307 9807 #define GPIO_BRR_BR5_Pos (5U)
AnnaBridge 167:e84263d55307 9808 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9809 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
AnnaBridge 167:e84263d55307 9810 #define GPIO_BRR_BR6_Pos (6U)
AnnaBridge 167:e84263d55307 9811 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9812 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
AnnaBridge 167:e84263d55307 9813 #define GPIO_BRR_BR7_Pos (7U)
AnnaBridge 167:e84263d55307 9814 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9815 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
AnnaBridge 167:e84263d55307 9816 #define GPIO_BRR_BR8_Pos (8U)
AnnaBridge 167:e84263d55307 9817 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9818 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
AnnaBridge 167:e84263d55307 9819 #define GPIO_BRR_BR9_Pos (9U)
AnnaBridge 167:e84263d55307 9820 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9821 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
AnnaBridge 167:e84263d55307 9822 #define GPIO_BRR_BR10_Pos (10U)
AnnaBridge 167:e84263d55307 9823 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9824 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
AnnaBridge 167:e84263d55307 9825 #define GPIO_BRR_BR11_Pos (11U)
AnnaBridge 167:e84263d55307 9826 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9827 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
AnnaBridge 167:e84263d55307 9828 #define GPIO_BRR_BR12_Pos (12U)
AnnaBridge 167:e84263d55307 9829 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9830 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
AnnaBridge 167:e84263d55307 9831 #define GPIO_BRR_BR13_Pos (13U)
AnnaBridge 167:e84263d55307 9832 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9833 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
AnnaBridge 167:e84263d55307 9834 #define GPIO_BRR_BR14_Pos (14U)
AnnaBridge 167:e84263d55307 9835 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 9836 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
AnnaBridge 167:e84263d55307 9837 #define GPIO_BRR_BR15_Pos (15U)
AnnaBridge 167:e84263d55307 9838 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9839 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
AnnaBridge 167:e84263d55307 9840
<> 144:ef7eb2e8f9f7 9841
<> 144:ef7eb2e8f9f7 9842 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9843 /* */
<> 144:ef7eb2e8f9f7 9844 /* Inter-integrated Circuit Interface */
<> 144:ef7eb2e8f9f7 9845 /* */
<> 144:ef7eb2e8f9f7 9846 /******************************************************************************/
<> 144:ef7eb2e8f9f7 9847 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 167:e84263d55307 9848 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 167:e84263d55307 9849 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9850 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
AnnaBridge 167:e84263d55307 9851 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 167:e84263d55307 9852 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9853 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
AnnaBridge 167:e84263d55307 9854 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 167:e84263d55307 9855 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9856 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
AnnaBridge 167:e84263d55307 9857 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 167:e84263d55307 9858 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9859 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
AnnaBridge 167:e84263d55307 9860 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 167:e84263d55307 9861 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9862 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
AnnaBridge 167:e84263d55307 9863 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 167:e84263d55307 9864 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9865 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
AnnaBridge 167:e84263d55307 9866 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 167:e84263d55307 9867 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9868 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
AnnaBridge 167:e84263d55307 9869 #define I2C_CR1_START_Pos (8U)
AnnaBridge 167:e84263d55307 9870 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9871 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
AnnaBridge 167:e84263d55307 9872 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 167:e84263d55307 9873 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9874 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
AnnaBridge 167:e84263d55307 9875 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 167:e84263d55307 9876 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9877 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
AnnaBridge 167:e84263d55307 9878 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 167:e84263d55307 9879 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9880 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
AnnaBridge 167:e84263d55307 9881 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 167:e84263d55307 9882 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9883 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
AnnaBridge 167:e84263d55307 9884 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 167:e84263d55307 9885 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 9886 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
AnnaBridge 167:e84263d55307 9887 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 167:e84263d55307 9888 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9889 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
<> 144:ef7eb2e8f9f7 9890
<> 144:ef7eb2e8f9f7 9891 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 167:e84263d55307 9892 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 167:e84263d55307 9893 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 167:e84263d55307 9894 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 167:e84263d55307 9895 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9896 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9897 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9898 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9899 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9900 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9901
AnnaBridge 167:e84263d55307 9902 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 167:e84263d55307 9903 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9904 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
AnnaBridge 167:e84263d55307 9905 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 167:e84263d55307 9906 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9907 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
AnnaBridge 167:e84263d55307 9908 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 167:e84263d55307 9909 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 9910 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
AnnaBridge 167:e84263d55307 9911 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 167:e84263d55307 9912 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 9913 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
AnnaBridge 167:e84263d55307 9914 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 167:e84263d55307 9915 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 9916 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
<> 144:ef7eb2e8f9f7 9917
<> 144:ef7eb2e8f9f7 9918 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 167:e84263d55307 9919 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
AnnaBridge 167:e84263d55307 9920 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
AnnaBridge 167:e84263d55307 9921
AnnaBridge 167:e84263d55307 9922 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 167:e84263d55307 9923 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9924 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
AnnaBridge 167:e84263d55307 9925 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 167:e84263d55307 9926 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9927 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
AnnaBridge 167:e84263d55307 9928 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 167:e84263d55307 9929 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9930 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
AnnaBridge 167:e84263d55307 9931 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 167:e84263d55307 9932 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9933 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
AnnaBridge 167:e84263d55307 9934 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 167:e84263d55307 9935 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9936 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
AnnaBridge 167:e84263d55307 9937 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 167:e84263d55307 9938 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 9939 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
AnnaBridge 167:e84263d55307 9940 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 167:e84263d55307 9941 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9942 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
AnnaBridge 167:e84263d55307 9943 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 167:e84263d55307 9944 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9945 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
AnnaBridge 167:e84263d55307 9946 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 167:e84263d55307 9947 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9948 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
AnnaBridge 167:e84263d55307 9949 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 167:e84263d55307 9950 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9951 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
AnnaBridge 167:e84263d55307 9952
AnnaBridge 167:e84263d55307 9953 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 167:e84263d55307 9954 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 9955 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
<> 144:ef7eb2e8f9f7 9956
<> 144:ef7eb2e8f9f7 9957 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 167:e84263d55307 9958 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 167:e84263d55307 9959 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9960 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
AnnaBridge 167:e84263d55307 9961 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 167:e84263d55307 9962 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 167:e84263d55307 9963 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
<> 144:ef7eb2e8f9f7 9964
<> 144:ef7eb2e8f9f7 9965 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 167:e84263d55307 9966 #define I2C_DR_DR_Pos (0U)
AnnaBridge 167:e84263d55307 9967 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 9968 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
<> 144:ef7eb2e8f9f7 9969
<> 144:ef7eb2e8f9f7 9970 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 167:e84263d55307 9971 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 167:e84263d55307 9972 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 9973 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
AnnaBridge 167:e84263d55307 9974 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 167:e84263d55307 9975 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 9976 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
AnnaBridge 167:e84263d55307 9977 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 167:e84263d55307 9978 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 9979 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
AnnaBridge 167:e84263d55307 9980 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 167:e84263d55307 9981 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 9982 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
AnnaBridge 167:e84263d55307 9983 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 167:e84263d55307 9984 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 9985 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
AnnaBridge 167:e84263d55307 9986 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 167:e84263d55307 9987 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 9988 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
AnnaBridge 167:e84263d55307 9989 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 167:e84263d55307 9990 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 9991 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
AnnaBridge 167:e84263d55307 9992 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 167:e84263d55307 9993 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 9994 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
AnnaBridge 167:e84263d55307 9995 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 167:e84263d55307 9996 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 9997 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
AnnaBridge 167:e84263d55307 9998 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 167:e84263d55307 9999 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10000 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
AnnaBridge 167:e84263d55307 10001 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 167:e84263d55307 10002 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10003 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
AnnaBridge 167:e84263d55307 10004 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 167:e84263d55307 10005 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10006 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
AnnaBridge 167:e84263d55307 10007 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 167:e84263d55307 10008 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10009 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
AnnaBridge 167:e84263d55307 10010 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 167:e84263d55307 10011 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 10012 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
<> 144:ef7eb2e8f9f7 10013
<> 144:ef7eb2e8f9f7 10014 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 167:e84263d55307 10015 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 167:e84263d55307 10016 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10017 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
AnnaBridge 167:e84263d55307 10018 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 167:e84263d55307 10019 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10020 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
AnnaBridge 167:e84263d55307 10021 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 167:e84263d55307 10022 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10023 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
AnnaBridge 167:e84263d55307 10024 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 167:e84263d55307 10025 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10026 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
AnnaBridge 167:e84263d55307 10027 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 167:e84263d55307 10028 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10029 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
AnnaBridge 167:e84263d55307 10030 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 167:e84263d55307 10031 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10032 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
AnnaBridge 167:e84263d55307 10033 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 167:e84263d55307 10034 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10035 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
AnnaBridge 167:e84263d55307 10036 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 167:e84263d55307 10037 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10038 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
<> 144:ef7eb2e8f9f7 10039
<> 144:ef7eb2e8f9f7 10040 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 167:e84263d55307 10041 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 167:e84263d55307 10042 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 10043 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 167:e84263d55307 10044 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 167:e84263d55307 10045 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10046 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
AnnaBridge 167:e84263d55307 10047 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 167:e84263d55307 10048 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 10049 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
<> 144:ef7eb2e8f9f7 10050
<> 144:ef7eb2e8f9f7 10051 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 167:e84263d55307 10052 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 167:e84263d55307 10053 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 167:e84263d55307 10054 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
<> 144:ef7eb2e8f9f7 10055
<> 144:ef7eb2e8f9f7 10056 /****************** Bit definition for I2C_FLTR register *******************/
AnnaBridge 167:e84263d55307 10057 #define I2C_FLTR_DNF_Pos (0U)
AnnaBridge 167:e84263d55307 10058 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 10059 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
AnnaBridge 167:e84263d55307 10060 #define I2C_FLTR_ANOFF_Pos (4U)
AnnaBridge 167:e84263d55307 10061 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10062 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
<> 144:ef7eb2e8f9f7 10063
<> 144:ef7eb2e8f9f7 10064 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10065 /* */
<> 144:ef7eb2e8f9f7 10066 /* Independent WATCHDOG */
<> 144:ef7eb2e8f9f7 10067 /* */
<> 144:ef7eb2e8f9f7 10068 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10069 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 167:e84263d55307 10070 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 167:e84263d55307 10071 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 10072 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
<> 144:ef7eb2e8f9f7 10073
<> 144:ef7eb2e8f9f7 10074 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 167:e84263d55307 10075 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 167:e84263d55307 10076 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 10077 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
AnnaBridge 167:e84263d55307 10078 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 167:e84263d55307 10079 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 167:e84263d55307 10080 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
<> 144:ef7eb2e8f9f7 10081
<> 144:ef7eb2e8f9f7 10082 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 167:e84263d55307 10083 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 167:e84263d55307 10084 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 10085 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
<> 144:ef7eb2e8f9f7 10086
<> 144:ef7eb2e8f9f7 10087 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 167:e84263d55307 10088 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 167:e84263d55307 10089 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10090 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
AnnaBridge 167:e84263d55307 10091 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 167:e84263d55307 10092 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10093 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 10094
<> 144:ef7eb2e8f9f7 10095
<> 144:ef7eb2e8f9f7 10096 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10097 /* */
<> 144:ef7eb2e8f9f7 10098 /* LCD-TFT Display Controller (LTDC) */
<> 144:ef7eb2e8f9f7 10099 /* */
<> 144:ef7eb2e8f9f7 10100 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10101
<> 144:ef7eb2e8f9f7 10102 /******************** Bit definition for LTDC_SSCR register *****************/
<> 144:ef7eb2e8f9f7 10103
AnnaBridge 167:e84263d55307 10104 #define LTDC_SSCR_VSH_Pos (0U)
AnnaBridge 167:e84263d55307 10105 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10106 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
AnnaBridge 167:e84263d55307 10107 #define LTDC_SSCR_HSW_Pos (16U)
AnnaBridge 167:e84263d55307 10108 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 10109 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
<> 144:ef7eb2e8f9f7 10110
<> 144:ef7eb2e8f9f7 10111 /******************** Bit definition for LTDC_BPCR register *****************/
<> 144:ef7eb2e8f9f7 10112
AnnaBridge 167:e84263d55307 10113 #define LTDC_BPCR_AVBP_Pos (0U)
AnnaBridge 167:e84263d55307 10114 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10115 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
AnnaBridge 167:e84263d55307 10116 #define LTDC_BPCR_AHBP_Pos (16U)
AnnaBridge 167:e84263d55307 10117 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 10118 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
<> 144:ef7eb2e8f9f7 10119
<> 144:ef7eb2e8f9f7 10120 /******************** Bit definition for LTDC_AWCR register *****************/
<> 144:ef7eb2e8f9f7 10121
AnnaBridge 167:e84263d55307 10122 #define LTDC_AWCR_AAH_Pos (0U)
AnnaBridge 167:e84263d55307 10123 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10124 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
AnnaBridge 167:e84263d55307 10125 #define LTDC_AWCR_AAW_Pos (16U)
AnnaBridge 167:e84263d55307 10126 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 10127 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
<> 144:ef7eb2e8f9f7 10128
<> 144:ef7eb2e8f9f7 10129 /******************** Bit definition for LTDC_TWCR register *****************/
<> 144:ef7eb2e8f9f7 10130
AnnaBridge 167:e84263d55307 10131 #define LTDC_TWCR_TOTALH_Pos (0U)
AnnaBridge 167:e84263d55307 10132 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10133 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
AnnaBridge 167:e84263d55307 10134 #define LTDC_TWCR_TOTALW_Pos (16U)
AnnaBridge 167:e84263d55307 10135 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
AnnaBridge 167:e84263d55307 10136 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
<> 144:ef7eb2e8f9f7 10137
<> 144:ef7eb2e8f9f7 10138 /******************** Bit definition for LTDC_GCR register ******************/
<> 144:ef7eb2e8f9f7 10139
AnnaBridge 167:e84263d55307 10140 #define LTDC_GCR_LTDCEN_Pos (0U)
AnnaBridge 167:e84263d55307 10141 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10142 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
AnnaBridge 167:e84263d55307 10143 #define LTDC_GCR_DBW_Pos (4U)
AnnaBridge 167:e84263d55307 10144 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 10145 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
AnnaBridge 167:e84263d55307 10146 #define LTDC_GCR_DGW_Pos (8U)
AnnaBridge 167:e84263d55307 10147 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
AnnaBridge 167:e84263d55307 10148 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
AnnaBridge 167:e84263d55307 10149 #define LTDC_GCR_DRW_Pos (12U)
AnnaBridge 167:e84263d55307 10150 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 10151 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
AnnaBridge 167:e84263d55307 10152 #define LTDC_GCR_DEN_Pos (16U)
AnnaBridge 167:e84263d55307 10153 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10154 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
AnnaBridge 167:e84263d55307 10155 #define LTDC_GCR_PCPOL_Pos (28U)
AnnaBridge 167:e84263d55307 10156 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 10157 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
AnnaBridge 167:e84263d55307 10158 #define LTDC_GCR_DEPOL_Pos (29U)
AnnaBridge 167:e84263d55307 10159 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 10160 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
AnnaBridge 167:e84263d55307 10161 #define LTDC_GCR_VSPOL_Pos (30U)
AnnaBridge 167:e84263d55307 10162 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 10163 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
AnnaBridge 167:e84263d55307 10164 #define LTDC_GCR_HSPOL_Pos (31U)
AnnaBridge 167:e84263d55307 10165 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 10166 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
<> 144:ef7eb2e8f9f7 10167
<> 144:ef7eb2e8f9f7 10168 /* Legacy defines */
<> 144:ef7eb2e8f9f7 10169 #define LTDC_GCR_DTEN LTDC_GCR_DEN
<> 144:ef7eb2e8f9f7 10170
<> 144:ef7eb2e8f9f7 10171 /******************** Bit definition for LTDC_SRCR register *****************/
<> 144:ef7eb2e8f9f7 10172
AnnaBridge 167:e84263d55307 10173 #define LTDC_SRCR_IMR_Pos (0U)
AnnaBridge 167:e84263d55307 10174 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10175 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
AnnaBridge 167:e84263d55307 10176 #define LTDC_SRCR_VBR_Pos (1U)
AnnaBridge 167:e84263d55307 10177 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10178 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
<> 144:ef7eb2e8f9f7 10179
<> 144:ef7eb2e8f9f7 10180 /******************** Bit definition for LTDC_BCCR register *****************/
<> 144:ef7eb2e8f9f7 10181
AnnaBridge 167:e84263d55307 10182 #define LTDC_BCCR_BCBLUE_Pos (0U)
AnnaBridge 167:e84263d55307 10183 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 10184 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
AnnaBridge 167:e84263d55307 10185 #define LTDC_BCCR_BCGREEN_Pos (8U)
AnnaBridge 167:e84263d55307 10186 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10187 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
AnnaBridge 167:e84263d55307 10188 #define LTDC_BCCR_BCRED_Pos (16U)
AnnaBridge 167:e84263d55307 10189 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 10190 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
<> 144:ef7eb2e8f9f7 10191
<> 144:ef7eb2e8f9f7 10192 /******************** Bit definition for LTDC_IER register ******************/
<> 144:ef7eb2e8f9f7 10193
AnnaBridge 167:e84263d55307 10194 #define LTDC_IER_LIE_Pos (0U)
AnnaBridge 167:e84263d55307 10195 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10196 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
AnnaBridge 167:e84263d55307 10197 #define LTDC_IER_FUIE_Pos (1U)
AnnaBridge 167:e84263d55307 10198 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10199 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
AnnaBridge 167:e84263d55307 10200 #define LTDC_IER_TERRIE_Pos (2U)
AnnaBridge 167:e84263d55307 10201 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10202 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
AnnaBridge 167:e84263d55307 10203 #define LTDC_IER_RRIE_Pos (3U)
AnnaBridge 167:e84263d55307 10204 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10205 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
<> 144:ef7eb2e8f9f7 10206
<> 144:ef7eb2e8f9f7 10207 /******************** Bit definition for LTDC_ISR register ******************/
<> 144:ef7eb2e8f9f7 10208
AnnaBridge 167:e84263d55307 10209 #define LTDC_ISR_LIF_Pos (0U)
AnnaBridge 167:e84263d55307 10210 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10211 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
AnnaBridge 167:e84263d55307 10212 #define LTDC_ISR_FUIF_Pos (1U)
AnnaBridge 167:e84263d55307 10213 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10214 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
AnnaBridge 167:e84263d55307 10215 #define LTDC_ISR_TERRIF_Pos (2U)
AnnaBridge 167:e84263d55307 10216 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10217 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
AnnaBridge 167:e84263d55307 10218 #define LTDC_ISR_RRIF_Pos (3U)
AnnaBridge 167:e84263d55307 10219 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10220 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
<> 144:ef7eb2e8f9f7 10221
<> 144:ef7eb2e8f9f7 10222 /******************** Bit definition for LTDC_ICR register ******************/
<> 144:ef7eb2e8f9f7 10223
AnnaBridge 167:e84263d55307 10224 #define LTDC_ICR_CLIF_Pos (0U)
AnnaBridge 167:e84263d55307 10225 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10226 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
AnnaBridge 167:e84263d55307 10227 #define LTDC_ICR_CFUIF_Pos (1U)
AnnaBridge 167:e84263d55307 10228 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10229 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
AnnaBridge 167:e84263d55307 10230 #define LTDC_ICR_CTERRIF_Pos (2U)
AnnaBridge 167:e84263d55307 10231 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10232 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
AnnaBridge 167:e84263d55307 10233 #define LTDC_ICR_CRRIF_Pos (3U)
AnnaBridge 167:e84263d55307 10234 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10235 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
<> 144:ef7eb2e8f9f7 10236
<> 144:ef7eb2e8f9f7 10237 /******************** Bit definition for LTDC_LIPCR register ****************/
<> 144:ef7eb2e8f9f7 10238
AnnaBridge 167:e84263d55307 10239 #define LTDC_LIPCR_LIPOS_Pos (0U)
AnnaBridge 167:e84263d55307 10240 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10241 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
<> 144:ef7eb2e8f9f7 10242
<> 144:ef7eb2e8f9f7 10243 /******************** Bit definition for LTDC_CPSR register *****************/
<> 144:ef7eb2e8f9f7 10244
AnnaBridge 167:e84263d55307 10245 #define LTDC_CPSR_CYPOS_Pos (0U)
AnnaBridge 167:e84263d55307 10246 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 10247 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
AnnaBridge 167:e84263d55307 10248 #define LTDC_CPSR_CXPOS_Pos (16U)
AnnaBridge 167:e84263d55307 10249 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 10250 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
<> 144:ef7eb2e8f9f7 10251
<> 144:ef7eb2e8f9f7 10252 /******************** Bit definition for LTDC_CDSR register *****************/
<> 144:ef7eb2e8f9f7 10253
AnnaBridge 167:e84263d55307 10254 #define LTDC_CDSR_VDES_Pos (0U)
AnnaBridge 167:e84263d55307 10255 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10256 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
AnnaBridge 167:e84263d55307 10257 #define LTDC_CDSR_HDES_Pos (1U)
AnnaBridge 167:e84263d55307 10258 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10259 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
AnnaBridge 167:e84263d55307 10260 #define LTDC_CDSR_VSYNCS_Pos (2U)
AnnaBridge 167:e84263d55307 10261 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10262 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
AnnaBridge 167:e84263d55307 10263 #define LTDC_CDSR_HSYNCS_Pos (3U)
AnnaBridge 167:e84263d55307 10264 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10265 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
<> 144:ef7eb2e8f9f7 10266
<> 144:ef7eb2e8f9f7 10267 /******************** Bit definition for LTDC_LxCR register *****************/
<> 144:ef7eb2e8f9f7 10268
AnnaBridge 167:e84263d55307 10269 #define LTDC_LxCR_LEN_Pos (0U)
AnnaBridge 167:e84263d55307 10270 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10271 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
AnnaBridge 167:e84263d55307 10272 #define LTDC_LxCR_COLKEN_Pos (1U)
AnnaBridge 167:e84263d55307 10273 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10274 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
AnnaBridge 167:e84263d55307 10275 #define LTDC_LxCR_CLUTEN_Pos (4U)
AnnaBridge 167:e84263d55307 10276 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10277 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
<> 144:ef7eb2e8f9f7 10278
<> 144:ef7eb2e8f9f7 10279 /******************** Bit definition for LTDC_LxWHPCR register **************/
<> 144:ef7eb2e8f9f7 10280
AnnaBridge 167:e84263d55307 10281 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
AnnaBridge 167:e84263d55307 10282 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 10283 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
AnnaBridge 167:e84263d55307 10284 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
AnnaBridge 167:e84263d55307 10285 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 10286 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
<> 144:ef7eb2e8f9f7 10287
<> 144:ef7eb2e8f9f7 10288 /******************** Bit definition for LTDC_LxWVPCR register **************/
<> 144:ef7eb2e8f9f7 10289
AnnaBridge 167:e84263d55307 10290 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
AnnaBridge 167:e84263d55307 10291 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 10292 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
AnnaBridge 167:e84263d55307 10293 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
AnnaBridge 167:e84263d55307 10294 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 10295 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
<> 144:ef7eb2e8f9f7 10296
<> 144:ef7eb2e8f9f7 10297 /******************** Bit definition for LTDC_LxCKCR register ***************/
<> 144:ef7eb2e8f9f7 10298
AnnaBridge 167:e84263d55307 10299 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
AnnaBridge 167:e84263d55307 10300 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 10301 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
AnnaBridge 167:e84263d55307 10302 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
AnnaBridge 167:e84263d55307 10303 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10304 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
AnnaBridge 167:e84263d55307 10305 #define LTDC_LxCKCR_CKRED_Pos (16U)
AnnaBridge 167:e84263d55307 10306 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 10307 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
<> 144:ef7eb2e8f9f7 10308
<> 144:ef7eb2e8f9f7 10309 /******************** Bit definition for LTDC_LxPFCR register ***************/
<> 144:ef7eb2e8f9f7 10310
AnnaBridge 167:e84263d55307 10311 #define LTDC_LxPFCR_PF_Pos (0U)
AnnaBridge 167:e84263d55307 10312 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 10313 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
<> 144:ef7eb2e8f9f7 10314
<> 144:ef7eb2e8f9f7 10315 /******************** Bit definition for LTDC_LxCACR register ***************/
<> 144:ef7eb2e8f9f7 10316
AnnaBridge 167:e84263d55307 10317 #define LTDC_LxCACR_CONSTA_Pos (0U)
AnnaBridge 167:e84263d55307 10318 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 10319 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
<> 144:ef7eb2e8f9f7 10320
<> 144:ef7eb2e8f9f7 10321 /******************** Bit definition for LTDC_LxDCCR register ***************/
<> 144:ef7eb2e8f9f7 10322
AnnaBridge 167:e84263d55307 10323 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
AnnaBridge 167:e84263d55307 10324 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 10325 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
AnnaBridge 167:e84263d55307 10326 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
AnnaBridge 167:e84263d55307 10327 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10328 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
AnnaBridge 167:e84263d55307 10329 #define LTDC_LxDCCR_DCRED_Pos (16U)
AnnaBridge 167:e84263d55307 10330 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 10331 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
AnnaBridge 167:e84263d55307 10332 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
AnnaBridge 167:e84263d55307 10333 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 10334 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
<> 144:ef7eb2e8f9f7 10335
<> 144:ef7eb2e8f9f7 10336 /******************** Bit definition for LTDC_LxBFCR register ***************/
<> 144:ef7eb2e8f9f7 10337
AnnaBridge 167:e84263d55307 10338 #define LTDC_LxBFCR_BF2_Pos (0U)
AnnaBridge 167:e84263d55307 10339 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 10340 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
AnnaBridge 167:e84263d55307 10341 #define LTDC_LxBFCR_BF1_Pos (8U)
AnnaBridge 167:e84263d55307 10342 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
AnnaBridge 167:e84263d55307 10343 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
<> 144:ef7eb2e8f9f7 10344
<> 144:ef7eb2e8f9f7 10345 /******************** Bit definition for LTDC_LxCFBAR register **************/
<> 144:ef7eb2e8f9f7 10346
AnnaBridge 167:e84263d55307 10347 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
AnnaBridge 167:e84263d55307 10348 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 10349 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
<> 144:ef7eb2e8f9f7 10350
<> 144:ef7eb2e8f9f7 10351 /******************** Bit definition for LTDC_LxCFBLR register **************/
<> 144:ef7eb2e8f9f7 10352
AnnaBridge 167:e84263d55307 10353 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
AnnaBridge 167:e84263d55307 10354 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
AnnaBridge 167:e84263d55307 10355 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
AnnaBridge 167:e84263d55307 10356 #define LTDC_LxCFBLR_CFBP_Pos (16U)
AnnaBridge 167:e84263d55307 10357 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
AnnaBridge 167:e84263d55307 10358 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
<> 144:ef7eb2e8f9f7 10359
<> 144:ef7eb2e8f9f7 10360 /******************** Bit definition for LTDC_LxCFBLNR register *************/
<> 144:ef7eb2e8f9f7 10361
AnnaBridge 167:e84263d55307 10362 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
AnnaBridge 167:e84263d55307 10363 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 10364 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
<> 144:ef7eb2e8f9f7 10365
<> 144:ef7eb2e8f9f7 10366 /******************** Bit definition for LTDC_LxCLUTWR register *************/
<> 144:ef7eb2e8f9f7 10367
AnnaBridge 167:e84263d55307 10368 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
AnnaBridge 167:e84263d55307 10369 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 10370 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
AnnaBridge 167:e84263d55307 10371 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
AnnaBridge 167:e84263d55307 10372 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10373 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
AnnaBridge 167:e84263d55307 10374 #define LTDC_LxCLUTWR_RED_Pos (16U)
AnnaBridge 167:e84263d55307 10375 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 10376 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
AnnaBridge 167:e84263d55307 10377 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
AnnaBridge 167:e84263d55307 10378 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 10379 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
<> 144:ef7eb2e8f9f7 10380
<> 144:ef7eb2e8f9f7 10381
<> 144:ef7eb2e8f9f7 10382 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10383 /* */
<> 144:ef7eb2e8f9f7 10384 /* Power Control */
<> 144:ef7eb2e8f9f7 10385 /* */
<> 144:ef7eb2e8f9f7 10386 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10387 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 167:e84263d55307 10388 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 167:e84263d55307 10389 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10390 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
AnnaBridge 167:e84263d55307 10391 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 167:e84263d55307 10392 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10393 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 167:e84263d55307 10394 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 167:e84263d55307 10395 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10396 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 167:e84263d55307 10397 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 167:e84263d55307 10398 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10399 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 167:e84263d55307 10400 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 167:e84263d55307 10401 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10402 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 167:e84263d55307 10403
AnnaBridge 167:e84263d55307 10404 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 167:e84263d55307 10405 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 167:e84263d55307 10406 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 167:e84263d55307 10407 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10408 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10409 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 10410
<> 144:ef7eb2e8f9f7 10411 /*!< PVD level configuration */
AnnaBridge 167:e84263d55307 10412 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
AnnaBridge 167:e84263d55307 10413 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
AnnaBridge 167:e84263d55307 10414 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
AnnaBridge 167:e84263d55307 10415 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
AnnaBridge 167:e84263d55307 10416 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
AnnaBridge 167:e84263d55307 10417 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
AnnaBridge 167:e84263d55307 10418 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
AnnaBridge 167:e84263d55307 10419 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
AnnaBridge 167:e84263d55307 10420 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 167:e84263d55307 10421 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10422 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 167:e84263d55307 10423 #define PWR_CR_FPDS_Pos (9U)
AnnaBridge 167:e84263d55307 10424 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10425 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
AnnaBridge 167:e84263d55307 10426 #define PWR_CR_LPLVDS_Pos (10U)
AnnaBridge 167:e84263d55307 10427 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10428 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
AnnaBridge 167:e84263d55307 10429 #define PWR_CR_MRLVDS_Pos (11U)
AnnaBridge 167:e84263d55307 10430 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10431 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
AnnaBridge 167:e84263d55307 10432 #define PWR_CR_ADCDC1_Pos (13U)
AnnaBridge 167:e84263d55307 10433 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10434 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 167:e84263d55307 10435 #define PWR_CR_VOS_Pos (14U)
AnnaBridge 167:e84263d55307 10436 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 10437 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
AnnaBridge 167:e84263d55307 10438 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
AnnaBridge 167:e84263d55307 10439 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
AnnaBridge 167:e84263d55307 10440 #define PWR_CR_ODEN_Pos (16U)
AnnaBridge 167:e84263d55307 10441 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10442 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
AnnaBridge 167:e84263d55307 10443 #define PWR_CR_ODSWEN_Pos (17U)
AnnaBridge 167:e84263d55307 10444 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10445 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
AnnaBridge 167:e84263d55307 10446 #define PWR_CR_UDEN_Pos (18U)
AnnaBridge 167:e84263d55307 10447 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 10448 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
AnnaBridge 167:e84263d55307 10449 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10450 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
<> 144:ef7eb2e8f9f7 10451
<> 144:ef7eb2e8f9f7 10452 /* Legacy define */
<> 144:ef7eb2e8f9f7 10453 #define PWR_CR_PMODE PWR_CR_VOS
AnnaBridge 167:e84263d55307 10454 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
AnnaBridge 167:e84263d55307 10455 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
<> 144:ef7eb2e8f9f7 10456
<> 144:ef7eb2e8f9f7 10457 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 167:e84263d55307 10458 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 167:e84263d55307 10459 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10460 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 167:e84263d55307 10461 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 167:e84263d55307 10462 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10463 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 167:e84263d55307 10464 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 167:e84263d55307 10465 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10466 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 167:e84263d55307 10467 #define PWR_CSR_BRR_Pos (3U)
AnnaBridge 167:e84263d55307 10468 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10469 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
AnnaBridge 167:e84263d55307 10470 #define PWR_CSR_EWUP_Pos (8U)
AnnaBridge 167:e84263d55307 10471 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10472 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
AnnaBridge 167:e84263d55307 10473 #define PWR_CSR_BRE_Pos (9U)
AnnaBridge 167:e84263d55307 10474 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10475 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
AnnaBridge 167:e84263d55307 10476 #define PWR_CSR_VOSRDY_Pos (14U)
AnnaBridge 167:e84263d55307 10477 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10478 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
AnnaBridge 167:e84263d55307 10479 #define PWR_CSR_ODRDY_Pos (16U)
AnnaBridge 167:e84263d55307 10480 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10481 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
AnnaBridge 167:e84263d55307 10482 #define PWR_CSR_ODSWRDY_Pos (17U)
AnnaBridge 167:e84263d55307 10483 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10484 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
AnnaBridge 167:e84263d55307 10485 #define PWR_CSR_UDRDY_Pos (18U)
AnnaBridge 167:e84263d55307 10486 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 10487 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
AnnaBridge 167:e84263d55307 10488 /* Legacy define */
AnnaBridge 167:e84263d55307 10489 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
<> 144:ef7eb2e8f9f7 10490
<> 144:ef7eb2e8f9f7 10491 /* Legacy define */
<> 144:ef7eb2e8f9f7 10492 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
<> 144:ef7eb2e8f9f7 10493
<> 144:ef7eb2e8f9f7 10494 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10495 /* */
<> 144:ef7eb2e8f9f7 10496 /* Reset and Clock Control */
<> 144:ef7eb2e8f9f7 10497 /* */
<> 144:ef7eb2e8f9f7 10498 /******************************************************************************/
<> 144:ef7eb2e8f9f7 10499 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 167:e84263d55307 10500 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 167:e84263d55307 10501 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10502 #define RCC_CR_HSION RCC_CR_HSION_Msk
AnnaBridge 167:e84263d55307 10503 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 167:e84263d55307 10504 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10505 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
AnnaBridge 167:e84263d55307 10506
AnnaBridge 167:e84263d55307 10507 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 167:e84263d55307 10508 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 167:e84263d55307 10509 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
AnnaBridge 167:e84263d55307 10510 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10511 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10512 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10513 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10514 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10515
AnnaBridge 167:e84263d55307 10516 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 167:e84263d55307 10517 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 10518 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
AnnaBridge 167:e84263d55307 10519 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10520 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10521 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10522 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10523 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10524 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10525 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10526 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 10527
AnnaBridge 167:e84263d55307 10528 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 167:e84263d55307 10529 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10530 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
AnnaBridge 167:e84263d55307 10531 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 167:e84263d55307 10532 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10533 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
AnnaBridge 167:e84263d55307 10534 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 167:e84263d55307 10535 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10536 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
AnnaBridge 167:e84263d55307 10537 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 167:e84263d55307 10538 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 10539 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
AnnaBridge 167:e84263d55307 10540 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 167:e84263d55307 10541 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 10542 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
AnnaBridge 167:e84263d55307 10543 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 167:e84263d55307 10544 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 10545 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
AnnaBridge 167:e84263d55307 10546 /*
AnnaBridge 167:e84263d55307 10547 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 10548 */
AnnaBridge 167:e84263d55307 10549 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
AnnaBridge 167:e84263d55307 10550
AnnaBridge 167:e84263d55307 10551 #define RCC_CR_PLLI2SON_Pos (26U)
AnnaBridge 167:e84263d55307 10552 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 10553 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
AnnaBridge 167:e84263d55307 10554 #define RCC_CR_PLLI2SRDY_Pos (27U)
AnnaBridge 167:e84263d55307 10555 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 10556 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
AnnaBridge 167:e84263d55307 10557 /*
AnnaBridge 167:e84263d55307 10558 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 10559 */
AnnaBridge 167:e84263d55307 10560 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
AnnaBridge 167:e84263d55307 10561
AnnaBridge 167:e84263d55307 10562 #define RCC_CR_PLLSAION_Pos (28U)
AnnaBridge 167:e84263d55307 10563 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 10564 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
AnnaBridge 167:e84263d55307 10565 #define RCC_CR_PLLSAIRDY_Pos (29U)
AnnaBridge 167:e84263d55307 10566 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 10567 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
<> 144:ef7eb2e8f9f7 10568
<> 144:ef7eb2e8f9f7 10569 /******************** Bit definition for RCC_PLLCFGR register ***************/
AnnaBridge 167:e84263d55307 10570 #define RCC_PLLCFGR_PLLM_Pos (0U)
AnnaBridge 167:e84263d55307 10571 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
AnnaBridge 167:e84263d55307 10572 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
AnnaBridge 167:e84263d55307 10573 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10574 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10575 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10576 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10577 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10578 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10579
AnnaBridge 167:e84263d55307 10580 #define RCC_PLLCFGR_PLLN_Pos (6U)
AnnaBridge 167:e84263d55307 10581 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
AnnaBridge 167:e84263d55307 10582 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
AnnaBridge 167:e84263d55307 10583 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10584 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10585 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10586 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10587 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10588 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10589 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10590 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10591 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10592
AnnaBridge 167:e84263d55307 10593 #define RCC_PLLCFGR_PLLP_Pos (16U)
AnnaBridge 167:e84263d55307 10594 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 10595 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
AnnaBridge 167:e84263d55307 10596 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10597 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10598
AnnaBridge 167:e84263d55307 10599 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
AnnaBridge 167:e84263d55307 10600 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10601 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
AnnaBridge 167:e84263d55307 10602 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
AnnaBridge 167:e84263d55307 10603 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10604 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
AnnaBridge 167:e84263d55307 10605 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
AnnaBridge 167:e84263d55307 10606
AnnaBridge 167:e84263d55307 10607 #define RCC_PLLCFGR_PLLQ_Pos (24U)
AnnaBridge 167:e84263d55307 10608 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 10609 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
AnnaBridge 167:e84263d55307 10610 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 10611 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 10612 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 10613 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 10614
<> 144:ef7eb2e8f9f7 10615
<> 144:ef7eb2e8f9f7 10616 /******************** Bit definition for RCC_CFGR register ******************/
<> 144:ef7eb2e8f9f7 10617 /*!< SW configuration */
AnnaBridge 167:e84263d55307 10618 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 167:e84263d55307 10619 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 10620 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 167:e84263d55307 10621 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10622 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10623
AnnaBridge 167:e84263d55307 10624 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
AnnaBridge 167:e84263d55307 10625 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
AnnaBridge 167:e84263d55307 10626 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 144:ef7eb2e8f9f7 10627
<> 144:ef7eb2e8f9f7 10628 /*!< SWS configuration */
AnnaBridge 167:e84263d55307 10629 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 167:e84263d55307 10630 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 10631 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 167:e84263d55307 10632 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10633 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10634
AnnaBridge 167:e84263d55307 10635 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
AnnaBridge 167:e84263d55307 10636 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
AnnaBridge 167:e84263d55307 10637 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 144:ef7eb2e8f9f7 10638
<> 144:ef7eb2e8f9f7 10639 /*!< HPRE configuration */
AnnaBridge 167:e84263d55307 10640 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 167:e84263d55307 10641 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 10642 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 167:e84263d55307 10643 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10644 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10645 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10646 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10647
AnnaBridge 167:e84263d55307 10648 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
AnnaBridge 167:e84263d55307 10649 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
AnnaBridge 167:e84263d55307 10650 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
AnnaBridge 167:e84263d55307 10651 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
AnnaBridge 167:e84263d55307 10652 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
AnnaBridge 167:e84263d55307 10653 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
AnnaBridge 167:e84263d55307 10654 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
AnnaBridge 167:e84263d55307 10655 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
AnnaBridge 167:e84263d55307 10656 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 144:ef7eb2e8f9f7 10657
<> 144:ef7eb2e8f9f7 10658 /*!< PPRE1 configuration */
AnnaBridge 167:e84263d55307 10659 #define RCC_CFGR_PPRE1_Pos (10U)
AnnaBridge 167:e84263d55307 10660 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
AnnaBridge 167:e84263d55307 10661 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 167:e84263d55307 10662 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10663 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10664 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10665
AnnaBridge 167:e84263d55307 10666 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 167:e84263d55307 10667 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
AnnaBridge 167:e84263d55307 10668 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
AnnaBridge 167:e84263d55307 10669 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
AnnaBridge 167:e84263d55307 10670 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 10671
<> 144:ef7eb2e8f9f7 10672 /*!< PPRE2 configuration */
AnnaBridge 167:e84263d55307 10673 #define RCC_CFGR_PPRE2_Pos (13U)
AnnaBridge 167:e84263d55307 10674 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
AnnaBridge 167:e84263d55307 10675 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 167:e84263d55307 10676 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10677 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10678 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 10679
AnnaBridge 167:e84263d55307 10680 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
AnnaBridge 167:e84263d55307 10681 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
AnnaBridge 167:e84263d55307 10682 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
AnnaBridge 167:e84263d55307 10683 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
AnnaBridge 167:e84263d55307 10684 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 144:ef7eb2e8f9f7 10685
<> 144:ef7eb2e8f9f7 10686 /*!< RTCPRE configuration */
AnnaBridge 167:e84263d55307 10687 #define RCC_CFGR_RTCPRE_Pos (16U)
AnnaBridge 167:e84263d55307 10688 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
AnnaBridge 167:e84263d55307 10689 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
AnnaBridge 167:e84263d55307 10690 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10691 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10692 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10693 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 10694 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
<> 144:ef7eb2e8f9f7 10695
<> 144:ef7eb2e8f9f7 10696 /*!< MCO1 configuration */
AnnaBridge 167:e84263d55307 10697 #define RCC_CFGR_MCO1_Pos (21U)
AnnaBridge 167:e84263d55307 10698 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
AnnaBridge 167:e84263d55307 10699 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
AnnaBridge 167:e84263d55307 10700 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 10701 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10702
AnnaBridge 167:e84263d55307 10703 #define RCC_CFGR_I2SSRC_Pos (23U)
AnnaBridge 167:e84263d55307 10704 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 10705 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
AnnaBridge 167:e84263d55307 10706
AnnaBridge 167:e84263d55307 10707 #define RCC_CFGR_MCO1PRE_Pos (24U)
AnnaBridge 167:e84263d55307 10708 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
AnnaBridge 167:e84263d55307 10709 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
AnnaBridge 167:e84263d55307 10710 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 10711 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 10712 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 10713
AnnaBridge 167:e84263d55307 10714 #define RCC_CFGR_MCO2PRE_Pos (27U)
AnnaBridge 167:e84263d55307 10715 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
AnnaBridge 167:e84263d55307 10716 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
AnnaBridge 167:e84263d55307 10717 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 10718 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 10719 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 10720
AnnaBridge 167:e84263d55307 10721 #define RCC_CFGR_MCO2_Pos (30U)
AnnaBridge 167:e84263d55307 10722 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
AnnaBridge 167:e84263d55307 10723 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
AnnaBridge 167:e84263d55307 10724 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 10725 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
<> 144:ef7eb2e8f9f7 10726
<> 144:ef7eb2e8f9f7 10727 /******************** Bit definition for RCC_CIR register *******************/
AnnaBridge 167:e84263d55307 10728 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 167:e84263d55307 10729 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10730 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
AnnaBridge 167:e84263d55307 10731 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 167:e84263d55307 10732 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10733 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
AnnaBridge 167:e84263d55307 10734 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 167:e84263d55307 10735 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10736 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
AnnaBridge 167:e84263d55307 10737 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 167:e84263d55307 10738 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10739 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
AnnaBridge 167:e84263d55307 10740 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 167:e84263d55307 10741 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10742 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
AnnaBridge 167:e84263d55307 10743 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
AnnaBridge 167:e84263d55307 10744 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10745 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
AnnaBridge 167:e84263d55307 10746
AnnaBridge 167:e84263d55307 10747 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
AnnaBridge 167:e84263d55307 10748 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10749 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
AnnaBridge 167:e84263d55307 10750 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 167:e84263d55307 10751 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10752 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
AnnaBridge 167:e84263d55307 10753 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 167:e84263d55307 10754 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10755 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
AnnaBridge 167:e84263d55307 10756 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 167:e84263d55307 10757 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10758 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
AnnaBridge 167:e84263d55307 10759 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 167:e84263d55307 10760 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10761 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
AnnaBridge 167:e84263d55307 10762 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 167:e84263d55307 10763 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10764 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
AnnaBridge 167:e84263d55307 10765 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 167:e84263d55307 10766 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10767 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
AnnaBridge 167:e84263d55307 10768 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
AnnaBridge 167:e84263d55307 10769 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10770 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
AnnaBridge 167:e84263d55307 10771
AnnaBridge 167:e84263d55307 10772 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
AnnaBridge 167:e84263d55307 10773 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10774 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
AnnaBridge 167:e84263d55307 10775 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 167:e84263d55307 10776 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10777 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
AnnaBridge 167:e84263d55307 10778 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 167:e84263d55307 10779 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10780 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
AnnaBridge 167:e84263d55307 10781 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 167:e84263d55307 10782 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10783 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
AnnaBridge 167:e84263d55307 10784 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 167:e84263d55307 10785 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 10786 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
AnnaBridge 167:e84263d55307 10787 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 167:e84263d55307 10788 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 10789 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
AnnaBridge 167:e84263d55307 10790 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
AnnaBridge 167:e84263d55307 10791 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 10792 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
AnnaBridge 167:e84263d55307 10793 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
AnnaBridge 167:e84263d55307 10794 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10795 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
AnnaBridge 167:e84263d55307 10796
AnnaBridge 167:e84263d55307 10797 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 167:e84263d55307 10798 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 10799 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
<> 144:ef7eb2e8f9f7 10800
<> 144:ef7eb2e8f9f7 10801 /******************** Bit definition for RCC_AHB1RSTR register **************/
AnnaBridge 167:e84263d55307 10802 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
AnnaBridge 167:e84263d55307 10803 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10804 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
AnnaBridge 167:e84263d55307 10805 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
AnnaBridge 167:e84263d55307 10806 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10807 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
AnnaBridge 167:e84263d55307 10808 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
AnnaBridge 167:e84263d55307 10809 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10810 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
AnnaBridge 167:e84263d55307 10811 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
AnnaBridge 167:e84263d55307 10812 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10813 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
AnnaBridge 167:e84263d55307 10814 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
AnnaBridge 167:e84263d55307 10815 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10816 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
AnnaBridge 167:e84263d55307 10817 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
AnnaBridge 167:e84263d55307 10818 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10819 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
AnnaBridge 167:e84263d55307 10820 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
AnnaBridge 167:e84263d55307 10821 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10822 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
AnnaBridge 167:e84263d55307 10823 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
AnnaBridge 167:e84263d55307 10824 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10825 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
AnnaBridge 167:e84263d55307 10826 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
AnnaBridge 167:e84263d55307 10827 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10828 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
AnnaBridge 167:e84263d55307 10829 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
AnnaBridge 167:e84263d55307 10830 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 10831 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
AnnaBridge 167:e84263d55307 10832 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
AnnaBridge 167:e84263d55307 10833 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 10834 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
AnnaBridge 167:e84263d55307 10835 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
AnnaBridge 167:e84263d55307 10836 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10837 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
AnnaBridge 167:e84263d55307 10838 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
AnnaBridge 167:e84263d55307 10839 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 10840 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
AnnaBridge 167:e84263d55307 10841 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
AnnaBridge 167:e84263d55307 10842 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10843 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
AnnaBridge 167:e84263d55307 10844 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
AnnaBridge 167:e84263d55307 10845 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 10846 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
AnnaBridge 167:e84263d55307 10847 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
AnnaBridge 167:e84263d55307 10848 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 10849 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
AnnaBridge 167:e84263d55307 10850 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
AnnaBridge 167:e84263d55307 10851 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 10852 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
<> 144:ef7eb2e8f9f7 10853
<> 144:ef7eb2e8f9f7 10854 /******************** Bit definition for RCC_AHB2RSTR register **************/
AnnaBridge 167:e84263d55307 10855 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
AnnaBridge 167:e84263d55307 10856 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10857 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
AnnaBridge 167:e84263d55307 10858 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
AnnaBridge 167:e84263d55307 10859 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10860 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
AnnaBridge 167:e84263d55307 10861 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
AnnaBridge 167:e84263d55307 10862 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10863 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
<> 144:ef7eb2e8f9f7 10864 /******************** Bit definition for RCC_AHB3RSTR register **************/
AnnaBridge 167:e84263d55307 10865 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
AnnaBridge 167:e84263d55307 10866 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10867 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
AnnaBridge 167:e84263d55307 10868
<> 144:ef7eb2e8f9f7 10869
<> 144:ef7eb2e8f9f7 10870 /******************** Bit definition for RCC_APB1RSTR register **************/
AnnaBridge 167:e84263d55307 10871 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 167:e84263d55307 10872 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10873 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
AnnaBridge 167:e84263d55307 10874 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 167:e84263d55307 10875 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10876 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
AnnaBridge 167:e84263d55307 10877 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 167:e84263d55307 10878 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 10879 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
AnnaBridge 167:e84263d55307 10880 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 167:e84263d55307 10881 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 10882 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
AnnaBridge 167:e84263d55307 10883 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 167:e84263d55307 10884 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10885 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
AnnaBridge 167:e84263d55307 10886 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 167:e84263d55307 10887 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10888 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
AnnaBridge 167:e84263d55307 10889 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
AnnaBridge 167:e84263d55307 10890 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 10891 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
AnnaBridge 167:e84263d55307 10892 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
AnnaBridge 167:e84263d55307 10893 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 10894 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
AnnaBridge 167:e84263d55307 10895 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 167:e84263d55307 10896 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10897 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
AnnaBridge 167:e84263d55307 10898 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 167:e84263d55307 10899 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10900 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
AnnaBridge 167:e84263d55307 10901 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 167:e84263d55307 10902 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10903 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
AnnaBridge 167:e84263d55307 10904 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 167:e84263d55307 10905 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 10906 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
AnnaBridge 167:e84263d55307 10907 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 167:e84263d55307 10908 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10909 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
AnnaBridge 167:e84263d55307 10910 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 167:e84263d55307 10911 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10912 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
AnnaBridge 167:e84263d55307 10913 #define RCC_APB1RSTR_UART4RST_Pos (19U)
AnnaBridge 167:e84263d55307 10914 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 10915 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
AnnaBridge 167:e84263d55307 10916 #define RCC_APB1RSTR_UART5RST_Pos (20U)
AnnaBridge 167:e84263d55307 10917 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 10918 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
AnnaBridge 167:e84263d55307 10919 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 167:e84263d55307 10920 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 10921 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
AnnaBridge 167:e84263d55307 10922 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 167:e84263d55307 10923 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10924 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
AnnaBridge 167:e84263d55307 10925 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
AnnaBridge 167:e84263d55307 10926 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 10927 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
AnnaBridge 167:e84263d55307 10928 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
AnnaBridge 167:e84263d55307 10929 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 10930 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
AnnaBridge 167:e84263d55307 10931 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
AnnaBridge 167:e84263d55307 10932 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 10933 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
AnnaBridge 167:e84263d55307 10934 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 167:e84263d55307 10935 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 10936 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
AnnaBridge 167:e84263d55307 10937 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 167:e84263d55307 10938 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 10939 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
AnnaBridge 167:e84263d55307 10940 #define RCC_APB1RSTR_UART7RST_Pos (30U)
AnnaBridge 167:e84263d55307 10941 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 10942 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
AnnaBridge 167:e84263d55307 10943 #define RCC_APB1RSTR_UART8RST_Pos (31U)
AnnaBridge 167:e84263d55307 10944 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 10945 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
<> 144:ef7eb2e8f9f7 10946
<> 144:ef7eb2e8f9f7 10947 /******************** Bit definition for RCC_APB2RSTR register **************/
AnnaBridge 167:e84263d55307 10948 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
AnnaBridge 167:e84263d55307 10949 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 10950 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
AnnaBridge 167:e84263d55307 10951 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
AnnaBridge 167:e84263d55307 10952 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 10953 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
AnnaBridge 167:e84263d55307 10954 #define RCC_APB2RSTR_USART1RST_Pos (4U)
AnnaBridge 167:e84263d55307 10955 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 10956 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
AnnaBridge 167:e84263d55307 10957 #define RCC_APB2RSTR_USART6RST_Pos (5U)
AnnaBridge 167:e84263d55307 10958 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 10959 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
AnnaBridge 167:e84263d55307 10960 #define RCC_APB2RSTR_ADCRST_Pos (8U)
AnnaBridge 167:e84263d55307 10961 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 10962 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
AnnaBridge 167:e84263d55307 10963 #define RCC_APB2RSTR_SDIORST_Pos (11U)
AnnaBridge 167:e84263d55307 10964 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 10965 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
AnnaBridge 167:e84263d55307 10966 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 167:e84263d55307 10967 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 10968 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
AnnaBridge 167:e84263d55307 10969 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
AnnaBridge 167:e84263d55307 10970 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 10971 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
AnnaBridge 167:e84263d55307 10972 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
AnnaBridge 167:e84263d55307 10973 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 10974 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
AnnaBridge 167:e84263d55307 10975 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
AnnaBridge 167:e84263d55307 10976 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 10977 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
AnnaBridge 167:e84263d55307 10978 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
AnnaBridge 167:e84263d55307 10979 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 10980 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
AnnaBridge 167:e84263d55307 10981 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
AnnaBridge 167:e84263d55307 10982 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 10983 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
AnnaBridge 167:e84263d55307 10984 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
AnnaBridge 167:e84263d55307 10985 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 10986 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
AnnaBridge 167:e84263d55307 10987 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
AnnaBridge 167:e84263d55307 10988 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 10989 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
AnnaBridge 167:e84263d55307 10990 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
AnnaBridge 167:e84263d55307 10991 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 10992 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
AnnaBridge 167:e84263d55307 10993 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
AnnaBridge 167:e84263d55307 10994 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 10995 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
<> 144:ef7eb2e8f9f7 10996
<> 144:ef7eb2e8f9f7 10997 /* Old SPI1RST bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 10998 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
<> 144:ef7eb2e8f9f7 10999
<> 144:ef7eb2e8f9f7 11000 /******************** Bit definition for RCC_AHB1ENR register ***************/
AnnaBridge 167:e84263d55307 11001 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
AnnaBridge 167:e84263d55307 11002 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11003 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
AnnaBridge 167:e84263d55307 11004 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
AnnaBridge 167:e84263d55307 11005 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11006 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
AnnaBridge 167:e84263d55307 11007 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
AnnaBridge 167:e84263d55307 11008 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11009 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
AnnaBridge 167:e84263d55307 11010 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
AnnaBridge 167:e84263d55307 11011 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11012 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
AnnaBridge 167:e84263d55307 11013 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
AnnaBridge 167:e84263d55307 11014 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11015 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
AnnaBridge 167:e84263d55307 11016 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
AnnaBridge 167:e84263d55307 11017 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11018 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
AnnaBridge 167:e84263d55307 11019 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
AnnaBridge 167:e84263d55307 11020 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11021 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
AnnaBridge 167:e84263d55307 11022 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
AnnaBridge 167:e84263d55307 11023 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11024 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
AnnaBridge 167:e84263d55307 11025 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
AnnaBridge 167:e84263d55307 11026 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11027 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
AnnaBridge 167:e84263d55307 11028 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
AnnaBridge 167:e84263d55307 11029 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11030 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
AnnaBridge 167:e84263d55307 11031 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
AnnaBridge 167:e84263d55307 11032 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11033 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
AnnaBridge 167:e84263d55307 11034 #define RCC_AHB1ENR_CRCEN_Pos (12U)
AnnaBridge 167:e84263d55307 11035 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11036 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
AnnaBridge 167:e84263d55307 11037 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
AnnaBridge 167:e84263d55307 11038 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11039 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
AnnaBridge 167:e84263d55307 11040 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
AnnaBridge 167:e84263d55307 11041 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11042 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
AnnaBridge 167:e84263d55307 11043 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
AnnaBridge 167:e84263d55307 11044 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11045 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
AnnaBridge 167:e84263d55307 11046 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
AnnaBridge 167:e84263d55307 11047 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11048 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
AnnaBridge 167:e84263d55307 11049 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
AnnaBridge 167:e84263d55307 11050 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11051 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
AnnaBridge 167:e84263d55307 11052 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
AnnaBridge 167:e84263d55307 11053 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11054 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
AnnaBridge 167:e84263d55307 11055 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
AnnaBridge 167:e84263d55307 11056 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11057 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
AnnaBridge 167:e84263d55307 11058 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
AnnaBridge 167:e84263d55307 11059 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11060 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
AnnaBridge 167:e84263d55307 11061 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
AnnaBridge 167:e84263d55307 11062 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11063 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
AnnaBridge 167:e84263d55307 11064 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
AnnaBridge 167:e84263d55307 11065 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11066 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
AnnaBridge 167:e84263d55307 11067 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
AnnaBridge 167:e84263d55307 11068 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11069 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
<> 144:ef7eb2e8f9f7 11070 /******************** Bit definition for RCC_AHB2ENR register ***************/
AnnaBridge 167:e84263d55307 11071 /*
AnnaBridge 167:e84263d55307 11072 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 11073 */
AnnaBridge 167:e84263d55307 11074 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
AnnaBridge 167:e84263d55307 11075
AnnaBridge 167:e84263d55307 11076 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
AnnaBridge 167:e84263d55307 11077 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11078 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
AnnaBridge 167:e84263d55307 11079 #define RCC_AHB2ENR_RNGEN_Pos (6U)
AnnaBridge 167:e84263d55307 11080 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11081 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
AnnaBridge 167:e84263d55307 11082 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
AnnaBridge 167:e84263d55307 11083 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11084 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
<> 144:ef7eb2e8f9f7 11085
<> 144:ef7eb2e8f9f7 11086 /******************** Bit definition for RCC_AHB3ENR register ***************/
AnnaBridge 167:e84263d55307 11087 /*
AnnaBridge 167:e84263d55307 11088 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 11089 */
AnnaBridge 167:e84263d55307 11090 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
AnnaBridge 167:e84263d55307 11091
AnnaBridge 167:e84263d55307 11092 #define RCC_AHB3ENR_FMCEN_Pos (0U)
AnnaBridge 167:e84263d55307 11093 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11094 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
<> 144:ef7eb2e8f9f7 11095
<> 144:ef7eb2e8f9f7 11096 /******************** Bit definition for RCC_APB1ENR register ***************/
AnnaBridge 167:e84263d55307 11097 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 167:e84263d55307 11098 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11099 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
AnnaBridge 167:e84263d55307 11100 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 167:e84263d55307 11101 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11102 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
AnnaBridge 167:e84263d55307 11103 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 167:e84263d55307 11104 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11105 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
AnnaBridge 167:e84263d55307 11106 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 167:e84263d55307 11107 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11108 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
AnnaBridge 167:e84263d55307 11109 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 167:e84263d55307 11110 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11111 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
AnnaBridge 167:e84263d55307 11112 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 167:e84263d55307 11113 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11114 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
AnnaBridge 167:e84263d55307 11115 #define RCC_APB1ENR_TIM12EN_Pos (6U)
AnnaBridge 167:e84263d55307 11116 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11117 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
AnnaBridge 167:e84263d55307 11118 #define RCC_APB1ENR_TIM13EN_Pos (7U)
AnnaBridge 167:e84263d55307 11119 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11120 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
AnnaBridge 167:e84263d55307 11121 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 167:e84263d55307 11122 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11123 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
AnnaBridge 167:e84263d55307 11124 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 167:e84263d55307 11125 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11126 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
AnnaBridge 167:e84263d55307 11127 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 167:e84263d55307 11128 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11129 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
AnnaBridge 167:e84263d55307 11130 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 167:e84263d55307 11131 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11132 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
AnnaBridge 167:e84263d55307 11133 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 167:e84263d55307 11134 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11135 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
AnnaBridge 167:e84263d55307 11136 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 167:e84263d55307 11137 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11138 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
AnnaBridge 167:e84263d55307 11139 #define RCC_APB1ENR_UART4EN_Pos (19U)
AnnaBridge 167:e84263d55307 11140 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11141 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
AnnaBridge 167:e84263d55307 11142 #define RCC_APB1ENR_UART5EN_Pos (20U)
AnnaBridge 167:e84263d55307 11143 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11144 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
AnnaBridge 167:e84263d55307 11145 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 167:e84263d55307 11146 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11147 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
AnnaBridge 167:e84263d55307 11148 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 167:e84263d55307 11149 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11150 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
AnnaBridge 167:e84263d55307 11151 #define RCC_APB1ENR_I2C3EN_Pos (23U)
AnnaBridge 167:e84263d55307 11152 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11153 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
AnnaBridge 167:e84263d55307 11154 #define RCC_APB1ENR_CAN1EN_Pos (25U)
AnnaBridge 167:e84263d55307 11155 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11156 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
AnnaBridge 167:e84263d55307 11157 #define RCC_APB1ENR_CAN2EN_Pos (26U)
AnnaBridge 167:e84263d55307 11158 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11159 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
AnnaBridge 167:e84263d55307 11160 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 167:e84263d55307 11161 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11162 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
AnnaBridge 167:e84263d55307 11163 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 167:e84263d55307 11164 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11165 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
AnnaBridge 167:e84263d55307 11166 #define RCC_APB1ENR_UART7EN_Pos (30U)
AnnaBridge 167:e84263d55307 11167 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11168 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
AnnaBridge 167:e84263d55307 11169 #define RCC_APB1ENR_UART8EN_Pos (31U)
AnnaBridge 167:e84263d55307 11170 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11171 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
<> 144:ef7eb2e8f9f7 11172
<> 144:ef7eb2e8f9f7 11173 /******************** Bit definition for RCC_APB2ENR register ***************/
AnnaBridge 167:e84263d55307 11174 #define RCC_APB2ENR_TIM1EN_Pos (0U)
AnnaBridge 167:e84263d55307 11175 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11176 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
AnnaBridge 167:e84263d55307 11177 #define RCC_APB2ENR_TIM8EN_Pos (1U)
AnnaBridge 167:e84263d55307 11178 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11179 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
AnnaBridge 167:e84263d55307 11180 #define RCC_APB2ENR_USART1EN_Pos (4U)
AnnaBridge 167:e84263d55307 11181 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11182 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
AnnaBridge 167:e84263d55307 11183 #define RCC_APB2ENR_USART6EN_Pos (5U)
AnnaBridge 167:e84263d55307 11184 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11185 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
AnnaBridge 167:e84263d55307 11186 #define RCC_APB2ENR_ADC1EN_Pos (8U)
AnnaBridge 167:e84263d55307 11187 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11188 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
AnnaBridge 167:e84263d55307 11189 #define RCC_APB2ENR_ADC2EN_Pos (9U)
AnnaBridge 167:e84263d55307 11190 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11191 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
AnnaBridge 167:e84263d55307 11192 #define RCC_APB2ENR_ADC3EN_Pos (10U)
AnnaBridge 167:e84263d55307 11193 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11194 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
AnnaBridge 167:e84263d55307 11195 #define RCC_APB2ENR_SDIOEN_Pos (11U)
AnnaBridge 167:e84263d55307 11196 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11197 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
AnnaBridge 167:e84263d55307 11198 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 167:e84263d55307 11199 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11200 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
AnnaBridge 167:e84263d55307 11201 #define RCC_APB2ENR_SPI4EN_Pos (13U)
AnnaBridge 167:e84263d55307 11202 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11203 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
AnnaBridge 167:e84263d55307 11204 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
AnnaBridge 167:e84263d55307 11205 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11206 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
AnnaBridge 167:e84263d55307 11207 #define RCC_APB2ENR_TIM9EN_Pos (16U)
AnnaBridge 167:e84263d55307 11208 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11209 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
AnnaBridge 167:e84263d55307 11210 #define RCC_APB2ENR_TIM10EN_Pos (17U)
AnnaBridge 167:e84263d55307 11211 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11212 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
AnnaBridge 167:e84263d55307 11213 #define RCC_APB2ENR_TIM11EN_Pos (18U)
AnnaBridge 167:e84263d55307 11214 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11215 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
AnnaBridge 167:e84263d55307 11216 #define RCC_APB2ENR_SPI5EN_Pos (20U)
AnnaBridge 167:e84263d55307 11217 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11218 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
AnnaBridge 167:e84263d55307 11219 #define RCC_APB2ENR_SPI6EN_Pos (21U)
AnnaBridge 167:e84263d55307 11220 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11221 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
AnnaBridge 167:e84263d55307 11222 #define RCC_APB2ENR_SAI1EN_Pos (22U)
AnnaBridge 167:e84263d55307 11223 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11224 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
AnnaBridge 167:e84263d55307 11225 #define RCC_APB2ENR_LTDCEN_Pos (26U)
AnnaBridge 167:e84263d55307 11226 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11227 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
<> 144:ef7eb2e8f9f7 11228
<> 144:ef7eb2e8f9f7 11229 /******************** Bit definition for RCC_AHB1LPENR register *************/
AnnaBridge 167:e84263d55307 11230 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
AnnaBridge 167:e84263d55307 11231 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11232 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
AnnaBridge 167:e84263d55307 11233 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 167:e84263d55307 11234 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11235 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
AnnaBridge 167:e84263d55307 11236 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 167:e84263d55307 11237 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11238 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
AnnaBridge 167:e84263d55307 11239 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
AnnaBridge 167:e84263d55307 11240 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11241 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
AnnaBridge 167:e84263d55307 11242 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
AnnaBridge 167:e84263d55307 11243 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11244 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
AnnaBridge 167:e84263d55307 11245 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
AnnaBridge 167:e84263d55307 11246 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11247 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
AnnaBridge 167:e84263d55307 11248 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
AnnaBridge 167:e84263d55307 11249 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11250 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
AnnaBridge 167:e84263d55307 11251 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
AnnaBridge 167:e84263d55307 11252 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11253 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
AnnaBridge 167:e84263d55307 11254 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
AnnaBridge 167:e84263d55307 11255 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11256 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
AnnaBridge 167:e84263d55307 11257 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
AnnaBridge 167:e84263d55307 11258 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11259 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
AnnaBridge 167:e84263d55307 11260 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
AnnaBridge 167:e84263d55307 11261 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11262 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
AnnaBridge 167:e84263d55307 11263 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
AnnaBridge 167:e84263d55307 11264 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11265 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
AnnaBridge 167:e84263d55307 11266 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
AnnaBridge 167:e84263d55307 11267 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11268 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
AnnaBridge 167:e84263d55307 11269 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
AnnaBridge 167:e84263d55307 11270 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11271 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
AnnaBridge 167:e84263d55307 11272 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
AnnaBridge 167:e84263d55307 11273 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11274 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
AnnaBridge 167:e84263d55307 11275 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
AnnaBridge 167:e84263d55307 11276 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11277 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
AnnaBridge 167:e84263d55307 11278 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
AnnaBridge 167:e84263d55307 11279 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11280 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
AnnaBridge 167:e84263d55307 11281 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
AnnaBridge 167:e84263d55307 11282 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11283 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
AnnaBridge 167:e84263d55307 11284 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
AnnaBridge 167:e84263d55307 11285 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11286 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
AnnaBridge 167:e84263d55307 11287 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
AnnaBridge 167:e84263d55307 11288 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11289 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
AnnaBridge 167:e84263d55307 11290
AnnaBridge 167:e84263d55307 11291 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
AnnaBridge 167:e84263d55307 11292 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11293 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
AnnaBridge 167:e84263d55307 11294 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
AnnaBridge 167:e84263d55307 11295 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11296 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
AnnaBridge 167:e84263d55307 11297 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
AnnaBridge 167:e84263d55307 11298 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11299 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
AnnaBridge 167:e84263d55307 11300 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
AnnaBridge 167:e84263d55307 11301 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11302 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
AnnaBridge 167:e84263d55307 11303 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
AnnaBridge 167:e84263d55307 11304 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11305 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
AnnaBridge 167:e84263d55307 11306 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
AnnaBridge 167:e84263d55307 11307 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11308 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
<> 144:ef7eb2e8f9f7 11309
<> 144:ef7eb2e8f9f7 11310 /******************** Bit definition for RCC_AHB2LPENR register *************/
AnnaBridge 167:e84263d55307 11311 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
AnnaBridge 167:e84263d55307 11312 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11313 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
AnnaBridge 167:e84263d55307 11314 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
AnnaBridge 167:e84263d55307 11315 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11316 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
AnnaBridge 167:e84263d55307 11317 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
AnnaBridge 167:e84263d55307 11318 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11319 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
<> 144:ef7eb2e8f9f7 11320
<> 144:ef7eb2e8f9f7 11321 /******************** Bit definition for RCC_AHB3LPENR register *************/
AnnaBridge 167:e84263d55307 11322 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
AnnaBridge 167:e84263d55307 11323 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11324 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
<> 144:ef7eb2e8f9f7 11325
<> 144:ef7eb2e8f9f7 11326 /******************** Bit definition for RCC_APB1LPENR register *************/
AnnaBridge 167:e84263d55307 11327 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 167:e84263d55307 11328 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11329 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
AnnaBridge 167:e84263d55307 11330 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 167:e84263d55307 11331 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11332 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
AnnaBridge 167:e84263d55307 11333 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 167:e84263d55307 11334 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11335 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
AnnaBridge 167:e84263d55307 11336 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 167:e84263d55307 11337 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11338 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
AnnaBridge 167:e84263d55307 11339 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 167:e84263d55307 11340 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11341 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
AnnaBridge 167:e84263d55307 11342 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 167:e84263d55307 11343 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11344 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
AnnaBridge 167:e84263d55307 11345 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
AnnaBridge 167:e84263d55307 11346 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11347 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
AnnaBridge 167:e84263d55307 11348 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
AnnaBridge 167:e84263d55307 11349 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11350 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
AnnaBridge 167:e84263d55307 11351 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
AnnaBridge 167:e84263d55307 11352 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11353 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
AnnaBridge 167:e84263d55307 11354 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 167:e84263d55307 11355 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11356 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
AnnaBridge 167:e84263d55307 11357 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 167:e84263d55307 11358 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11359 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
AnnaBridge 167:e84263d55307 11360 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 167:e84263d55307 11361 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11362 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
AnnaBridge 167:e84263d55307 11363 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 167:e84263d55307 11364 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11365 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
AnnaBridge 167:e84263d55307 11366 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 167:e84263d55307 11367 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11368 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
AnnaBridge 167:e84263d55307 11369 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
AnnaBridge 167:e84263d55307 11370 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11371 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
AnnaBridge 167:e84263d55307 11372 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
AnnaBridge 167:e84263d55307 11373 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11374 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
AnnaBridge 167:e84263d55307 11375 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 167:e84263d55307 11376 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11377 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
AnnaBridge 167:e84263d55307 11378 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 167:e84263d55307 11379 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11380 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
AnnaBridge 167:e84263d55307 11381 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
AnnaBridge 167:e84263d55307 11382 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11383 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
AnnaBridge 167:e84263d55307 11384 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
AnnaBridge 167:e84263d55307 11385 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11386 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
AnnaBridge 167:e84263d55307 11387 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
AnnaBridge 167:e84263d55307 11388 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11389 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
AnnaBridge 167:e84263d55307 11390 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 167:e84263d55307 11391 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11392 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
AnnaBridge 167:e84263d55307 11393 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 167:e84263d55307 11394 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11395 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
AnnaBridge 167:e84263d55307 11396 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
AnnaBridge 167:e84263d55307 11397 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11398 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
AnnaBridge 167:e84263d55307 11399 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
AnnaBridge 167:e84263d55307 11400 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11401 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
<> 144:ef7eb2e8f9f7 11402
<> 144:ef7eb2e8f9f7 11403 /******************** Bit definition for RCC_APB2LPENR register *************/
AnnaBridge 167:e84263d55307 11404 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
AnnaBridge 167:e84263d55307 11405 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11406 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
AnnaBridge 167:e84263d55307 11407 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
AnnaBridge 167:e84263d55307 11408 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11409 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
AnnaBridge 167:e84263d55307 11410 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
AnnaBridge 167:e84263d55307 11411 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11412 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
AnnaBridge 167:e84263d55307 11413 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
AnnaBridge 167:e84263d55307 11414 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11415 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
AnnaBridge 167:e84263d55307 11416 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
AnnaBridge 167:e84263d55307 11417 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11418 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
AnnaBridge 167:e84263d55307 11419 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
AnnaBridge 167:e84263d55307 11420 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11421 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
AnnaBridge 167:e84263d55307 11422 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
AnnaBridge 167:e84263d55307 11423 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11424 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
AnnaBridge 167:e84263d55307 11425 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
AnnaBridge 167:e84263d55307 11426 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11427 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
AnnaBridge 167:e84263d55307 11428 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 167:e84263d55307 11429 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11430 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
AnnaBridge 167:e84263d55307 11431 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
AnnaBridge 167:e84263d55307 11432 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11433 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
AnnaBridge 167:e84263d55307 11434 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
AnnaBridge 167:e84263d55307 11435 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11436 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
AnnaBridge 167:e84263d55307 11437 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
AnnaBridge 167:e84263d55307 11438 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11439 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
AnnaBridge 167:e84263d55307 11440 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
AnnaBridge 167:e84263d55307 11441 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11442 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
AnnaBridge 167:e84263d55307 11443 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
AnnaBridge 167:e84263d55307 11444 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11445 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
AnnaBridge 167:e84263d55307 11446 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
AnnaBridge 167:e84263d55307 11447 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11448 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
AnnaBridge 167:e84263d55307 11449 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
AnnaBridge 167:e84263d55307 11450 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11451 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
AnnaBridge 167:e84263d55307 11452 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
AnnaBridge 167:e84263d55307 11453 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11454 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
AnnaBridge 167:e84263d55307 11455 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
AnnaBridge 167:e84263d55307 11456 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11457 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
<> 144:ef7eb2e8f9f7 11458
<> 144:ef7eb2e8f9f7 11459 /******************** Bit definition for RCC_BDCR register ******************/
AnnaBridge 167:e84263d55307 11460 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 167:e84263d55307 11461 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11462 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
AnnaBridge 167:e84263d55307 11463 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 167:e84263d55307 11464 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11465 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
AnnaBridge 167:e84263d55307 11466 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 167:e84263d55307 11467 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11468 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
AnnaBridge 167:e84263d55307 11469
AnnaBridge 167:e84263d55307 11470 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 167:e84263d55307 11471 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 11472 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
AnnaBridge 167:e84263d55307 11473 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11474 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11475
AnnaBridge 167:e84263d55307 11476 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 167:e84263d55307 11477 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11478 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
AnnaBridge 167:e84263d55307 11479 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 167:e84263d55307 11480 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11481 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
<> 144:ef7eb2e8f9f7 11482
<> 144:ef7eb2e8f9f7 11483 /******************** Bit definition for RCC_CSR register *******************/
AnnaBridge 167:e84263d55307 11484 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 167:e84263d55307 11485 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11486 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
AnnaBridge 167:e84263d55307 11487 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 167:e84263d55307 11488 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11489 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
AnnaBridge 167:e84263d55307 11490 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 167:e84263d55307 11491 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11492 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
AnnaBridge 167:e84263d55307 11493 #define RCC_CSR_BORRSTF_Pos (25U)
AnnaBridge 167:e84263d55307 11494 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11495 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
AnnaBridge 167:e84263d55307 11496 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 167:e84263d55307 11497 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11498 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
AnnaBridge 167:e84263d55307 11499 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 167:e84263d55307 11500 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11501 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
AnnaBridge 167:e84263d55307 11502 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 167:e84263d55307 11503 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11504 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
AnnaBridge 167:e84263d55307 11505 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 167:e84263d55307 11506 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11507 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
AnnaBridge 167:e84263d55307 11508 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 167:e84263d55307 11509 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11510 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
AnnaBridge 167:e84263d55307 11511 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 167:e84263d55307 11512 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11513 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
AnnaBridge 167:e84263d55307 11514 /* Legacy defines */
AnnaBridge 167:e84263d55307 11515 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
AnnaBridge 167:e84263d55307 11516 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
<> 144:ef7eb2e8f9f7 11517
<> 144:ef7eb2e8f9f7 11518 /******************** Bit definition for RCC_SSCGR register *****************/
AnnaBridge 167:e84263d55307 11519 #define RCC_SSCGR_MODPER_Pos (0U)
AnnaBridge 167:e84263d55307 11520 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
AnnaBridge 167:e84263d55307 11521 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
AnnaBridge 167:e84263d55307 11522 #define RCC_SSCGR_INCSTEP_Pos (13U)
AnnaBridge 167:e84263d55307 11523 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
AnnaBridge 167:e84263d55307 11524 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
AnnaBridge 167:e84263d55307 11525 #define RCC_SSCGR_SPREADSEL_Pos (30U)
AnnaBridge 167:e84263d55307 11526 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11527 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
AnnaBridge 167:e84263d55307 11528 #define RCC_SSCGR_SSCGEN_Pos (31U)
AnnaBridge 167:e84263d55307 11529 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11530 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
<> 144:ef7eb2e8f9f7 11531
<> 144:ef7eb2e8f9f7 11532 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
AnnaBridge 167:e84263d55307 11533 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
AnnaBridge 167:e84263d55307 11534 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
AnnaBridge 167:e84263d55307 11535 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
AnnaBridge 167:e84263d55307 11536 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11537 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11538 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11539 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11540 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11541 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11542 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11543 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11544 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11545
AnnaBridge 167:e84263d55307 11546 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
AnnaBridge 167:e84263d55307 11547 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 11548 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
AnnaBridge 167:e84263d55307 11549 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11550 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11551 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11552 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11553 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
AnnaBridge 167:e84263d55307 11554 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
AnnaBridge 167:e84263d55307 11555 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
AnnaBridge 167:e84263d55307 11556 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11557 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11558 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 11559
<> 144:ef7eb2e8f9f7 11560 /******************** Bit definition for RCC_PLLSAICFGR register ************/
AnnaBridge 167:e84263d55307 11561 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
AnnaBridge 167:e84263d55307 11562 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
AnnaBridge 167:e84263d55307 11563 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
AnnaBridge 167:e84263d55307 11564 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11565 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11566 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11567 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11568 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11569 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11570 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11571 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11572 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11573
AnnaBridge 167:e84263d55307 11574
AnnaBridge 167:e84263d55307 11575 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
AnnaBridge 167:e84263d55307 11576 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 11577 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
AnnaBridge 167:e84263d55307 11578 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11579 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11580 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11581 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11582
AnnaBridge 167:e84263d55307 11583 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
AnnaBridge 167:e84263d55307 11584 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
AnnaBridge 167:e84263d55307 11585 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
AnnaBridge 167:e84263d55307 11586 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11587 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11588 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 11589
<> 144:ef7eb2e8f9f7 11590 /******************** Bit definition for RCC_DCKCFGR register ***************/
AnnaBridge 167:e84263d55307 11591 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
AnnaBridge 167:e84263d55307 11592 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 11593 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
AnnaBridge 167:e84263d55307 11594 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11595 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11596 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11597 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11598 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11599
AnnaBridge 167:e84263d55307 11600 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
AnnaBridge 167:e84263d55307 11601 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
AnnaBridge 167:e84263d55307 11602 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
AnnaBridge 167:e84263d55307 11603 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11604 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11605 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11606 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11607 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11608 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
AnnaBridge 167:e84263d55307 11609 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 11610 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
AnnaBridge 167:e84263d55307 11611 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11612 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11613
AnnaBridge 167:e84263d55307 11614 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
AnnaBridge 167:e84263d55307 11615 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 11616 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
AnnaBridge 167:e84263d55307 11617 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11618 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11619 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
AnnaBridge 167:e84263d55307 11620 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
AnnaBridge 167:e84263d55307 11621 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
AnnaBridge 167:e84263d55307 11622 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11623 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11624 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
AnnaBridge 167:e84263d55307 11625 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11626 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
<> 144:ef7eb2e8f9f7 11627
<> 144:ef7eb2e8f9f7 11628
<> 144:ef7eb2e8f9f7 11629 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11630 /* */
<> 144:ef7eb2e8f9f7 11631 /* RNG */
<> 144:ef7eb2e8f9f7 11632 /* */
<> 144:ef7eb2e8f9f7 11633 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11634 /******************** Bits definition for RNG_CR register *******************/
AnnaBridge 167:e84263d55307 11635 #define RNG_CR_RNGEN_Pos (2U)
AnnaBridge 167:e84263d55307 11636 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11637 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
AnnaBridge 167:e84263d55307 11638 #define RNG_CR_IE_Pos (3U)
AnnaBridge 167:e84263d55307 11639 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11640 #define RNG_CR_IE RNG_CR_IE_Msk
<> 144:ef7eb2e8f9f7 11641
<> 144:ef7eb2e8f9f7 11642 /******************** Bits definition for RNG_SR register *******************/
AnnaBridge 167:e84263d55307 11643 #define RNG_SR_DRDY_Pos (0U)
AnnaBridge 167:e84263d55307 11644 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11645 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
AnnaBridge 167:e84263d55307 11646 #define RNG_SR_CECS_Pos (1U)
AnnaBridge 167:e84263d55307 11647 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11648 #define RNG_SR_CECS RNG_SR_CECS_Msk
AnnaBridge 167:e84263d55307 11649 #define RNG_SR_SECS_Pos (2U)
AnnaBridge 167:e84263d55307 11650 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11651 #define RNG_SR_SECS RNG_SR_SECS_Msk
AnnaBridge 167:e84263d55307 11652 #define RNG_SR_CEIS_Pos (5U)
AnnaBridge 167:e84263d55307 11653 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11654 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
AnnaBridge 167:e84263d55307 11655 #define RNG_SR_SEIS_Pos (6U)
AnnaBridge 167:e84263d55307 11656 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11657 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
<> 144:ef7eb2e8f9f7 11658
<> 144:ef7eb2e8f9f7 11659 /******************************************************************************/
<> 144:ef7eb2e8f9f7 11660 /* */
<> 144:ef7eb2e8f9f7 11661 /* Real-Time Clock (RTC) */
<> 144:ef7eb2e8f9f7 11662 /* */
<> 144:ef7eb2e8f9f7 11663 /******************************************************************************/
AnnaBridge 167:e84263d55307 11664 /*
AnnaBridge 167:e84263d55307 11665 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
AnnaBridge 167:e84263d55307 11666 */
AnnaBridge 167:e84263d55307 11667 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 167:e84263d55307 11668 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
<> 144:ef7eb2e8f9f7 11669 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 167:e84263d55307 11670 #define RTC_TR_PM_Pos (22U)
AnnaBridge 167:e84263d55307 11671 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11672 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 167:e84263d55307 11673 #define RTC_TR_HT_Pos (20U)
AnnaBridge 167:e84263d55307 11674 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 11675 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 167:e84263d55307 11676 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11677 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11678 #define RTC_TR_HU_Pos (16U)
AnnaBridge 167:e84263d55307 11679 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 11680 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 167:e84263d55307 11681 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11682 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11683 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11684 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11685 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 167:e84263d55307 11686 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 11687 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 167:e84263d55307 11688 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11689 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11690 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11691 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 167:e84263d55307 11692 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 11693 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 167:e84263d55307 11694 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11695 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11696 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11697 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11698 #define RTC_TR_ST_Pos (4U)
AnnaBridge 167:e84263d55307 11699 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 11700 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 167:e84263d55307 11701 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11702 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11703 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11704 #define RTC_TR_SU_Pos (0U)
AnnaBridge 167:e84263d55307 11705 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 11706 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 167:e84263d55307 11707 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11708 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11709 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11710 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 11711
<> 144:ef7eb2e8f9f7 11712 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 167:e84263d55307 11713 #define RTC_DR_YT_Pos (20U)
AnnaBridge 167:e84263d55307 11714 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 11715 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 167:e84263d55307 11716 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11717 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11718 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11719 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11720 #define RTC_DR_YU_Pos (16U)
AnnaBridge 167:e84263d55307 11721 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 11722 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 167:e84263d55307 11723 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11724 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11725 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11726 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11727 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 167:e84263d55307 11728 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 167:e84263d55307 11729 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 167:e84263d55307 11730 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11731 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11732 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11733 #define RTC_DR_MT_Pos (12U)
AnnaBridge 167:e84263d55307 11734 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11735 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 167:e84263d55307 11736 #define RTC_DR_MU_Pos (8U)
AnnaBridge 167:e84263d55307 11737 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 11738 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 167:e84263d55307 11739 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11740 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11741 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11742 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11743 #define RTC_DR_DT_Pos (4U)
AnnaBridge 167:e84263d55307 11744 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 11745 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 167:e84263d55307 11746 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11747 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11748 #define RTC_DR_DU_Pos (0U)
AnnaBridge 167:e84263d55307 11749 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 11750 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 167:e84263d55307 11751 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11752 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11753 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11754 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 11755
<> 144:ef7eb2e8f9f7 11756 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 167:e84263d55307 11757 #define RTC_CR_COE_Pos (23U)
AnnaBridge 167:e84263d55307 11758 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11759 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 167:e84263d55307 11760 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 167:e84263d55307 11761 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 167:e84263d55307 11762 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 167:e84263d55307 11763 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11764 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11765 #define RTC_CR_POL_Pos (20U)
AnnaBridge 167:e84263d55307 11766 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11767 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 167:e84263d55307 11768 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 167:e84263d55307 11769 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11770 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 167:e84263d55307 11771 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 167:e84263d55307 11772 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11773 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 167:e84263d55307 11774 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 167:e84263d55307 11775 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11776 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 167:e84263d55307 11777 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 167:e84263d55307 11778 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11779 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 167:e84263d55307 11780 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 167:e84263d55307 11781 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11782 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 167:e84263d55307 11783 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 167:e84263d55307 11784 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11785 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 167:e84263d55307 11786 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 167:e84263d55307 11787 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11788 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 167:e84263d55307 11789 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 167:e84263d55307 11790 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11791 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 167:e84263d55307 11792 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 167:e84263d55307 11793 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11794 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 167:e84263d55307 11795 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 167:e84263d55307 11796 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11797 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 167:e84263d55307 11798 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 167:e84263d55307 11799 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11800 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 167:e84263d55307 11801 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 167:e84263d55307 11802 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11803 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 167:e84263d55307 11804 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 167:e84263d55307 11805 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11806 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 167:e84263d55307 11807 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 167:e84263d55307 11808 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11809 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 167:e84263d55307 11810 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 167:e84263d55307 11811 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11812 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 167:e84263d55307 11813 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 167:e84263d55307 11814 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11815 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 167:e84263d55307 11816 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 167:e84263d55307 11817 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11818 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 167:e84263d55307 11819 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 167:e84263d55307 11820 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 11821 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 167:e84263d55307 11822 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11823 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11824 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11825
AnnaBridge 167:e84263d55307 11826 /* Legacy defines */
AnnaBridge 167:e84263d55307 11827 #define RTC_CR_BCK RTC_CR_BKP
<> 144:ef7eb2e8f9f7 11828
<> 144:ef7eb2e8f9f7 11829 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 167:e84263d55307 11830 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 167:e84263d55307 11831 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11832 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 167:e84263d55307 11833 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 167:e84263d55307 11834 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11835 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 167:e84263d55307 11836 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 167:e84263d55307 11837 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11838 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 167:e84263d55307 11839 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 167:e84263d55307 11840 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11841 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 167:e84263d55307 11842 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 167:e84263d55307 11843 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11844 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 167:e84263d55307 11845 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 167:e84263d55307 11846 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11847 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 167:e84263d55307 11848 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 167:e84263d55307 11849 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11850 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 167:e84263d55307 11851 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 167:e84263d55307 11852 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11853 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 167:e84263d55307 11854 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 167:e84263d55307 11855 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11856 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 167:e84263d55307 11857 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 167:e84263d55307 11858 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11859 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 167:e84263d55307 11860 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 167:e84263d55307 11861 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11862 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 167:e84263d55307 11863 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 167:e84263d55307 11864 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11865 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 167:e84263d55307 11866 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 167:e84263d55307 11867 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 11868 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 167:e84263d55307 11869 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 167:e84263d55307 11870 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11871 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 167:e84263d55307 11872 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 167:e84263d55307 11873 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11874 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 167:e84263d55307 11875 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 167:e84263d55307 11876 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11877 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
<> 144:ef7eb2e8f9f7 11878
<> 144:ef7eb2e8f9f7 11879 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 167:e84263d55307 11880 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 167:e84263d55307 11881 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 167:e84263d55307 11882 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 167:e84263d55307 11883 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 167:e84263d55307 11884 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 167:e84263d55307 11885 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
<> 144:ef7eb2e8f9f7 11886
<> 144:ef7eb2e8f9f7 11887 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 167:e84263d55307 11888 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 167:e84263d55307 11889 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 11890 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
<> 144:ef7eb2e8f9f7 11891
<> 144:ef7eb2e8f9f7 11892 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 167:e84263d55307 11893 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 167:e84263d55307 11894 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11895 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 167:e84263d55307 11896 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 167:e84263d55307 11897 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 11898 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
<> 144:ef7eb2e8f9f7 11899
<> 144:ef7eb2e8f9f7 11900 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 167:e84263d55307 11901 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 167:e84263d55307 11902 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11903 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 167:e84263d55307 11904 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 167:e84263d55307 11905 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11906 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 167:e84263d55307 11907 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 167:e84263d55307 11908 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 11909 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 167:e84263d55307 11910 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11911 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11912 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 167:e84263d55307 11913 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 11914 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 167:e84263d55307 11915 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11916 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11917 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11918 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11919 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 167:e84263d55307 11920 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11921 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 167:e84263d55307 11922 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 167:e84263d55307 11923 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11924 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 167:e84263d55307 11925 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 167:e84263d55307 11926 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 11927 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 167:e84263d55307 11928 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11929 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 11930 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 167:e84263d55307 11931 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 11932 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 167:e84263d55307 11933 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 11934 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 11935 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 11936 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 11937 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 167:e84263d55307 11938 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 11939 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 167:e84263d55307 11940 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 167:e84263d55307 11941 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 11942 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 167:e84263d55307 11943 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 11944 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 11945 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 11946 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 167:e84263d55307 11947 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 11948 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 167:e84263d55307 11949 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 11950 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 11951 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 11952 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 11953 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 167:e84263d55307 11954 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 11955 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 167:e84263d55307 11956 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 167:e84263d55307 11957 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 11958 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 167:e84263d55307 11959 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 11960 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 11961 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 11962 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 167:e84263d55307 11963 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 11964 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 167:e84263d55307 11965 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 11966 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 11967 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 11968 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 11969
<> 144:ef7eb2e8f9f7 11970 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 167:e84263d55307 11971 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 167:e84263d55307 11972 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 11973 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 167:e84263d55307 11974 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 167:e84263d55307 11975 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 11976 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 167:e84263d55307 11977 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 167:e84263d55307 11978 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 167:e84263d55307 11979 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 167:e84263d55307 11980 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 11981 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 11982 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 167:e84263d55307 11983 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 11984 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 167:e84263d55307 11985 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 11986 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 11987 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 11988 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 11989 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 167:e84263d55307 11990 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 11991 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 167:e84263d55307 11992 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 167:e84263d55307 11993 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 11994 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 167:e84263d55307 11995 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 167:e84263d55307 11996 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 11997 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 167:e84263d55307 11998 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 11999 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 12000 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 167:e84263d55307 12001 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 12002 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 167:e84263d55307 12003 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12004 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12005 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12006 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 12007 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 167:e84263d55307 12008 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12009 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 167:e84263d55307 12010 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 167:e84263d55307 12011 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 12012 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 167:e84263d55307 12013 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12014 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12015 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12016 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 167:e84263d55307 12017 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 12018 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 167:e84263d55307 12019 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12020 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12021 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12022 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12023 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 167:e84263d55307 12024 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12025 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 167:e84263d55307 12026 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 167:e84263d55307 12027 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 12028 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 167:e84263d55307 12029 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12030 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12031 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12032 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 167:e84263d55307 12033 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 12034 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 167:e84263d55307 12035 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12036 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12037 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12038 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12039
<> 144:ef7eb2e8f9f7 12040 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 167:e84263d55307 12041 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 167:e84263d55307 12042 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 12043 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
<> 144:ef7eb2e8f9f7 12044
<> 144:ef7eb2e8f9f7 12045 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 167:e84263d55307 12046 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 167:e84263d55307 12047 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 12048 #define RTC_SSR_SS RTC_SSR_SS_Msk
<> 144:ef7eb2e8f9f7 12049
<> 144:ef7eb2e8f9f7 12050 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 167:e84263d55307 12051 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 167:e84263d55307 12052 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 167:e84263d55307 12053 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 167:e84263d55307 12054 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 167:e84263d55307 12055 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 12056 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
<> 144:ef7eb2e8f9f7 12057
<> 144:ef7eb2e8f9f7 12058 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 167:e84263d55307 12059 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 167:e84263d55307 12060 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 12061 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 167:e84263d55307 12062 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 167:e84263d55307 12063 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 12064 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 167:e84263d55307 12065 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 12066 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 12067 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 167:e84263d55307 12068 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 167:e84263d55307 12069 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 167:e84263d55307 12070 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12071 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12072 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12073 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 12074 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 167:e84263d55307 12075 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 12076 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 167:e84263d55307 12077 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12078 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12079 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12080 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 167:e84263d55307 12081 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 12082 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 167:e84263d55307 12083 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12084 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12085 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12086 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12087 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 167:e84263d55307 12088 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 12089 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 167:e84263d55307 12090 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12091 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12092 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12093 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 167:e84263d55307 12094 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 12095 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 167:e84263d55307 12096 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12097 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12098 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12099 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12100
<> 144:ef7eb2e8f9f7 12101 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 167:e84263d55307 12102 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 167:e84263d55307 12103 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 167:e84263d55307 12104 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 167:e84263d55307 12105 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12106 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12107 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12108 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 167:e84263d55307 12109 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12110 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 167:e84263d55307 12111 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 167:e84263d55307 12112 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 12113 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 167:e84263d55307 12114 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12115 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12116 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12117 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12118 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 167:e84263d55307 12119 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 12120 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 167:e84263d55307 12121 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12122 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12123 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 167:e84263d55307 12124 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 12125 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 167:e84263d55307 12126 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12127 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12128 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12129 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
<> 144:ef7eb2e8f9f7 12130
<> 144:ef7eb2e8f9f7 12131 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 167:e84263d55307 12132 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 167:e84263d55307 12133 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 12134 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
<> 144:ef7eb2e8f9f7 12135
<> 144:ef7eb2e8f9f7 12136 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 167:e84263d55307 12137 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 167:e84263d55307 12138 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12139 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 167:e84263d55307 12140 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 167:e84263d55307 12141 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12142 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 167:e84263d55307 12143 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 167:e84263d55307 12144 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12145 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 167:e84263d55307 12146 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 167:e84263d55307 12147 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 167:e84263d55307 12148 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 167:e84263d55307 12149 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12150 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12151 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12152 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12153 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12154 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12155 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12156 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12157 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
<> 144:ef7eb2e8f9f7 12158
<> 144:ef7eb2e8f9f7 12159 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 167:e84263d55307 12160 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 167:e84263d55307 12161 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12162 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 167:e84263d55307 12163 #define RTC_TAFCR_TSINSEL_Pos (17U)
AnnaBridge 167:e84263d55307 12164 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12165 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
AnnaBridge 167:e84263d55307 12166 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
AnnaBridge 167:e84263d55307 12167 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12168 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
AnnaBridge 167:e84263d55307 12169 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 167:e84263d55307 12170 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12171 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 167:e84263d55307 12172 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 167:e84263d55307 12173 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 167:e84263d55307 12174 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 167:e84263d55307 12175 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12176 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12177 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 167:e84263d55307 12178 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 167:e84263d55307 12179 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 167:e84263d55307 12180 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12181 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12182 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 167:e84263d55307 12183 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 167:e84263d55307 12184 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 167:e84263d55307 12185 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12186 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12187 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12188 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 167:e84263d55307 12189 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12190 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 167:e84263d55307 12191 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 167:e84263d55307 12192 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12193 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 167:e84263d55307 12194 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 167:e84263d55307 12195 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12196 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 167:e84263d55307 12197 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 167:e84263d55307 12198 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12199 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 167:e84263d55307 12200 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 167:e84263d55307 12201 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12202 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 167:e84263d55307 12203 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 167:e84263d55307 12204 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12205 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 167:e84263d55307 12206
AnnaBridge 167:e84263d55307 12207 /* Legacy defines */
AnnaBridge 167:e84263d55307 12208 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
<> 144:ef7eb2e8f9f7 12209
<> 144:ef7eb2e8f9f7 12210 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 167:e84263d55307 12211 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 167:e84263d55307 12212 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 12213 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 167:e84263d55307 12214 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 12215 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 12216 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 12217 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 12218 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 167:e84263d55307 12219 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 167:e84263d55307 12220 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
<> 144:ef7eb2e8f9f7 12221
<> 144:ef7eb2e8f9f7 12222 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 167:e84263d55307 12223 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 167:e84263d55307 12224 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 167:e84263d55307 12225 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 167:e84263d55307 12226 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 12227 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 12228 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 12229 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 12230 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 167:e84263d55307 12231 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 167:e84263d55307 12232 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
<> 144:ef7eb2e8f9f7 12233
<> 144:ef7eb2e8f9f7 12234 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 167:e84263d55307 12235 #define RTC_BKP0R_Pos (0U)
AnnaBridge 167:e84263d55307 12236 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12237 #define RTC_BKP0R RTC_BKP0R_Msk
<> 144:ef7eb2e8f9f7 12238
<> 144:ef7eb2e8f9f7 12239 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 167:e84263d55307 12240 #define RTC_BKP1R_Pos (0U)
AnnaBridge 167:e84263d55307 12241 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12242 #define RTC_BKP1R RTC_BKP1R_Msk
<> 144:ef7eb2e8f9f7 12243
<> 144:ef7eb2e8f9f7 12244 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 167:e84263d55307 12245 #define RTC_BKP2R_Pos (0U)
AnnaBridge 167:e84263d55307 12246 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12247 #define RTC_BKP2R RTC_BKP2R_Msk
<> 144:ef7eb2e8f9f7 12248
<> 144:ef7eb2e8f9f7 12249 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 167:e84263d55307 12250 #define RTC_BKP3R_Pos (0U)
AnnaBridge 167:e84263d55307 12251 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12252 #define RTC_BKP3R RTC_BKP3R_Msk
<> 144:ef7eb2e8f9f7 12253
<> 144:ef7eb2e8f9f7 12254 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 167:e84263d55307 12255 #define RTC_BKP4R_Pos (0U)
AnnaBridge 167:e84263d55307 12256 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12257 #define RTC_BKP4R RTC_BKP4R_Msk
<> 144:ef7eb2e8f9f7 12258
<> 144:ef7eb2e8f9f7 12259 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 167:e84263d55307 12260 #define RTC_BKP5R_Pos (0U)
AnnaBridge 167:e84263d55307 12261 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12262 #define RTC_BKP5R RTC_BKP5R_Msk
<> 144:ef7eb2e8f9f7 12263
<> 144:ef7eb2e8f9f7 12264 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 167:e84263d55307 12265 #define RTC_BKP6R_Pos (0U)
AnnaBridge 167:e84263d55307 12266 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12267 #define RTC_BKP6R RTC_BKP6R_Msk
<> 144:ef7eb2e8f9f7 12268
<> 144:ef7eb2e8f9f7 12269 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 167:e84263d55307 12270 #define RTC_BKP7R_Pos (0U)
AnnaBridge 167:e84263d55307 12271 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12272 #define RTC_BKP7R RTC_BKP7R_Msk
<> 144:ef7eb2e8f9f7 12273
<> 144:ef7eb2e8f9f7 12274 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 167:e84263d55307 12275 #define RTC_BKP8R_Pos (0U)
AnnaBridge 167:e84263d55307 12276 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12277 #define RTC_BKP8R RTC_BKP8R_Msk
<> 144:ef7eb2e8f9f7 12278
<> 144:ef7eb2e8f9f7 12279 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 167:e84263d55307 12280 #define RTC_BKP9R_Pos (0U)
AnnaBridge 167:e84263d55307 12281 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12282 #define RTC_BKP9R RTC_BKP9R_Msk
<> 144:ef7eb2e8f9f7 12283
<> 144:ef7eb2e8f9f7 12284 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 167:e84263d55307 12285 #define RTC_BKP10R_Pos (0U)
AnnaBridge 167:e84263d55307 12286 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12287 #define RTC_BKP10R RTC_BKP10R_Msk
<> 144:ef7eb2e8f9f7 12288
<> 144:ef7eb2e8f9f7 12289 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 167:e84263d55307 12290 #define RTC_BKP11R_Pos (0U)
AnnaBridge 167:e84263d55307 12291 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12292 #define RTC_BKP11R RTC_BKP11R_Msk
<> 144:ef7eb2e8f9f7 12293
<> 144:ef7eb2e8f9f7 12294 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 167:e84263d55307 12295 #define RTC_BKP12R_Pos (0U)
AnnaBridge 167:e84263d55307 12296 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12297 #define RTC_BKP12R RTC_BKP12R_Msk
<> 144:ef7eb2e8f9f7 12298
<> 144:ef7eb2e8f9f7 12299 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 167:e84263d55307 12300 #define RTC_BKP13R_Pos (0U)
AnnaBridge 167:e84263d55307 12301 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12302 #define RTC_BKP13R RTC_BKP13R_Msk
<> 144:ef7eb2e8f9f7 12303
<> 144:ef7eb2e8f9f7 12304 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 167:e84263d55307 12305 #define RTC_BKP14R_Pos (0U)
AnnaBridge 167:e84263d55307 12306 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12307 #define RTC_BKP14R RTC_BKP14R_Msk
<> 144:ef7eb2e8f9f7 12308
<> 144:ef7eb2e8f9f7 12309 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 167:e84263d55307 12310 #define RTC_BKP15R_Pos (0U)
AnnaBridge 167:e84263d55307 12311 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12312 #define RTC_BKP15R RTC_BKP15R_Msk
<> 144:ef7eb2e8f9f7 12313
<> 144:ef7eb2e8f9f7 12314 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 167:e84263d55307 12315 #define RTC_BKP16R_Pos (0U)
AnnaBridge 167:e84263d55307 12316 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12317 #define RTC_BKP16R RTC_BKP16R_Msk
<> 144:ef7eb2e8f9f7 12318
<> 144:ef7eb2e8f9f7 12319 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 167:e84263d55307 12320 #define RTC_BKP17R_Pos (0U)
AnnaBridge 167:e84263d55307 12321 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12322 #define RTC_BKP17R RTC_BKP17R_Msk
<> 144:ef7eb2e8f9f7 12323
<> 144:ef7eb2e8f9f7 12324 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 167:e84263d55307 12325 #define RTC_BKP18R_Pos (0U)
AnnaBridge 167:e84263d55307 12326 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12327 #define RTC_BKP18R RTC_BKP18R_Msk
<> 144:ef7eb2e8f9f7 12328
<> 144:ef7eb2e8f9f7 12329 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 167:e84263d55307 12330 #define RTC_BKP19R_Pos (0U)
AnnaBridge 167:e84263d55307 12331 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12332 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 167:e84263d55307 12333
AnnaBridge 167:e84263d55307 12334 /******************** Number of backup registers ******************************/
AnnaBridge 167:e84263d55307 12335 #define RTC_BKP_NUMBER 0x000000014U
AnnaBridge 167:e84263d55307 12336
<> 144:ef7eb2e8f9f7 12337 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12338 /* */
<> 144:ef7eb2e8f9f7 12339 /* Serial Audio Interface */
<> 144:ef7eb2e8f9f7 12340 /* */
<> 144:ef7eb2e8f9f7 12341 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12342 /******************** Bit definition for SAI_GCR register *******************/
AnnaBridge 167:e84263d55307 12343 #define SAI_GCR_SYNCIN_Pos (0U)
AnnaBridge 167:e84263d55307 12344 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 12345 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
AnnaBridge 167:e84263d55307 12346 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12347 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12348
AnnaBridge 167:e84263d55307 12349 #define SAI_GCR_SYNCOUT_Pos (4U)
AnnaBridge 167:e84263d55307 12350 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 12351 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
AnnaBridge 167:e84263d55307 12352 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12353 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
<> 144:ef7eb2e8f9f7 12354
<> 144:ef7eb2e8f9f7 12355 /******************* Bit definition for SAI_xCR1 register *******************/
AnnaBridge 167:e84263d55307 12356 #define SAI_xCR1_MODE_Pos (0U)
AnnaBridge 167:e84263d55307 12357 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 12358 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
AnnaBridge 167:e84263d55307 12359 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12360 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12361
AnnaBridge 167:e84263d55307 12362 #define SAI_xCR1_PRTCFG_Pos (2U)
AnnaBridge 167:e84263d55307 12363 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 12364 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
AnnaBridge 167:e84263d55307 12365 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12366 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12367
AnnaBridge 167:e84263d55307 12368 #define SAI_xCR1_DS_Pos (5U)
AnnaBridge 167:e84263d55307 12369 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
AnnaBridge 167:e84263d55307 12370 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
AnnaBridge 167:e84263d55307 12371 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12372 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12373 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12374
AnnaBridge 167:e84263d55307 12375 #define SAI_xCR1_LSBFIRST_Pos (8U)
AnnaBridge 167:e84263d55307 12376 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12377 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
AnnaBridge 167:e84263d55307 12378 #define SAI_xCR1_CKSTR_Pos (9U)
AnnaBridge 167:e84263d55307 12379 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12380 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
AnnaBridge 167:e84263d55307 12381
AnnaBridge 167:e84263d55307 12382 #define SAI_xCR1_SYNCEN_Pos (10U)
AnnaBridge 167:e84263d55307 12383 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 12384 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
AnnaBridge 167:e84263d55307 12385 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12386 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12387
AnnaBridge 167:e84263d55307 12388 #define SAI_xCR1_MONO_Pos (12U)
AnnaBridge 167:e84263d55307 12389 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12390 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
AnnaBridge 167:e84263d55307 12391 #define SAI_xCR1_OUTDRIV_Pos (13U)
AnnaBridge 167:e84263d55307 12392 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12393 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
AnnaBridge 167:e84263d55307 12394 #define SAI_xCR1_SAIEN_Pos (16U)
AnnaBridge 167:e84263d55307 12395 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12396 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
AnnaBridge 167:e84263d55307 12397 #define SAI_xCR1_DMAEN_Pos (17U)
AnnaBridge 167:e84263d55307 12398 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12399 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
AnnaBridge 167:e84263d55307 12400 #define SAI_xCR1_NODIV_Pos (19U)
AnnaBridge 167:e84263d55307 12401 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 12402 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
AnnaBridge 167:e84263d55307 12403
AnnaBridge 167:e84263d55307 12404 #define SAI_xCR1_MCKDIV_Pos (20U)
AnnaBridge 167:e84263d55307 12405 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
AnnaBridge 167:e84263d55307 12406 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
AnnaBridge 167:e84263d55307 12407 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 12408 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 12409 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 12410 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
<> 144:ef7eb2e8f9f7 12411
<> 144:ef7eb2e8f9f7 12412 /******************* Bit definition for SAI_xCR2 register *******************/
AnnaBridge 167:e84263d55307 12413 #define SAI_xCR2_FTH_Pos (0U)
AnnaBridge 167:e84263d55307 12414 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 12415 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
AnnaBridge 167:e84263d55307 12416 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12417 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12418 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12419
AnnaBridge 167:e84263d55307 12420 #define SAI_xCR2_FFLUSH_Pos (3U)
AnnaBridge 167:e84263d55307 12421 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12422 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
AnnaBridge 167:e84263d55307 12423 #define SAI_xCR2_TRIS_Pos (4U)
AnnaBridge 167:e84263d55307 12424 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12425 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
AnnaBridge 167:e84263d55307 12426 #define SAI_xCR2_MUTE_Pos (5U)
AnnaBridge 167:e84263d55307 12427 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12428 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
AnnaBridge 167:e84263d55307 12429 #define SAI_xCR2_MUTEVAL_Pos (6U)
AnnaBridge 167:e84263d55307 12430 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12431 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
AnnaBridge 167:e84263d55307 12432
AnnaBridge 167:e84263d55307 12433 #define SAI_xCR2_MUTECNT_Pos (7U)
AnnaBridge 167:e84263d55307 12434 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
AnnaBridge 167:e84263d55307 12435 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
AnnaBridge 167:e84263d55307 12436 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12437 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12438 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12439 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12440 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12441 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12442
AnnaBridge 167:e84263d55307 12443 #define SAI_xCR2_CPL_Pos (13U)
AnnaBridge 167:e84263d55307 12444 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12445 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
AnnaBridge 167:e84263d55307 12446
AnnaBridge 167:e84263d55307 12447 #define SAI_xCR2_COMP_Pos (14U)
AnnaBridge 167:e84263d55307 12448 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 12449 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
AnnaBridge 167:e84263d55307 12450 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12451 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
<> 144:ef7eb2e8f9f7 12452
<> 144:ef7eb2e8f9f7 12453 /****************** Bit definition for SAI_xFRCR register *******************/
AnnaBridge 167:e84263d55307 12454 #define SAI_xFRCR_FRL_Pos (0U)
AnnaBridge 167:e84263d55307 12455 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 12456 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
AnnaBridge 167:e84263d55307 12457 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12458 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12459 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12460 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12461 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12462 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12463 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12464 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12465
AnnaBridge 167:e84263d55307 12466 #define SAI_xFRCR_FSALL_Pos (8U)
AnnaBridge 167:e84263d55307 12467 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
AnnaBridge 167:e84263d55307 12468 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
AnnaBridge 167:e84263d55307 12469 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12470 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12471 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12472 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12473 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12474 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12475 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12476
AnnaBridge 167:e84263d55307 12477 #define SAI_xFRCR_FSDEF_Pos (16U)
AnnaBridge 167:e84263d55307 12478 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12479 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
AnnaBridge 167:e84263d55307 12480 #define SAI_xFRCR_FSPOL_Pos (17U)
AnnaBridge 167:e84263d55307 12481 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12482 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
AnnaBridge 167:e84263d55307 12483 #define SAI_xFRCR_FSOFF_Pos (18U)
AnnaBridge 167:e84263d55307 12484 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12485 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
<> 144:ef7eb2e8f9f7 12486 /* Legacy defines */
<> 144:ef7eb2e8f9f7 12487 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
<> 144:ef7eb2e8f9f7 12488
<> 144:ef7eb2e8f9f7 12489 /****************** Bit definition for SAI_xSLOTR register *******************/
AnnaBridge 167:e84263d55307 12490 #define SAI_xSLOTR_FBOFF_Pos (0U)
AnnaBridge 167:e84263d55307 12491 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 12492 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
AnnaBridge 167:e84263d55307 12493 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12494 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12495 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12496 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12497 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12498
AnnaBridge 167:e84263d55307 12499 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
AnnaBridge 167:e84263d55307 12500 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 12501 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
AnnaBridge 167:e84263d55307 12502 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12503 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12504
AnnaBridge 167:e84263d55307 12505 #define SAI_xSLOTR_NBSLOT_Pos (8U)
AnnaBridge 167:e84263d55307 12506 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 12507 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
AnnaBridge 167:e84263d55307 12508 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12509 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12510 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12511 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12512
AnnaBridge 167:e84263d55307 12513 #define SAI_xSLOTR_SLOTEN_Pos (16U)
AnnaBridge 167:e84263d55307 12514 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 12515 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
<> 144:ef7eb2e8f9f7 12516
<> 144:ef7eb2e8f9f7 12517 /******************* Bit definition for SAI_xIMR register *******************/
AnnaBridge 167:e84263d55307 12518 #define SAI_xIMR_OVRUDRIE_Pos (0U)
AnnaBridge 167:e84263d55307 12519 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12520 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
AnnaBridge 167:e84263d55307 12521 #define SAI_xIMR_MUTEDETIE_Pos (1U)
AnnaBridge 167:e84263d55307 12522 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12523 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
AnnaBridge 167:e84263d55307 12524 #define SAI_xIMR_WCKCFGIE_Pos (2U)
AnnaBridge 167:e84263d55307 12525 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12526 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
AnnaBridge 167:e84263d55307 12527 #define SAI_xIMR_FREQIE_Pos (3U)
AnnaBridge 167:e84263d55307 12528 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12529 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
AnnaBridge 167:e84263d55307 12530 #define SAI_xIMR_CNRDYIE_Pos (4U)
AnnaBridge 167:e84263d55307 12531 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12532 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
AnnaBridge 167:e84263d55307 12533 #define SAI_xIMR_AFSDETIE_Pos (5U)
AnnaBridge 167:e84263d55307 12534 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12535 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
AnnaBridge 167:e84263d55307 12536 #define SAI_xIMR_LFSDETIE_Pos (6U)
AnnaBridge 167:e84263d55307 12537 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12538 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
<> 144:ef7eb2e8f9f7 12539
<> 144:ef7eb2e8f9f7 12540 /******************** Bit definition for SAI_xSR register *******************/
AnnaBridge 167:e84263d55307 12541 #define SAI_xSR_OVRUDR_Pos (0U)
AnnaBridge 167:e84263d55307 12542 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12543 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
AnnaBridge 167:e84263d55307 12544 #define SAI_xSR_MUTEDET_Pos (1U)
AnnaBridge 167:e84263d55307 12545 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12546 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
AnnaBridge 167:e84263d55307 12547 #define SAI_xSR_WCKCFG_Pos (2U)
AnnaBridge 167:e84263d55307 12548 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12549 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
AnnaBridge 167:e84263d55307 12550 #define SAI_xSR_FREQ_Pos (3U)
AnnaBridge 167:e84263d55307 12551 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12552 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
AnnaBridge 167:e84263d55307 12553 #define SAI_xSR_CNRDY_Pos (4U)
AnnaBridge 167:e84263d55307 12554 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12555 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
AnnaBridge 167:e84263d55307 12556 #define SAI_xSR_AFSDET_Pos (5U)
AnnaBridge 167:e84263d55307 12557 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12558 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
AnnaBridge 167:e84263d55307 12559 #define SAI_xSR_LFSDET_Pos (6U)
AnnaBridge 167:e84263d55307 12560 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12561 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
AnnaBridge 167:e84263d55307 12562
AnnaBridge 167:e84263d55307 12563 #define SAI_xSR_FLVL_Pos (16U)
AnnaBridge 167:e84263d55307 12564 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 12565 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
AnnaBridge 167:e84263d55307 12566 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12567 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12568 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
<> 144:ef7eb2e8f9f7 12569
<> 144:ef7eb2e8f9f7 12570 /****************** Bit definition for SAI_xCLRFR register ******************/
AnnaBridge 167:e84263d55307 12571 #define SAI_xCLRFR_COVRUDR_Pos (0U)
AnnaBridge 167:e84263d55307 12572 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12573 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
AnnaBridge 167:e84263d55307 12574 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
AnnaBridge 167:e84263d55307 12575 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12576 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
AnnaBridge 167:e84263d55307 12577 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
AnnaBridge 167:e84263d55307 12578 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12579 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
AnnaBridge 167:e84263d55307 12580 #define SAI_xCLRFR_CFREQ_Pos (3U)
AnnaBridge 167:e84263d55307 12581 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12582 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
AnnaBridge 167:e84263d55307 12583 #define SAI_xCLRFR_CCNRDY_Pos (4U)
AnnaBridge 167:e84263d55307 12584 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12585 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
AnnaBridge 167:e84263d55307 12586 #define SAI_xCLRFR_CAFSDET_Pos (5U)
AnnaBridge 167:e84263d55307 12587 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12588 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
AnnaBridge 167:e84263d55307 12589 #define SAI_xCLRFR_CLFSDET_Pos (6U)
AnnaBridge 167:e84263d55307 12590 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12591 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
<> 144:ef7eb2e8f9f7 12592
<> 144:ef7eb2e8f9f7 12593 /****************** Bit definition for SAI_xDR register ******************/
AnnaBridge 167:e84263d55307 12594 #define SAI_xDR_DATA_Pos (0U)
AnnaBridge 167:e84263d55307 12595 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12596 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
<> 144:ef7eb2e8f9f7 12597
<> 144:ef7eb2e8f9f7 12598
<> 144:ef7eb2e8f9f7 12599 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12600 /* */
<> 144:ef7eb2e8f9f7 12601 /* SD host Interface */
<> 144:ef7eb2e8f9f7 12602 /* */
<> 144:ef7eb2e8f9f7 12603 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12604 /****************** Bit definition for SDIO_POWER register ******************/
AnnaBridge 167:e84263d55307 12605 #define SDIO_POWER_PWRCTRL_Pos (0U)
AnnaBridge 167:e84263d55307 12606 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 12607 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
AnnaBridge 167:e84263d55307 12608 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
AnnaBridge 167:e84263d55307 12609 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
<> 144:ef7eb2e8f9f7 12610
<> 144:ef7eb2e8f9f7 12611 /****************** Bit definition for SDIO_CLKCR register ******************/
AnnaBridge 167:e84263d55307 12612 #define SDIO_CLKCR_CLKDIV_Pos (0U)
AnnaBridge 167:e84263d55307 12613 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 12614 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
AnnaBridge 167:e84263d55307 12615 #define SDIO_CLKCR_CLKEN_Pos (8U)
AnnaBridge 167:e84263d55307 12616 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12617 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
AnnaBridge 167:e84263d55307 12618 #define SDIO_CLKCR_PWRSAV_Pos (9U)
AnnaBridge 167:e84263d55307 12619 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12620 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
AnnaBridge 167:e84263d55307 12621 #define SDIO_CLKCR_BYPASS_Pos (10U)
AnnaBridge 167:e84263d55307 12622 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12623 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
AnnaBridge 167:e84263d55307 12624
AnnaBridge 167:e84263d55307 12625 #define SDIO_CLKCR_WIDBUS_Pos (11U)
AnnaBridge 167:e84263d55307 12626 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
AnnaBridge 167:e84263d55307 12627 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
AnnaBridge 167:e84263d55307 12628 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
AnnaBridge 167:e84263d55307 12629 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 12630
AnnaBridge 167:e84263d55307 12631 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
AnnaBridge 167:e84263d55307 12632 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12633 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
AnnaBridge 167:e84263d55307 12634 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
AnnaBridge 167:e84263d55307 12635 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12636 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
<> 144:ef7eb2e8f9f7 12637
<> 144:ef7eb2e8f9f7 12638 /******************* Bit definition for SDIO_ARG register *******************/
AnnaBridge 167:e84263d55307 12639 #define SDIO_ARG_CMDARG_Pos (0U)
AnnaBridge 167:e84263d55307 12640 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12641 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
<> 144:ef7eb2e8f9f7 12642
<> 144:ef7eb2e8f9f7 12643 /******************* Bit definition for SDIO_CMD register *******************/
AnnaBridge 167:e84263d55307 12644 #define SDIO_CMD_CMDINDEX_Pos (0U)
AnnaBridge 167:e84263d55307 12645 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
AnnaBridge 167:e84263d55307 12646 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
AnnaBridge 167:e84263d55307 12647
AnnaBridge 167:e84263d55307 12648 #define SDIO_CMD_WAITRESP_Pos (6U)
AnnaBridge 167:e84263d55307 12649 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 12650 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
AnnaBridge 167:e84263d55307 12651 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 12652 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 12653
AnnaBridge 167:e84263d55307 12654 #define SDIO_CMD_WAITINT_Pos (8U)
AnnaBridge 167:e84263d55307 12655 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12656 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
AnnaBridge 167:e84263d55307 12657 #define SDIO_CMD_WAITPEND_Pos (9U)
AnnaBridge 167:e84263d55307 12658 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12659 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
AnnaBridge 167:e84263d55307 12660 #define SDIO_CMD_CPSMEN_Pos (10U)
AnnaBridge 167:e84263d55307 12661 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12662 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
AnnaBridge 167:e84263d55307 12663 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
AnnaBridge 167:e84263d55307 12664 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12665 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
AnnaBridge 167:e84263d55307 12666 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
AnnaBridge 167:e84263d55307 12667 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12668 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!<Enable CMD completion */
AnnaBridge 167:e84263d55307 12669 #define SDIO_CMD_NIEN_Pos (13U)
AnnaBridge 167:e84263d55307 12670 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12671 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!<Not Interrupt Enable */
AnnaBridge 167:e84263d55307 12672 #define SDIO_CMD_CEATACMD_Pos (14U)
AnnaBridge 167:e84263d55307 12673 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12674 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!<CE-ATA command */
<> 144:ef7eb2e8f9f7 12675
<> 144:ef7eb2e8f9f7 12676 /***************** Bit definition for SDIO_RESPCMD register *****************/
AnnaBridge 167:e84263d55307 12677 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
AnnaBridge 167:e84263d55307 12678 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
AnnaBridge 167:e84263d55307 12679 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
<> 144:ef7eb2e8f9f7 12680
<> 144:ef7eb2e8f9f7 12681 /****************** Bit definition for SDIO_RESP0 register ******************/
AnnaBridge 167:e84263d55307 12682 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
AnnaBridge 167:e84263d55307 12683 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12684 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 12685
<> 144:ef7eb2e8f9f7 12686 /****************** Bit definition for SDIO_RESP1 register ******************/
AnnaBridge 167:e84263d55307 12687 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
AnnaBridge 167:e84263d55307 12688 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12689 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 12690
<> 144:ef7eb2e8f9f7 12691 /****************** Bit definition for SDIO_RESP2 register ******************/
AnnaBridge 167:e84263d55307 12692 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
AnnaBridge 167:e84263d55307 12693 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12694 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 12695
<> 144:ef7eb2e8f9f7 12696 /****************** Bit definition for SDIO_RESP3 register ******************/
AnnaBridge 167:e84263d55307 12697 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
AnnaBridge 167:e84263d55307 12698 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12699 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 12700
<> 144:ef7eb2e8f9f7 12701 /****************** Bit definition for SDIO_RESP4 register ******************/
AnnaBridge 167:e84263d55307 12702 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
AnnaBridge 167:e84263d55307 12703 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12704 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
<> 144:ef7eb2e8f9f7 12705
<> 144:ef7eb2e8f9f7 12706 /****************** Bit definition for SDIO_DTIMER register *****************/
AnnaBridge 167:e84263d55307 12707 #define SDIO_DTIMER_DATATIME_Pos (0U)
AnnaBridge 167:e84263d55307 12708 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12709 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
<> 144:ef7eb2e8f9f7 12710
<> 144:ef7eb2e8f9f7 12711 /****************** Bit definition for SDIO_DLEN register *******************/
AnnaBridge 167:e84263d55307 12712 #define SDIO_DLEN_DATALENGTH_Pos (0U)
AnnaBridge 167:e84263d55307 12713 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
AnnaBridge 167:e84263d55307 12714 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
<> 144:ef7eb2e8f9f7 12715
<> 144:ef7eb2e8f9f7 12716 /****************** Bit definition for SDIO_DCTRL register ******************/
AnnaBridge 167:e84263d55307 12717 #define SDIO_DCTRL_DTEN_Pos (0U)
AnnaBridge 167:e84263d55307 12718 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12719 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
AnnaBridge 167:e84263d55307 12720 #define SDIO_DCTRL_DTDIR_Pos (1U)
AnnaBridge 167:e84263d55307 12721 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12722 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
AnnaBridge 167:e84263d55307 12723 #define SDIO_DCTRL_DTMODE_Pos (2U)
AnnaBridge 167:e84263d55307 12724 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12725 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
AnnaBridge 167:e84263d55307 12726 #define SDIO_DCTRL_DMAEN_Pos (3U)
AnnaBridge 167:e84263d55307 12727 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12728 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
AnnaBridge 167:e84263d55307 12729
AnnaBridge 167:e84263d55307 12730 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
AnnaBridge 167:e84263d55307 12731 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 12732 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
AnnaBridge 167:e84263d55307 12733 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 12734 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 12735 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 12736 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 12737
AnnaBridge 167:e84263d55307 12738 #define SDIO_DCTRL_RWSTART_Pos (8U)
AnnaBridge 167:e84263d55307 12739 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12740 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
AnnaBridge 167:e84263d55307 12741 #define SDIO_DCTRL_RWSTOP_Pos (9U)
AnnaBridge 167:e84263d55307 12742 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12743 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
AnnaBridge 167:e84263d55307 12744 #define SDIO_DCTRL_RWMOD_Pos (10U)
AnnaBridge 167:e84263d55307 12745 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12746 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
AnnaBridge 167:e84263d55307 12747 #define SDIO_DCTRL_SDIOEN_Pos (11U)
AnnaBridge 167:e84263d55307 12748 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12749 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
<> 144:ef7eb2e8f9f7 12750
<> 144:ef7eb2e8f9f7 12751 /****************** Bit definition for SDIO_DCOUNT register *****************/
AnnaBridge 167:e84263d55307 12752 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
AnnaBridge 167:e84263d55307 12753 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
AnnaBridge 167:e84263d55307 12754 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
<> 144:ef7eb2e8f9f7 12755
<> 144:ef7eb2e8f9f7 12756 /****************** Bit definition for SDIO_STA register ********************/
AnnaBridge 167:e84263d55307 12757 #define SDIO_STA_CCRCFAIL_Pos (0U)
AnnaBridge 167:e84263d55307 12758 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12759 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
AnnaBridge 167:e84263d55307 12760 #define SDIO_STA_DCRCFAIL_Pos (1U)
AnnaBridge 167:e84263d55307 12761 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12762 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
AnnaBridge 167:e84263d55307 12763 #define SDIO_STA_CTIMEOUT_Pos (2U)
AnnaBridge 167:e84263d55307 12764 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12765 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
AnnaBridge 167:e84263d55307 12766 #define SDIO_STA_DTIMEOUT_Pos (3U)
AnnaBridge 167:e84263d55307 12767 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12768 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
AnnaBridge 167:e84263d55307 12769 #define SDIO_STA_TXUNDERR_Pos (4U)
AnnaBridge 167:e84263d55307 12770 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12771 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
AnnaBridge 167:e84263d55307 12772 #define SDIO_STA_RXOVERR_Pos (5U)
AnnaBridge 167:e84263d55307 12773 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12774 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
AnnaBridge 167:e84263d55307 12775 #define SDIO_STA_CMDREND_Pos (6U)
AnnaBridge 167:e84263d55307 12776 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12777 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
AnnaBridge 167:e84263d55307 12778 #define SDIO_STA_CMDSENT_Pos (7U)
AnnaBridge 167:e84263d55307 12779 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12780 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
AnnaBridge 167:e84263d55307 12781 #define SDIO_STA_DATAEND_Pos (8U)
AnnaBridge 167:e84263d55307 12782 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12783 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
AnnaBridge 167:e84263d55307 12784 #define SDIO_STA_STBITERR_Pos (9U)
AnnaBridge 167:e84263d55307 12785 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12786 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!<Start bit not detected on all data signals in wide bus mode */
AnnaBridge 167:e84263d55307 12787 #define SDIO_STA_DBCKEND_Pos (10U)
AnnaBridge 167:e84263d55307 12788 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12789 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
AnnaBridge 167:e84263d55307 12790 #define SDIO_STA_CMDACT_Pos (11U)
AnnaBridge 167:e84263d55307 12791 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12792 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
AnnaBridge 167:e84263d55307 12793 #define SDIO_STA_TXACT_Pos (12U)
AnnaBridge 167:e84263d55307 12794 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12795 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
AnnaBridge 167:e84263d55307 12796 #define SDIO_STA_RXACT_Pos (13U)
AnnaBridge 167:e84263d55307 12797 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12798 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
AnnaBridge 167:e84263d55307 12799 #define SDIO_STA_TXFIFOHE_Pos (14U)
AnnaBridge 167:e84263d55307 12800 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12801 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
AnnaBridge 167:e84263d55307 12802 #define SDIO_STA_RXFIFOHF_Pos (15U)
AnnaBridge 167:e84263d55307 12803 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12804 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
AnnaBridge 167:e84263d55307 12805 #define SDIO_STA_TXFIFOF_Pos (16U)
AnnaBridge 167:e84263d55307 12806 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12807 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
AnnaBridge 167:e84263d55307 12808 #define SDIO_STA_RXFIFOF_Pos (17U)
AnnaBridge 167:e84263d55307 12809 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12810 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
AnnaBridge 167:e84263d55307 12811 #define SDIO_STA_TXFIFOE_Pos (18U)
AnnaBridge 167:e84263d55307 12812 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12813 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
AnnaBridge 167:e84263d55307 12814 #define SDIO_STA_RXFIFOE_Pos (19U)
AnnaBridge 167:e84263d55307 12815 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 12816 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
AnnaBridge 167:e84263d55307 12817 #define SDIO_STA_TXDAVL_Pos (20U)
AnnaBridge 167:e84263d55307 12818 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 12819 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
AnnaBridge 167:e84263d55307 12820 #define SDIO_STA_RXDAVL_Pos (21U)
AnnaBridge 167:e84263d55307 12821 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 12822 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
AnnaBridge 167:e84263d55307 12823 #define SDIO_STA_SDIOIT_Pos (22U)
AnnaBridge 167:e84263d55307 12824 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 12825 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
AnnaBridge 167:e84263d55307 12826 #define SDIO_STA_CEATAEND_Pos (23U)
AnnaBridge 167:e84263d55307 12827 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 12828 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!<CE-ATA command completion signal received for CMD61 */
<> 144:ef7eb2e8f9f7 12829
<> 144:ef7eb2e8f9f7 12830 /******************* Bit definition for SDIO_ICR register *******************/
AnnaBridge 167:e84263d55307 12831 #define SDIO_ICR_CCRCFAILC_Pos (0U)
AnnaBridge 167:e84263d55307 12832 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12833 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
AnnaBridge 167:e84263d55307 12834 #define SDIO_ICR_DCRCFAILC_Pos (1U)
AnnaBridge 167:e84263d55307 12835 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12836 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
AnnaBridge 167:e84263d55307 12837 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
AnnaBridge 167:e84263d55307 12838 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12839 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
AnnaBridge 167:e84263d55307 12840 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
AnnaBridge 167:e84263d55307 12841 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12842 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
AnnaBridge 167:e84263d55307 12843 #define SDIO_ICR_TXUNDERRC_Pos (4U)
AnnaBridge 167:e84263d55307 12844 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12845 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
AnnaBridge 167:e84263d55307 12846 #define SDIO_ICR_RXOVERRC_Pos (5U)
AnnaBridge 167:e84263d55307 12847 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12848 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
AnnaBridge 167:e84263d55307 12849 #define SDIO_ICR_CMDRENDC_Pos (6U)
AnnaBridge 167:e84263d55307 12850 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12851 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
AnnaBridge 167:e84263d55307 12852 #define SDIO_ICR_CMDSENTC_Pos (7U)
AnnaBridge 167:e84263d55307 12853 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12854 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
AnnaBridge 167:e84263d55307 12855 #define SDIO_ICR_DATAENDC_Pos (8U)
AnnaBridge 167:e84263d55307 12856 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12857 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
AnnaBridge 167:e84263d55307 12858 #define SDIO_ICR_STBITERRC_Pos (9U)
AnnaBridge 167:e84263d55307 12859 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12860 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!<STBITERR flag clear bit */
AnnaBridge 167:e84263d55307 12861 #define SDIO_ICR_DBCKENDC_Pos (10U)
AnnaBridge 167:e84263d55307 12862 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12863 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
AnnaBridge 167:e84263d55307 12864 #define SDIO_ICR_SDIOITC_Pos (22U)
AnnaBridge 167:e84263d55307 12865 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 12866 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
AnnaBridge 167:e84263d55307 12867 #define SDIO_ICR_CEATAENDC_Pos (23U)
AnnaBridge 167:e84263d55307 12868 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 12869 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!<CEATAEND flag clear bit */
<> 144:ef7eb2e8f9f7 12870
<> 144:ef7eb2e8f9f7 12871 /****************** Bit definition for SDIO_MASK register *******************/
AnnaBridge 167:e84263d55307 12872 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
AnnaBridge 167:e84263d55307 12873 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12874 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
AnnaBridge 167:e84263d55307 12875 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
AnnaBridge 167:e84263d55307 12876 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12877 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
AnnaBridge 167:e84263d55307 12878 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
AnnaBridge 167:e84263d55307 12879 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12880 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
AnnaBridge 167:e84263d55307 12881 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
AnnaBridge 167:e84263d55307 12882 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12883 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
AnnaBridge 167:e84263d55307 12884 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
AnnaBridge 167:e84263d55307 12885 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12886 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
AnnaBridge 167:e84263d55307 12887 #define SDIO_MASK_RXOVERRIE_Pos (5U)
AnnaBridge 167:e84263d55307 12888 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12889 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
AnnaBridge 167:e84263d55307 12890 #define SDIO_MASK_CMDRENDIE_Pos (6U)
AnnaBridge 167:e84263d55307 12891 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12892 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
AnnaBridge 167:e84263d55307 12893 #define SDIO_MASK_CMDSENTIE_Pos (7U)
AnnaBridge 167:e84263d55307 12894 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12895 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
AnnaBridge 167:e84263d55307 12896 #define SDIO_MASK_DATAENDIE_Pos (8U)
AnnaBridge 167:e84263d55307 12897 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12898 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
AnnaBridge 167:e84263d55307 12899 #define SDIO_MASK_STBITERRIE_Pos (9U)
AnnaBridge 167:e84263d55307 12900 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12901 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!<Start Bit Error Interrupt Enable */
AnnaBridge 167:e84263d55307 12902 #define SDIO_MASK_DBCKENDIE_Pos (10U)
AnnaBridge 167:e84263d55307 12903 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12904 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
AnnaBridge 167:e84263d55307 12905 #define SDIO_MASK_CMDACTIE_Pos (11U)
AnnaBridge 167:e84263d55307 12906 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12907 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
AnnaBridge 167:e84263d55307 12908 #define SDIO_MASK_TXACTIE_Pos (12U)
AnnaBridge 167:e84263d55307 12909 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 12910 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
AnnaBridge 167:e84263d55307 12911 #define SDIO_MASK_RXACTIE_Pos (13U)
AnnaBridge 167:e84263d55307 12912 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 12913 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
AnnaBridge 167:e84263d55307 12914 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
AnnaBridge 167:e84263d55307 12915 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 12916 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
AnnaBridge 167:e84263d55307 12917 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
AnnaBridge 167:e84263d55307 12918 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 12919 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
AnnaBridge 167:e84263d55307 12920 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
AnnaBridge 167:e84263d55307 12921 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 12922 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
AnnaBridge 167:e84263d55307 12923 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
AnnaBridge 167:e84263d55307 12924 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 12925 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
AnnaBridge 167:e84263d55307 12926 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
AnnaBridge 167:e84263d55307 12927 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 12928 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
AnnaBridge 167:e84263d55307 12929 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
AnnaBridge 167:e84263d55307 12930 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 12931 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
AnnaBridge 167:e84263d55307 12932 #define SDIO_MASK_TXDAVLIE_Pos (20U)
AnnaBridge 167:e84263d55307 12933 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 12934 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
AnnaBridge 167:e84263d55307 12935 #define SDIO_MASK_RXDAVLIE_Pos (21U)
AnnaBridge 167:e84263d55307 12936 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 12937 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
AnnaBridge 167:e84263d55307 12938 #define SDIO_MASK_SDIOITIE_Pos (22U)
AnnaBridge 167:e84263d55307 12939 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 12940 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
AnnaBridge 167:e84263d55307 12941 #define SDIO_MASK_CEATAENDIE_Pos (23U)
AnnaBridge 167:e84263d55307 12942 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 12943 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!<CE-ATA command completion signal received Interrupt Enable */
<> 144:ef7eb2e8f9f7 12944
<> 144:ef7eb2e8f9f7 12945 /***************** Bit definition for SDIO_FIFOCNT register *****************/
AnnaBridge 167:e84263d55307 12946 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
AnnaBridge 167:e84263d55307 12947 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
AnnaBridge 167:e84263d55307 12948 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
<> 144:ef7eb2e8f9f7 12949
<> 144:ef7eb2e8f9f7 12950 /****************** Bit definition for SDIO_FIFO register *******************/
AnnaBridge 167:e84263d55307 12951 #define SDIO_FIFO_FIFODATA_Pos (0U)
AnnaBridge 167:e84263d55307 12952 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 12953 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
<> 144:ef7eb2e8f9f7 12954
<> 144:ef7eb2e8f9f7 12955 /******************************************************************************/
<> 144:ef7eb2e8f9f7 12956 /* */
<> 144:ef7eb2e8f9f7 12957 /* Serial Peripheral Interface */
<> 144:ef7eb2e8f9f7 12958 /* */
<> 144:ef7eb2e8f9f7 12959 /******************************************************************************/
AnnaBridge 167:e84263d55307 12960 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
AnnaBridge 167:e84263d55307 12961
<> 144:ef7eb2e8f9f7 12962 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 167:e84263d55307 12963 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 167:e84263d55307 12964 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 12965 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
AnnaBridge 167:e84263d55307 12966 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 167:e84263d55307 12967 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 12968 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 167:e84263d55307 12969 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 167:e84263d55307 12970 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 12971 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
AnnaBridge 167:e84263d55307 12972
AnnaBridge 167:e84263d55307 12973 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 167:e84263d55307 12974 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 167:e84263d55307 12975 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
AnnaBridge 167:e84263d55307 12976 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 12977 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 12978 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 12979
AnnaBridge 167:e84263d55307 12980 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 167:e84263d55307 12981 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 12982 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
AnnaBridge 167:e84263d55307 12983 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 167:e84263d55307 12984 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 12985 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
AnnaBridge 167:e84263d55307 12986 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 167:e84263d55307 12987 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 12988 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
AnnaBridge 167:e84263d55307 12989 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 167:e84263d55307 12990 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 12991 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
AnnaBridge 167:e84263d55307 12992 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 167:e84263d55307 12993 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 12994 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
AnnaBridge 167:e84263d55307 12995 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 167:e84263d55307 12996 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 12997 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
AnnaBridge 167:e84263d55307 12998 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 167:e84263d55307 12999 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13000 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
AnnaBridge 167:e84263d55307 13001 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 167:e84263d55307 13002 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 13003 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
AnnaBridge 167:e84263d55307 13004 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 167:e84263d55307 13005 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 13006 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
AnnaBridge 167:e84263d55307 13007 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 167:e84263d55307 13008 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13009 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
<> 144:ef7eb2e8f9f7 13010
<> 144:ef7eb2e8f9f7 13011 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 167:e84263d55307 13012 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 167:e84263d55307 13013 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13014 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
AnnaBridge 167:e84263d55307 13015 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 167:e84263d55307 13016 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13017 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
AnnaBridge 167:e84263d55307 13018 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 167:e84263d55307 13019 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13020 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
AnnaBridge 167:e84263d55307 13021 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 167:e84263d55307 13022 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13023 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
AnnaBridge 167:e84263d55307 13024 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 167:e84263d55307 13025 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13026 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 167:e84263d55307 13027 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 167:e84263d55307 13028 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13029 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
AnnaBridge 167:e84263d55307 13030 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 167:e84263d55307 13031 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13032 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
<> 144:ef7eb2e8f9f7 13033
<> 144:ef7eb2e8f9f7 13034 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 167:e84263d55307 13035 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 167:e84263d55307 13036 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13037 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
AnnaBridge 167:e84263d55307 13038 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 167:e84263d55307 13039 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13040 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
AnnaBridge 167:e84263d55307 13041 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 167:e84263d55307 13042 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13043 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
AnnaBridge 167:e84263d55307 13044 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 167:e84263d55307 13045 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13046 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
AnnaBridge 167:e84263d55307 13047 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 167:e84263d55307 13048 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13049 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
AnnaBridge 167:e84263d55307 13050 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 167:e84263d55307 13051 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13052 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
AnnaBridge 167:e84263d55307 13053 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 167:e84263d55307 13054 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13055 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
AnnaBridge 167:e84263d55307 13056 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 167:e84263d55307 13057 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13058 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
AnnaBridge 167:e84263d55307 13059 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 167:e84263d55307 13060 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13061 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
<> 144:ef7eb2e8f9f7 13062
<> 144:ef7eb2e8f9f7 13063 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 167:e84263d55307 13064 #define SPI_DR_DR_Pos (0U)
AnnaBridge 167:e84263d55307 13065 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13066 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
<> 144:ef7eb2e8f9f7 13067
<> 144:ef7eb2e8f9f7 13068 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 167:e84263d55307 13069 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 167:e84263d55307 13070 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13071 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
<> 144:ef7eb2e8f9f7 13072
<> 144:ef7eb2e8f9f7 13073 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 167:e84263d55307 13074 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 167:e84263d55307 13075 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13076 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
<> 144:ef7eb2e8f9f7 13077
<> 144:ef7eb2e8f9f7 13078 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 167:e84263d55307 13079 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 167:e84263d55307 13080 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13081 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
<> 144:ef7eb2e8f9f7 13082
<> 144:ef7eb2e8f9f7 13083 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 167:e84263d55307 13084 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 167:e84263d55307 13085 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13086 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 167:e84263d55307 13087
AnnaBridge 167:e84263d55307 13088 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 167:e84263d55307 13089 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 167:e84263d55307 13090 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 167:e84263d55307 13091 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13092 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13093
AnnaBridge 167:e84263d55307 13094 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 167:e84263d55307 13095 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13096 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 167:e84263d55307 13097
AnnaBridge 167:e84263d55307 13098 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 167:e84263d55307 13099 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 13100 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 167:e84263d55307 13101 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13102 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13103
AnnaBridge 167:e84263d55307 13104 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 167:e84263d55307 13105 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13106 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 167:e84263d55307 13107
AnnaBridge 167:e84263d55307 13108 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 167:e84263d55307 13109 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 13110 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 167:e84263d55307 13111 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13112 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13113
AnnaBridge 167:e84263d55307 13114 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 167:e84263d55307 13115 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13116 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 167:e84263d55307 13117 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 167:e84263d55307 13118 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13119 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
<> 144:ef7eb2e8f9f7 13120
<> 144:ef7eb2e8f9f7 13121 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 167:e84263d55307 13122 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 167:e84263d55307 13123 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 13124 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 167:e84263d55307 13125 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 167:e84263d55307 13126 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13127 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 167:e84263d55307 13128 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 167:e84263d55307 13129 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13130 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
<> 144:ef7eb2e8f9f7 13131
<> 144:ef7eb2e8f9f7 13132 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13133 /* */
<> 144:ef7eb2e8f9f7 13134 /* SYSCFG */
<> 144:ef7eb2e8f9f7 13135 /* */
<> 144:ef7eb2e8f9f7 13136 /******************************************************************************/
AnnaBridge 167:e84263d55307 13137 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
AnnaBridge 167:e84263d55307 13138 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 167:e84263d55307 13139 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 13140 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 167:e84263d55307 13141 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13142 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13143 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13144 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
AnnaBridge 167:e84263d55307 13145 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13146 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
AnnaBridge 167:e84263d55307 13147 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
AnnaBridge 167:e84263d55307 13148 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 13149 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
AnnaBridge 167:e84263d55307 13150 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13151 /* Legacy Defines */
AnnaBridge 167:e84263d55307 13152 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
<> 144:ef7eb2e8f9f7 13153 /****************** Bit definition for SYSCFG_PMC register ******************/
AnnaBridge 167:e84263d55307 13154 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
AnnaBridge 167:e84263d55307 13155 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
AnnaBridge 167:e84263d55307 13156 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 167:e84263d55307 13157 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
AnnaBridge 167:e84263d55307 13158 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 13159 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 167:e84263d55307 13160 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
AnnaBridge 167:e84263d55307 13161 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 13162 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 167:e84263d55307 13163 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
AnnaBridge 167:e84263d55307 13164 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 13165 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
AnnaBridge 167:e84263d55307 13166 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
AnnaBridge 167:e84263d55307 13167 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 13168 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
<> 144:ef7eb2e8f9f7 13169 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
AnnaBridge 167:e84263d55307 13170 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
<> 144:ef7eb2e8f9f7 13171
<> 144:ef7eb2e8f9f7 13172 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 167:e84263d55307 13173 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 167:e84263d55307 13174 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 13175 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
AnnaBridge 167:e84263d55307 13176 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 167:e84263d55307 13177 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13178 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
AnnaBridge 167:e84263d55307 13179 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 167:e84263d55307 13180 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 13181 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
AnnaBridge 167:e84263d55307 13182 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 167:e84263d55307 13183 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13184 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
AnnaBridge 167:e84263d55307 13185 /**
<> 144:ef7eb2e8f9f7 13186 * @brief EXTI0 configuration
AnnaBridge 167:e84263d55307 13187 */
AnnaBridge 167:e84263d55307 13188 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
AnnaBridge 167:e84263d55307 13189 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
AnnaBridge 167:e84263d55307 13190 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
AnnaBridge 167:e84263d55307 13191 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
AnnaBridge 167:e84263d55307 13192 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
AnnaBridge 167:e84263d55307 13193 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
AnnaBridge 167:e84263d55307 13194 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
AnnaBridge 167:e84263d55307 13195 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
AnnaBridge 167:e84263d55307 13196 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
AnnaBridge 167:e84263d55307 13197 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
AnnaBridge 167:e84263d55307 13198 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
AnnaBridge 167:e84263d55307 13199
AnnaBridge 167:e84263d55307 13200 /**
<> 144:ef7eb2e8f9f7 13201 * @brief EXTI1 configuration
AnnaBridge 167:e84263d55307 13202 */
AnnaBridge 167:e84263d55307 13203 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
AnnaBridge 167:e84263d55307 13204 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
AnnaBridge 167:e84263d55307 13205 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
AnnaBridge 167:e84263d55307 13206 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
AnnaBridge 167:e84263d55307 13207 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
AnnaBridge 167:e84263d55307 13208 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
AnnaBridge 167:e84263d55307 13209 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
AnnaBridge 167:e84263d55307 13210 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
AnnaBridge 167:e84263d55307 13211 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
AnnaBridge 167:e84263d55307 13212 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
AnnaBridge 167:e84263d55307 13213 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
AnnaBridge 167:e84263d55307 13214
AnnaBridge 167:e84263d55307 13215 /**
<> 144:ef7eb2e8f9f7 13216 * @brief EXTI2 configuration
AnnaBridge 167:e84263d55307 13217 */
AnnaBridge 167:e84263d55307 13218 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
AnnaBridge 167:e84263d55307 13219 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
AnnaBridge 167:e84263d55307 13220 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
AnnaBridge 167:e84263d55307 13221 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
AnnaBridge 167:e84263d55307 13222 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
AnnaBridge 167:e84263d55307 13223 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
AnnaBridge 167:e84263d55307 13224 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
AnnaBridge 167:e84263d55307 13225 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
AnnaBridge 167:e84263d55307 13226 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
AnnaBridge 167:e84263d55307 13227 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
AnnaBridge 167:e84263d55307 13228 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
AnnaBridge 167:e84263d55307 13229
AnnaBridge 167:e84263d55307 13230 /**
<> 144:ef7eb2e8f9f7 13231 * @brief EXTI3 configuration
AnnaBridge 167:e84263d55307 13232 */
AnnaBridge 167:e84263d55307 13233 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
AnnaBridge 167:e84263d55307 13234 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
AnnaBridge 167:e84263d55307 13235 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
AnnaBridge 167:e84263d55307 13236 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
AnnaBridge 167:e84263d55307 13237 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
AnnaBridge 167:e84263d55307 13238 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
AnnaBridge 167:e84263d55307 13239 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
AnnaBridge 167:e84263d55307 13240 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
AnnaBridge 167:e84263d55307 13241 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
AnnaBridge 167:e84263d55307 13242 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
AnnaBridge 167:e84263d55307 13243 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
<> 144:ef7eb2e8f9f7 13244
<> 144:ef7eb2e8f9f7 13245 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
AnnaBridge 167:e84263d55307 13246 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 167:e84263d55307 13247 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 13248 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
AnnaBridge 167:e84263d55307 13249 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 167:e84263d55307 13250 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13251 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
AnnaBridge 167:e84263d55307 13252 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 167:e84263d55307 13253 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 13254 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
AnnaBridge 167:e84263d55307 13255 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 167:e84263d55307 13256 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13257 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
AnnaBridge 167:e84263d55307 13258
AnnaBridge 167:e84263d55307 13259 /**
<> 144:ef7eb2e8f9f7 13260 * @brief EXTI4 configuration
AnnaBridge 167:e84263d55307 13261 */
AnnaBridge 167:e84263d55307 13262 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
AnnaBridge 167:e84263d55307 13263 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
AnnaBridge 167:e84263d55307 13264 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
AnnaBridge 167:e84263d55307 13265 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
AnnaBridge 167:e84263d55307 13266 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
AnnaBridge 167:e84263d55307 13267 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
AnnaBridge 167:e84263d55307 13268 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
AnnaBridge 167:e84263d55307 13269 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
AnnaBridge 167:e84263d55307 13270 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
AnnaBridge 167:e84263d55307 13271 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
AnnaBridge 167:e84263d55307 13272 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
AnnaBridge 167:e84263d55307 13273
AnnaBridge 167:e84263d55307 13274 /**
<> 144:ef7eb2e8f9f7 13275 * @brief EXTI5 configuration
AnnaBridge 167:e84263d55307 13276 */
AnnaBridge 167:e84263d55307 13277 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
AnnaBridge 167:e84263d55307 13278 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
AnnaBridge 167:e84263d55307 13279 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
AnnaBridge 167:e84263d55307 13280 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
AnnaBridge 167:e84263d55307 13281 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
AnnaBridge 167:e84263d55307 13282 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
AnnaBridge 167:e84263d55307 13283 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
AnnaBridge 167:e84263d55307 13284 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
AnnaBridge 167:e84263d55307 13285 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
AnnaBridge 167:e84263d55307 13286 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
AnnaBridge 167:e84263d55307 13287 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
AnnaBridge 167:e84263d55307 13288
AnnaBridge 167:e84263d55307 13289 /**
<> 144:ef7eb2e8f9f7 13290 * @brief EXTI6 configuration
AnnaBridge 167:e84263d55307 13291 */
AnnaBridge 167:e84263d55307 13292 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
AnnaBridge 167:e84263d55307 13293 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
AnnaBridge 167:e84263d55307 13294 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
AnnaBridge 167:e84263d55307 13295 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
AnnaBridge 167:e84263d55307 13296 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
AnnaBridge 167:e84263d55307 13297 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
AnnaBridge 167:e84263d55307 13298 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
AnnaBridge 167:e84263d55307 13299 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
AnnaBridge 167:e84263d55307 13300 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
AnnaBridge 167:e84263d55307 13301 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
AnnaBridge 167:e84263d55307 13302 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
AnnaBridge 167:e84263d55307 13303
AnnaBridge 167:e84263d55307 13304 /**
<> 144:ef7eb2e8f9f7 13305 * @brief EXTI7 configuration
AnnaBridge 167:e84263d55307 13306 */
AnnaBridge 167:e84263d55307 13307 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
AnnaBridge 167:e84263d55307 13308 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
AnnaBridge 167:e84263d55307 13309 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
AnnaBridge 167:e84263d55307 13310 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
AnnaBridge 167:e84263d55307 13311 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
AnnaBridge 167:e84263d55307 13312 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
AnnaBridge 167:e84263d55307 13313 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
AnnaBridge 167:e84263d55307 13314 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
AnnaBridge 167:e84263d55307 13315 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
AnnaBridge 167:e84263d55307 13316 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
AnnaBridge 167:e84263d55307 13317 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
<> 144:ef7eb2e8f9f7 13318
<> 144:ef7eb2e8f9f7 13319 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
AnnaBridge 167:e84263d55307 13320 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 167:e84263d55307 13321 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 13322 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
AnnaBridge 167:e84263d55307 13323 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 167:e84263d55307 13324 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13325 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
AnnaBridge 167:e84263d55307 13326 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 167:e84263d55307 13327 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 13328 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
AnnaBridge 167:e84263d55307 13329 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 167:e84263d55307 13330 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13331 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
AnnaBridge 167:e84263d55307 13332
AnnaBridge 167:e84263d55307 13333 /**
<> 144:ef7eb2e8f9f7 13334 * @brief EXTI8 configuration
AnnaBridge 167:e84263d55307 13335 */
AnnaBridge 167:e84263d55307 13336 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
AnnaBridge 167:e84263d55307 13337 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
AnnaBridge 167:e84263d55307 13338 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
AnnaBridge 167:e84263d55307 13339 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
AnnaBridge 167:e84263d55307 13340 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
AnnaBridge 167:e84263d55307 13341 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
AnnaBridge 167:e84263d55307 13342 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
AnnaBridge 167:e84263d55307 13343 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
AnnaBridge 167:e84263d55307 13344 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
AnnaBridge 167:e84263d55307 13345 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
AnnaBridge 167:e84263d55307 13346
AnnaBridge 167:e84263d55307 13347 /**
<> 144:ef7eb2e8f9f7 13348 * @brief EXTI9 configuration
AnnaBridge 167:e84263d55307 13349 */
AnnaBridge 167:e84263d55307 13350 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
AnnaBridge 167:e84263d55307 13351 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
AnnaBridge 167:e84263d55307 13352 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
AnnaBridge 167:e84263d55307 13353 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
AnnaBridge 167:e84263d55307 13354 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
AnnaBridge 167:e84263d55307 13355 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
AnnaBridge 167:e84263d55307 13356 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
AnnaBridge 167:e84263d55307 13357 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
AnnaBridge 167:e84263d55307 13358 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
AnnaBridge 167:e84263d55307 13359 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
AnnaBridge 167:e84263d55307 13360
AnnaBridge 167:e84263d55307 13361 /**
<> 144:ef7eb2e8f9f7 13362 * @brief EXTI10 configuration
AnnaBridge 167:e84263d55307 13363 */
AnnaBridge 167:e84263d55307 13364 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
AnnaBridge 167:e84263d55307 13365 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
AnnaBridge 167:e84263d55307 13366 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
AnnaBridge 167:e84263d55307 13367 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
AnnaBridge 167:e84263d55307 13368 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
AnnaBridge 167:e84263d55307 13369 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
AnnaBridge 167:e84263d55307 13370 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
AnnaBridge 167:e84263d55307 13371 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
AnnaBridge 167:e84263d55307 13372 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
AnnaBridge 167:e84263d55307 13373 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
AnnaBridge 167:e84263d55307 13374
AnnaBridge 167:e84263d55307 13375 /**
<> 144:ef7eb2e8f9f7 13376 * @brief EXTI11 configuration
AnnaBridge 167:e84263d55307 13377 */
AnnaBridge 167:e84263d55307 13378 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
AnnaBridge 167:e84263d55307 13379 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
AnnaBridge 167:e84263d55307 13380 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
AnnaBridge 167:e84263d55307 13381 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
AnnaBridge 167:e84263d55307 13382 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
AnnaBridge 167:e84263d55307 13383 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
AnnaBridge 167:e84263d55307 13384 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
AnnaBridge 167:e84263d55307 13385 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
AnnaBridge 167:e84263d55307 13386 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
AnnaBridge 167:e84263d55307 13387 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
<> 144:ef7eb2e8f9f7 13388
<> 144:ef7eb2e8f9f7 13389
<> 144:ef7eb2e8f9f7 13390 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
AnnaBridge 167:e84263d55307 13391 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 167:e84263d55307 13392 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 13393 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
AnnaBridge 167:e84263d55307 13394 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 167:e84263d55307 13395 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13396 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
AnnaBridge 167:e84263d55307 13397 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 167:e84263d55307 13398 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 13399 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
AnnaBridge 167:e84263d55307 13400 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 167:e84263d55307 13401 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13402 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
AnnaBridge 167:e84263d55307 13403
AnnaBridge 167:e84263d55307 13404 /**
<> 144:ef7eb2e8f9f7 13405 * @brief EXTI12 configuration
AnnaBridge 167:e84263d55307 13406 */
AnnaBridge 167:e84263d55307 13407 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
AnnaBridge 167:e84263d55307 13408 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
AnnaBridge 167:e84263d55307 13409 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
AnnaBridge 167:e84263d55307 13410 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
AnnaBridge 167:e84263d55307 13411 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
AnnaBridge 167:e84263d55307 13412 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
AnnaBridge 167:e84263d55307 13413 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
AnnaBridge 167:e84263d55307 13414 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
AnnaBridge 167:e84263d55307 13415 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
AnnaBridge 167:e84263d55307 13416 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
AnnaBridge 167:e84263d55307 13417
AnnaBridge 167:e84263d55307 13418 /**
<> 144:ef7eb2e8f9f7 13419 * @brief EXTI13 configuration
AnnaBridge 167:e84263d55307 13420 */
AnnaBridge 167:e84263d55307 13421 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
AnnaBridge 167:e84263d55307 13422 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
AnnaBridge 167:e84263d55307 13423 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
AnnaBridge 167:e84263d55307 13424 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
AnnaBridge 167:e84263d55307 13425 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
AnnaBridge 167:e84263d55307 13426 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
AnnaBridge 167:e84263d55307 13427 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
AnnaBridge 167:e84263d55307 13428 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
AnnaBridge 167:e84263d55307 13429 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
AnnaBridge 167:e84263d55307 13430 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
AnnaBridge 167:e84263d55307 13431
AnnaBridge 167:e84263d55307 13432 /**
<> 144:ef7eb2e8f9f7 13433 * @brief EXTI14 configuration
AnnaBridge 167:e84263d55307 13434 */
AnnaBridge 167:e84263d55307 13435 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
AnnaBridge 167:e84263d55307 13436 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
AnnaBridge 167:e84263d55307 13437 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
AnnaBridge 167:e84263d55307 13438 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
AnnaBridge 167:e84263d55307 13439 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
AnnaBridge 167:e84263d55307 13440 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
AnnaBridge 167:e84263d55307 13441 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
AnnaBridge 167:e84263d55307 13442 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
AnnaBridge 167:e84263d55307 13443 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
AnnaBridge 167:e84263d55307 13444 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
AnnaBridge 167:e84263d55307 13445
AnnaBridge 167:e84263d55307 13446 /**
<> 144:ef7eb2e8f9f7 13447 * @brief EXTI15 configuration
AnnaBridge 167:e84263d55307 13448 */
AnnaBridge 167:e84263d55307 13449 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
AnnaBridge 167:e84263d55307 13450 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
AnnaBridge 167:e84263d55307 13451 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
AnnaBridge 167:e84263d55307 13452 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
AnnaBridge 167:e84263d55307 13453 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
AnnaBridge 167:e84263d55307 13454 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
AnnaBridge 167:e84263d55307 13455 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
AnnaBridge 167:e84263d55307 13456 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
AnnaBridge 167:e84263d55307 13457 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
AnnaBridge 167:e84263d55307 13458 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
AnnaBridge 167:e84263d55307 13459
AnnaBridge 167:e84263d55307 13460 /****************** Bit definition for SYSCFG_CMPCR register ****************/
AnnaBridge 167:e84263d55307 13461 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
AnnaBridge 167:e84263d55307 13462 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13463 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
AnnaBridge 167:e84263d55307 13464 #define SYSCFG_CMPCR_READY_Pos (8U)
AnnaBridge 167:e84263d55307 13465 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13466 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
<> 144:ef7eb2e8f9f7 13467
<> 144:ef7eb2e8f9f7 13468 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13469 /* */
<> 144:ef7eb2e8f9f7 13470 /* TIM */
<> 144:ef7eb2e8f9f7 13471 /* */
<> 144:ef7eb2e8f9f7 13472 /******************************************************************************/
<> 144:ef7eb2e8f9f7 13473 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 167:e84263d55307 13474 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 167:e84263d55307 13475 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13476 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 167:e84263d55307 13477 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 167:e84263d55307 13478 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13479 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 167:e84263d55307 13480 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 167:e84263d55307 13481 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13482 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 167:e84263d55307 13483 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 167:e84263d55307 13484 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13485 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 167:e84263d55307 13486 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 167:e84263d55307 13487 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13488 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 167:e84263d55307 13489
AnnaBridge 167:e84263d55307 13490 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 167:e84263d55307 13491 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 167:e84263d55307 13492 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 167:e84263d55307 13493 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13494 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13495
AnnaBridge 167:e84263d55307 13496 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 167:e84263d55307 13497 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13498 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 167:e84263d55307 13499
AnnaBridge 167:e84263d55307 13500 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 167:e84263d55307 13501 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 13502 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 167:e84263d55307 13503 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13504 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
<> 144:ef7eb2e8f9f7 13505
<> 144:ef7eb2e8f9f7 13506 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 167:e84263d55307 13507 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 167:e84263d55307 13508 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13509 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 167:e84263d55307 13510 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 167:e84263d55307 13511 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13512 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 167:e84263d55307 13513 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 167:e84263d55307 13514 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13515 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 167:e84263d55307 13516
AnnaBridge 167:e84263d55307 13517 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 167:e84263d55307 13518 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 13519 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 167:e84263d55307 13520 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13521 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13522 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13523
AnnaBridge 167:e84263d55307 13524 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 167:e84263d55307 13525 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13526 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 167:e84263d55307 13527 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 167:e84263d55307 13528 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13529 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 167:e84263d55307 13530 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 167:e84263d55307 13531 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13532 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 167:e84263d55307 13533 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 167:e84263d55307 13534 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13535 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 167:e84263d55307 13536 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 167:e84263d55307 13537 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13538 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 167:e84263d55307 13539 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 167:e84263d55307 13540 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13541 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 167:e84263d55307 13542 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 167:e84263d55307 13543 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 13544 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 167:e84263d55307 13545 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 167:e84263d55307 13546 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 13547 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
<> 144:ef7eb2e8f9f7 13548
<> 144:ef7eb2e8f9f7 13549 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 167:e84263d55307 13550 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 167:e84263d55307 13551 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 13552 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 167:e84263d55307 13553 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 13554 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 13555 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 13556
AnnaBridge 167:e84263d55307 13557 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 167:e84263d55307 13558 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 13559 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 167:e84263d55307 13560 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13561 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13562 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13563
AnnaBridge 167:e84263d55307 13564 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 167:e84263d55307 13565 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13566 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 167:e84263d55307 13567
AnnaBridge 167:e84263d55307 13568 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 167:e84263d55307 13569 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 167:e84263d55307 13570 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 167:e84263d55307 13571 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13572 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
AnnaBridge 167:e84263d55307 13573 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
AnnaBridge 167:e84263d55307 13574 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
AnnaBridge 167:e84263d55307 13575
AnnaBridge 167:e84263d55307 13576 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 167:e84263d55307 13577 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 13578 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 167:e84263d55307 13579 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 13580 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 13581
AnnaBridge 167:e84263d55307 13582 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 167:e84263d55307 13583 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 13584 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 167:e84263d55307 13585 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 167:e84263d55307 13586 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13587 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
<> 144:ef7eb2e8f9f7 13588
<> 144:ef7eb2e8f9f7 13589 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 167:e84263d55307 13590 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 167:e84263d55307 13591 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13592 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 167:e84263d55307 13593 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 167:e84263d55307 13594 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13595 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 167:e84263d55307 13596 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 167:e84263d55307 13597 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13598 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 167:e84263d55307 13599 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 167:e84263d55307 13600 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13601 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 167:e84263d55307 13602 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 167:e84263d55307 13603 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13604 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 167:e84263d55307 13605 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 167:e84263d55307 13606 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13607 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 167:e84263d55307 13608 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 167:e84263d55307 13609 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13610 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 167:e84263d55307 13611 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 167:e84263d55307 13612 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13613 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 167:e84263d55307 13614 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 167:e84263d55307 13615 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13616 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 167:e84263d55307 13617 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 167:e84263d55307 13618 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13619 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 167:e84263d55307 13620 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 167:e84263d55307 13621 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13622 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 167:e84263d55307 13623 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 167:e84263d55307 13624 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13625 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 167:e84263d55307 13626 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 167:e84263d55307 13627 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13628 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 167:e84263d55307 13629 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 167:e84263d55307 13630 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 13631 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 167:e84263d55307 13632 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 167:e84263d55307 13633 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 13634 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
<> 144:ef7eb2e8f9f7 13635
<> 144:ef7eb2e8f9f7 13636 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 167:e84263d55307 13637 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 167:e84263d55307 13638 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13639 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 167:e84263d55307 13640 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 167:e84263d55307 13641 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13642 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 167:e84263d55307 13643 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 167:e84263d55307 13644 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13645 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 167:e84263d55307 13646 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 167:e84263d55307 13647 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13648 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 167:e84263d55307 13649 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 167:e84263d55307 13650 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13651 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 167:e84263d55307 13652 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 167:e84263d55307 13653 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13654 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 167:e84263d55307 13655 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 167:e84263d55307 13656 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13657 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 167:e84263d55307 13658 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 167:e84263d55307 13659 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13660 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 167:e84263d55307 13661 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 167:e84263d55307 13662 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13663 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 167:e84263d55307 13664 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 167:e84263d55307 13665 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13666 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 167:e84263d55307 13667 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 167:e84263d55307 13668 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13669 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 167:e84263d55307 13670 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 167:e84263d55307 13671 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13672 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
<> 144:ef7eb2e8f9f7 13673
<> 144:ef7eb2e8f9f7 13674 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 167:e84263d55307 13675 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 167:e84263d55307 13676 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13677 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 167:e84263d55307 13678 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 167:e84263d55307 13679 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13680 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 167:e84263d55307 13681 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 167:e84263d55307 13682 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13683 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 167:e84263d55307 13684 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 167:e84263d55307 13685 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13686 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 167:e84263d55307 13687 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 167:e84263d55307 13688 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13689 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 167:e84263d55307 13690 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 167:e84263d55307 13691 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13692 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 167:e84263d55307 13693 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 167:e84263d55307 13694 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13695 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 167:e84263d55307 13696 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 167:e84263d55307 13697 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13698 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
<> 144:ef7eb2e8f9f7 13699
<> 144:ef7eb2e8f9f7 13700 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 167:e84263d55307 13701 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 167:e84263d55307 13702 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 13703 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 167:e84263d55307 13704 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 13705 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 13706
AnnaBridge 167:e84263d55307 13707 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 167:e84263d55307 13708 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13709 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 167:e84263d55307 13710 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 167:e84263d55307 13711 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13712 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 167:e84263d55307 13713
AnnaBridge 167:e84263d55307 13714 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 167:e84263d55307 13715 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 13716 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 167:e84263d55307 13717 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13718 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13719 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13720
AnnaBridge 167:e84263d55307 13721 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 167:e84263d55307 13722 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13723 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 167:e84263d55307 13724
AnnaBridge 167:e84263d55307 13725 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 167:e84263d55307 13726 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 13727 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 167:e84263d55307 13728 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13729 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
AnnaBridge 167:e84263d55307 13730
AnnaBridge 167:e84263d55307 13731 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 167:e84263d55307 13732 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13733 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 167:e84263d55307 13734 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 167:e84263d55307 13735 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13736 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 167:e84263d55307 13737
AnnaBridge 167:e84263d55307 13738 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 167:e84263d55307 13739 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 13740 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 167:e84263d55307 13741 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 13742 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 13743 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
AnnaBridge 167:e84263d55307 13744
AnnaBridge 167:e84263d55307 13745 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 167:e84263d55307 13746 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13747 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
<> 144:ef7eb2e8f9f7 13748
<> 144:ef7eb2e8f9f7 13749 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 13750
AnnaBridge 167:e84263d55307 13751 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 167:e84263d55307 13752 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 13753 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 167:e84263d55307 13754 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 13755 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 13756
AnnaBridge 167:e84263d55307 13757 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 167:e84263d55307 13758 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13759 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 167:e84263d55307 13760 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13761 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13762 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13763 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 13764
AnnaBridge 167:e84263d55307 13765 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 167:e84263d55307 13766 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 13767 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 167:e84263d55307 13768 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
AnnaBridge 167:e84263d55307 13769 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
AnnaBridge 167:e84263d55307 13770
AnnaBridge 167:e84263d55307 13771 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 167:e84263d55307 13772 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13773 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 167:e84263d55307 13774 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 13775 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 13776 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
AnnaBridge 167:e84263d55307 13777 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
<> 144:ef7eb2e8f9f7 13778
<> 144:ef7eb2e8f9f7 13779 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 167:e84263d55307 13780 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 167:e84263d55307 13781 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 13782 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 167:e84263d55307 13783 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 13784 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 13785
AnnaBridge 167:e84263d55307 13786 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 167:e84263d55307 13787 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13788 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 167:e84263d55307 13789 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 167:e84263d55307 13790 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13791 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 167:e84263d55307 13792
AnnaBridge 167:e84263d55307 13793 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 167:e84263d55307 13794 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 13795 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 167:e84263d55307 13796 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13797 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13798 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13799
AnnaBridge 167:e84263d55307 13800 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 167:e84263d55307 13801 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13802 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 167:e84263d55307 13803
AnnaBridge 167:e84263d55307 13804 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 167:e84263d55307 13805 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 13806 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 167:e84263d55307 13807 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13808 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
AnnaBridge 167:e84263d55307 13809
AnnaBridge 167:e84263d55307 13810 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 167:e84263d55307 13811 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13812 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 167:e84263d55307 13813 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 167:e84263d55307 13814 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13815 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 167:e84263d55307 13816
AnnaBridge 167:e84263d55307 13817 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 167:e84263d55307 13818 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 167:e84263d55307 13819 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 167:e84263d55307 13820 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 13821 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 13822 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
AnnaBridge 167:e84263d55307 13823
AnnaBridge 167:e84263d55307 13824 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 167:e84263d55307 13825 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13826 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
<> 144:ef7eb2e8f9f7 13827
<> 144:ef7eb2e8f9f7 13828 /*----------------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 13829
AnnaBridge 167:e84263d55307 13830 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 167:e84263d55307 13831 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 13832 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 167:e84263d55307 13833 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 13834 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 13835
AnnaBridge 167:e84263d55307 13836 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 167:e84263d55307 13837 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 167:e84263d55307 13838 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 167:e84263d55307 13839 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13840 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13841 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13842 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 13843
AnnaBridge 167:e84263d55307 13844 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 167:e84263d55307 13845 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 13846 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 167:e84263d55307 13847 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
AnnaBridge 167:e84263d55307 13848 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
AnnaBridge 167:e84263d55307 13849
AnnaBridge 167:e84263d55307 13850 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 167:e84263d55307 13851 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 167:e84263d55307 13852 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 167:e84263d55307 13853 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 13854 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 13855 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
AnnaBridge 167:e84263d55307 13856 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
<> 144:ef7eb2e8f9f7 13857
<> 144:ef7eb2e8f9f7 13858 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 167:e84263d55307 13859 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 167:e84263d55307 13860 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 13861 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 167:e84263d55307 13862 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 167:e84263d55307 13863 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 13864 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 167:e84263d55307 13865 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 167:e84263d55307 13866 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 13867 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 167:e84263d55307 13868 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 167:e84263d55307 13869 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 13870 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 167:e84263d55307 13871 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 167:e84263d55307 13872 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 13873 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 167:e84263d55307 13874 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 167:e84263d55307 13875 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 13876 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 167:e84263d55307 13877 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 167:e84263d55307 13878 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 13879 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 167:e84263d55307 13880 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 167:e84263d55307 13881 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 13882 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 167:e84263d55307 13883 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 167:e84263d55307 13884 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 13885 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 167:e84263d55307 13886 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 167:e84263d55307 13887 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 13888 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 167:e84263d55307 13889 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 167:e84263d55307 13890 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13891 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 167:e84263d55307 13892 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 167:e84263d55307 13893 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13894 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 167:e84263d55307 13895 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 167:e84263d55307 13896 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13897 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 167:e84263d55307 13898 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 167:e84263d55307 13899 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 13900 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 167:e84263d55307 13901 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 167:e84263d55307 13902 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13903 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
<> 144:ef7eb2e8f9f7 13904
<> 144:ef7eb2e8f9f7 13905 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 167:e84263d55307 13906 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 167:e84263d55307 13907 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 13908 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
<> 144:ef7eb2e8f9f7 13909
<> 144:ef7eb2e8f9f7 13910 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 167:e84263d55307 13911 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 167:e84263d55307 13912 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13913 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
<> 144:ef7eb2e8f9f7 13914
<> 144:ef7eb2e8f9f7 13915 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 167:e84263d55307 13916 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 167:e84263d55307 13917 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 13918 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
<> 144:ef7eb2e8f9f7 13919
<> 144:ef7eb2e8f9f7 13920 /******************* Bit definition for TIM_RCR register ********************/
AnnaBridge 167:e84263d55307 13921 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 167:e84263d55307 13922 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 13923 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
<> 144:ef7eb2e8f9f7 13924
<> 144:ef7eb2e8f9f7 13925 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 167:e84263d55307 13926 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 167:e84263d55307 13927 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13928 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
<> 144:ef7eb2e8f9f7 13929
<> 144:ef7eb2e8f9f7 13930 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 167:e84263d55307 13931 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 167:e84263d55307 13932 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13933 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
<> 144:ef7eb2e8f9f7 13934
<> 144:ef7eb2e8f9f7 13935 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 167:e84263d55307 13936 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 167:e84263d55307 13937 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13938 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
<> 144:ef7eb2e8f9f7 13939
<> 144:ef7eb2e8f9f7 13940 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 167:e84263d55307 13941 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 167:e84263d55307 13942 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 13943 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
<> 144:ef7eb2e8f9f7 13944
<> 144:ef7eb2e8f9f7 13945 /******************* Bit definition for TIM_BDTR register *******************/
AnnaBridge 167:e84263d55307 13946 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 167:e84263d55307 13947 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 13948 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 167:e84263d55307 13949 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 13950 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 13951 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 13952 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 13953 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13954 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 13955 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 13956 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 13957
AnnaBridge 167:e84263d55307 13958 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 167:e84263d55307 13959 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 13960 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 167:e84263d55307 13961 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13962 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
AnnaBridge 167:e84263d55307 13963
AnnaBridge 167:e84263d55307 13964 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 167:e84263d55307 13965 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 13966 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 167:e84263d55307 13967 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 167:e84263d55307 13968 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 13969 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 167:e84263d55307 13970 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 167:e84263d55307 13971 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 13972 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 167:e84263d55307 13973 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 167:e84263d55307 13974 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 13975 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 167:e84263d55307 13976 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 167:e84263d55307 13977 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 13978 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 167:e84263d55307 13979 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 167:e84263d55307 13980 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 13981 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
<> 144:ef7eb2e8f9f7 13982
<> 144:ef7eb2e8f9f7 13983 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 167:e84263d55307 13984 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 167:e84263d55307 13985 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 167:e84263d55307 13986 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 167:e84263d55307 13987 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 13988 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 13989 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 13990 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 13991 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 13992
AnnaBridge 167:e84263d55307 13993 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 167:e84263d55307 13994 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 167:e84263d55307 13995 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 167:e84263d55307 13996 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
AnnaBridge 167:e84263d55307 13997 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
AnnaBridge 167:e84263d55307 13998 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
AnnaBridge 167:e84263d55307 13999 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
AnnaBridge 167:e84263d55307 14000 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
<> 144:ef7eb2e8f9f7 14001
<> 144:ef7eb2e8f9f7 14002 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 167:e84263d55307 14003 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 167:e84263d55307 14004 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14005 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
<> 144:ef7eb2e8f9f7 14006
<> 144:ef7eb2e8f9f7 14007 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 167:e84263d55307 14008 #define TIM_OR_TI1_RMP_Pos (0U)
AnnaBridge 167:e84263d55307 14009 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 14010 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
AnnaBridge 167:e84263d55307 14011 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14012 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14013
AnnaBridge 167:e84263d55307 14014 #define TIM_OR_TI4_RMP_Pos (6U)
AnnaBridge 167:e84263d55307 14015 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 14016 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
AnnaBridge 167:e84263d55307 14017 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 14018 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 14019 #define TIM_OR_ITR1_RMP_Pos (10U)
AnnaBridge 167:e84263d55307 14020 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 14021 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
AnnaBridge 167:e84263d55307 14022 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
AnnaBridge 167:e84263d55307 14023 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
<> 144:ef7eb2e8f9f7 14024
<> 144:ef7eb2e8f9f7 14025
<> 144:ef7eb2e8f9f7 14026 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14027 /* */
<> 144:ef7eb2e8f9f7 14028 /* Universal Synchronous Asynchronous Receiver Transmitter */
<> 144:ef7eb2e8f9f7 14029 /* */
<> 144:ef7eb2e8f9f7 14030 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14031 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 167:e84263d55307 14032 #define USART_SR_PE_Pos (0U)
AnnaBridge 167:e84263d55307 14033 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14034 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
AnnaBridge 167:e84263d55307 14035 #define USART_SR_FE_Pos (1U)
AnnaBridge 167:e84263d55307 14036 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14037 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
AnnaBridge 167:e84263d55307 14038 #define USART_SR_NE_Pos (2U)
AnnaBridge 167:e84263d55307 14039 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14040 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
AnnaBridge 167:e84263d55307 14041 #define USART_SR_ORE_Pos (3U)
AnnaBridge 167:e84263d55307 14042 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14043 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
AnnaBridge 167:e84263d55307 14044 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 167:e84263d55307 14045 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14046 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
AnnaBridge 167:e84263d55307 14047 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 167:e84263d55307 14048 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14049 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
AnnaBridge 167:e84263d55307 14050 #define USART_SR_TC_Pos (6U)
AnnaBridge 167:e84263d55307 14051 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14052 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
AnnaBridge 167:e84263d55307 14053 #define USART_SR_TXE_Pos (7U)
AnnaBridge 167:e84263d55307 14054 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14055 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
AnnaBridge 167:e84263d55307 14056 #define USART_SR_LBD_Pos (8U)
AnnaBridge 167:e84263d55307 14057 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14058 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
AnnaBridge 167:e84263d55307 14059 #define USART_SR_CTS_Pos (9U)
AnnaBridge 167:e84263d55307 14060 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14061 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
<> 144:ef7eb2e8f9f7 14062
<> 144:ef7eb2e8f9f7 14063 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 167:e84263d55307 14064 #define USART_DR_DR_Pos (0U)
AnnaBridge 167:e84263d55307 14065 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 167:e84263d55307 14066 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
<> 144:ef7eb2e8f9f7 14067
<> 144:ef7eb2e8f9f7 14068 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 167:e84263d55307 14069 #define USART_BRR_DIV_Fraction_Pos (0U)
AnnaBridge 167:e84263d55307 14070 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 14071 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
AnnaBridge 167:e84263d55307 14072 #define USART_BRR_DIV_Mantissa_Pos (4U)
AnnaBridge 167:e84263d55307 14073 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
AnnaBridge 167:e84263d55307 14074 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
<> 144:ef7eb2e8f9f7 14075
<> 144:ef7eb2e8f9f7 14076 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 167:e84263d55307 14077 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 167:e84263d55307 14078 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14079 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
AnnaBridge 167:e84263d55307 14080 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 167:e84263d55307 14081 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14082 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
AnnaBridge 167:e84263d55307 14083 #define USART_CR1_RE_Pos (2U)
AnnaBridge 167:e84263d55307 14084 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14085 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
AnnaBridge 167:e84263d55307 14086 #define USART_CR1_TE_Pos (3U)
AnnaBridge 167:e84263d55307 14087 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14088 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
AnnaBridge 167:e84263d55307 14089 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 167:e84263d55307 14090 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14091 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
AnnaBridge 167:e84263d55307 14092 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 167:e84263d55307 14093 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14094 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
AnnaBridge 167:e84263d55307 14095 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 167:e84263d55307 14096 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14097 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
AnnaBridge 167:e84263d55307 14098 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 167:e84263d55307 14099 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14100 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 167:e84263d55307 14101 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 167:e84263d55307 14102 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14103 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
AnnaBridge 167:e84263d55307 14104 #define USART_CR1_PS_Pos (9U)
AnnaBridge 167:e84263d55307 14105 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14106 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
AnnaBridge 167:e84263d55307 14107 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 167:e84263d55307 14108 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14109 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
AnnaBridge 167:e84263d55307 14110 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 167:e84263d55307 14111 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14112 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
AnnaBridge 167:e84263d55307 14113 #define USART_CR1_M_Pos (12U)
AnnaBridge 167:e84263d55307 14114 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 14115 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
AnnaBridge 167:e84263d55307 14116 #define USART_CR1_UE_Pos (13U)
AnnaBridge 167:e84263d55307 14117 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 14118 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
AnnaBridge 167:e84263d55307 14119 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 167:e84263d55307 14120 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 14121 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
<> 144:ef7eb2e8f9f7 14122
<> 144:ef7eb2e8f9f7 14123 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 167:e84263d55307 14124 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 167:e84263d55307 14125 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 14126 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
AnnaBridge 167:e84263d55307 14127 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 167:e84263d55307 14128 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14129 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
AnnaBridge 167:e84263d55307 14130 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 167:e84263d55307 14131 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14132 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
AnnaBridge 167:e84263d55307 14133 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 167:e84263d55307 14134 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14135 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
AnnaBridge 167:e84263d55307 14136 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 167:e84263d55307 14137 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14138 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
AnnaBridge 167:e84263d55307 14139 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 167:e84263d55307 14140 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14141 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
AnnaBridge 167:e84263d55307 14142 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 167:e84263d55307 14143 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14144 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
AnnaBridge 167:e84263d55307 14145
AnnaBridge 167:e84263d55307 14146 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 167:e84263d55307 14147 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 167:e84263d55307 14148 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
AnnaBridge 167:e84263d55307 14149 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
AnnaBridge 167:e84263d55307 14150 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
AnnaBridge 167:e84263d55307 14151
AnnaBridge 167:e84263d55307 14152 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 167:e84263d55307 14153 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 14154 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
<> 144:ef7eb2e8f9f7 14155
<> 144:ef7eb2e8f9f7 14156 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 167:e84263d55307 14157 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 167:e84263d55307 14158 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14159 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
AnnaBridge 167:e84263d55307 14160 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 167:e84263d55307 14161 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14162 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
AnnaBridge 167:e84263d55307 14163 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 167:e84263d55307 14164 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14165 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
AnnaBridge 167:e84263d55307 14166 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 167:e84263d55307 14167 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14168 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
AnnaBridge 167:e84263d55307 14169 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 167:e84263d55307 14170 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14171 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
AnnaBridge 167:e84263d55307 14172 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 167:e84263d55307 14173 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14174 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
AnnaBridge 167:e84263d55307 14175 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 167:e84263d55307 14176 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14177 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
AnnaBridge 167:e84263d55307 14178 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 167:e84263d55307 14179 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14180 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
AnnaBridge 167:e84263d55307 14181 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 167:e84263d55307 14182 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14183 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
AnnaBridge 167:e84263d55307 14184 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 167:e84263d55307 14185 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14186 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
AnnaBridge 167:e84263d55307 14187 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 167:e84263d55307 14188 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14189 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
AnnaBridge 167:e84263d55307 14190 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 167:e84263d55307 14191 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14192 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
<> 144:ef7eb2e8f9f7 14193
<> 144:ef7eb2e8f9f7 14194 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 167:e84263d55307 14195 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 167:e84263d55307 14196 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 14197 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
AnnaBridge 167:e84263d55307 14198 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 14199 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 14200 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 14201 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 14202 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 14203 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 14204 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
AnnaBridge 167:e84263d55307 14205 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 14206
AnnaBridge 167:e84263d55307 14207 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 167:e84263d55307 14208 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 167:e84263d55307 14209 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
<> 144:ef7eb2e8f9f7 14210
<> 144:ef7eb2e8f9f7 14211 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14212 /* */
<> 144:ef7eb2e8f9f7 14213 /* Window WATCHDOG */
<> 144:ef7eb2e8f9f7 14214 /* */
<> 144:ef7eb2e8f9f7 14215 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14216 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 167:e84263d55307 14217 #define WWDG_CR_T_Pos (0U)
AnnaBridge 167:e84263d55307 14218 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 167:e84263d55307 14219 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 167:e84263d55307 14220 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
AnnaBridge 167:e84263d55307 14221 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
AnnaBridge 167:e84263d55307 14222 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
AnnaBridge 167:e84263d55307 14223 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
AnnaBridge 167:e84263d55307 14224 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
AnnaBridge 167:e84263d55307 14225 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
AnnaBridge 167:e84263d55307 14226 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
<> 144:ef7eb2e8f9f7 14227 /* Legacy defines */
<> 144:ef7eb2e8f9f7 14228 #define WWDG_CR_T0 WWDG_CR_T_0
<> 144:ef7eb2e8f9f7 14229 #define WWDG_CR_T1 WWDG_CR_T_1
<> 144:ef7eb2e8f9f7 14230 #define WWDG_CR_T2 WWDG_CR_T_2
<> 144:ef7eb2e8f9f7 14231 #define WWDG_CR_T3 WWDG_CR_T_3
<> 144:ef7eb2e8f9f7 14232 #define WWDG_CR_T4 WWDG_CR_T_4
<> 144:ef7eb2e8f9f7 14233 #define WWDG_CR_T5 WWDG_CR_T_5
<> 144:ef7eb2e8f9f7 14234 #define WWDG_CR_T6 WWDG_CR_T_6
<> 144:ef7eb2e8f9f7 14235
AnnaBridge 167:e84263d55307 14236 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 167:e84263d55307 14237 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14238 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
<> 144:ef7eb2e8f9f7 14239
<> 144:ef7eb2e8f9f7 14240 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 167:e84263d55307 14241 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 167:e84263d55307 14242 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 167:e84263d55307 14243 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
AnnaBridge 167:e84263d55307 14244 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
AnnaBridge 167:e84263d55307 14245 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
AnnaBridge 167:e84263d55307 14246 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
AnnaBridge 167:e84263d55307 14247 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
AnnaBridge 167:e84263d55307 14248 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
AnnaBridge 167:e84263d55307 14249 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
AnnaBridge 167:e84263d55307 14250 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
<> 144:ef7eb2e8f9f7 14251 /* Legacy defines */
<> 144:ef7eb2e8f9f7 14252 #define WWDG_CFR_W0 WWDG_CFR_W_0
<> 144:ef7eb2e8f9f7 14253 #define WWDG_CFR_W1 WWDG_CFR_W_1
<> 144:ef7eb2e8f9f7 14254 #define WWDG_CFR_W2 WWDG_CFR_W_2
<> 144:ef7eb2e8f9f7 14255 #define WWDG_CFR_W3 WWDG_CFR_W_3
<> 144:ef7eb2e8f9f7 14256 #define WWDG_CFR_W4 WWDG_CFR_W_4
<> 144:ef7eb2e8f9f7 14257 #define WWDG_CFR_W5 WWDG_CFR_W_5
<> 144:ef7eb2e8f9f7 14258 #define WWDG_CFR_W6 WWDG_CFR_W_6
<> 144:ef7eb2e8f9f7 14259
AnnaBridge 167:e84263d55307 14260 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 167:e84263d55307 14261 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 167:e84263d55307 14262 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
AnnaBridge 167:e84263d55307 14263 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
AnnaBridge 167:e84263d55307 14264 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
<> 144:ef7eb2e8f9f7 14265 /* Legacy defines */
<> 144:ef7eb2e8f9f7 14266 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
<> 144:ef7eb2e8f9f7 14267 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
<> 144:ef7eb2e8f9f7 14268
AnnaBridge 167:e84263d55307 14269 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 167:e84263d55307 14270 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14271 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
<> 144:ef7eb2e8f9f7 14272
<> 144:ef7eb2e8f9f7 14273 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 167:e84263d55307 14274 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 167:e84263d55307 14275 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14276 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
<> 144:ef7eb2e8f9f7 14277
<> 144:ef7eb2e8f9f7 14278
<> 144:ef7eb2e8f9f7 14279 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14280 /* */
<> 144:ef7eb2e8f9f7 14281 /* DBG */
<> 144:ef7eb2e8f9f7 14282 /* */
<> 144:ef7eb2e8f9f7 14283 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14284 /******************** Bit definition for DBGMCU_IDCODE register *************/
AnnaBridge 167:e84263d55307 14285 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 167:e84263d55307 14286 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 14287 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
AnnaBridge 167:e84263d55307 14288 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 167:e84263d55307 14289 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 14290 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
<> 144:ef7eb2e8f9f7 14291
<> 144:ef7eb2e8f9f7 14292 /******************** Bit definition for DBGMCU_CR register *****************/
AnnaBridge 167:e84263d55307 14293 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 167:e84263d55307 14294 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14295 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
AnnaBridge 167:e84263d55307 14296 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 167:e84263d55307 14297 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14298 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
AnnaBridge 167:e84263d55307 14299 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 167:e84263d55307 14300 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14301 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
AnnaBridge 167:e84263d55307 14302 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 167:e84263d55307 14303 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14304 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
AnnaBridge 167:e84263d55307 14305
AnnaBridge 167:e84263d55307 14306 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 167:e84263d55307 14307 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 14308 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
AnnaBridge 167:e84263d55307 14309 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14310 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
<> 144:ef7eb2e8f9f7 14311
<> 144:ef7eb2e8f9f7 14312 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
AnnaBridge 167:e84263d55307 14313 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 167:e84263d55307 14314 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14315 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
AnnaBridge 167:e84263d55307 14316 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 167:e84263d55307 14317 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14318 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
AnnaBridge 167:e84263d55307 14319 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 167:e84263d55307 14320 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14321 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
AnnaBridge 167:e84263d55307 14322 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 167:e84263d55307 14323 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14324 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
AnnaBridge 167:e84263d55307 14325 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 167:e84263d55307 14326 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14327 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
AnnaBridge 167:e84263d55307 14328 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 167:e84263d55307 14329 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14330 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
AnnaBridge 167:e84263d55307 14331 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
AnnaBridge 167:e84263d55307 14332 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14333 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
AnnaBridge 167:e84263d55307 14334 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
AnnaBridge 167:e84263d55307 14335 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14336 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
AnnaBridge 167:e84263d55307 14337 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 167:e84263d55307 14338 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14339 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
AnnaBridge 167:e84263d55307 14340 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 167:e84263d55307 14341 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14342 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
AnnaBridge 167:e84263d55307 14343 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 167:e84263d55307 14344 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14345 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
AnnaBridge 167:e84263d55307 14346 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 167:e84263d55307 14347 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 14348 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
AnnaBridge 167:e84263d55307 14349 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 167:e84263d55307 14350 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 14351 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
AnnaBridge 167:e84263d55307 14352 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 167:e84263d55307 14353 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 14354 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
AnnaBridge 167:e84263d55307 14355 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
AnnaBridge 167:e84263d55307 14356 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 14357 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
AnnaBridge 167:e84263d55307 14358 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
AnnaBridge 167:e84263d55307 14359 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 14360 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
AnnaBridge 167:e84263d55307 14361 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
AnnaBridge 167:e84263d55307 14362 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 14363 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
<> 144:ef7eb2e8f9f7 14364 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
<> 144:ef7eb2e8f9f7 14365 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
<> 144:ef7eb2e8f9f7 14366
<> 144:ef7eb2e8f9f7 14367 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
AnnaBridge 167:e84263d55307 14368 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
AnnaBridge 167:e84263d55307 14369 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14370 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
AnnaBridge 167:e84263d55307 14371 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
AnnaBridge 167:e84263d55307 14372 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14373 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
AnnaBridge 167:e84263d55307 14374 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
AnnaBridge 167:e84263d55307 14375 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 14376 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
AnnaBridge 167:e84263d55307 14377 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
AnnaBridge 167:e84263d55307 14378 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 14379 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
AnnaBridge 167:e84263d55307 14380 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
AnnaBridge 167:e84263d55307 14381 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 14382 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
<> 144:ef7eb2e8f9f7 14383
<> 144:ef7eb2e8f9f7 14384 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14385 /* */
<> 144:ef7eb2e8f9f7 14386 /* Ethernet MAC Registers bits definitions */
<> 144:ef7eb2e8f9f7 14387 /* */
<> 144:ef7eb2e8f9f7 14388 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14389 /* Bit definition for Ethernet MAC Control Register register */
AnnaBridge 167:e84263d55307 14390 #define ETH_MACCR_WD_Pos (23U)
AnnaBridge 167:e84263d55307 14391 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 14392 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
AnnaBridge 167:e84263d55307 14393 #define ETH_MACCR_JD_Pos (22U)
AnnaBridge 167:e84263d55307 14394 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 14395 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
AnnaBridge 167:e84263d55307 14396 #define ETH_MACCR_IFG_Pos (17U)
AnnaBridge 167:e84263d55307 14397 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 14398 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
AnnaBridge 167:e84263d55307 14399 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
AnnaBridge 167:e84263d55307 14400 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
AnnaBridge 167:e84263d55307 14401 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
AnnaBridge 167:e84263d55307 14402 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
AnnaBridge 167:e84263d55307 14403 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
AnnaBridge 167:e84263d55307 14404 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
AnnaBridge 167:e84263d55307 14405 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
AnnaBridge 167:e84263d55307 14406 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
AnnaBridge 167:e84263d55307 14407 #define ETH_MACCR_CSD_Pos (16U)
AnnaBridge 167:e84263d55307 14408 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 14409 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
AnnaBridge 167:e84263d55307 14410 #define ETH_MACCR_FES_Pos (14U)
AnnaBridge 167:e84263d55307 14411 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 14412 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
AnnaBridge 167:e84263d55307 14413 #define ETH_MACCR_ROD_Pos (13U)
AnnaBridge 167:e84263d55307 14414 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 14415 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
AnnaBridge 167:e84263d55307 14416 #define ETH_MACCR_LM_Pos (12U)
AnnaBridge 167:e84263d55307 14417 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 14418 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
AnnaBridge 167:e84263d55307 14419 #define ETH_MACCR_DM_Pos (11U)
AnnaBridge 167:e84263d55307 14420 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14421 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
AnnaBridge 167:e84263d55307 14422 #define ETH_MACCR_IPCO_Pos (10U)
AnnaBridge 167:e84263d55307 14423 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14424 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
AnnaBridge 167:e84263d55307 14425 #define ETH_MACCR_RD_Pos (9U)
AnnaBridge 167:e84263d55307 14426 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14427 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
AnnaBridge 167:e84263d55307 14428 #define ETH_MACCR_APCS_Pos (7U)
AnnaBridge 167:e84263d55307 14429 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14430 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
AnnaBridge 167:e84263d55307 14431 #define ETH_MACCR_BL_Pos (5U)
AnnaBridge 167:e84263d55307 14432 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
AnnaBridge 167:e84263d55307 14433 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
<> 144:ef7eb2e8f9f7 14434 a transmission attempt during retries after a collision: 0 =< r <2^k */
AnnaBridge 167:e84263d55307 14435 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
AnnaBridge 167:e84263d55307 14436 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
AnnaBridge 167:e84263d55307 14437 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
AnnaBridge 167:e84263d55307 14438 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
AnnaBridge 167:e84263d55307 14439 #define ETH_MACCR_DC_Pos (4U)
AnnaBridge 167:e84263d55307 14440 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14441 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
AnnaBridge 167:e84263d55307 14442 #define ETH_MACCR_TE_Pos (3U)
AnnaBridge 167:e84263d55307 14443 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14444 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
AnnaBridge 167:e84263d55307 14445 #define ETH_MACCR_RE_Pos (2U)
AnnaBridge 167:e84263d55307 14446 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14447 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
<> 144:ef7eb2e8f9f7 14448
<> 144:ef7eb2e8f9f7 14449 /* Bit definition for Ethernet MAC Frame Filter Register */
AnnaBridge 167:e84263d55307 14450 #define ETH_MACFFR_RA_Pos (31U)
AnnaBridge 167:e84263d55307 14451 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14452 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
AnnaBridge 167:e84263d55307 14453 #define ETH_MACFFR_HPF_Pos (10U)
AnnaBridge 167:e84263d55307 14454 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14455 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
AnnaBridge 167:e84263d55307 14456 #define ETH_MACFFR_SAF_Pos (9U)
AnnaBridge 167:e84263d55307 14457 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14458 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
AnnaBridge 167:e84263d55307 14459 #define ETH_MACFFR_SAIF_Pos (8U)
AnnaBridge 167:e84263d55307 14460 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14461 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
AnnaBridge 167:e84263d55307 14462 #define ETH_MACFFR_PCF_Pos (6U)
AnnaBridge 167:e84263d55307 14463 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 14464 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
AnnaBridge 167:e84263d55307 14465 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
AnnaBridge 167:e84263d55307 14466 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14467 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
AnnaBridge 167:e84263d55307 14468 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
AnnaBridge 167:e84263d55307 14469 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14470 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 167:e84263d55307 14471 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
AnnaBridge 167:e84263d55307 14472 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
AnnaBridge 167:e84263d55307 14473 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
AnnaBridge 167:e84263d55307 14474 #define ETH_MACFFR_BFD_Pos (5U)
AnnaBridge 167:e84263d55307 14475 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14476 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
AnnaBridge 167:e84263d55307 14477 #define ETH_MACFFR_PAM_Pos (4U)
AnnaBridge 167:e84263d55307 14478 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14479 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
AnnaBridge 167:e84263d55307 14480 #define ETH_MACFFR_DAIF_Pos (3U)
AnnaBridge 167:e84263d55307 14481 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14482 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
AnnaBridge 167:e84263d55307 14483 #define ETH_MACFFR_HM_Pos (2U)
AnnaBridge 167:e84263d55307 14484 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14485 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
AnnaBridge 167:e84263d55307 14486 #define ETH_MACFFR_HU_Pos (1U)
AnnaBridge 167:e84263d55307 14487 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14488 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
AnnaBridge 167:e84263d55307 14489 #define ETH_MACFFR_PM_Pos (0U)
AnnaBridge 167:e84263d55307 14490 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14491 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
<> 144:ef7eb2e8f9f7 14492
<> 144:ef7eb2e8f9f7 14493 /* Bit definition for Ethernet MAC Hash Table High Register */
AnnaBridge 167:e84263d55307 14494 #define ETH_MACHTHR_HTH_Pos (0U)
AnnaBridge 167:e84263d55307 14495 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14496 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
<> 144:ef7eb2e8f9f7 14497
<> 144:ef7eb2e8f9f7 14498 /* Bit definition for Ethernet MAC Hash Table Low Register */
AnnaBridge 167:e84263d55307 14499 #define ETH_MACHTLR_HTL_Pos (0U)
AnnaBridge 167:e84263d55307 14500 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14501 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
<> 144:ef7eb2e8f9f7 14502
<> 144:ef7eb2e8f9f7 14503 /* Bit definition for Ethernet MAC MII Address Register */
AnnaBridge 167:e84263d55307 14504 #define ETH_MACMIIAR_PA_Pos (11U)
AnnaBridge 167:e84263d55307 14505 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
AnnaBridge 167:e84263d55307 14506 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
AnnaBridge 167:e84263d55307 14507 #define ETH_MACMIIAR_MR_Pos (6U)
AnnaBridge 167:e84263d55307 14508 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
AnnaBridge 167:e84263d55307 14509 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
AnnaBridge 167:e84263d55307 14510 #define ETH_MACMIIAR_CR_Pos (2U)
AnnaBridge 167:e84263d55307 14511 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
AnnaBridge 167:e84263d55307 14512 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
AnnaBridge 167:e84263d55307 14513 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
AnnaBridge 167:e84263d55307 14514 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
AnnaBridge 167:e84263d55307 14515 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14516 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
AnnaBridge 167:e84263d55307 14517 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
AnnaBridge 167:e84263d55307 14518 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14519 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
AnnaBridge 167:e84263d55307 14520 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
AnnaBridge 167:e84263d55307 14521 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
AnnaBridge 167:e84263d55307 14522 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
AnnaBridge 167:e84263d55307 14523 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
AnnaBridge 167:e84263d55307 14524 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14525 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
AnnaBridge 167:e84263d55307 14526 #define ETH_MACMIIAR_MW_Pos (1U)
AnnaBridge 167:e84263d55307 14527 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14528 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
AnnaBridge 167:e84263d55307 14529 #define ETH_MACMIIAR_MB_Pos (0U)
AnnaBridge 167:e84263d55307 14530 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14531 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
AnnaBridge 167:e84263d55307 14532
<> 144:ef7eb2e8f9f7 14533 /* Bit definition for Ethernet MAC MII Data Register */
AnnaBridge 167:e84263d55307 14534 #define ETH_MACMIIDR_MD_Pos (0U)
AnnaBridge 167:e84263d55307 14535 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14536 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
<> 144:ef7eb2e8f9f7 14537
<> 144:ef7eb2e8f9f7 14538 /* Bit definition for Ethernet MAC Flow Control Register */
AnnaBridge 167:e84263d55307 14539 #define ETH_MACFCR_PT_Pos (16U)
AnnaBridge 167:e84263d55307 14540 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 14541 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
AnnaBridge 167:e84263d55307 14542 #define ETH_MACFCR_ZQPD_Pos (7U)
AnnaBridge 167:e84263d55307 14543 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 14544 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
AnnaBridge 167:e84263d55307 14545 #define ETH_MACFCR_PLT_Pos (4U)
AnnaBridge 167:e84263d55307 14546 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 14547 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
AnnaBridge 167:e84263d55307 14548 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
AnnaBridge 167:e84263d55307 14549 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
AnnaBridge 167:e84263d55307 14550 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14551 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
AnnaBridge 167:e84263d55307 14552 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
AnnaBridge 167:e84263d55307 14553 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14554 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
AnnaBridge 167:e84263d55307 14555 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
AnnaBridge 167:e84263d55307 14556 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
AnnaBridge 167:e84263d55307 14557 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
AnnaBridge 167:e84263d55307 14558 #define ETH_MACFCR_UPFD_Pos (3U)
AnnaBridge 167:e84263d55307 14559 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14560 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
AnnaBridge 167:e84263d55307 14561 #define ETH_MACFCR_RFCE_Pos (2U)
AnnaBridge 167:e84263d55307 14562 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14563 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
AnnaBridge 167:e84263d55307 14564 #define ETH_MACFCR_TFCE_Pos (1U)
AnnaBridge 167:e84263d55307 14565 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14566 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
AnnaBridge 167:e84263d55307 14567 #define ETH_MACFCR_FCBBPA_Pos (0U)
AnnaBridge 167:e84263d55307 14568 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14569 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
<> 144:ef7eb2e8f9f7 14570
<> 144:ef7eb2e8f9f7 14571 /* Bit definition for Ethernet MAC VLAN Tag Register */
AnnaBridge 167:e84263d55307 14572 #define ETH_MACVLANTR_VLANTC_Pos (16U)
AnnaBridge 167:e84263d55307 14573 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 14574 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
AnnaBridge 167:e84263d55307 14575 #define ETH_MACVLANTR_VLANTI_Pos (0U)
AnnaBridge 167:e84263d55307 14576 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14577 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
<> 144:ef7eb2e8f9f7 14578
<> 144:ef7eb2e8f9f7 14579 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
AnnaBridge 167:e84263d55307 14580 #define ETH_MACRWUFFR_D_Pos (0U)
AnnaBridge 167:e84263d55307 14581 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14582 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
<> 144:ef7eb2e8f9f7 14583 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
<> 144:ef7eb2e8f9f7 14584 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
<> 144:ef7eb2e8f9f7 14585 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
<> 144:ef7eb2e8f9f7 14586 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
<> 144:ef7eb2e8f9f7 14587 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
<> 144:ef7eb2e8f9f7 14588 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
<> 144:ef7eb2e8f9f7 14589 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
<> 144:ef7eb2e8f9f7 14590 RSVD - Filter1 Command - RSVD - Filter0 Command
<> 144:ef7eb2e8f9f7 14591 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
<> 144:ef7eb2e8f9f7 14592 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
<> 144:ef7eb2e8f9f7 14593 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
<> 144:ef7eb2e8f9f7 14594
<> 144:ef7eb2e8f9f7 14595 /* Bit definition for Ethernet MAC PMT Control and Status Register */
AnnaBridge 167:e84263d55307 14596 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
AnnaBridge 167:e84263d55307 14597 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14598 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 167:e84263d55307 14599 #define ETH_MACPMTCSR_GU_Pos (9U)
AnnaBridge 167:e84263d55307 14600 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14601 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
AnnaBridge 167:e84263d55307 14602 #define ETH_MACPMTCSR_WFR_Pos (6U)
AnnaBridge 167:e84263d55307 14603 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14604 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
AnnaBridge 167:e84263d55307 14605 #define ETH_MACPMTCSR_MPR_Pos (5U)
AnnaBridge 167:e84263d55307 14606 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14607 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
AnnaBridge 167:e84263d55307 14608 #define ETH_MACPMTCSR_WFE_Pos (2U)
AnnaBridge 167:e84263d55307 14609 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14610 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
AnnaBridge 167:e84263d55307 14611 #define ETH_MACPMTCSR_MPE_Pos (1U)
AnnaBridge 167:e84263d55307 14612 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14613 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
AnnaBridge 167:e84263d55307 14614 #define ETH_MACPMTCSR_PD_Pos (0U)
AnnaBridge 167:e84263d55307 14615 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14616 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
AnnaBridge 167:e84263d55307 14617
AnnaBridge 167:e84263d55307 14618 /* Bit definition for Ethernet MAC debug Register */
AnnaBridge 167:e84263d55307 14619 #define ETH_MACDBGR_TFF_Pos (25U)
AnnaBridge 167:e84263d55307 14620 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 14621 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
AnnaBridge 167:e84263d55307 14622 #define ETH_MACDBGR_TFNE_Pos (24U)
AnnaBridge 167:e84263d55307 14623 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 14624 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
AnnaBridge 167:e84263d55307 14625 #define ETH_MACDBGR_TFWA_Pos (22U)
AnnaBridge 167:e84263d55307 14626 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 14627 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
AnnaBridge 167:e84263d55307 14628 #define ETH_MACDBGR_TFRS_Pos (20U)
AnnaBridge 167:e84263d55307 14629 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 14630 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
AnnaBridge 167:e84263d55307 14631 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
AnnaBridge 167:e84263d55307 14632 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 14633 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge 167:e84263d55307 14634 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
AnnaBridge 167:e84263d55307 14635 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 14636 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
AnnaBridge 167:e84263d55307 14637 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
AnnaBridge 167:e84263d55307 14638 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 14639 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
AnnaBridge 167:e84263d55307 14640 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
AnnaBridge 167:e84263d55307 14641 #define ETH_MACDBGR_MTP_Pos (19U)
AnnaBridge 167:e84263d55307 14642 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 14643 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
AnnaBridge 167:e84263d55307 14644 #define ETH_MACDBGR_MTFCS_Pos (17U)
AnnaBridge 167:e84263d55307 14645 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
AnnaBridge 167:e84263d55307 14646 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
AnnaBridge 167:e84263d55307 14647 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
AnnaBridge 167:e84263d55307 14648 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
AnnaBridge 167:e84263d55307 14649 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
AnnaBridge 167:e84263d55307 14650 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
AnnaBridge 167:e84263d55307 14651 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 14652 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge 167:e84263d55307 14653 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
AnnaBridge 167:e84263d55307 14654 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 14655 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge 167:e84263d55307 14656 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
AnnaBridge 167:e84263d55307 14657 #define ETH_MACDBGR_MMTEA_Pos (16U)
AnnaBridge 167:e84263d55307 14658 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 14659 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
AnnaBridge 167:e84263d55307 14660 #define ETH_MACDBGR_RFFL_Pos (8U)
AnnaBridge 167:e84263d55307 14661 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 14662 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
AnnaBridge 167:e84263d55307 14663 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
AnnaBridge 167:e84263d55307 14664 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
AnnaBridge 167:e84263d55307 14665 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
AnnaBridge 167:e84263d55307 14666 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
AnnaBridge 167:e84263d55307 14667 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14668 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
AnnaBridge 167:e84263d55307 14669 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
AnnaBridge 167:e84263d55307 14670 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14671 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
AnnaBridge 167:e84263d55307 14672 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
AnnaBridge 167:e84263d55307 14673 #define ETH_MACDBGR_RFRCS_Pos (5U)
AnnaBridge 167:e84263d55307 14674 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
AnnaBridge 167:e84263d55307 14675 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
AnnaBridge 167:e84263d55307 14676 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
AnnaBridge 167:e84263d55307 14677 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
AnnaBridge 167:e84263d55307 14678 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
AnnaBridge 167:e84263d55307 14679 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
AnnaBridge 167:e84263d55307 14680 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14681 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
AnnaBridge 167:e84263d55307 14682 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
AnnaBridge 167:e84263d55307 14683 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14684 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
AnnaBridge 167:e84263d55307 14685 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
AnnaBridge 167:e84263d55307 14686 #define ETH_MACDBGR_RFWRA_Pos (4U)
AnnaBridge 167:e84263d55307 14687 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14688 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
AnnaBridge 167:e84263d55307 14689 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
AnnaBridge 167:e84263d55307 14690 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
AnnaBridge 167:e84263d55307 14691 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
AnnaBridge 167:e84263d55307 14692 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14693 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14694 #define ETH_MACDBGR_MMRPEA_Pos (0U)
AnnaBridge 167:e84263d55307 14695 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14696 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
<> 144:ef7eb2e8f9f7 14697
<> 144:ef7eb2e8f9f7 14698 /* Bit definition for Ethernet MAC Status Register */
AnnaBridge 167:e84263d55307 14699 #define ETH_MACSR_TSTS_Pos (9U)
AnnaBridge 167:e84263d55307 14700 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14701 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
AnnaBridge 167:e84263d55307 14702 #define ETH_MACSR_MMCTS_Pos (6U)
AnnaBridge 167:e84263d55307 14703 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14704 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
AnnaBridge 167:e84263d55307 14705 #define ETH_MACSR_MMMCRS_Pos (5U)
AnnaBridge 167:e84263d55307 14706 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14707 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
AnnaBridge 167:e84263d55307 14708 #define ETH_MACSR_MMCS_Pos (4U)
AnnaBridge 167:e84263d55307 14709 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14710 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
AnnaBridge 167:e84263d55307 14711 #define ETH_MACSR_PMTS_Pos (3U)
AnnaBridge 167:e84263d55307 14712 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14713 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
<> 144:ef7eb2e8f9f7 14714
<> 144:ef7eb2e8f9f7 14715 /* Bit definition for Ethernet MAC Interrupt Mask Register */
AnnaBridge 167:e84263d55307 14716 #define ETH_MACIMR_TSTIM_Pos (9U)
AnnaBridge 167:e84263d55307 14717 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14718 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
AnnaBridge 167:e84263d55307 14719 #define ETH_MACIMR_PMTIM_Pos (3U)
AnnaBridge 167:e84263d55307 14720 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14721 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
<> 144:ef7eb2e8f9f7 14722
<> 144:ef7eb2e8f9f7 14723 /* Bit definition for Ethernet MAC Address0 High Register */
AnnaBridge 167:e84263d55307 14724 #define ETH_MACA0HR_MACA0H_Pos (0U)
AnnaBridge 167:e84263d55307 14725 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14726 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
<> 144:ef7eb2e8f9f7 14727
<> 144:ef7eb2e8f9f7 14728 /* Bit definition for Ethernet MAC Address0 Low Register */
AnnaBridge 167:e84263d55307 14729 #define ETH_MACA0LR_MACA0L_Pos (0U)
AnnaBridge 167:e84263d55307 14730 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14731 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
<> 144:ef7eb2e8f9f7 14732
<> 144:ef7eb2e8f9f7 14733 /* Bit definition for Ethernet MAC Address1 High Register */
AnnaBridge 167:e84263d55307 14734 #define ETH_MACA1HR_AE_Pos (31U)
AnnaBridge 167:e84263d55307 14735 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14736 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
AnnaBridge 167:e84263d55307 14737 #define ETH_MACA1HR_SA_Pos (30U)
AnnaBridge 167:e84263d55307 14738 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 14739 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
AnnaBridge 167:e84263d55307 14740 #define ETH_MACA1HR_MBC_Pos (24U)
AnnaBridge 167:e84263d55307 14741 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 167:e84263d55307 14742 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
AnnaBridge 167:e84263d55307 14743 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 167:e84263d55307 14744 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 167:e84263d55307 14745 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 167:e84263d55307 14746 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 167:e84263d55307 14747 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 167:e84263d55307 14748 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
AnnaBridge 167:e84263d55307 14749 #define ETH_MACA1HR_MACA1H_Pos (0U)
AnnaBridge 167:e84263d55307 14750 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14751 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
<> 144:ef7eb2e8f9f7 14752
<> 144:ef7eb2e8f9f7 14753 /* Bit definition for Ethernet MAC Address1 Low Register */
AnnaBridge 167:e84263d55307 14754 #define ETH_MACA1LR_MACA1L_Pos (0U)
AnnaBridge 167:e84263d55307 14755 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14756 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
<> 144:ef7eb2e8f9f7 14757
<> 144:ef7eb2e8f9f7 14758 /* Bit definition for Ethernet MAC Address2 High Register */
AnnaBridge 167:e84263d55307 14759 #define ETH_MACA2HR_AE_Pos (31U)
AnnaBridge 167:e84263d55307 14760 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14761 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
AnnaBridge 167:e84263d55307 14762 #define ETH_MACA2HR_SA_Pos (30U)
AnnaBridge 167:e84263d55307 14763 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 14764 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
AnnaBridge 167:e84263d55307 14765 #define ETH_MACA2HR_MBC_Pos (24U)
AnnaBridge 167:e84263d55307 14766 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 167:e84263d55307 14767 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
AnnaBridge 167:e84263d55307 14768 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 167:e84263d55307 14769 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 167:e84263d55307 14770 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 167:e84263d55307 14771 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 167:e84263d55307 14772 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 167:e84263d55307 14773 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 167:e84263d55307 14774 #define ETH_MACA2HR_MACA2H_Pos (0U)
AnnaBridge 167:e84263d55307 14775 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14776 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
<> 144:ef7eb2e8f9f7 14777
<> 144:ef7eb2e8f9f7 14778 /* Bit definition for Ethernet MAC Address2 Low Register */
AnnaBridge 167:e84263d55307 14779 #define ETH_MACA2LR_MACA2L_Pos (0U)
AnnaBridge 167:e84263d55307 14780 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14781 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
<> 144:ef7eb2e8f9f7 14782
<> 144:ef7eb2e8f9f7 14783 /* Bit definition for Ethernet MAC Address3 High Register */
AnnaBridge 167:e84263d55307 14784 #define ETH_MACA3HR_AE_Pos (31U)
AnnaBridge 167:e84263d55307 14785 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14786 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
AnnaBridge 167:e84263d55307 14787 #define ETH_MACA3HR_SA_Pos (30U)
AnnaBridge 167:e84263d55307 14788 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 14789 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
AnnaBridge 167:e84263d55307 14790 #define ETH_MACA3HR_MBC_Pos (24U)
AnnaBridge 167:e84263d55307 14791 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
AnnaBridge 167:e84263d55307 14792 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
AnnaBridge 167:e84263d55307 14793 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
AnnaBridge 167:e84263d55307 14794 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
AnnaBridge 167:e84263d55307 14795 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
AnnaBridge 167:e84263d55307 14796 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
AnnaBridge 167:e84263d55307 14797 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
AnnaBridge 167:e84263d55307 14798 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
AnnaBridge 167:e84263d55307 14799 #define ETH_MACA3HR_MACA3H_Pos (0U)
AnnaBridge 167:e84263d55307 14800 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 14801 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
<> 144:ef7eb2e8f9f7 14802
<> 144:ef7eb2e8f9f7 14803 /* Bit definition for Ethernet MAC Address3 Low Register */
AnnaBridge 167:e84263d55307 14804 #define ETH_MACA3LR_MACA3L_Pos (0U)
AnnaBridge 167:e84263d55307 14805 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14806 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
<> 144:ef7eb2e8f9f7 14807
<> 144:ef7eb2e8f9f7 14808 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14809 /* Ethernet MMC Registers bits definition */
<> 144:ef7eb2e8f9f7 14810 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14811
<> 144:ef7eb2e8f9f7 14812 /* Bit definition for Ethernet MMC Contol Register */
AnnaBridge 167:e84263d55307 14813 #define ETH_MMCCR_MCFHP_Pos (5U)
AnnaBridge 167:e84263d55307 14814 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14815 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
AnnaBridge 167:e84263d55307 14816 #define ETH_MMCCR_MCP_Pos (4U)
AnnaBridge 167:e84263d55307 14817 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14818 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
AnnaBridge 167:e84263d55307 14819 #define ETH_MMCCR_MCF_Pos (3U)
AnnaBridge 167:e84263d55307 14820 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14821 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
AnnaBridge 167:e84263d55307 14822 #define ETH_MMCCR_ROR_Pos (2U)
AnnaBridge 167:e84263d55307 14823 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14824 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
AnnaBridge 167:e84263d55307 14825 #define ETH_MMCCR_CSR_Pos (1U)
AnnaBridge 167:e84263d55307 14826 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14827 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
AnnaBridge 167:e84263d55307 14828 #define ETH_MMCCR_CR_Pos (0U)
AnnaBridge 167:e84263d55307 14829 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14830 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
<> 144:ef7eb2e8f9f7 14831
<> 144:ef7eb2e8f9f7 14832 /* Bit definition for Ethernet MMC Receive Interrupt Register */
AnnaBridge 167:e84263d55307 14833 #define ETH_MMCRIR_RGUFS_Pos (17U)
AnnaBridge 167:e84263d55307 14834 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 14835 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14836 #define ETH_MMCRIR_RFAES_Pos (6U)
AnnaBridge 167:e84263d55307 14837 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14838 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14839 #define ETH_MMCRIR_RFCES_Pos (5U)
AnnaBridge 167:e84263d55307 14840 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14841 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 14842
<> 144:ef7eb2e8f9f7 14843 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
AnnaBridge 167:e84263d55307 14844 #define ETH_MMCTIR_TGFS_Pos (21U)
AnnaBridge 167:e84263d55307 14845 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 14846 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14847 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
AnnaBridge 167:e84263d55307 14848 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 14849 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14850 #define ETH_MMCTIR_TGFSCS_Pos (14U)
AnnaBridge 167:e84263d55307 14851 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 14852 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 14853
<> 144:ef7eb2e8f9f7 14854 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
AnnaBridge 167:e84263d55307 14855 #define ETH_MMCRIMR_RGUFM_Pos (17U)
AnnaBridge 167:e84263d55307 14856 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 14857 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14858 #define ETH_MMCRIMR_RFAEM_Pos (6U)
AnnaBridge 167:e84263d55307 14859 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 14860 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14861 #define ETH_MMCRIMR_RFCEM_Pos (5U)
AnnaBridge 167:e84263d55307 14862 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14863 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 14864
<> 144:ef7eb2e8f9f7 14865 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
AnnaBridge 167:e84263d55307 14866 #define ETH_MMCTIMR_TGFM_Pos (21U)
AnnaBridge 167:e84263d55307 14867 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 14868 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14869 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
AnnaBridge 167:e84263d55307 14870 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 14871 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
AnnaBridge 167:e84263d55307 14872 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
AnnaBridge 167:e84263d55307 14873 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 14874 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 14875
<> 144:ef7eb2e8f9f7 14876 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
AnnaBridge 167:e84263d55307 14877 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
AnnaBridge 167:e84263d55307 14878 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14879 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 14880
<> 144:ef7eb2e8f9f7 14881 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
AnnaBridge 167:e84263d55307 14882 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
AnnaBridge 167:e84263d55307 14883 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14884 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
<> 144:ef7eb2e8f9f7 14885
<> 144:ef7eb2e8f9f7 14886 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
AnnaBridge 167:e84263d55307 14887 #define ETH_MMCTGFCR_TGFC_Pos (0U)
AnnaBridge 167:e84263d55307 14888 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14889 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
<> 144:ef7eb2e8f9f7 14890
<> 144:ef7eb2e8f9f7 14891 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
AnnaBridge 167:e84263d55307 14892 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
AnnaBridge 167:e84263d55307 14893 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14894 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
<> 144:ef7eb2e8f9f7 14895
<> 144:ef7eb2e8f9f7 14896 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
AnnaBridge 167:e84263d55307 14897 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
AnnaBridge 167:e84263d55307 14898 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14899 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
<> 144:ef7eb2e8f9f7 14900
<> 144:ef7eb2e8f9f7 14901 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
AnnaBridge 167:e84263d55307 14902 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
AnnaBridge 167:e84263d55307 14903 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14904 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
<> 144:ef7eb2e8f9f7 14905
<> 144:ef7eb2e8f9f7 14906 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14907 /* Ethernet PTP Registers bits definition */
<> 144:ef7eb2e8f9f7 14908 /******************************************************************************/
<> 144:ef7eb2e8f9f7 14909
<> 144:ef7eb2e8f9f7 14910 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
AnnaBridge 167:e84263d55307 14911 #define ETH_PTPTSCR_TSCNT_Pos (16U)
AnnaBridge 167:e84263d55307 14912 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
AnnaBridge 167:e84263d55307 14913 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
AnnaBridge 167:e84263d55307 14914 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
AnnaBridge 167:e84263d55307 14915 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 14916 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
AnnaBridge 167:e84263d55307 14917 #define ETH_PTPTSSR_TSSEME_Pos (14U)
AnnaBridge 167:e84263d55307 14918 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 14919 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
AnnaBridge 167:e84263d55307 14920 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
AnnaBridge 167:e84263d55307 14921 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 14922 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
AnnaBridge 167:e84263d55307 14923 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
AnnaBridge 167:e84263d55307 14924 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 14925 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
AnnaBridge 167:e84263d55307 14926 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
AnnaBridge 167:e84263d55307 14927 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 14928 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
AnnaBridge 167:e84263d55307 14929 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
AnnaBridge 167:e84263d55307 14930 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 14931 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
AnnaBridge 167:e84263d55307 14932 #define ETH_PTPTSSR_TSSSR_Pos (9U)
AnnaBridge 167:e84263d55307 14933 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 14934 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
AnnaBridge 167:e84263d55307 14935 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
AnnaBridge 167:e84263d55307 14936 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 14937 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
AnnaBridge 167:e84263d55307 14938
AnnaBridge 167:e84263d55307 14939 #define ETH_PTPTSCR_TSARU_Pos (5U)
AnnaBridge 167:e84263d55307 14940 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 14941 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
AnnaBridge 167:e84263d55307 14942 #define ETH_PTPTSCR_TSITE_Pos (4U)
AnnaBridge 167:e84263d55307 14943 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 14944 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
AnnaBridge 167:e84263d55307 14945 #define ETH_PTPTSCR_TSSTU_Pos (3U)
AnnaBridge 167:e84263d55307 14946 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 14947 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
AnnaBridge 167:e84263d55307 14948 #define ETH_PTPTSCR_TSSTI_Pos (2U)
AnnaBridge 167:e84263d55307 14949 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 14950 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
AnnaBridge 167:e84263d55307 14951 #define ETH_PTPTSCR_TSFCU_Pos (1U)
AnnaBridge 167:e84263d55307 14952 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 14953 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
AnnaBridge 167:e84263d55307 14954 #define ETH_PTPTSCR_TSE_Pos (0U)
AnnaBridge 167:e84263d55307 14955 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 14956 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
<> 144:ef7eb2e8f9f7 14957
<> 144:ef7eb2e8f9f7 14958 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
AnnaBridge 167:e84263d55307 14959 #define ETH_PTPSSIR_STSSI_Pos (0U)
AnnaBridge 167:e84263d55307 14960 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
AnnaBridge 167:e84263d55307 14961 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
<> 144:ef7eb2e8f9f7 14962
<> 144:ef7eb2e8f9f7 14963 /* Bit definition for Ethernet PTP Time Stamp High Register */
AnnaBridge 167:e84263d55307 14964 #define ETH_PTPTSHR_STS_Pos (0U)
AnnaBridge 167:e84263d55307 14965 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14966 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
<> 144:ef7eb2e8f9f7 14967
<> 144:ef7eb2e8f9f7 14968 /* Bit definition for Ethernet PTP Time Stamp Low Register */
AnnaBridge 167:e84263d55307 14969 #define ETH_PTPTSLR_STPNS_Pos (31U)
AnnaBridge 167:e84263d55307 14970 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14971 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
AnnaBridge 167:e84263d55307 14972 #define ETH_PTPTSLR_STSS_Pos (0U)
AnnaBridge 167:e84263d55307 14973 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 167:e84263d55307 14974 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
<> 144:ef7eb2e8f9f7 14975
<> 144:ef7eb2e8f9f7 14976 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
AnnaBridge 167:e84263d55307 14977 #define ETH_PTPTSHUR_TSUS_Pos (0U)
AnnaBridge 167:e84263d55307 14978 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14979 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
<> 144:ef7eb2e8f9f7 14980
<> 144:ef7eb2e8f9f7 14981 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
AnnaBridge 167:e84263d55307 14982 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
AnnaBridge 167:e84263d55307 14983 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 14984 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
AnnaBridge 167:e84263d55307 14985 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
AnnaBridge 167:e84263d55307 14986 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
AnnaBridge 167:e84263d55307 14987 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
<> 144:ef7eb2e8f9f7 14988
<> 144:ef7eb2e8f9f7 14989 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
AnnaBridge 167:e84263d55307 14990 #define ETH_PTPTSAR_TSA_Pos (0U)
AnnaBridge 167:e84263d55307 14991 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14992 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
<> 144:ef7eb2e8f9f7 14993
<> 144:ef7eb2e8f9f7 14994 /* Bit definition for Ethernet PTP Target Time High Register */
AnnaBridge 167:e84263d55307 14995 #define ETH_PTPTTHR_TTSH_Pos (0U)
AnnaBridge 167:e84263d55307 14996 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 14997 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
<> 144:ef7eb2e8f9f7 14998
<> 144:ef7eb2e8f9f7 14999 /* Bit definition for Ethernet PTP Target Time Low Register */
AnnaBridge 167:e84263d55307 15000 #define ETH_PTPTTLR_TTSL_Pos (0U)
AnnaBridge 167:e84263d55307 15001 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15002 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
<> 144:ef7eb2e8f9f7 15003
<> 144:ef7eb2e8f9f7 15004 /* Bit definition for Ethernet PTP Time Stamp Status Register */
AnnaBridge 167:e84263d55307 15005 #define ETH_PTPTSSR_TSTTR_Pos (5U)
AnnaBridge 167:e84263d55307 15006 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15007 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
AnnaBridge 167:e84263d55307 15008 #define ETH_PTPTSSR_TSSO_Pos (4U)
AnnaBridge 167:e84263d55307 15009 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15010 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
<> 144:ef7eb2e8f9f7 15011
<> 144:ef7eb2e8f9f7 15012 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15013 /* Ethernet DMA Registers bits definition */
<> 144:ef7eb2e8f9f7 15014 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15015
<> 144:ef7eb2e8f9f7 15016 /* Bit definition for Ethernet DMA Bus Mode Register */
AnnaBridge 167:e84263d55307 15017 #define ETH_DMABMR_AAB_Pos (25U)
AnnaBridge 167:e84263d55307 15018 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15019 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
AnnaBridge 167:e84263d55307 15020 #define ETH_DMABMR_FPM_Pos (24U)
AnnaBridge 167:e84263d55307 15021 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15022 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
AnnaBridge 167:e84263d55307 15023 #define ETH_DMABMR_USP_Pos (23U)
AnnaBridge 167:e84263d55307 15024 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15025 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
AnnaBridge 167:e84263d55307 15026 #define ETH_DMABMR_RDP_Pos (17U)
AnnaBridge 167:e84263d55307 15027 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
AnnaBridge 167:e84263d55307 15028 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
AnnaBridge 167:e84263d55307 15029 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 167:e84263d55307 15030 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 167:e84263d55307 15031 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 167:e84263d55307 15032 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 167:e84263d55307 15033 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 167:e84263d55307 15034 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 167:e84263d55307 15035 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 167:e84263d55307 15036 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 167:e84263d55307 15037 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 167:e84263d55307 15038 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 167:e84263d55307 15039 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 167:e84263d55307 15040 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
AnnaBridge 167:e84263d55307 15041 #define ETH_DMABMR_FB_Pos (16U)
AnnaBridge 167:e84263d55307 15042 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15043 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
AnnaBridge 167:e84263d55307 15044 #define ETH_DMABMR_RTPR_Pos (14U)
AnnaBridge 167:e84263d55307 15045 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 15046 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
AnnaBridge 167:e84263d55307 15047 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
AnnaBridge 167:e84263d55307 15048 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
AnnaBridge 167:e84263d55307 15049 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
AnnaBridge 167:e84263d55307 15050 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
AnnaBridge 167:e84263d55307 15051 #define ETH_DMABMR_PBL_Pos (8U)
AnnaBridge 167:e84263d55307 15052 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
AnnaBridge 167:e84263d55307 15053 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
AnnaBridge 167:e84263d55307 15054 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 167:e84263d55307 15055 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 167:e84263d55307 15056 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 167:e84263d55307 15057 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 167:e84263d55307 15058 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 167:e84263d55307 15059 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 167:e84263d55307 15060 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 167:e84263d55307 15061 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 167:e84263d55307 15062 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 167:e84263d55307 15063 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 167:e84263d55307 15064 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 167:e84263d55307 15065 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
AnnaBridge 167:e84263d55307 15066 #define ETH_DMABMR_EDE_Pos (7U)
AnnaBridge 167:e84263d55307 15067 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15068 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
AnnaBridge 167:e84263d55307 15069 #define ETH_DMABMR_DSL_Pos (2U)
AnnaBridge 167:e84263d55307 15070 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
AnnaBridge 167:e84263d55307 15071 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
AnnaBridge 167:e84263d55307 15072 #define ETH_DMABMR_DA_Pos (1U)
AnnaBridge 167:e84263d55307 15073 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15074 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
AnnaBridge 167:e84263d55307 15075 #define ETH_DMABMR_SR_Pos (0U)
AnnaBridge 167:e84263d55307 15076 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15077 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
<> 144:ef7eb2e8f9f7 15078
<> 144:ef7eb2e8f9f7 15079 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
AnnaBridge 167:e84263d55307 15080 #define ETH_DMATPDR_TPD_Pos (0U)
AnnaBridge 167:e84263d55307 15081 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15082 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
<> 144:ef7eb2e8f9f7 15083
<> 144:ef7eb2e8f9f7 15084 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
AnnaBridge 167:e84263d55307 15085 #define ETH_DMARPDR_RPD_Pos (0U)
AnnaBridge 167:e84263d55307 15086 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15087 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
<> 144:ef7eb2e8f9f7 15088
<> 144:ef7eb2e8f9f7 15089 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
AnnaBridge 167:e84263d55307 15090 #define ETH_DMARDLAR_SRL_Pos (0U)
AnnaBridge 167:e84263d55307 15091 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15092 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
<> 144:ef7eb2e8f9f7 15093
<> 144:ef7eb2e8f9f7 15094 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
AnnaBridge 167:e84263d55307 15095 #define ETH_DMATDLAR_STL_Pos (0U)
AnnaBridge 167:e84263d55307 15096 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15097 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
<> 144:ef7eb2e8f9f7 15098
<> 144:ef7eb2e8f9f7 15099 /* Bit definition for Ethernet DMA Status Register */
AnnaBridge 167:e84263d55307 15100 #define ETH_DMASR_TSTS_Pos (29U)
AnnaBridge 167:e84263d55307 15101 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 15102 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
AnnaBridge 167:e84263d55307 15103 #define ETH_DMASR_PMTS_Pos (28U)
AnnaBridge 167:e84263d55307 15104 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 15105 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
AnnaBridge 167:e84263d55307 15106 #define ETH_DMASR_MMCS_Pos (27U)
AnnaBridge 167:e84263d55307 15107 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 15108 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
AnnaBridge 167:e84263d55307 15109 #define ETH_DMASR_EBS_Pos (23U)
AnnaBridge 167:e84263d55307 15110 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
AnnaBridge 167:e84263d55307 15111 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
<> 144:ef7eb2e8f9f7 15112 /* combination with EBS[2:0] for GetFlagStatus function */
AnnaBridge 167:e84263d55307 15113 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
AnnaBridge 167:e84263d55307 15114 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15115 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
AnnaBridge 167:e84263d55307 15116 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
AnnaBridge 167:e84263d55307 15117 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15118 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
AnnaBridge 167:e84263d55307 15119 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
AnnaBridge 167:e84263d55307 15120 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15121 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 167:e84263d55307 15122 #define ETH_DMASR_TPS_Pos (20U)
AnnaBridge 167:e84263d55307 15123 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
AnnaBridge 167:e84263d55307 15124 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
AnnaBridge 167:e84263d55307 15125 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
AnnaBridge 167:e84263d55307 15126 #define ETH_DMASR_TPS_Fetching_Pos (20U)
AnnaBridge 167:e84263d55307 15127 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15128 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
AnnaBridge 167:e84263d55307 15129 #define ETH_DMASR_TPS_Waiting_Pos (21U)
AnnaBridge 167:e84263d55307 15130 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15131 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
AnnaBridge 167:e84263d55307 15132 #define ETH_DMASR_TPS_Reading_Pos (20U)
AnnaBridge 167:e84263d55307 15133 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 15134 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
AnnaBridge 167:e84263d55307 15135 #define ETH_DMASR_TPS_Suspended_Pos (21U)
AnnaBridge 167:e84263d55307 15136 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
AnnaBridge 167:e84263d55307 15137 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
AnnaBridge 167:e84263d55307 15138 #define ETH_DMASR_TPS_Closing_Pos (20U)
AnnaBridge 167:e84263d55307 15139 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
AnnaBridge 167:e84263d55307 15140 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
AnnaBridge 167:e84263d55307 15141 #define ETH_DMASR_RPS_Pos (17U)
AnnaBridge 167:e84263d55307 15142 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 15143 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
AnnaBridge 167:e84263d55307 15144 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
AnnaBridge 167:e84263d55307 15145 #define ETH_DMASR_RPS_Fetching_Pos (17U)
AnnaBridge 167:e84263d55307 15146 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15147 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
AnnaBridge 167:e84263d55307 15148 #define ETH_DMASR_RPS_Waiting_Pos (17U)
AnnaBridge 167:e84263d55307 15149 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
AnnaBridge 167:e84263d55307 15150 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
AnnaBridge 167:e84263d55307 15151 #define ETH_DMASR_RPS_Suspended_Pos (19U)
AnnaBridge 167:e84263d55307 15152 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15153 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
AnnaBridge 167:e84263d55307 15154 #define ETH_DMASR_RPS_Closing_Pos (17U)
AnnaBridge 167:e84263d55307 15155 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
AnnaBridge 167:e84263d55307 15156 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
AnnaBridge 167:e84263d55307 15157 #define ETH_DMASR_RPS_Queuing_Pos (17U)
AnnaBridge 167:e84263d55307 15158 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
AnnaBridge 167:e84263d55307 15159 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
AnnaBridge 167:e84263d55307 15160 #define ETH_DMASR_NIS_Pos (16U)
AnnaBridge 167:e84263d55307 15161 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15162 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
AnnaBridge 167:e84263d55307 15163 #define ETH_DMASR_AIS_Pos (15U)
AnnaBridge 167:e84263d55307 15164 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15165 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
AnnaBridge 167:e84263d55307 15166 #define ETH_DMASR_ERS_Pos (14U)
AnnaBridge 167:e84263d55307 15167 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 15168 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
AnnaBridge 167:e84263d55307 15169 #define ETH_DMASR_FBES_Pos (13U)
AnnaBridge 167:e84263d55307 15170 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15171 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
AnnaBridge 167:e84263d55307 15172 #define ETH_DMASR_ETS_Pos (10U)
AnnaBridge 167:e84263d55307 15173 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15174 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
AnnaBridge 167:e84263d55307 15175 #define ETH_DMASR_RWTS_Pos (9U)
AnnaBridge 167:e84263d55307 15176 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15177 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
AnnaBridge 167:e84263d55307 15178 #define ETH_DMASR_RPSS_Pos (8U)
AnnaBridge 167:e84263d55307 15179 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15180 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
AnnaBridge 167:e84263d55307 15181 #define ETH_DMASR_RBUS_Pos (7U)
AnnaBridge 167:e84263d55307 15182 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15183 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
AnnaBridge 167:e84263d55307 15184 #define ETH_DMASR_RS_Pos (6U)
AnnaBridge 167:e84263d55307 15185 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15186 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
AnnaBridge 167:e84263d55307 15187 #define ETH_DMASR_TUS_Pos (5U)
AnnaBridge 167:e84263d55307 15188 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15189 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
AnnaBridge 167:e84263d55307 15190 #define ETH_DMASR_ROS_Pos (4U)
AnnaBridge 167:e84263d55307 15191 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15192 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
AnnaBridge 167:e84263d55307 15193 #define ETH_DMASR_TJTS_Pos (3U)
AnnaBridge 167:e84263d55307 15194 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15195 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
AnnaBridge 167:e84263d55307 15196 #define ETH_DMASR_TBUS_Pos (2U)
AnnaBridge 167:e84263d55307 15197 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15198 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
AnnaBridge 167:e84263d55307 15199 #define ETH_DMASR_TPSS_Pos (1U)
AnnaBridge 167:e84263d55307 15200 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15201 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
AnnaBridge 167:e84263d55307 15202 #define ETH_DMASR_TS_Pos (0U)
AnnaBridge 167:e84263d55307 15203 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15204 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
<> 144:ef7eb2e8f9f7 15205
<> 144:ef7eb2e8f9f7 15206 /* Bit definition for Ethernet DMA Operation Mode Register */
AnnaBridge 167:e84263d55307 15207 #define ETH_DMAOMR_DTCEFD_Pos (26U)
AnnaBridge 167:e84263d55307 15208 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 15209 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
AnnaBridge 167:e84263d55307 15210 #define ETH_DMAOMR_RSF_Pos (25U)
AnnaBridge 167:e84263d55307 15211 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15212 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
AnnaBridge 167:e84263d55307 15213 #define ETH_DMAOMR_DFRF_Pos (24U)
AnnaBridge 167:e84263d55307 15214 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15215 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
AnnaBridge 167:e84263d55307 15216 #define ETH_DMAOMR_TSF_Pos (21U)
AnnaBridge 167:e84263d55307 15217 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15218 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
AnnaBridge 167:e84263d55307 15219 #define ETH_DMAOMR_FTF_Pos (20U)
AnnaBridge 167:e84263d55307 15220 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15221 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
AnnaBridge 167:e84263d55307 15222 #define ETH_DMAOMR_TTC_Pos (14U)
AnnaBridge 167:e84263d55307 15223 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
AnnaBridge 167:e84263d55307 15224 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
AnnaBridge 167:e84263d55307 15225 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 167:e84263d55307 15226 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 167:e84263d55307 15227 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 167:e84263d55307 15228 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 167:e84263d55307 15229 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 167:e84263d55307 15230 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 167:e84263d55307 15231 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 167:e84263d55307 15232 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
AnnaBridge 167:e84263d55307 15233 #define ETH_DMAOMR_ST_Pos (13U)
AnnaBridge 167:e84263d55307 15234 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15235 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
AnnaBridge 167:e84263d55307 15236 #define ETH_DMAOMR_FEF_Pos (7U)
AnnaBridge 167:e84263d55307 15237 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15238 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
AnnaBridge 167:e84263d55307 15239 #define ETH_DMAOMR_FUGF_Pos (6U)
AnnaBridge 167:e84263d55307 15240 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15241 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
AnnaBridge 167:e84263d55307 15242 #define ETH_DMAOMR_RTC_Pos (3U)
AnnaBridge 167:e84263d55307 15243 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
AnnaBridge 167:e84263d55307 15244 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
AnnaBridge 167:e84263d55307 15245 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 167:e84263d55307 15246 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 167:e84263d55307 15247 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 167:e84263d55307 15248 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
AnnaBridge 167:e84263d55307 15249 #define ETH_DMAOMR_OSF_Pos (2U)
AnnaBridge 167:e84263d55307 15250 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15251 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
AnnaBridge 167:e84263d55307 15252 #define ETH_DMAOMR_SR_Pos (1U)
AnnaBridge 167:e84263d55307 15253 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15254 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
<> 144:ef7eb2e8f9f7 15255
<> 144:ef7eb2e8f9f7 15256 /* Bit definition for Ethernet DMA Interrupt Enable Register */
AnnaBridge 167:e84263d55307 15257 #define ETH_DMAIER_NISE_Pos (16U)
AnnaBridge 167:e84263d55307 15258 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15259 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
AnnaBridge 167:e84263d55307 15260 #define ETH_DMAIER_AISE_Pos (15U)
AnnaBridge 167:e84263d55307 15261 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15262 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
AnnaBridge 167:e84263d55307 15263 #define ETH_DMAIER_ERIE_Pos (14U)
AnnaBridge 167:e84263d55307 15264 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 15265 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
AnnaBridge 167:e84263d55307 15266 #define ETH_DMAIER_FBEIE_Pos (13U)
AnnaBridge 167:e84263d55307 15267 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15268 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
AnnaBridge 167:e84263d55307 15269 #define ETH_DMAIER_ETIE_Pos (10U)
AnnaBridge 167:e84263d55307 15270 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15271 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
AnnaBridge 167:e84263d55307 15272 #define ETH_DMAIER_RWTIE_Pos (9U)
AnnaBridge 167:e84263d55307 15273 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15274 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
AnnaBridge 167:e84263d55307 15275 #define ETH_DMAIER_RPSIE_Pos (8U)
AnnaBridge 167:e84263d55307 15276 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15277 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
AnnaBridge 167:e84263d55307 15278 #define ETH_DMAIER_RBUIE_Pos (7U)
AnnaBridge 167:e84263d55307 15279 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15280 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
AnnaBridge 167:e84263d55307 15281 #define ETH_DMAIER_RIE_Pos (6U)
AnnaBridge 167:e84263d55307 15282 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15283 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
AnnaBridge 167:e84263d55307 15284 #define ETH_DMAIER_TUIE_Pos (5U)
AnnaBridge 167:e84263d55307 15285 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15286 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
AnnaBridge 167:e84263d55307 15287 #define ETH_DMAIER_ROIE_Pos (4U)
AnnaBridge 167:e84263d55307 15288 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15289 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
AnnaBridge 167:e84263d55307 15290 #define ETH_DMAIER_TJTIE_Pos (3U)
AnnaBridge 167:e84263d55307 15291 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15292 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
AnnaBridge 167:e84263d55307 15293 #define ETH_DMAIER_TBUIE_Pos (2U)
AnnaBridge 167:e84263d55307 15294 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15295 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
AnnaBridge 167:e84263d55307 15296 #define ETH_DMAIER_TPSIE_Pos (1U)
AnnaBridge 167:e84263d55307 15297 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15298 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
AnnaBridge 167:e84263d55307 15299 #define ETH_DMAIER_TIE_Pos (0U)
AnnaBridge 167:e84263d55307 15300 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15301 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
<> 144:ef7eb2e8f9f7 15302
<> 144:ef7eb2e8f9f7 15303 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
AnnaBridge 167:e84263d55307 15304 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
AnnaBridge 167:e84263d55307 15305 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 15306 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
AnnaBridge 167:e84263d55307 15307 #define ETH_DMAMFBOCR_MFA_Pos (17U)
AnnaBridge 167:e84263d55307 15308 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
AnnaBridge 167:e84263d55307 15309 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
AnnaBridge 167:e84263d55307 15310 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
AnnaBridge 167:e84263d55307 15311 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15312 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
AnnaBridge 167:e84263d55307 15313 #define ETH_DMAMFBOCR_MFC_Pos (0U)
AnnaBridge 167:e84263d55307 15314 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15315 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
<> 144:ef7eb2e8f9f7 15316
<> 144:ef7eb2e8f9f7 15317 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
AnnaBridge 167:e84263d55307 15318 #define ETH_DMACHTDR_HTDAP_Pos (0U)
AnnaBridge 167:e84263d55307 15319 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15320 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
<> 144:ef7eb2e8f9f7 15321
<> 144:ef7eb2e8f9f7 15322 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
AnnaBridge 167:e84263d55307 15323 #define ETH_DMACHRDR_HRDAP_Pos (0U)
AnnaBridge 167:e84263d55307 15324 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15325 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
<> 144:ef7eb2e8f9f7 15326
<> 144:ef7eb2e8f9f7 15327 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
AnnaBridge 167:e84263d55307 15328 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
AnnaBridge 167:e84263d55307 15329 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15330 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
<> 144:ef7eb2e8f9f7 15331
<> 144:ef7eb2e8f9f7 15332 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
AnnaBridge 167:e84263d55307 15333 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
AnnaBridge 167:e84263d55307 15334 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 15335 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
<> 144:ef7eb2e8f9f7 15336
<> 144:ef7eb2e8f9f7 15337 /******************************************************************************/
<> 144:ef7eb2e8f9f7 15338 /* */
AnnaBridge 167:e84263d55307 15339 /* USB_OTG */
<> 144:ef7eb2e8f9f7 15340 /* */
<> 144:ef7eb2e8f9f7 15341 /******************************************************************************/
AnnaBridge 167:e84263d55307 15342 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
AnnaBridge 167:e84263d55307 15343 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
AnnaBridge 167:e84263d55307 15344 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15345 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
AnnaBridge 167:e84263d55307 15346 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
AnnaBridge 167:e84263d55307 15347 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15348 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
AnnaBridge 167:e84263d55307 15349 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
AnnaBridge 167:e84263d55307 15350 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15351 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
AnnaBridge 167:e84263d55307 15352 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
AnnaBridge 167:e84263d55307 15353 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15354 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
AnnaBridge 167:e84263d55307 15355 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
AnnaBridge 167:e84263d55307 15356 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15357 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
AnnaBridge 167:e84263d55307 15358 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
AnnaBridge 167:e84263d55307 15359 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15360 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
AnnaBridge 167:e84263d55307 15361 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
AnnaBridge 167:e84263d55307 15362 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15363 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
AnnaBridge 167:e84263d55307 15364 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
AnnaBridge 167:e84263d55307 15365 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15366 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
AnnaBridge 167:e84263d55307 15367 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
AnnaBridge 167:e84263d55307 15368 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15369 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
AnnaBridge 167:e84263d55307 15370 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
AnnaBridge 167:e84263d55307 15371 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15372 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */
<> 144:ef7eb2e8f9f7 15373
<> 144:ef7eb2e8f9f7 15374 /******************** Bit definition forUSB_OTG_HCFG register ********************/
<> 144:ef7eb2e8f9f7 15375
AnnaBridge 167:e84263d55307 15376 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
AnnaBridge 167:e84263d55307 15377 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 15378 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
AnnaBridge 167:e84263d55307 15379 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15380 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15381 #define USB_OTG_HCFG_FSLSS_Pos (2U)
AnnaBridge 167:e84263d55307 15382 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15383 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
AnnaBridge 167:e84263d55307 15384
AnnaBridge 167:e84263d55307 15385 /******************** Bit definition for USB_OTG_DCFG register ********************/
AnnaBridge 167:e84263d55307 15386
AnnaBridge 167:e84263d55307 15387 #define USB_OTG_DCFG_DSPD_Pos (0U)
AnnaBridge 167:e84263d55307 15388 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
AnnaBridge 167:e84263d55307 15389 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
AnnaBridge 167:e84263d55307 15390 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15391 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15392 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
AnnaBridge 167:e84263d55307 15393 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15394 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
AnnaBridge 167:e84263d55307 15395
AnnaBridge 167:e84263d55307 15396 #define USB_OTG_DCFG_DAD_Pos (4U)
AnnaBridge 167:e84263d55307 15397 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
AnnaBridge 167:e84263d55307 15398 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
AnnaBridge 167:e84263d55307 15399 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15400 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15401 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15402 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15403 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15404 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15405 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15406
AnnaBridge 167:e84263d55307 15407 #define USB_OTG_DCFG_PFIVL_Pos (11U)
AnnaBridge 167:e84263d55307 15408 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
AnnaBridge 167:e84263d55307 15409 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
AnnaBridge 167:e84263d55307 15410 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15411 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 15412
AnnaBridge 167:e84263d55307 15413 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
AnnaBridge 167:e84263d55307 15414 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
AnnaBridge 167:e84263d55307 15415 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
AnnaBridge 167:e84263d55307 15416 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15417 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15418
AnnaBridge 167:e84263d55307 15419 /******************** Bit definition for USB_OTG_PCGCR register ********************/
AnnaBridge 167:e84263d55307 15420 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
AnnaBridge 167:e84263d55307 15421 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15422 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
AnnaBridge 167:e84263d55307 15423 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
AnnaBridge 167:e84263d55307 15424 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15425 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
AnnaBridge 167:e84263d55307 15426 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
AnnaBridge 167:e84263d55307 15427 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15428 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
AnnaBridge 167:e84263d55307 15429
AnnaBridge 167:e84263d55307 15430 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
AnnaBridge 167:e84263d55307 15431 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
AnnaBridge 167:e84263d55307 15432 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15433 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
AnnaBridge 167:e84263d55307 15434 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
AnnaBridge 167:e84263d55307 15435 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15436 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
AnnaBridge 167:e84263d55307 15437 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
AnnaBridge 167:e84263d55307 15438 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15439 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
AnnaBridge 167:e84263d55307 15440 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
AnnaBridge 167:e84263d55307 15441 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15442 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
AnnaBridge 167:e84263d55307 15443 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
AnnaBridge 167:e84263d55307 15444 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15445 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
AnnaBridge 167:e84263d55307 15446 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
AnnaBridge 167:e84263d55307 15447 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15448 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
AnnaBridge 167:e84263d55307 15449
AnnaBridge 167:e84263d55307 15450 /******************** Bit definition for USB_OTG_DCTL register ********************/
AnnaBridge 167:e84263d55307 15451 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
AnnaBridge 167:e84263d55307 15452 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15453 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
AnnaBridge 167:e84263d55307 15454 #define USB_OTG_DCTL_SDIS_Pos (1U)
AnnaBridge 167:e84263d55307 15455 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15456 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
AnnaBridge 167:e84263d55307 15457 #define USB_OTG_DCTL_GINSTS_Pos (2U)
AnnaBridge 167:e84263d55307 15458 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15459 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
AnnaBridge 167:e84263d55307 15460 #define USB_OTG_DCTL_GONSTS_Pos (3U)
AnnaBridge 167:e84263d55307 15461 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15462 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
AnnaBridge 167:e84263d55307 15463
AnnaBridge 167:e84263d55307 15464 #define USB_OTG_DCTL_TCTL_Pos (4U)
AnnaBridge 167:e84263d55307 15465 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
AnnaBridge 167:e84263d55307 15466 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
AnnaBridge 167:e84263d55307 15467 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15468 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15469 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15470 #define USB_OTG_DCTL_SGINAK_Pos (7U)
AnnaBridge 167:e84263d55307 15471 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15472 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
AnnaBridge 167:e84263d55307 15473 #define USB_OTG_DCTL_CGINAK_Pos (8U)
AnnaBridge 167:e84263d55307 15474 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15475 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
AnnaBridge 167:e84263d55307 15476 #define USB_OTG_DCTL_SGONAK_Pos (9U)
AnnaBridge 167:e84263d55307 15477 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15478 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
AnnaBridge 167:e84263d55307 15479 #define USB_OTG_DCTL_CGONAK_Pos (10U)
AnnaBridge 167:e84263d55307 15480 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15481 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
AnnaBridge 167:e84263d55307 15482 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
AnnaBridge 167:e84263d55307 15483 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15484 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
AnnaBridge 167:e84263d55307 15485
AnnaBridge 167:e84263d55307 15486 /******************** Bit definition for USB_OTG_HFIR register ********************/
AnnaBridge 167:e84263d55307 15487 #define USB_OTG_HFIR_FRIVL_Pos (0U)
AnnaBridge 167:e84263d55307 15488 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15489 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
AnnaBridge 167:e84263d55307 15490
AnnaBridge 167:e84263d55307 15491 /******************** Bit definition for USB_OTG_HFNUM register ********************/
AnnaBridge 167:e84263d55307 15492 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15493 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15494 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
AnnaBridge 167:e84263d55307 15495 #define USB_OTG_HFNUM_FTREM_Pos (16U)
AnnaBridge 167:e84263d55307 15496 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 15497 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
AnnaBridge 167:e84263d55307 15498
AnnaBridge 167:e84263d55307 15499 /******************** Bit definition for USB_OTG_DSTS register ********************/
AnnaBridge 167:e84263d55307 15500 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
AnnaBridge 167:e84263d55307 15501 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15502 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
AnnaBridge 167:e84263d55307 15503
AnnaBridge 167:e84263d55307 15504 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
AnnaBridge 167:e84263d55307 15505 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
AnnaBridge 167:e84263d55307 15506 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
AnnaBridge 167:e84263d55307 15507 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15508 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15509 #define USB_OTG_DSTS_EERR_Pos (3U)
AnnaBridge 167:e84263d55307 15510 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15511 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
AnnaBridge 167:e84263d55307 15512 #define USB_OTG_DSTS_FNSOF_Pos (8U)
AnnaBridge 167:e84263d55307 15513 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
AnnaBridge 167:e84263d55307 15514 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
AnnaBridge 167:e84263d55307 15515
AnnaBridge 167:e84263d55307 15516 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
AnnaBridge 167:e84263d55307 15517 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
AnnaBridge 167:e84263d55307 15518 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15519 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
AnnaBridge 167:e84263d55307 15520 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
AnnaBridge 167:e84263d55307 15521 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
AnnaBridge 167:e84263d55307 15522 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
AnnaBridge 167:e84263d55307 15523 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
AnnaBridge 167:e84263d55307 15524 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
AnnaBridge 167:e84263d55307 15525 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
AnnaBridge 167:e84263d55307 15526 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
AnnaBridge 167:e84263d55307 15527 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
AnnaBridge 167:e84263d55307 15528 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
AnnaBridge 167:e84263d55307 15529 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15530 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
AnnaBridge 167:e84263d55307 15531 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
AnnaBridge 167:e84263d55307 15532 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15533 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
AnnaBridge 167:e84263d55307 15534 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
AnnaBridge 167:e84263d55307 15535 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15536 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
AnnaBridge 167:e84263d55307 15537
AnnaBridge 167:e84263d55307 15538 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
AnnaBridge 167:e84263d55307 15539
AnnaBridge 167:e84263d55307 15540 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
AnnaBridge 167:e84263d55307 15541 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
AnnaBridge 167:e84263d55307 15542 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
AnnaBridge 167:e84263d55307 15543 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15544 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15545 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15546 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
AnnaBridge 167:e84263d55307 15547 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15548 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
AnnaBridge 167:e84263d55307 15549 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
AnnaBridge 167:e84263d55307 15550 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15551 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
AnnaBridge 167:e84263d55307 15552 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
AnnaBridge 167:e84263d55307 15553 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15554 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
AnnaBridge 167:e84263d55307 15555 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
AnnaBridge 167:e84263d55307 15556 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
AnnaBridge 167:e84263d55307 15557 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
AnnaBridge 167:e84263d55307 15558 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15559 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15560 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 15561 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15562 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
AnnaBridge 167:e84263d55307 15563 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15564 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
AnnaBridge 167:e84263d55307 15565 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
AnnaBridge 167:e84263d55307 15566 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15567 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
AnnaBridge 167:e84263d55307 15568 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
AnnaBridge 167:e84263d55307 15569 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15570 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
AnnaBridge 167:e84263d55307 15571 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
AnnaBridge 167:e84263d55307 15572 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15573 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
AnnaBridge 167:e84263d55307 15574 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
AnnaBridge 167:e84263d55307 15575 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15576 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
AnnaBridge 167:e84263d55307 15577 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
AnnaBridge 167:e84263d55307 15578 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15579 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
AnnaBridge 167:e84263d55307 15580 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
AnnaBridge 167:e84263d55307 15581 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15582 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
AnnaBridge 167:e84263d55307 15583 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
AnnaBridge 167:e84263d55307 15584 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15585 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
AnnaBridge 167:e84263d55307 15586 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
AnnaBridge 167:e84263d55307 15587 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15588 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
AnnaBridge 167:e84263d55307 15589 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
AnnaBridge 167:e84263d55307 15590 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15591 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
AnnaBridge 167:e84263d55307 15592 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
AnnaBridge 167:e84263d55307 15593 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 15594 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
AnnaBridge 167:e84263d55307 15595 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
AnnaBridge 167:e84263d55307 15596 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 15597 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
AnnaBridge 167:e84263d55307 15598 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
AnnaBridge 167:e84263d55307 15599 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 15600 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
AnnaBridge 167:e84263d55307 15601
AnnaBridge 167:e84263d55307 15602 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
AnnaBridge 167:e84263d55307 15603 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
AnnaBridge 167:e84263d55307 15604 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15605 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
AnnaBridge 167:e84263d55307 15606 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
AnnaBridge 167:e84263d55307 15607 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15608 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
AnnaBridge 167:e84263d55307 15609 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
AnnaBridge 167:e84263d55307 15610 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15611 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
AnnaBridge 167:e84263d55307 15612 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
AnnaBridge 167:e84263d55307 15613 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15614 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
AnnaBridge 167:e84263d55307 15615 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
AnnaBridge 167:e84263d55307 15616 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15617 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
AnnaBridge 167:e84263d55307 15618
AnnaBridge 167:e84263d55307 15619
AnnaBridge 167:e84263d55307 15620 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
AnnaBridge 167:e84263d55307 15621 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
AnnaBridge 167:e84263d55307 15622 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 167:e84263d55307 15623 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15624 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15625 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15626 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15627 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15628 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
AnnaBridge 167:e84263d55307 15629 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 15630 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
AnnaBridge 167:e84263d55307 15631 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
AnnaBridge 167:e84263d55307 15632 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 15633 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
AnnaBridge 167:e84263d55307 15634
AnnaBridge 167:e84263d55307 15635 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
AnnaBridge 167:e84263d55307 15636 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
AnnaBridge 167:e84263d55307 15637 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15638 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 167:e84263d55307 15639 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
AnnaBridge 167:e84263d55307 15640 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15641 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 167:e84263d55307 15642 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
AnnaBridge 167:e84263d55307 15643 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15644 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 167:e84263d55307 15645 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
AnnaBridge 167:e84263d55307 15646 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15647 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 167:e84263d55307 15648 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
AnnaBridge 167:e84263d55307 15649 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15650 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 167:e84263d55307 15651 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
AnnaBridge 167:e84263d55307 15652 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15653 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 167:e84263d55307 15654 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
AnnaBridge 167:e84263d55307 15655 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15656 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 167:e84263d55307 15657 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
AnnaBridge 167:e84263d55307 15658 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15659 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 167:e84263d55307 15660
AnnaBridge 167:e84263d55307 15661 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
AnnaBridge 167:e84263d55307 15662 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
AnnaBridge 167:e84263d55307 15663 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15664 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
AnnaBridge 167:e84263d55307 15665 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
AnnaBridge 167:e84263d55307 15666 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 15667 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
AnnaBridge 167:e84263d55307 15668 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15669 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15670 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15671 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15672 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15673 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15674 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15675 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15676
AnnaBridge 167:e84263d55307 15677 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
AnnaBridge 167:e84263d55307 15678 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
AnnaBridge 167:e84263d55307 15679 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
AnnaBridge 167:e84263d55307 15680 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15681 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15682 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 15683 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 15684 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 15685 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 15686 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 15687 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 15688
AnnaBridge 167:e84263d55307 15689 /******************** Bit definition for USB_OTG_HAINT register ********************/
AnnaBridge 167:e84263d55307 15690 #define USB_OTG_HAINT_HAINT_Pos (0U)
AnnaBridge 167:e84263d55307 15691 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15692 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
AnnaBridge 167:e84263d55307 15693
AnnaBridge 167:e84263d55307 15694 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
AnnaBridge 167:e84263d55307 15695 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
AnnaBridge 167:e84263d55307 15696 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15697 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 167:e84263d55307 15698 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
AnnaBridge 167:e84263d55307 15699 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15700 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 167:e84263d55307 15701 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
AnnaBridge 167:e84263d55307 15702 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15703 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
AnnaBridge 167:e84263d55307 15704 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
AnnaBridge 167:e84263d55307 15705 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15706 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
AnnaBridge 167:e84263d55307 15707 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
AnnaBridge 167:e84263d55307 15708 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15709 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
AnnaBridge 167:e84263d55307 15710 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
AnnaBridge 167:e84263d55307 15711 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 15712 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
AnnaBridge 167:e84263d55307 15713 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
AnnaBridge 167:e84263d55307 15714 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 15715 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
AnnaBridge 167:e84263d55307 15716
AnnaBridge 167:e84263d55307 15717 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
AnnaBridge 167:e84263d55307 15718 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
AnnaBridge 167:e84263d55307 15719 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15720 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
AnnaBridge 167:e84263d55307 15721 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
AnnaBridge 167:e84263d55307 15722 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15723 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
AnnaBridge 167:e84263d55307 15724 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
AnnaBridge 167:e84263d55307 15725 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15726 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
AnnaBridge 167:e84263d55307 15727 #define USB_OTG_GINTSTS_SOF_Pos (3U)
AnnaBridge 167:e84263d55307 15728 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15729 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
AnnaBridge 167:e84263d55307 15730 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
AnnaBridge 167:e84263d55307 15731 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15732 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
AnnaBridge 167:e84263d55307 15733 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
AnnaBridge 167:e84263d55307 15734 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15735 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
AnnaBridge 167:e84263d55307 15736 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
AnnaBridge 167:e84263d55307 15737 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15738 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
AnnaBridge 167:e84263d55307 15739 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
AnnaBridge 167:e84263d55307 15740 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15741 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
AnnaBridge 167:e84263d55307 15742 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
AnnaBridge 167:e84263d55307 15743 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15744 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
AnnaBridge 167:e84263d55307 15745 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
AnnaBridge 167:e84263d55307 15746 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15747 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
AnnaBridge 167:e84263d55307 15748 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
AnnaBridge 167:e84263d55307 15749 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 15750 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
AnnaBridge 167:e84263d55307 15751 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
AnnaBridge 167:e84263d55307 15752 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15753 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
AnnaBridge 167:e84263d55307 15754 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
AnnaBridge 167:e84263d55307 15755 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 15756 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
AnnaBridge 167:e84263d55307 15757 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
AnnaBridge 167:e84263d55307 15758 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15759 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
AnnaBridge 167:e84263d55307 15760 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
AnnaBridge 167:e84263d55307 15761 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15762 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
AnnaBridge 167:e84263d55307 15763 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
AnnaBridge 167:e84263d55307 15764 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15765 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
AnnaBridge 167:e84263d55307 15766 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
AnnaBridge 167:e84263d55307 15767 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15768 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
AnnaBridge 167:e84263d55307 15769 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
AnnaBridge 167:e84263d55307 15770 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15771 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
AnnaBridge 167:e84263d55307 15772 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
AnnaBridge 167:e84263d55307 15773 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15774 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
AnnaBridge 167:e84263d55307 15775 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
AnnaBridge 167:e84263d55307 15776 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15777 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
AnnaBridge 167:e84263d55307 15778 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
AnnaBridge 167:e84263d55307 15779 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15780 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
AnnaBridge 167:e84263d55307 15781 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
AnnaBridge 167:e84263d55307 15782 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 15783 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
AnnaBridge 167:e84263d55307 15784 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
AnnaBridge 167:e84263d55307 15785 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 15786 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
AnnaBridge 167:e84263d55307 15787 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
AnnaBridge 167:e84263d55307 15788 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 15789 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
AnnaBridge 167:e84263d55307 15790 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
AnnaBridge 167:e84263d55307 15791 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 15792 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
AnnaBridge 167:e84263d55307 15793 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
AnnaBridge 167:e84263d55307 15794 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 15795 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
AnnaBridge 167:e84263d55307 15796
AnnaBridge 167:e84263d55307 15797 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
AnnaBridge 167:e84263d55307 15798 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
AnnaBridge 167:e84263d55307 15799 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15800 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
AnnaBridge 167:e84263d55307 15801 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
AnnaBridge 167:e84263d55307 15802 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15803 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
AnnaBridge 167:e84263d55307 15804 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
AnnaBridge 167:e84263d55307 15805 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15806 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
AnnaBridge 167:e84263d55307 15807 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
AnnaBridge 167:e84263d55307 15808 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 15809 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
AnnaBridge 167:e84263d55307 15810 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
AnnaBridge 167:e84263d55307 15811 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 15812 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
AnnaBridge 167:e84263d55307 15813 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
AnnaBridge 167:e84263d55307 15814 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 15815 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
AnnaBridge 167:e84263d55307 15816 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
AnnaBridge 167:e84263d55307 15817 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 15818 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
AnnaBridge 167:e84263d55307 15819 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
AnnaBridge 167:e84263d55307 15820 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 15821 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
AnnaBridge 167:e84263d55307 15822 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
AnnaBridge 167:e84263d55307 15823 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 15824 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
AnnaBridge 167:e84263d55307 15825 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
AnnaBridge 167:e84263d55307 15826 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 15827 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
AnnaBridge 167:e84263d55307 15828 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
AnnaBridge 167:e84263d55307 15829 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 15830 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
AnnaBridge 167:e84263d55307 15831 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
AnnaBridge 167:e84263d55307 15832 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 15833 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
AnnaBridge 167:e84263d55307 15834 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
AnnaBridge 167:e84263d55307 15835 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15836 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
AnnaBridge 167:e84263d55307 15837 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
AnnaBridge 167:e84263d55307 15838 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15839 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
AnnaBridge 167:e84263d55307 15840 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
AnnaBridge 167:e84263d55307 15841 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15842 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
AnnaBridge 167:e84263d55307 15843 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
AnnaBridge 167:e84263d55307 15844 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15845 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
AnnaBridge 167:e84263d55307 15846 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
AnnaBridge 167:e84263d55307 15847 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15848 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
AnnaBridge 167:e84263d55307 15849 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
AnnaBridge 167:e84263d55307 15850 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15851 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
AnnaBridge 167:e84263d55307 15852 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
AnnaBridge 167:e84263d55307 15853 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15854 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
AnnaBridge 167:e84263d55307 15855 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
AnnaBridge 167:e84263d55307 15856 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15857 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
AnnaBridge 167:e84263d55307 15858 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
AnnaBridge 167:e84263d55307 15859 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 15860 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
AnnaBridge 167:e84263d55307 15861 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
AnnaBridge 167:e84263d55307 15862 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 15863 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
AnnaBridge 167:e84263d55307 15864 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
AnnaBridge 167:e84263d55307 15865 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 15866 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
AnnaBridge 167:e84263d55307 15867 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
AnnaBridge 167:e84263d55307 15868 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 15869 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
AnnaBridge 167:e84263d55307 15870 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
AnnaBridge 167:e84263d55307 15871 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 15872 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
AnnaBridge 167:e84263d55307 15873 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
AnnaBridge 167:e84263d55307 15874 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 15875 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
AnnaBridge 167:e84263d55307 15876
AnnaBridge 167:e84263d55307 15877 /******************** Bit definition for USB_OTG_DAINT register ********************/
AnnaBridge 167:e84263d55307 15878 #define USB_OTG_DAINT_IEPINT_Pos (0U)
AnnaBridge 167:e84263d55307 15879 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15880 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
AnnaBridge 167:e84263d55307 15881 #define USB_OTG_DAINT_OEPINT_Pos (16U)
AnnaBridge 167:e84263d55307 15882 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 15883 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
AnnaBridge 167:e84263d55307 15884
AnnaBridge 167:e84263d55307 15885 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
AnnaBridge 167:e84263d55307 15886 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
AnnaBridge 167:e84263d55307 15887 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15888 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
<> 144:ef7eb2e8f9f7 15889
<> 144:ef7eb2e8f9f7 15890 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
AnnaBridge 167:e84263d55307 15891 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15892 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 15893 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 167:e84263d55307 15894 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
AnnaBridge 167:e84263d55307 15895 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 167:e84263d55307 15896 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 167:e84263d55307 15897 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
AnnaBridge 167:e84263d55307 15898 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 167:e84263d55307 15899 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 167:e84263d55307 15900 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
AnnaBridge 167:e84263d55307 15901 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 167:e84263d55307 15902 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
AnnaBridge 167:e84263d55307 15903
AnnaBridge 167:e84263d55307 15904 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
AnnaBridge 167:e84263d55307 15905 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
AnnaBridge 167:e84263d55307 15906 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 15907 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
AnnaBridge 167:e84263d55307 15908 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
AnnaBridge 167:e84263d55307 15909 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 15910 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
<> 144:ef7eb2e8f9f7 15911
<> 144:ef7eb2e8f9f7 15912 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 15913
AnnaBridge 167:e84263d55307 15914 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15915 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 15916 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 167:e84263d55307 15917 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15918 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15919 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15920 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15921 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 167:e84263d55307 15922 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 167:e84263d55307 15923 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 167:e84263d55307 15924
AnnaBridge 167:e84263d55307 15925 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 167:e84263d55307 15926 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 167:e84263d55307 15927 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 167:e84263d55307 15928 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15929 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15930
AnnaBridge 167:e84263d55307 15931 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 167:e84263d55307 15932 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 167:e84263d55307 15933 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 167:e84263d55307 15934 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15935 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15936 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15937 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15938
AnnaBridge 167:e84263d55307 15939 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15940 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 15941 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 167:e84263d55307 15942 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15943 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15944 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15945 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15946
AnnaBridge 167:e84263d55307 15947 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 167:e84263d55307 15948 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 167:e84263d55307 15949 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 167:e84263d55307 15950 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15951 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15952 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15953 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
<> 144:ef7eb2e8f9f7 15954
<> 144:ef7eb2e8f9f7 15955 /******************** Bit definition for OTG register ********************/
<> 144:ef7eb2e8f9f7 15956
AnnaBridge 167:e84263d55307 15957 #define USB_OTG_CHNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15958 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 15959 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
AnnaBridge 167:e84263d55307 15960 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15961 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15962 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15963 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15964 #define USB_OTG_BCNT_Pos (4U)
AnnaBridge 167:e84263d55307 15965 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
AnnaBridge 167:e84263d55307 15966 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
AnnaBridge 167:e84263d55307 15967
AnnaBridge 167:e84263d55307 15968 #define USB_OTG_DPID_Pos (15U)
AnnaBridge 167:e84263d55307 15969 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
AnnaBridge 167:e84263d55307 15970 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
AnnaBridge 167:e84263d55307 15971 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 15972 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 15973
AnnaBridge 167:e84263d55307 15974 #define USB_OTG_PKTSTS_Pos (17U)
AnnaBridge 167:e84263d55307 15975 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
AnnaBridge 167:e84263d55307 15976 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
AnnaBridge 167:e84263d55307 15977 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 15978 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 15979 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 15980 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 15981
AnnaBridge 167:e84263d55307 15982 #define USB_OTG_EPNUM_Pos (0U)
AnnaBridge 167:e84263d55307 15983 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
AnnaBridge 167:e84263d55307 15984 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 167:e84263d55307 15985 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 15986 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 15987 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 15988 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 15989
AnnaBridge 167:e84263d55307 15990 #define USB_OTG_FRMNUM_Pos (21U)
AnnaBridge 167:e84263d55307 15991 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
AnnaBridge 167:e84263d55307 15992 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
AnnaBridge 167:e84263d55307 15993 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 15994 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 15995 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 15996 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 15997
AnnaBridge 167:e84263d55307 15998 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
AnnaBridge 167:e84263d55307 15999 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
AnnaBridge 167:e84263d55307 16000 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16001 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
AnnaBridge 167:e84263d55307 16002
AnnaBridge 167:e84263d55307 16003 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
AnnaBridge 167:e84263d55307 16004 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
AnnaBridge 167:e84263d55307 16005 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16006 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
<> 144:ef7eb2e8f9f7 16007
<> 144:ef7eb2e8f9f7 16008 /******************** Bit definition for OTG register ********************/
AnnaBridge 167:e84263d55307 16009 #define USB_OTG_NPTXFSA_Pos (0U)
AnnaBridge 167:e84263d55307 16010 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16011 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
AnnaBridge 167:e84263d55307 16012 #define USB_OTG_NPTXFD_Pos (16U)
AnnaBridge 167:e84263d55307 16013 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 16014 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
AnnaBridge 167:e84263d55307 16015 #define USB_OTG_TX0FSA_Pos (0U)
AnnaBridge 167:e84263d55307 16016 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16017 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
AnnaBridge 167:e84263d55307 16018 #define USB_OTG_TX0FD_Pos (16U)
AnnaBridge 167:e84263d55307 16019 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 16020 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
<> 144:ef7eb2e8f9f7 16021
<> 144:ef7eb2e8f9f7 16022 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
AnnaBridge 167:e84263d55307 16023 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
AnnaBridge 167:e84263d55307 16024 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
AnnaBridge 167:e84263d55307 16025 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
AnnaBridge 167:e84263d55307 16026
AnnaBridge 167:e84263d55307 16027 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
AnnaBridge 167:e84263d55307 16028 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
AnnaBridge 167:e84263d55307 16029 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16030 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
AnnaBridge 167:e84263d55307 16031
AnnaBridge 167:e84263d55307 16032 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
AnnaBridge 167:e84263d55307 16033 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
AnnaBridge 167:e84263d55307 16034 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
AnnaBridge 167:e84263d55307 16035 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16036 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16037 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16038 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16039 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 16040 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16041 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 16042 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 16043
AnnaBridge 167:e84263d55307 16044 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
AnnaBridge 167:e84263d55307 16045 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
AnnaBridge 167:e84263d55307 16046 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
AnnaBridge 167:e84263d55307 16047 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 16048 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 16049 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 16050 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 16051 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 16052 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16053 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 16054
AnnaBridge 167:e84263d55307 16055 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
AnnaBridge 167:e84263d55307 16056 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
AnnaBridge 167:e84263d55307 16057 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16058 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
AnnaBridge 167:e84263d55307 16059 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
AnnaBridge 167:e84263d55307 16060 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16061 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
AnnaBridge 167:e84263d55307 16062
AnnaBridge 167:e84263d55307 16063 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
AnnaBridge 167:e84263d55307 16064 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
AnnaBridge 167:e84263d55307 16065 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
AnnaBridge 167:e84263d55307 16066 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 16067 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16068 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16069 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16070 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16071 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16072 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16073 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16074 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 16075 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
AnnaBridge 167:e84263d55307 16076 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16077 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
AnnaBridge 167:e84263d55307 16078
AnnaBridge 167:e84263d55307 16079 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
AnnaBridge 167:e84263d55307 16080 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
AnnaBridge 167:e84263d55307 16081 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
AnnaBridge 167:e84263d55307 16082 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16083 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16084 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16085 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 16086 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16087 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 16088 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 16089 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 16090 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 16091 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
AnnaBridge 167:e84263d55307 16092 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 16093 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
AnnaBridge 167:e84263d55307 16094
AnnaBridge 167:e84263d55307 16095 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
AnnaBridge 167:e84263d55307 16096 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
AnnaBridge 167:e84263d55307 16097 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16098 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
AnnaBridge 167:e84263d55307 16099
AnnaBridge 167:e84263d55307 16100 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
AnnaBridge 167:e84263d55307 16101 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
AnnaBridge 167:e84263d55307 16102 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16103 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
AnnaBridge 167:e84263d55307 16104 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
AnnaBridge 167:e84263d55307 16105 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16106 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
AnnaBridge 167:e84263d55307 16107
AnnaBridge 167:e84263d55307 16108 /******************** Bit definition for USB_OTG_GCCFG register ********************/
AnnaBridge 167:e84263d55307 16109 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
AnnaBridge 167:e84263d55307 16110 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16111 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
AnnaBridge 167:e84263d55307 16112 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
AnnaBridge 167:e84263d55307 16113 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1U << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16114 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/
AnnaBridge 167:e84263d55307 16115 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
AnnaBridge 167:e84263d55307 16116 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1U << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16117 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 167:e84263d55307 16118 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
AnnaBridge 167:e84263d55307 16119 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1U << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16120 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */
AnnaBridge 167:e84263d55307 16121 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
AnnaBridge 167:e84263d55307 16122 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1U << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 16123 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */
AnnaBridge 167:e84263d55307 16124 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
AnnaBridge 167:e84263d55307 16125 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1U << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16126 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/
<> 144:ef7eb2e8f9f7 16127
<> 144:ef7eb2e8f9f7 16128 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
AnnaBridge 167:e84263d55307 16129 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
AnnaBridge 167:e84263d55307 16130 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16131 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
AnnaBridge 167:e84263d55307 16132 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
AnnaBridge 167:e84263d55307 16133 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16134 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
AnnaBridge 167:e84263d55307 16135
AnnaBridge 167:e84263d55307 16136 /******************** Bit definition for USB_OTG_CID register ********************/
AnnaBridge 167:e84263d55307 16137 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
AnnaBridge 167:e84263d55307 16138 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 16139 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
AnnaBridge 167:e84263d55307 16140
AnnaBridge 167:e84263d55307 16141 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
AnnaBridge 167:e84263d55307 16142 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 167:e84263d55307 16143 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16144 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 167:e84263d55307 16145 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 167:e84263d55307 16146 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16147 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 167:e84263d55307 16148 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 167:e84263d55307 16149 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16150 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
AnnaBridge 167:e84263d55307 16151 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 167:e84263d55307 16152 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16153 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 167:e84263d55307 16154 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 167:e84263d55307 16155 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16156 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 167:e84263d55307 16157 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 167:e84263d55307 16158 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16159 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 167:e84263d55307 16160 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 167:e84263d55307 16161 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16162 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
AnnaBridge 167:e84263d55307 16163 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 167:e84263d55307 16164 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16165 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 167:e84263d55307 16166 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 167:e84263d55307 16167 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16168 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 167:e84263d55307 16169
AnnaBridge 167:e84263d55307 16170 /******************** Bit definition for USB_OTG_HPRT register ********************/
AnnaBridge 167:e84263d55307 16171 #define USB_OTG_HPRT_PCSTS_Pos (0U)
AnnaBridge 167:e84263d55307 16172 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16173 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
AnnaBridge 167:e84263d55307 16174 #define USB_OTG_HPRT_PCDET_Pos (1U)
AnnaBridge 167:e84263d55307 16175 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16176 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
AnnaBridge 167:e84263d55307 16177 #define USB_OTG_HPRT_PENA_Pos (2U)
AnnaBridge 167:e84263d55307 16178 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 16179 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
AnnaBridge 167:e84263d55307 16180 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
AnnaBridge 167:e84263d55307 16181 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16182 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
AnnaBridge 167:e84263d55307 16183 #define USB_OTG_HPRT_POCA_Pos (4U)
AnnaBridge 167:e84263d55307 16184 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16185 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
AnnaBridge 167:e84263d55307 16186 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
AnnaBridge 167:e84263d55307 16187 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16188 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
AnnaBridge 167:e84263d55307 16189 #define USB_OTG_HPRT_PRES_Pos (6U)
AnnaBridge 167:e84263d55307 16190 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16191 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
AnnaBridge 167:e84263d55307 16192 #define USB_OTG_HPRT_PSUSP_Pos (7U)
AnnaBridge 167:e84263d55307 16193 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16194 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
AnnaBridge 167:e84263d55307 16195 #define USB_OTG_HPRT_PRST_Pos (8U)
AnnaBridge 167:e84263d55307 16196 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16197 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
AnnaBridge 167:e84263d55307 16198
AnnaBridge 167:e84263d55307 16199 #define USB_OTG_HPRT_PLSTS_Pos (10U)
AnnaBridge 167:e84263d55307 16200 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
AnnaBridge 167:e84263d55307 16201 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
AnnaBridge 167:e84263d55307 16202 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 16203 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 16204 #define USB_OTG_HPRT_PPWR_Pos (12U)
AnnaBridge 167:e84263d55307 16205 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 16206 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
AnnaBridge 167:e84263d55307 16207
AnnaBridge 167:e84263d55307 16208 #define USB_OTG_HPRT_PTCTL_Pos (13U)
AnnaBridge 167:e84263d55307 16209 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
AnnaBridge 167:e84263d55307 16210 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
AnnaBridge 167:e84263d55307 16211 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16212 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 16213 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 16214 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16215
AnnaBridge 167:e84263d55307 16216 #define USB_OTG_HPRT_PSPD_Pos (17U)
AnnaBridge 167:e84263d55307 16217 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
AnnaBridge 167:e84263d55307 16218 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
AnnaBridge 167:e84263d55307 16219 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16220 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16221
AnnaBridge 167:e84263d55307 16222 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
AnnaBridge 167:e84263d55307 16223 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
AnnaBridge 167:e84263d55307 16224 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16225 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
AnnaBridge 167:e84263d55307 16226 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
AnnaBridge 167:e84263d55307 16227 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16228 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
AnnaBridge 167:e84263d55307 16229 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
AnnaBridge 167:e84263d55307 16230 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16231 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
AnnaBridge 167:e84263d55307 16232 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
AnnaBridge 167:e84263d55307 16233 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16234 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
AnnaBridge 167:e84263d55307 16235 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
AnnaBridge 167:e84263d55307 16236 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16237 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
AnnaBridge 167:e84263d55307 16238 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
AnnaBridge 167:e84263d55307 16239 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16240 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
AnnaBridge 167:e84263d55307 16241 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
AnnaBridge 167:e84263d55307 16242 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16243 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
AnnaBridge 167:e84263d55307 16244 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
AnnaBridge 167:e84263d55307 16245 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16246 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
AnnaBridge 167:e84263d55307 16247 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
AnnaBridge 167:e84263d55307 16248 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 16249 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
AnnaBridge 167:e84263d55307 16250 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
AnnaBridge 167:e84263d55307 16251 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16252 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
AnnaBridge 167:e84263d55307 16253 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
AnnaBridge 167:e84263d55307 16254 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 16255 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
AnnaBridge 167:e84263d55307 16256
AnnaBridge 167:e84263d55307 16257 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
AnnaBridge 167:e84263d55307 16258 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
AnnaBridge 167:e84263d55307 16259 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16260 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
AnnaBridge 167:e84263d55307 16261 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
AnnaBridge 167:e84263d55307 16262 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 16263 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
AnnaBridge 167:e84263d55307 16264
AnnaBridge 167:e84263d55307 16265 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
AnnaBridge 167:e84263d55307 16266 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16267 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 16268 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 167:e84263d55307 16269 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
AnnaBridge 167:e84263d55307 16270 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 16271 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 167:e84263d55307 16272 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
AnnaBridge 167:e84263d55307 16273 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16274 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
AnnaBridge 167:e84263d55307 16275 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
AnnaBridge 167:e84263d55307 16276 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16277 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 167:e84263d55307 16278
AnnaBridge 167:e84263d55307 16279 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
AnnaBridge 167:e84263d55307 16280 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 16281 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 167:e84263d55307 16282 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16283 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16284 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
AnnaBridge 167:e84263d55307 16285 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16286 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 167:e84263d55307 16287
AnnaBridge 167:e84263d55307 16288 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
AnnaBridge 167:e84263d55307 16289 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
AnnaBridge 167:e84263d55307 16290 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
AnnaBridge 167:e84263d55307 16291 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 16292 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 16293 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 16294 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 16295 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
AnnaBridge 167:e84263d55307 16296 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 16297 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 167:e84263d55307 16298 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
AnnaBridge 167:e84263d55307 16299 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 16300 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 167:e84263d55307 16301 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 167:e84263d55307 16302 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 16303 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 167:e84263d55307 16304 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
AnnaBridge 167:e84263d55307 16305 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16306 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 167:e84263d55307 16307 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
AnnaBridge 167:e84263d55307 16308 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 16309 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 167:e84263d55307 16310 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
AnnaBridge 167:e84263d55307 16311 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 16312 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 167:e84263d55307 16313
AnnaBridge 167:e84263d55307 16314 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
AnnaBridge 167:e84263d55307 16315 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16316 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 16317 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
AnnaBridge 167:e84263d55307 16318
AnnaBridge 167:e84263d55307 16319 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
AnnaBridge 167:e84263d55307 16320 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
AnnaBridge 167:e84263d55307 16321 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
AnnaBridge 167:e84263d55307 16322 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 16323 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 16324 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16325 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 16326 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
AnnaBridge 167:e84263d55307 16327 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 16328 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
AnnaBridge 167:e84263d55307 16329 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
AnnaBridge 167:e84263d55307 16330 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16331 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
AnnaBridge 167:e84263d55307 16332
AnnaBridge 167:e84263d55307 16333 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
AnnaBridge 167:e84263d55307 16334 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 16335 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 167:e84263d55307 16336 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16337 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16338
AnnaBridge 167:e84263d55307 16339 #define USB_OTG_HCCHAR_MC_Pos (20U)
AnnaBridge 167:e84263d55307 16340 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
AnnaBridge 167:e84263d55307 16341 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
AnnaBridge 167:e84263d55307 16342 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 16343 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16344
AnnaBridge 167:e84263d55307 16345 #define USB_OTG_HCCHAR_DAD_Pos (22U)
AnnaBridge 167:e84263d55307 16346 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
AnnaBridge 167:e84263d55307 16347 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
AnnaBridge 167:e84263d55307 16348 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
AnnaBridge 167:e84263d55307 16349 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
AnnaBridge 167:e84263d55307 16350 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
AnnaBridge 167:e84263d55307 16351 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
AnnaBridge 167:e84263d55307 16352 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 16353 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 16354 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 16355 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
AnnaBridge 167:e84263d55307 16356 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16357 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
AnnaBridge 167:e84263d55307 16358 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
AnnaBridge 167:e84263d55307 16359 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 16360 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
AnnaBridge 167:e84263d55307 16361 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
AnnaBridge 167:e84263d55307 16362 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 16363 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
AnnaBridge 167:e84263d55307 16364
AnnaBridge 167:e84263d55307 16365 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
AnnaBridge 167:e84263d55307 16366
AnnaBridge 167:e84263d55307 16367 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
AnnaBridge 167:e84263d55307 16368 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
AnnaBridge 167:e84263d55307 16369 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
AnnaBridge 167:e84263d55307 16370 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16371 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16372 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 16373 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16374 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16375 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16376 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16377
AnnaBridge 167:e84263d55307 16378 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
AnnaBridge 167:e84263d55307 16379 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
AnnaBridge 167:e84263d55307 16380 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
AnnaBridge 167:e84263d55307 16381 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16382 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16383 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16384 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 16385 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 16386 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 16387 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16388
AnnaBridge 167:e84263d55307 16389 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
AnnaBridge 167:e84263d55307 16390 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
AnnaBridge 167:e84263d55307 16391 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
AnnaBridge 167:e84263d55307 16392 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 16393 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 16394 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
AnnaBridge 167:e84263d55307 16395 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
AnnaBridge 167:e84263d55307 16396 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
AnnaBridge 167:e84263d55307 16397 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
AnnaBridge 167:e84263d55307 16398 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 16399 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
AnnaBridge 167:e84263d55307 16400
AnnaBridge 167:e84263d55307 16401 /******************** Bit definition for USB_OTG_HCINT register ********************/
AnnaBridge 167:e84263d55307 16402 #define USB_OTG_HCINT_XFRC_Pos (0U)
AnnaBridge 167:e84263d55307 16403 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16404 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
AnnaBridge 167:e84263d55307 16405 #define USB_OTG_HCINT_CHH_Pos (1U)
AnnaBridge 167:e84263d55307 16406 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16407 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
AnnaBridge 167:e84263d55307 16408 #define USB_OTG_HCINT_AHBERR_Pos (2U)
AnnaBridge 167:e84263d55307 16409 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 16410 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
AnnaBridge 167:e84263d55307 16411 #define USB_OTG_HCINT_STALL_Pos (3U)
AnnaBridge 167:e84263d55307 16412 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16413 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
AnnaBridge 167:e84263d55307 16414 #define USB_OTG_HCINT_NAK_Pos (4U)
AnnaBridge 167:e84263d55307 16415 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16416 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
AnnaBridge 167:e84263d55307 16417 #define USB_OTG_HCINT_ACK_Pos (5U)
AnnaBridge 167:e84263d55307 16418 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16419 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
AnnaBridge 167:e84263d55307 16420 #define USB_OTG_HCINT_NYET_Pos (6U)
AnnaBridge 167:e84263d55307 16421 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16422 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
AnnaBridge 167:e84263d55307 16423 #define USB_OTG_HCINT_TXERR_Pos (7U)
AnnaBridge 167:e84263d55307 16424 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16425 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
AnnaBridge 167:e84263d55307 16426 #define USB_OTG_HCINT_BBERR_Pos (8U)
AnnaBridge 167:e84263d55307 16427 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16428 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
AnnaBridge 167:e84263d55307 16429 #define USB_OTG_HCINT_FRMOR_Pos (9U)
AnnaBridge 167:e84263d55307 16430 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16431 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
AnnaBridge 167:e84263d55307 16432 #define USB_OTG_HCINT_DTERR_Pos (10U)
AnnaBridge 167:e84263d55307 16433 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 16434 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
AnnaBridge 167:e84263d55307 16435
AnnaBridge 167:e84263d55307 16436 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
AnnaBridge 167:e84263d55307 16437 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
AnnaBridge 167:e84263d55307 16438 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16439 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 167:e84263d55307 16440 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
AnnaBridge 167:e84263d55307 16441 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16442 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 167:e84263d55307 16443 #define USB_OTG_DIEPINT_TOC_Pos (3U)
AnnaBridge 167:e84263d55307 16444 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16445 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
AnnaBridge 167:e84263d55307 16446 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
AnnaBridge 167:e84263d55307 16447 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16448 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
AnnaBridge 167:e84263d55307 16449 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
AnnaBridge 167:e84263d55307 16450 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16451 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
AnnaBridge 167:e84263d55307 16452 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
AnnaBridge 167:e84263d55307 16453 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16454 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
AnnaBridge 167:e84263d55307 16455 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
AnnaBridge 167:e84263d55307 16456 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16457 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
AnnaBridge 167:e84263d55307 16458 #define USB_OTG_DIEPINT_BNA_Pos (9U)
AnnaBridge 167:e84263d55307 16459 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16460 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
AnnaBridge 167:e84263d55307 16461 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
AnnaBridge 167:e84263d55307 16462 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
AnnaBridge 167:e84263d55307 16463 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
AnnaBridge 167:e84263d55307 16464 #define USB_OTG_DIEPINT_BERR_Pos (12U)
AnnaBridge 167:e84263d55307 16465 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
AnnaBridge 167:e84263d55307 16466 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
AnnaBridge 167:e84263d55307 16467 #define USB_OTG_DIEPINT_NAK_Pos (13U)
AnnaBridge 167:e84263d55307 16468 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
AnnaBridge 167:e84263d55307 16469 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
<> 144:ef7eb2e8f9f7 16470
<> 144:ef7eb2e8f9f7 16471 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
AnnaBridge 167:e84263d55307 16472 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
AnnaBridge 167:e84263d55307 16473 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16474 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
AnnaBridge 167:e84263d55307 16475 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
AnnaBridge 167:e84263d55307 16476 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16477 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
AnnaBridge 167:e84263d55307 16478 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
AnnaBridge 167:e84263d55307 16479 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
AnnaBridge 167:e84263d55307 16480 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
AnnaBridge 167:e84263d55307 16481 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
AnnaBridge 167:e84263d55307 16482 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16483 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
AnnaBridge 167:e84263d55307 16484 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
AnnaBridge 167:e84263d55307 16485 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16486 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
AnnaBridge 167:e84263d55307 16487 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
AnnaBridge 167:e84263d55307 16488 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
AnnaBridge 167:e84263d55307 16489 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
AnnaBridge 167:e84263d55307 16490 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
AnnaBridge 167:e84263d55307 16491 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16492 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
AnnaBridge 167:e84263d55307 16493 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
AnnaBridge 167:e84263d55307 16494 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
AnnaBridge 167:e84263d55307 16495 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
AnnaBridge 167:e84263d55307 16496 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
AnnaBridge 167:e84263d55307 16497 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
AnnaBridge 167:e84263d55307 16498 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
AnnaBridge 167:e84263d55307 16499 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
AnnaBridge 167:e84263d55307 16500 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
AnnaBridge 167:e84263d55307 16501 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
AnnaBridge 167:e84263d55307 16502 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
AnnaBridge 167:e84263d55307 16503 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
AnnaBridge 167:e84263d55307 16504 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
<> 144:ef7eb2e8f9f7 16505
<> 144:ef7eb2e8f9f7 16506 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 144:ef7eb2e8f9f7 16507
AnnaBridge 167:e84263d55307 16508 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16509 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 167:e84263d55307 16510 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 167:e84263d55307 16511 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 167:e84263d55307 16512 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 167:e84263d55307 16513 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 167:e84263d55307 16514 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
AnnaBridge 167:e84263d55307 16515 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
AnnaBridge 167:e84263d55307 16516 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
AnnaBridge 167:e84263d55307 16517 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
AnnaBridge 167:e84263d55307 16518 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16519 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 167:e84263d55307 16520 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 167:e84263d55307 16521 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
AnnaBridge 167:e84263d55307 16522 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 167:e84263d55307 16523 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 167:e84263d55307 16524 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
AnnaBridge 167:e84263d55307 16525 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 16526 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
AnnaBridge 167:e84263d55307 16527 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
AnnaBridge 167:e84263d55307 16528 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
AnnaBridge 167:e84263d55307 16529 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
AnnaBridge 167:e84263d55307 16530 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16531 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 16532
AnnaBridge 167:e84263d55307 16533 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
AnnaBridge 167:e84263d55307 16534 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
AnnaBridge 167:e84263d55307 16535 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 16536 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 167:e84263d55307 16537
AnnaBridge 167:e84263d55307 16538 /******************** Bit definition for USB_OTG_HCDMA register ********************/
AnnaBridge 167:e84263d55307 16539 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
AnnaBridge 167:e84263d55307 16540 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 167:e84263d55307 16541 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
AnnaBridge 167:e84263d55307 16542
AnnaBridge 167:e84263d55307 16543 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
AnnaBridge 167:e84263d55307 16544 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
AnnaBridge 167:e84263d55307 16545 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16546 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
AnnaBridge 167:e84263d55307 16547
AnnaBridge 167:e84263d55307 16548 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
AnnaBridge 167:e84263d55307 16549 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
AnnaBridge 167:e84263d55307 16550 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
AnnaBridge 167:e84263d55307 16551 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
AnnaBridge 167:e84263d55307 16552 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
AnnaBridge 167:e84263d55307 16553 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 167:e84263d55307 16554 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
AnnaBridge 167:e84263d55307 16555
AnnaBridge 167:e84263d55307 16556 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
AnnaBridge 167:e84263d55307 16557
AnnaBridge 167:e84263d55307 16558 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16559 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
AnnaBridge 167:e84263d55307 16560 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
AnnaBridge 167:e84263d55307 16561 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
AnnaBridge 167:e84263d55307 16562 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
AnnaBridge 167:e84263d55307 16563 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
AnnaBridge 167:e84263d55307 16564 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
AnnaBridge 167:e84263d55307 16565 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
AnnaBridge 167:e84263d55307 16566 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
AnnaBridge 167:e84263d55307 16567 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
AnnaBridge 167:e84263d55307 16568 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
AnnaBridge 167:e84263d55307 16569 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
AnnaBridge 167:e84263d55307 16570 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
AnnaBridge 167:e84263d55307 16571 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16572 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
AnnaBridge 167:e84263d55307 16573 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
AnnaBridge 167:e84263d55307 16574 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
AnnaBridge 167:e84263d55307 16575 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
AnnaBridge 167:e84263d55307 16576 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
AnnaBridge 167:e84263d55307 16577 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
AnnaBridge 167:e84263d55307 16578 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
AnnaBridge 167:e84263d55307 16579 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
AnnaBridge 167:e84263d55307 16580 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
AnnaBridge 167:e84263d55307 16581 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
AnnaBridge 167:e84263d55307 16582 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
AnnaBridge 167:e84263d55307 16583 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
AnnaBridge 167:e84263d55307 16584 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
AnnaBridge 167:e84263d55307 16585 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
AnnaBridge 167:e84263d55307 16586 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
AnnaBridge 167:e84263d55307 16587 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
AnnaBridge 167:e84263d55307 16588 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
AnnaBridge 167:e84263d55307 16589 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
AnnaBridge 167:e84263d55307 16590 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
AnnaBridge 167:e84263d55307 16591 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
AnnaBridge 167:e84263d55307 16592 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
AnnaBridge 167:e84263d55307 16593 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
AnnaBridge 167:e84263d55307 16594 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
AnnaBridge 167:e84263d55307 16595 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
AnnaBridge 167:e84263d55307 16596
AnnaBridge 167:e84263d55307 16597 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
AnnaBridge 167:e84263d55307 16598 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
AnnaBridge 167:e84263d55307 16599 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16600 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
AnnaBridge 167:e84263d55307 16601 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
AnnaBridge 167:e84263d55307 16602 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16603 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
AnnaBridge 167:e84263d55307 16604 #define USB_OTG_DOEPINT_STUP_Pos (3U)
AnnaBridge 167:e84263d55307 16605 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
AnnaBridge 167:e84263d55307 16606 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
AnnaBridge 167:e84263d55307 16607 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
AnnaBridge 167:e84263d55307 16608 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16609 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
AnnaBridge 167:e84263d55307 16610 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
AnnaBridge 167:e84263d55307 16611 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
AnnaBridge 167:e84263d55307 16612 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
AnnaBridge 167:e84263d55307 16613 #define USB_OTG_DOEPINT_NYET_Pos (14U)
AnnaBridge 167:e84263d55307 16614 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
AnnaBridge 167:e84263d55307 16615 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
AnnaBridge 167:e84263d55307 16616
AnnaBridge 167:e84263d55307 16617 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
AnnaBridge 167:e84263d55307 16618
AnnaBridge 167:e84263d55307 16619 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
AnnaBridge 167:e84263d55307 16620 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
AnnaBridge 167:e84263d55307 16621 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
AnnaBridge 167:e84263d55307 16622 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
AnnaBridge 167:e84263d55307 16623 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
AnnaBridge 167:e84263d55307 16624 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
AnnaBridge 167:e84263d55307 16625
AnnaBridge 167:e84263d55307 16626 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
AnnaBridge 167:e84263d55307 16627 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
AnnaBridge 167:e84263d55307 16628 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
AnnaBridge 167:e84263d55307 16629 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
AnnaBridge 167:e84263d55307 16630 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
<> 144:ef7eb2e8f9f7 16631
<> 144:ef7eb2e8f9f7 16632 /******************** Bit definition for PCGCCTL register ********************/
AnnaBridge 167:e84263d55307 16633 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
AnnaBridge 167:e84263d55307 16634 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
AnnaBridge 167:e84263d55307 16635 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
AnnaBridge 167:e84263d55307 16636 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
AnnaBridge 167:e84263d55307 16637 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
AnnaBridge 167:e84263d55307 16638 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
AnnaBridge 167:e84263d55307 16639 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
AnnaBridge 167:e84263d55307 16640 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
AnnaBridge 167:e84263d55307 16641 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
<> 144:ef7eb2e8f9f7 16642
<> 144:ef7eb2e8f9f7 16643 /**
<> 144:ef7eb2e8f9f7 16644 * @}
<> 144:ef7eb2e8f9f7 16645 */
<> 144:ef7eb2e8f9f7 16646
<> 144:ef7eb2e8f9f7 16647 /**
<> 144:ef7eb2e8f9f7 16648 * @}
<> 144:ef7eb2e8f9f7 16649 */
<> 144:ef7eb2e8f9f7 16650
<> 144:ef7eb2e8f9f7 16651 /** @addtogroup Exported_macros
<> 144:ef7eb2e8f9f7 16652 * @{
<> 144:ef7eb2e8f9f7 16653 */
<> 144:ef7eb2e8f9f7 16654
<> 144:ef7eb2e8f9f7 16655 /******************************* ADC Instances ********************************/
<> 144:ef7eb2e8f9f7 16656 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
<> 144:ef7eb2e8f9f7 16657 ((INSTANCE) == ADC2) || \
<> 144:ef7eb2e8f9f7 16658 ((INSTANCE) == ADC3))
<> 144:ef7eb2e8f9f7 16659
AnnaBridge 167:e84263d55307 16660 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 167:e84263d55307 16661
AnnaBridge 167:e84263d55307 16662 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
AnnaBridge 167:e84263d55307 16663
<> 144:ef7eb2e8f9f7 16664 /******************************* CAN Instances ********************************/
<> 144:ef7eb2e8f9f7 16665 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
<> 144:ef7eb2e8f9f7 16666 ((INSTANCE) == CAN2))
<> 144:ef7eb2e8f9f7 16667 /******************************* CRC Instances ********************************/
<> 144:ef7eb2e8f9f7 16668 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
<> 144:ef7eb2e8f9f7 16669
<> 144:ef7eb2e8f9f7 16670 /******************************* DAC Instances ********************************/
AnnaBridge 167:e84263d55307 16671 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
<> 144:ef7eb2e8f9f7 16672
<> 144:ef7eb2e8f9f7 16673 /******************************* DCMI Instances *******************************/
<> 144:ef7eb2e8f9f7 16674 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
<> 144:ef7eb2e8f9f7 16675
<> 144:ef7eb2e8f9f7 16676 /******************************* DMA2D Instances *******************************/
<> 144:ef7eb2e8f9f7 16677 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
<> 144:ef7eb2e8f9f7 16678
<> 144:ef7eb2e8f9f7 16679 /******************************** DMA Instances *******************************/
<> 144:ef7eb2e8f9f7 16680 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
<> 144:ef7eb2e8f9f7 16681 ((INSTANCE) == DMA1_Stream1) || \
<> 144:ef7eb2e8f9f7 16682 ((INSTANCE) == DMA1_Stream2) || \
<> 144:ef7eb2e8f9f7 16683 ((INSTANCE) == DMA1_Stream3) || \
<> 144:ef7eb2e8f9f7 16684 ((INSTANCE) == DMA1_Stream4) || \
<> 144:ef7eb2e8f9f7 16685 ((INSTANCE) == DMA1_Stream5) || \
<> 144:ef7eb2e8f9f7 16686 ((INSTANCE) == DMA1_Stream6) || \
<> 144:ef7eb2e8f9f7 16687 ((INSTANCE) == DMA1_Stream7) || \
<> 144:ef7eb2e8f9f7 16688 ((INSTANCE) == DMA2_Stream0) || \
<> 144:ef7eb2e8f9f7 16689 ((INSTANCE) == DMA2_Stream1) || \
<> 144:ef7eb2e8f9f7 16690 ((INSTANCE) == DMA2_Stream2) || \
<> 144:ef7eb2e8f9f7 16691 ((INSTANCE) == DMA2_Stream3) || \
<> 144:ef7eb2e8f9f7 16692 ((INSTANCE) == DMA2_Stream4) || \
<> 144:ef7eb2e8f9f7 16693 ((INSTANCE) == DMA2_Stream5) || \
<> 144:ef7eb2e8f9f7 16694 ((INSTANCE) == DMA2_Stream6) || \
<> 144:ef7eb2e8f9f7 16695 ((INSTANCE) == DMA2_Stream7))
<> 144:ef7eb2e8f9f7 16696
<> 144:ef7eb2e8f9f7 16697 /******************************* GPIO Instances *******************************/
<> 144:ef7eb2e8f9f7 16698 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
<> 144:ef7eb2e8f9f7 16699 ((INSTANCE) == GPIOB) || \
<> 144:ef7eb2e8f9f7 16700 ((INSTANCE) == GPIOC) || \
<> 144:ef7eb2e8f9f7 16701 ((INSTANCE) == GPIOD) || \
<> 144:ef7eb2e8f9f7 16702 ((INSTANCE) == GPIOE) || \
<> 144:ef7eb2e8f9f7 16703 ((INSTANCE) == GPIOF) || \
<> 144:ef7eb2e8f9f7 16704 ((INSTANCE) == GPIOG) || \
<> 144:ef7eb2e8f9f7 16705 ((INSTANCE) == GPIOH) || \
<> 144:ef7eb2e8f9f7 16706 ((INSTANCE) == GPIOI) || \
<> 144:ef7eb2e8f9f7 16707 ((INSTANCE) == GPIOJ) || \
<> 144:ef7eb2e8f9f7 16708 ((INSTANCE) == GPIOK))
<> 144:ef7eb2e8f9f7 16709
<> 144:ef7eb2e8f9f7 16710 /******************************** I2C Instances *******************************/
<> 144:ef7eb2e8f9f7 16711 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
<> 144:ef7eb2e8f9f7 16712 ((INSTANCE) == I2C2) || \
<> 144:ef7eb2e8f9f7 16713 ((INSTANCE) == I2C3))
<> 144:ef7eb2e8f9f7 16714
AnnaBridge 167:e84263d55307 16715 /******************************* SMBUS Instances ******************************/
AnnaBridge 167:e84263d55307 16716 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
AnnaBridge 167:e84263d55307 16717
<> 144:ef7eb2e8f9f7 16718 /******************************** I2S Instances *******************************/
AnnaBridge 167:e84263d55307 16719
<> 144:ef7eb2e8f9f7 16720 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 167:e84263d55307 16721 ((INSTANCE) == SPI3))
<> 144:ef7eb2e8f9f7 16722
<> 144:ef7eb2e8f9f7 16723 /*************************** I2S Extended Instances ***************************/
AnnaBridge 167:e84263d55307 16724 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
AnnaBridge 167:e84263d55307 16725 ((INSTANCE) == I2S3ext))
AnnaBridge 167:e84263d55307 16726 /* Legacy Defines */
AnnaBridge 167:e84263d55307 16727 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
<> 144:ef7eb2e8f9f7 16728
<> 144:ef7eb2e8f9f7 16729 /****************************** LTDC Instances ********************************/
<> 144:ef7eb2e8f9f7 16730 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
<> 144:ef7eb2e8f9f7 16731 /******************************* RNG Instances ********************************/
<> 144:ef7eb2e8f9f7 16732 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
<> 144:ef7eb2e8f9f7 16733
<> 144:ef7eb2e8f9f7 16734 /****************************** RTC Instances *********************************/
<> 144:ef7eb2e8f9f7 16735 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
<> 144:ef7eb2e8f9f7 16736
<> 144:ef7eb2e8f9f7 16737 /******************************* SAI Instances ********************************/
<> 144:ef7eb2e8f9f7 16738 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
<> 144:ef7eb2e8f9f7 16739 ((PERIPH) == SAI1_Block_B))
<> 144:ef7eb2e8f9f7 16740 /* Legacy define */
AnnaBridge 167:e84263d55307 16741
<> 144:ef7eb2e8f9f7 16742 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
<> 144:ef7eb2e8f9f7 16743
<> 144:ef7eb2e8f9f7 16744 /******************************** SPI Instances *******************************/
AnnaBridge 167:e84263d55307 16745 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 167:e84263d55307 16746 ((INSTANCE) == SPI2) || \
AnnaBridge 167:e84263d55307 16747 ((INSTANCE) == SPI3) || \
AnnaBridge 167:e84263d55307 16748 ((INSTANCE) == SPI4) || \
AnnaBridge 167:e84263d55307 16749 ((INSTANCE) == SPI5) || \
<> 144:ef7eb2e8f9f7 16750 ((INSTANCE) == SPI6))
<> 144:ef7eb2e8f9f7 16751
<> 144:ef7eb2e8f9f7 16752
<> 144:ef7eb2e8f9f7 16753 /****************** TIM Instances : All supported instances *******************/
AnnaBridge 167:e84263d55307 16754 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16755 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 16756 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 16757 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 16758 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16759 ((INSTANCE) == TIM6) || \
AnnaBridge 167:e84263d55307 16760 ((INSTANCE) == TIM7) || \
AnnaBridge 167:e84263d55307 16761 ((INSTANCE) == TIM8) || \
AnnaBridge 167:e84263d55307 16762 ((INSTANCE) == TIM9) || \
AnnaBridge 167:e84263d55307 16763 ((INSTANCE) == TIM10)|| \
AnnaBridge 167:e84263d55307 16764 ((INSTANCE) == TIM11)|| \
AnnaBridge 167:e84263d55307 16765 ((INSTANCE) == TIM12)|| \
AnnaBridge 167:e84263d55307 16766 ((INSTANCE) == TIM13)|| \
AnnaBridge 167:e84263d55307 16767 ((INSTANCE) == TIM14))
<> 144:ef7eb2e8f9f7 16768
<> 144:ef7eb2e8f9f7 16769 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 144:ef7eb2e8f9f7 16770 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16771 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16772 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16773 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16774 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16775 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 16776 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 16777 ((INSTANCE) == TIM10) || \
<> 144:ef7eb2e8f9f7 16778 ((INSTANCE) == TIM11) || \
<> 144:ef7eb2e8f9f7 16779 ((INSTANCE) == TIM12) || \
<> 144:ef7eb2e8f9f7 16780 ((INSTANCE) == TIM13) || \
<> 144:ef7eb2e8f9f7 16781 ((INSTANCE) == TIM14))
<> 144:ef7eb2e8f9f7 16782
<> 144:ef7eb2e8f9f7 16783 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 16784 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16785 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16786 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16787 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16788 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16789 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 16790 ((INSTANCE) == TIM9) || \
AnnaBridge 167:e84263d55307 16791 ((INSTANCE) == TIM12))
<> 144:ef7eb2e8f9f7 16792
<> 144:ef7eb2e8f9f7 16793 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 16794 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16795 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16796 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16797 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16798 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16799 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16800
<> 144:ef7eb2e8f9f7 16801 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 144:ef7eb2e8f9f7 16802 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16803 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16804 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16805 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16806 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16807 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16808
<> 144:ef7eb2e8f9f7 16809 /******************** TIM Instances : Advanced-control timers *****************/
<> 144:ef7eb2e8f9f7 16810 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16811 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16812
<> 144:ef7eb2e8f9f7 16813 /******************* TIM Instances : Timer input XOR function *****************/
<> 144:ef7eb2e8f9f7 16814 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16815 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16816 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16817 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16818 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16819 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16820
<> 144:ef7eb2e8f9f7 16821 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 144:ef7eb2e8f9f7 16822 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16823 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16824 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16825 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16826 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16827 ((INSTANCE) == TIM6) || \
<> 144:ef7eb2e8f9f7 16828 ((INSTANCE) == TIM7) || \
<> 144:ef7eb2e8f9f7 16829 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16830
<> 144:ef7eb2e8f9f7 16831 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 144:ef7eb2e8f9f7 16832 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16833 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16834 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16835 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16836 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16837 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16838
<> 144:ef7eb2e8f9f7 16839 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 144:ef7eb2e8f9f7 16840 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16841 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16842 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16843 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16844 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16845 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16846
<> 144:ef7eb2e8f9f7 16847 /******************** TIM Instances : DMA burst feature ***********************/
<> 144:ef7eb2e8f9f7 16848 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16849 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16850 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16851 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16852 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16853 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16854
<> 144:ef7eb2e8f9f7 16855 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
AnnaBridge 167:e84263d55307 16856 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16857 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 16858 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 16859 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 16860 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16861 ((INSTANCE) == TIM6) || \
AnnaBridge 167:e84263d55307 16862 ((INSTANCE) == TIM7) || \
AnnaBridge 167:e84263d55307 16863 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16864
<> 144:ef7eb2e8f9f7 16865 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 144:ef7eb2e8f9f7 16866 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16867 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16868 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16869 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16870 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16871 ((INSTANCE) == TIM8) || \
<> 144:ef7eb2e8f9f7 16872 ((INSTANCE) == TIM9) || \
<> 144:ef7eb2e8f9f7 16873 ((INSTANCE) == TIM12))
<> 144:ef7eb2e8f9f7 16874
<> 144:ef7eb2e8f9f7 16875 /********************** TIM Instances : 32 bit Counter ************************/
<> 144:ef7eb2e8f9f7 16876 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16877 ((INSTANCE) == TIM5))
<> 144:ef7eb2e8f9f7 16878
<> 144:ef7eb2e8f9f7 16879 /***************** TIM Instances : external trigger input availabe ************/
<> 144:ef7eb2e8f9f7 16880 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
<> 144:ef7eb2e8f9f7 16881 ((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16882 ((INSTANCE) == TIM3) || \
<> 144:ef7eb2e8f9f7 16883 ((INSTANCE) == TIM4) || \
<> 144:ef7eb2e8f9f7 16884 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16885 ((INSTANCE) == TIM8))
<> 144:ef7eb2e8f9f7 16886
<> 144:ef7eb2e8f9f7 16887 /****************** TIM Instances : remapping capability **********************/
<> 144:ef7eb2e8f9f7 16888 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
<> 144:ef7eb2e8f9f7 16889 ((INSTANCE) == TIM5) || \
<> 144:ef7eb2e8f9f7 16890 ((INSTANCE) == TIM11))
<> 144:ef7eb2e8f9f7 16891
<> 144:ef7eb2e8f9f7 16892 /******************* TIM Instances : output(s) available **********************/
<> 144:ef7eb2e8f9f7 16893 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 16894 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 16895 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16896 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16897 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16898 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16899 || \
<> 144:ef7eb2e8f9f7 16900 (((INSTANCE) == TIM2) && \
<> 144:ef7eb2e8f9f7 16901 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16902 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16903 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16904 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16905 || \
<> 144:ef7eb2e8f9f7 16906 (((INSTANCE) == TIM3) && \
<> 144:ef7eb2e8f9f7 16907 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16908 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16909 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16910 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16911 || \
<> 144:ef7eb2e8f9f7 16912 (((INSTANCE) == TIM4) && \
<> 144:ef7eb2e8f9f7 16913 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16914 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16915 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16916 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16917 || \
<> 144:ef7eb2e8f9f7 16918 (((INSTANCE) == TIM5) && \
<> 144:ef7eb2e8f9f7 16919 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16920 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16921 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16922 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16923 || \
<> 144:ef7eb2e8f9f7 16924 (((INSTANCE) == TIM8) && \
<> 144:ef7eb2e8f9f7 16925 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16926 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16927 ((CHANNEL) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 16928 ((CHANNEL) == TIM_CHANNEL_4))) \
<> 144:ef7eb2e8f9f7 16929 || \
<> 144:ef7eb2e8f9f7 16930 (((INSTANCE) == TIM9) && \
<> 144:ef7eb2e8f9f7 16931 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16932 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 16933 || \
<> 144:ef7eb2e8f9f7 16934 (((INSTANCE) == TIM10) && \
<> 144:ef7eb2e8f9f7 16935 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 16936 || \
<> 144:ef7eb2e8f9f7 16937 (((INSTANCE) == TIM11) && \
<> 144:ef7eb2e8f9f7 16938 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 16939 || \
<> 144:ef7eb2e8f9f7 16940 (((INSTANCE) == TIM12) && \
<> 144:ef7eb2e8f9f7 16941 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16942 ((CHANNEL) == TIM_CHANNEL_2))) \
<> 144:ef7eb2e8f9f7 16943 || \
<> 144:ef7eb2e8f9f7 16944 (((INSTANCE) == TIM13) && \
<> 144:ef7eb2e8f9f7 16945 (((CHANNEL) == TIM_CHANNEL_1))) \
<> 144:ef7eb2e8f9f7 16946 || \
<> 144:ef7eb2e8f9f7 16947 (((INSTANCE) == TIM14) && \
<> 144:ef7eb2e8f9f7 16948 (((CHANNEL) == TIM_CHANNEL_1))))
<> 144:ef7eb2e8f9f7 16949
<> 144:ef7eb2e8f9f7 16950 /************ TIM Instances : complementary output(s) available ***************/
<> 144:ef7eb2e8f9f7 16951 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
<> 144:ef7eb2e8f9f7 16952 ((((INSTANCE) == TIM1) && \
<> 144:ef7eb2e8f9f7 16953 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16954 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16955 ((CHANNEL) == TIM_CHANNEL_3))) \
<> 144:ef7eb2e8f9f7 16956 || \
<> 144:ef7eb2e8f9f7 16957 (((INSTANCE) == TIM8) && \
<> 144:ef7eb2e8f9f7 16958 (((CHANNEL) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 16959 ((CHANNEL) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 16960 ((CHANNEL) == TIM_CHANNEL_3))))
<> 144:ef7eb2e8f9f7 16961
AnnaBridge 167:e84263d55307 16962 /****************** TIM Instances : supporting counting mode selection ********/
AnnaBridge 167:e84263d55307 16963 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16964 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 16965 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 16966 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 16967 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16968 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 16969
AnnaBridge 167:e84263d55307 16970 /****************** TIM Instances : supporting clock division *****************/
AnnaBridge 167:e84263d55307 16971 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16972 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 16973 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 16974 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 16975 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16976 ((INSTANCE) == TIM8) || \
AnnaBridge 167:e84263d55307 16977 ((INSTANCE) == TIM9) || \
AnnaBridge 167:e84263d55307 16978 ((INSTANCE) == TIM10)|| \
AnnaBridge 167:e84263d55307 16979 ((INSTANCE) == TIM11)|| \
AnnaBridge 167:e84263d55307 16980 ((INSTANCE) == TIM12)|| \
AnnaBridge 167:e84263d55307 16981 ((INSTANCE) == TIM13)|| \
AnnaBridge 167:e84263d55307 16982 ((INSTANCE) == TIM14))
AnnaBridge 167:e84263d55307 16983
AnnaBridge 167:e84263d55307 16984 /****************** TIM Instances : supporting commutation event generation ***/
AnnaBridge 167:e84263d55307 16985 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
AnnaBridge 167:e84263d55307 16986 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 16987
AnnaBridge 167:e84263d55307 16988
AnnaBridge 167:e84263d55307 16989 /****************** TIM Instances : supporting OCxREF clear *******************/
AnnaBridge 167:e84263d55307 16990 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16991 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 16992 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 16993 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 16994 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 16995 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 16996
AnnaBridge 167:e84263d55307 16997 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
AnnaBridge 167:e84263d55307 16998 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 16999 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 17000 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 17001 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 17002 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 17003 ((INSTANCE) == TIM8) || \
AnnaBridge 167:e84263d55307 17004 ((INSTANCE) == TIM9) || \
AnnaBridge 167:e84263d55307 17005 ((INSTANCE) == TIM12))
AnnaBridge 167:e84263d55307 17006
AnnaBridge 167:e84263d55307 17007 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
AnnaBridge 167:e84263d55307 17008 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 17009 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 17010 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 17011 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 17012 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 17013 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 17014
AnnaBridge 167:e84263d55307 17015 /****************** TIM Instances : supporting repetition counter *************/
AnnaBridge 167:e84263d55307 17016 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 17017 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 17018
AnnaBridge 167:e84263d55307 17019 /****************** TIM Instances : supporting encoder interface **************/
AnnaBridge 167:e84263d55307 17020 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 17021 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 17022 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 17023 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 17024 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 17025 ((INSTANCE) == TIM8) || \
AnnaBridge 167:e84263d55307 17026 ((INSTANCE) == TIM9) || \
AnnaBridge 167:e84263d55307 17027 ((INSTANCE) == TIM12))
AnnaBridge 167:e84263d55307 17028 /****************** TIM Instances : supporting Hall sensor interface **********/
AnnaBridge 167:e84263d55307 17029 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 17030 ((INSTANCE) == TIM2) || \
AnnaBridge 167:e84263d55307 17031 ((INSTANCE) == TIM3) || \
AnnaBridge 167:e84263d55307 17032 ((INSTANCE) == TIM4) || \
AnnaBridge 167:e84263d55307 17033 ((INSTANCE) == TIM5) || \
AnnaBridge 167:e84263d55307 17034 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 17035 /****************** TIM Instances : supporting the break function *************/
AnnaBridge 167:e84263d55307 17036 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
AnnaBridge 167:e84263d55307 17037 ((INSTANCE) == TIM8))
AnnaBridge 167:e84263d55307 17038
<> 144:ef7eb2e8f9f7 17039 /******************** USART Instances : Synchronous mode **********************/
<> 144:ef7eb2e8f9f7 17040 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 17041 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 17042 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 17043 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 17044
AnnaBridge 167:e84263d55307 17045 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 167:e84263d55307 17046 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 167:e84263d55307 17047 ((INSTANCE) == USART2) || \
AnnaBridge 167:e84263d55307 17048 ((INSTANCE) == USART3) || \
AnnaBridge 167:e84263d55307 17049 ((INSTANCE) == UART4) || \
AnnaBridge 167:e84263d55307 17050 ((INSTANCE) == UART5) || \
AnnaBridge 167:e84263d55307 17051 ((INSTANCE) == USART6) || \
AnnaBridge 167:e84263d55307 17052 ((INSTANCE) == UART7) || \
AnnaBridge 167:e84263d55307 17053 ((INSTANCE) == UART8))
AnnaBridge 167:e84263d55307 17054
AnnaBridge 167:e84263d55307 17055 /* Legacy defines */
AnnaBridge 167:e84263d55307 17056 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
<> 144:ef7eb2e8f9f7 17057
<> 144:ef7eb2e8f9f7 17058 /****************** UART Instances : Hardware Flow control ********************/
<> 144:ef7eb2e8f9f7 17059 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 17060 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 17061 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 17062 ((INSTANCE) == USART6))
AnnaBridge 167:e84263d55307 17063 /******************** UART Instances : LIN mode **********************/
AnnaBridge 167:e84263d55307 17064 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
AnnaBridge 167:e84263d55307 17065
AnnaBridge 167:e84263d55307 17066 /********************* UART Instances : Smart card mode ***********************/
<> 144:ef7eb2e8f9f7 17067 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 17068 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 17069 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 17070 ((INSTANCE) == USART6))
<> 144:ef7eb2e8f9f7 17071
<> 144:ef7eb2e8f9f7 17072 /*********************** UART Instances : IRDA mode ***************************/
<> 144:ef7eb2e8f9f7 17073 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
<> 144:ef7eb2e8f9f7 17074 ((INSTANCE) == USART2) || \
<> 144:ef7eb2e8f9f7 17075 ((INSTANCE) == USART3) || \
<> 144:ef7eb2e8f9f7 17076 ((INSTANCE) == UART4) || \
<> 144:ef7eb2e8f9f7 17077 ((INSTANCE) == UART5) || \
<> 144:ef7eb2e8f9f7 17078 ((INSTANCE) == USART6) || \
<> 144:ef7eb2e8f9f7 17079 ((INSTANCE) == UART7) || \
AnnaBridge 167:e84263d55307 17080 ((INSTANCE) == UART8))
<> 144:ef7eb2e8f9f7 17081
<> 144:ef7eb2e8f9f7 17082 /*********************** PCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 17083 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
AnnaBridge 167:e84263d55307 17084 ((INSTANCE) == USB_OTG_HS))
<> 144:ef7eb2e8f9f7 17085
<> 144:ef7eb2e8f9f7 17086 /*********************** HCD Instances ****************************************/
<> 144:ef7eb2e8f9f7 17087 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
<> 144:ef7eb2e8f9f7 17088 ((INSTANCE) == USB_OTG_HS))
<> 144:ef7eb2e8f9f7 17089
AnnaBridge 167:e84263d55307 17090 /****************************** SDIO Instances ********************************/
AnnaBridge 167:e84263d55307 17091 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
<> 144:ef7eb2e8f9f7 17092
<> 144:ef7eb2e8f9f7 17093 /****************************** IWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 17094 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
<> 144:ef7eb2e8f9f7 17095
<> 144:ef7eb2e8f9f7 17096 /****************************** WWDG Instances ********************************/
<> 144:ef7eb2e8f9f7 17097 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
<> 144:ef7eb2e8f9f7 17098
<> 144:ef7eb2e8f9f7 17099 /****************************** USB Exported Constants ************************/
<> 144:ef7eb2e8f9f7 17100 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
<> 144:ef7eb2e8f9f7 17101 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 17102 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
<> 144:ef7eb2e8f9f7 17103 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
<> 144:ef7eb2e8f9f7 17104
AnnaBridge 167:e84263d55307 17105 /*
AnnaBridge 167:e84263d55307 17106 * @brief Specific devices reset values definitions
AnnaBridge 167:e84263d55307 17107 */
AnnaBridge 167:e84263d55307 17108 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
AnnaBridge 167:e84263d55307 17109 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
AnnaBridge 167:e84263d55307 17110 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
AnnaBridge 167:e84263d55307 17111
AnnaBridge 167:e84263d55307 17112 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
AnnaBridge 167:e84263d55307 17113 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
AnnaBridge 167:e84263d55307 17114 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
AnnaBridge 167:e84263d55307 17115 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
AnnaBridge 167:e84263d55307 17116 #define RCC_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
AnnaBridge 167:e84263d55307 17117 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
AnnaBridge 167:e84263d55307 17118 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
AnnaBridge 167:e84263d55307 17119 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
AnnaBridge 167:e84263d55307 17120
AnnaBridge 167:e84263d55307 17121 #define RCC_PLLN_MIN_VALUE 50U
AnnaBridge 167:e84263d55307 17122 #define RCC_PLLN_MAX_VALUE 432U
AnnaBridge 167:e84263d55307 17123
AnnaBridge 167:e84263d55307 17124 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
AnnaBridge 167:e84263d55307 17125 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
AnnaBridge 167:e84263d55307 17126 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
AnnaBridge 167:e84263d55307 17127 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
AnnaBridge 167:e84263d55307 17128 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
AnnaBridge 167:e84263d55307 17129
AnnaBridge 167:e84263d55307 17130 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
AnnaBridge 167:e84263d55307 17131 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
AnnaBridge 167:e84263d55307 17132 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
AnnaBridge 167:e84263d55307 17133 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
AnnaBridge 167:e84263d55307 17134 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
AnnaBridge 167:e84263d55307 17135
AnnaBridge 167:e84263d55307 17136 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
AnnaBridge 167:e84263d55307 17137 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
AnnaBridge 167:e84263d55307 17138 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
AnnaBridge 167:e84263d55307 17139
<> 144:ef7eb2e8f9f7 17140 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U
<> 144:ef7eb2e8f9f7 17141 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
<> 144:ef7eb2e8f9f7 17142 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
<> 144:ef7eb2e8f9f7 17143 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
<> 144:ef7eb2e8f9f7 17144 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17145 /* For a painless codes migration between the STM32F4xx device product */
<> 144:ef7eb2e8f9f7 17146 /* lines, the aliases defined below are put in place to overcome the */
<> 144:ef7eb2e8f9f7 17147 /* differences in the interrupt handlers and IRQn definitions. */
<> 144:ef7eb2e8f9f7 17148 /* No need to update developed interrupt code when moving across */
<> 144:ef7eb2e8f9f7 17149 /* product lines within the same STM32F4 Family */
<> 144:ef7eb2e8f9f7 17150 /******************************************************************************/
<> 144:ef7eb2e8f9f7 17151 /* Aliases for __IRQn */
<> 144:ef7eb2e8f9f7 17152 #define FSMC_IRQn FMC_IRQn
<> 144:ef7eb2e8f9f7 17153
<> 144:ef7eb2e8f9f7 17154 /* Aliases for __IRQHandler */
<> 144:ef7eb2e8f9f7 17155 #define FSMC_IRQHandler FMC_IRQHandler
<> 144:ef7eb2e8f9f7 17156
<> 144:ef7eb2e8f9f7 17157 /**
<> 144:ef7eb2e8f9f7 17158 * @}
<> 144:ef7eb2e8f9f7 17159 */
AnnaBridge 167:e84263d55307 17160
<> 144:ef7eb2e8f9f7 17161 /**
<> 144:ef7eb2e8f9f7 17162 * @}
<> 144:ef7eb2e8f9f7 17163 */
<> 144:ef7eb2e8f9f7 17164
<> 144:ef7eb2e8f9f7 17165 /**
<> 144:ef7eb2e8f9f7 17166 * @}
<> 144:ef7eb2e8f9f7 17167 */
<> 144:ef7eb2e8f9f7 17168
<> 144:ef7eb2e8f9f7 17169 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 17170 }
<> 144:ef7eb2e8f9f7 17171 #endif /* __cplusplus */
<> 144:ef7eb2e8f9f7 17172
<> 144:ef7eb2e8f9f7 17173 #endif /* __STM32F429xx_H */
<> 144:ef7eb2e8f9f7 17174
<> 144:ef7eb2e8f9f7 17175
<> 144:ef7eb2e8f9f7 17176
<> 144:ef7eb2e8f9f7 17177 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/