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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
160:d5399cc887bb 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file system_stm32f4xx.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V2.6.1
AnnaBridge 167:e84263d55307 6 * @date 14-February-2017
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides two functions and one global variable to be called from
<> 144:ef7eb2e8f9f7 10 * user application:
<> 144:ef7eb2e8f9f7 11 * - SystemInit(): This function is called at startup just after reset and
<> 144:ef7eb2e8f9f7 12 * before branch to main program. This call is made inside
<> 144:ef7eb2e8f9f7 13 * the "startup_stm32f4xx.s" file.
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
<> 144:ef7eb2e8f9f7 16 * by the user application to setup the SysTick
<> 144:ef7eb2e8f9f7 17 * timer or configure other parameters.
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
<> 144:ef7eb2e8f9f7 20 * be called whenever the core clock is changed
<> 144:ef7eb2e8f9f7 21 * during program execution.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * This file configures the system clock as follows:
<> 144:ef7eb2e8f9f7 24 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
<> 144:ef7eb2e8f9f7 26 * | (external 8 MHz clock) | (external 8 MHz clock)
<> 144:ef7eb2e8f9f7 27 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28 * SYSCLK(MHz) | 168 | 180
<> 144:ef7eb2e8f9f7 29 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30 * AHBCLK (MHz) | 168 | 180
<> 144:ef7eb2e8f9f7 31 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32 * APB1CLK (MHz) | 42 | 45
<> 144:ef7eb2e8f9f7 33 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 34 * APB2CLK (MHz) | 84 | 90
<> 144:ef7eb2e8f9f7 35 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 36 * USB capable (48 MHz precise clock) | YES | NO
<> 144:ef7eb2e8f9f7 37 *--------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 * @attention
<> 144:ef7eb2e8f9f7 40 *
<> 160:d5399cc887bb 41 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 44 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 45 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 46 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 47 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 48 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 49 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 51 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 52 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 53 *
<> 144:ef7eb2e8f9f7 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 64 *
<> 144:ef7eb2e8f9f7 65 ******************************************************************************
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /** @addtogroup CMSIS
<> 144:ef7eb2e8f9f7 69 * @{
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup stm32f4xx_system
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /** @addtogroup STM32F4xx_System_Private_Includes
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 #include "stm32f4xx.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 #if !defined (HSE_VALUE)
<> 144:ef7eb2e8f9f7 84 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
<> 144:ef7eb2e8f9f7 85 #endif /* HSE_VALUE */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 #if !defined (HSI_VALUE)
<> 144:ef7eb2e8f9f7 88 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
<> 144:ef7eb2e8f9f7 89 #endif /* HSI_VALUE */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @}
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
<> 144:ef7eb2e8f9f7 96 * @{
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup STM32F4xx_System_Private_Defines
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /************************* Miscellaneous Configuration ************************/
<> 144:ef7eb2e8f9f7 108 /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
<> 144:ef7eb2e8f9f7 109 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 110 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 111 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 112 /* #define DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 113 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
<> 144:ef7eb2e8f9f7 114 STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 117 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 118 /* #define DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 119 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
<> 144:ef7eb2e8f9f7 120 STM32F479xx */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /*!< Uncomment the following line if you need to relocate your vector Table in
<> 144:ef7eb2e8f9f7 123 Internal SRAM. */
<> 144:ef7eb2e8f9f7 124 /* #define VECT_TAB_SRAM */
<> 144:ef7eb2e8f9f7 125 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
<> 144:ef7eb2e8f9f7 126 This value must be a multiple of 0x200. */
<> 144:ef7eb2e8f9f7 127 /******************************************************************************/
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @}
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @addtogroup STM32F4xx_System_Private_Macros
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
<> 144:ef7eb2e8f9f7 138 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
<> 144:ef7eb2e8f9f7 139 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /**
<> 144:ef7eb2e8f9f7 142 * @}
<> 144:ef7eb2e8f9f7 143 */
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 /** @addtogroup STM32F4xx_System_Private_Variables
<> 144:ef7eb2e8f9f7 146 * @{
<> 144:ef7eb2e8f9f7 147 */
<> 144:ef7eb2e8f9f7 148 /* This variable is updated in three ways:
<> 144:ef7eb2e8f9f7 149 1) by calling CMSIS function SystemCoreClockUpdate()
<> 144:ef7eb2e8f9f7 150 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
<> 144:ef7eb2e8f9f7 151 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
<> 144:ef7eb2e8f9f7 152 Note: If you use this function to configure the system clock; then there
<> 144:ef7eb2e8f9f7 153 is no need to call the 2 first functions listed above, since SystemCoreClock
<> 144:ef7eb2e8f9f7 154 variable is updated automatically.
<> 144:ef7eb2e8f9f7 155 */
<> 144:ef7eb2e8f9f7 156 uint32_t SystemCoreClock = 168000000;
<> 144:ef7eb2e8f9f7 157 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
AnnaBridge 167:e84263d55307 158 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
<> 144:ef7eb2e8f9f7 159 /**
<> 144:ef7eb2e8f9f7 160 * @}
<> 144:ef7eb2e8f9f7 161 */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 168 static void SystemInit_ExtMemCtl(void);
<> 144:ef7eb2e8f9f7 169 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 void SetSysClock(void);
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @}
<> 144:ef7eb2e8f9f7 174 */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /** @addtogroup STM32F4xx_System_Private_Functions
<> 144:ef7eb2e8f9f7 177 * @{
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /**
<> 144:ef7eb2e8f9f7 181 * @brief Setup the microcontroller system
<> 144:ef7eb2e8f9f7 182 * Initialize the FPU setting, vector table location and External memory
<> 144:ef7eb2e8f9f7 183 * configuration.
<> 144:ef7eb2e8f9f7 184 * @param None
<> 144:ef7eb2e8f9f7 185 * @retval None
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 void SystemInit(void)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Reset the RCC clock configuration to the default reset state ------------*/
<> 144:ef7eb2e8f9f7 190 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 191 RCC->CR |= (uint32_t)0x00000001;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 194 RCC->CFGR = 0x00000000;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Reset HSEON, CSSON and PLLON bits */
<> 144:ef7eb2e8f9f7 197 RCC->CR &= (uint32_t)0xFEF6FFFF;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 200 RCC->PLLCFGR = 0x24003010;
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 203 RCC->CR &= (uint32_t)0xFFFBFFFF;
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 206 RCC->CIR = 0x00000000;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 209 SystemInit_ExtMemCtl();
<> 144:ef7eb2e8f9f7 210 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 }
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief Update SystemCoreClock variable according to Clock Register Values.
<> 144:ef7eb2e8f9f7 216 * The SystemCoreClock variable contains the core clock (HCLK), it can
<> 144:ef7eb2e8f9f7 217 * be used by the user application to setup the SysTick timer or configure
<> 144:ef7eb2e8f9f7 218 * other parameters.
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * @note Each time the core clock (HCLK) changes, this function must be called
<> 144:ef7eb2e8f9f7 221 * to update SystemCoreClock variable value. Otherwise, any configuration
<> 144:ef7eb2e8f9f7 222 * based on this variable will be incorrect.
<> 144:ef7eb2e8f9f7 223 *
<> 144:ef7eb2e8f9f7 224 * @note - The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 225 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 226 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 227 *
<> 144:ef7eb2e8f9f7 228 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 229 *
<> 144:ef7eb2e8f9f7 230 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 231 *
<> 144:ef7eb2e8f9f7 232 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 233 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 234 *
<> 144:ef7eb2e8f9f7 235 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 236 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 237 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 238 *
<> 144:ef7eb2e8f9f7 239 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
<> 144:ef7eb2e8f9f7 240 * depends on the application requirements), user has to ensure that HSE_VALUE
<> 144:ef7eb2e8f9f7 241 * is same as the real frequency of the crystal used. Otherwise, this function
<> 144:ef7eb2e8f9f7 242 * may have wrong result.
<> 144:ef7eb2e8f9f7 243 *
<> 144:ef7eb2e8f9f7 244 * - The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 245 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 246 *
<> 144:ef7eb2e8f9f7 247 * @param None
<> 144:ef7eb2e8f9f7 248 * @retval None
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 255 tmp = RCC->CFGR & RCC_CFGR_SWS;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 switch (tmp)
<> 144:ef7eb2e8f9f7 258 {
<> 144:ef7eb2e8f9f7 259 case 0x00: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 260 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 261 break;
<> 144:ef7eb2e8f9f7 262 case 0x04: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 263 SystemCoreClock = HSE_VALUE;
<> 144:ef7eb2e8f9f7 264 break;
<> 144:ef7eb2e8f9f7 265 case 0x08: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
<> 144:ef7eb2e8f9f7 268 SYSCLK = PLL_VCO / PLL_P
<> 144:ef7eb2e8f9f7 269 */
<> 144:ef7eb2e8f9f7 270 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
<> 144:ef7eb2e8f9f7 271 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 if (pllsource != 0)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 276 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 277 }
<> 144:ef7eb2e8f9f7 278 else
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 281 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
<> 144:ef7eb2e8f9f7 285 SystemCoreClock = pllvco/pllp;
<> 144:ef7eb2e8f9f7 286 break;
<> 144:ef7eb2e8f9f7 287 default:
<> 144:ef7eb2e8f9f7 288 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 289 break;
<> 144:ef7eb2e8f9f7 290 }
<> 144:ef7eb2e8f9f7 291 /* Compute HCLK frequency --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 292 /* Get HCLK prescaler */
<> 144:ef7eb2e8f9f7 293 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
<> 144:ef7eb2e8f9f7 294 /* HCLK frequency */
<> 144:ef7eb2e8f9f7 295 SystemCoreClock >>= tmp;
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
AnnaBridge 167:e84263d55307 299 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
AnnaBridge 167:e84263d55307 300 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 303 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 304 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 305 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 306 * @param None
<> 144:ef7eb2e8f9f7 307 * @retval None
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 314 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
<> 144:ef7eb2e8f9f7 317 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 320 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 323 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 324 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 325 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 326 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 327 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 328 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 329 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 330 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 331 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 332 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 335 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 336 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 337 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 338 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 339 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 340 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 341 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 342 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 343 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 344 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 347 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 348 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 349 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 350 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 351 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 352 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 353 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 354 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 355 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 356 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 359 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 360 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 361 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 362 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 363 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 364 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 365 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 366 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 367 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 368 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 371 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 372 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 373 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 374 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 375 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 376 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 377 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 378 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 379 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 380 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 383 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 384 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 385 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 386 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 387 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 388 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 389 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 390 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 391 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 392 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 395 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 396 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 397 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 398 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 401 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 404 /* Clock enable command */
<> 144:ef7eb2e8f9f7 405 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 406 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 407 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 408 {
<> 144:ef7eb2e8f9f7 409 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 410 }
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Delay */
<> 144:ef7eb2e8f9f7 413 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* PALL command */
<> 144:ef7eb2e8f9f7 416 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 417 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 418 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 424 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 425 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 426 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 427 {
<> 144:ef7eb2e8f9f7 428 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 /* MRD register program */
<> 144:ef7eb2e8f9f7 432 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 433 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 434 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Set refresh count */
<> 144:ef7eb2e8f9f7 440 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 441 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Disable write protection */
<> 144:ef7eb2e8f9f7 444 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 445 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 448 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 449 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 450 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 451 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 452 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 453 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 454 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 455 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 456 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 457 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 458 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 (void)(tmp);
<> 144:ef7eb2e8f9f7 461 }
<> 144:ef7eb2e8f9f7 462 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 463 #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 464 /**
<> 144:ef7eb2e8f9f7 465 * @brief Setup the external memory controller.
<> 144:ef7eb2e8f9f7 466 * Called in startup_stm32f4xx.s before jump to main.
<> 144:ef7eb2e8f9f7 467 * This function configures the external memories (SRAM/SDRAM)
<> 144:ef7eb2e8f9f7 468 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
<> 144:ef7eb2e8f9f7 469 * @param None
<> 144:ef7eb2e8f9f7 470 * @retval None
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 void SystemInit_ExtMemCtl(void)
<> 144:ef7eb2e8f9f7 473 {
<> 144:ef7eb2e8f9f7 474 __IO uint32_t tmp = 0x00;
<> 144:ef7eb2e8f9f7 475 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 476 || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 477 #if defined (DATA_IN_ExtSDRAM)
<> 144:ef7eb2e8f9f7 478 register uint32_t tmpreg = 0, timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 479 register __IO uint32_t index;
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 482 /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
<> 144:ef7eb2e8f9f7 483 clock */
<> 144:ef7eb2e8f9f7 484 RCC->AHB1ENR |= 0x0000007D;
<> 144:ef7eb2e8f9f7 485 #else
<> 144:ef7eb2e8f9f7 486 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
<> 144:ef7eb2e8f9f7 487 clock */
<> 144:ef7eb2e8f9f7 488 RCC->AHB1ENR |= 0x000001F8;
<> 144:ef7eb2e8f9f7 489 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 490 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 491 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 494 /* Connect PAx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 495 GPIOA->AFR[0] |= 0xC0000000;
<> 144:ef7eb2e8f9f7 496 GPIOA->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 497 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 498 GPIOA->MODER |= 0x00008000;
<> 144:ef7eb2e8f9f7 499 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 500 GPIOA->OSPEEDR |= 0x00008000;
<> 144:ef7eb2e8f9f7 501 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 502 GPIOA->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 503 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 504 GPIOA->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Connect PCx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 507 GPIOC->AFR[0] |= 0x00CC0000;
<> 144:ef7eb2e8f9f7 508 GPIOC->AFR[1] |= 0x00000000;
<> 144:ef7eb2e8f9f7 509 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 510 GPIOC->MODER |= 0x00000A00;
<> 144:ef7eb2e8f9f7 511 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 512 GPIOC->OSPEEDR |= 0x00000A00;
<> 144:ef7eb2e8f9f7 513 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 514 GPIOC->OTYPER |= 0x00000000;
<> 144:ef7eb2e8f9f7 515 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 516 GPIOC->PUPDR |= 0x00000000;
<> 144:ef7eb2e8f9f7 517 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 520 GPIOD->AFR[0] = 0x000000CC;
<> 144:ef7eb2e8f9f7 521 GPIOD->AFR[1] = 0xCC000CCC;
<> 144:ef7eb2e8f9f7 522 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 523 GPIOD->MODER = 0xA02A000A;
<> 144:ef7eb2e8f9f7 524 /* Configure PDx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 525 GPIOD->OSPEEDR = 0xA02A000A;
<> 144:ef7eb2e8f9f7 526 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 527 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 528 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 529 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 532 GPIOE->AFR[0] = 0xC00000CC;
<> 144:ef7eb2e8f9f7 533 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 534 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 535 GPIOE->MODER = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 536 /* Configure PEx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 537 GPIOE->OSPEEDR = 0xAAAA800A;
<> 144:ef7eb2e8f9f7 538 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 539 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 540 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 541 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 544 GPIOF->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 545 GPIOF->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 546 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 547 GPIOF->MODER = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 548 /* Configure PFx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 549 GPIOF->OSPEEDR = 0xAA800AAA;
<> 144:ef7eb2e8f9f7 550 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 551 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 552 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 553 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 556 GPIOG->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 557 GPIOG->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 558 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 559 GPIOG->MODER = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 560 /* Configure PGx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 561 GPIOG->OSPEEDR = 0xAAAAAAAA;
<> 144:ef7eb2e8f9f7 562 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 563 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 564 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 565 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 568 || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 569 /* Connect PHx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 570 GPIOH->AFR[0] = 0x00C0CC00;
<> 144:ef7eb2e8f9f7 571 GPIOH->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 572 /* Configure PHx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 573 GPIOH->MODER = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 574 /* Configure PHx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 575 GPIOH->OSPEEDR = 0xAAAA08A0;
<> 144:ef7eb2e8f9f7 576 /* Configure PHx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 577 GPIOH->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 578 /* No pull-up, pull-down for PHx pins */
<> 144:ef7eb2e8f9f7 579 GPIOH->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Connect PIx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 582 GPIOI->AFR[0] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 583 GPIOI->AFR[1] = 0x00000CC0;
<> 144:ef7eb2e8f9f7 584 /* Configure PIx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 585 GPIOI->MODER = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 586 /* Configure PIx pins speed to 50 MHz */
<> 144:ef7eb2e8f9f7 587 GPIOI->OSPEEDR = 0x0028AAAA;
<> 144:ef7eb2e8f9f7 588 /* Configure PIx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 589 GPIOI->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 590 /* No pull-up, pull-down for PIx pins */
<> 144:ef7eb2e8f9f7 591 GPIOI->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 592 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /*-- FMC Configuration -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 595 /* Enable the FMC interface clock */
<> 144:ef7eb2e8f9f7 596 RCC->AHB3ENR |= 0x00000001;
<> 144:ef7eb2e8f9f7 597 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 598 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Configure and enable SDRAM bank1 */
<> 144:ef7eb2e8f9f7 601 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 602 FMC_Bank5_6->SDCR[0] = 0x00001954;
<> 144:ef7eb2e8f9f7 603 #else
<> 144:ef7eb2e8f9f7 604 FMC_Bank5_6->SDCR[0] = 0x000019E4;
<> 144:ef7eb2e8f9f7 605 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 606 FMC_Bank5_6->SDTR[0] = 0x01115351;
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 /* SDRAM initialization sequence */
<> 144:ef7eb2e8f9f7 609 /* Clock enable command */
<> 144:ef7eb2e8f9f7 610 FMC_Bank5_6->SDCMR = 0x00000011;
<> 144:ef7eb2e8f9f7 611 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 612 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 613 {
<> 144:ef7eb2e8f9f7 614 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 615 }
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /* Delay */
<> 144:ef7eb2e8f9f7 618 for (index = 0; index<1000; index++);
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* PALL command */
<> 144:ef7eb2e8f9f7 621 FMC_Bank5_6->SDCMR = 0x00000012;
<> 144:ef7eb2e8f9f7 622 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 623 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 624 {
<> 144:ef7eb2e8f9f7 625 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 626 }
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Auto refresh command */
<> 144:ef7eb2e8f9f7 629 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 630 FMC_Bank5_6->SDCMR = 0x000000F3;
<> 144:ef7eb2e8f9f7 631 #else
<> 144:ef7eb2e8f9f7 632 FMC_Bank5_6->SDCMR = 0x00000073;
<> 144:ef7eb2e8f9f7 633 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 634 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 635 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* MRD register program */
<> 144:ef7eb2e8f9f7 641 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 642 FMC_Bank5_6->SDCMR = 0x00044014;
<> 144:ef7eb2e8f9f7 643 #else
<> 144:ef7eb2e8f9f7 644 FMC_Bank5_6->SDCMR = 0x00046014;
<> 144:ef7eb2e8f9f7 645 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 646 timeout = 0xFFFF;
<> 144:ef7eb2e8f9f7 647 while((tmpreg != 0) && (timeout-- > 0))
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
<> 144:ef7eb2e8f9f7 650 }
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /* Set refresh count */
<> 144:ef7eb2e8f9f7 653 tmpreg = FMC_Bank5_6->SDRTR;
<> 144:ef7eb2e8f9f7 654 #if defined(STM32F446xx)
<> 144:ef7eb2e8f9f7 655 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
<> 144:ef7eb2e8f9f7 656 #else
<> 144:ef7eb2e8f9f7 657 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
<> 144:ef7eb2e8f9f7 658 #endif /* STM32F446xx */
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660 /* Disable write protection */
<> 144:ef7eb2e8f9f7 661 tmpreg = FMC_Bank5_6->SDCR[0];
<> 144:ef7eb2e8f9f7 662 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
<> 144:ef7eb2e8f9f7 663 #endif /* DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 667 || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
<> 144:ef7eb2e8f9f7 668 || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 #if defined(DATA_IN_ExtSRAM)
<> 144:ef7eb2e8f9f7 671 /*-- GPIOs Configuration -----------------------------------------------------*/
<> 144:ef7eb2e8f9f7 672 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
<> 144:ef7eb2e8f9f7 673 RCC->AHB1ENR |= 0x00000078;
<> 144:ef7eb2e8f9f7 674 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 675 tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Connect PDx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 678 GPIOD->AFR[0] = 0x00CCC0CC;
<> 144:ef7eb2e8f9f7 679 GPIOD->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 680 /* Configure PDx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 681 GPIOD->MODER = 0xAAAA0A8A;
<> 144:ef7eb2e8f9f7 682 /* Configure PDx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 683 GPIOD->OSPEEDR = 0xFFFF0FCF;
<> 144:ef7eb2e8f9f7 684 /* Configure PDx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 685 GPIOD->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 686 /* No pull-up, pull-down for PDx pins */
<> 144:ef7eb2e8f9f7 687 GPIOD->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Connect PEx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 690 GPIOE->AFR[0] = 0xC00CC0CC;
<> 144:ef7eb2e8f9f7 691 GPIOE->AFR[1] = 0xCCCCCCCC;
<> 144:ef7eb2e8f9f7 692 /* Configure PEx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 693 GPIOE->MODER = 0xAAAA828A;
<> 144:ef7eb2e8f9f7 694 /* Configure PEx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 695 GPIOE->OSPEEDR = 0xFFFFC3CF;
<> 144:ef7eb2e8f9f7 696 /* Configure PEx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 697 GPIOE->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 698 /* No pull-up, pull-down for PEx pins */
<> 144:ef7eb2e8f9f7 699 GPIOE->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /* Connect PFx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 702 GPIOF->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 703 GPIOF->AFR[1] = 0xCCCC0000;
<> 144:ef7eb2e8f9f7 704 /* Configure PFx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 705 GPIOF->MODER = 0xAA000AAA;
<> 144:ef7eb2e8f9f7 706 /* Configure PFx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 707 GPIOF->OSPEEDR = 0xFF000FFF;
<> 144:ef7eb2e8f9f7 708 /* Configure PFx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 709 GPIOF->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 710 /* No pull-up, pull-down for PFx pins */
<> 144:ef7eb2e8f9f7 711 GPIOF->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /* Connect PGx pins to FMC Alternate function */
<> 144:ef7eb2e8f9f7 714 GPIOG->AFR[0] = 0x00CCCCCC;
<> 144:ef7eb2e8f9f7 715 GPIOG->AFR[1] = 0x000000C0;
<> 144:ef7eb2e8f9f7 716 /* Configure PGx pins in Alternate function mode */
<> 144:ef7eb2e8f9f7 717 GPIOG->MODER = 0x00085AAA;
<> 144:ef7eb2e8f9f7 718 /* Configure PGx pins speed to 100 MHz */
<> 144:ef7eb2e8f9f7 719 GPIOG->OSPEEDR = 0x000CAFFF;
<> 144:ef7eb2e8f9f7 720 /* Configure PGx pins Output type to push-pull */
<> 144:ef7eb2e8f9f7 721 GPIOG->OTYPER = 0x00000000;
<> 144:ef7eb2e8f9f7 722 /* No pull-up, pull-down for PGx pins */
<> 144:ef7eb2e8f9f7 723 GPIOG->PUPDR = 0x00000000;
<> 144:ef7eb2e8f9f7 724
<> 160:d5399cc887bb 725 /*-- FMC/FSMC Configuration --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 726 /* Enable the FMC/FSMC interface clock */
<> 144:ef7eb2e8f9f7 727 RCC->AHB3ENR |= 0x00000001;
<> 160:d5399cc887bb 728
<> 160:d5399cc887bb 729 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 160:d5399cc887bb 730 /* Delay after an RCC peripheral clock enabling */
<> 160:d5399cc887bb 731 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 732 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 733 FMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 734 FMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 735 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 736 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 737 #if defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 738 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 739 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
<> 144:ef7eb2e8f9f7 740 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 741 FMC_Bank1->BTCR[2] = 0x00001091;
<> 144:ef7eb2e8f9f7 742 FMC_Bank1->BTCR[3] = 0x00110212;
<> 144:ef7eb2e8f9f7 743 FMC_Bank1E->BWTR[2] = 0x0fffffff;
<> 144:ef7eb2e8f9f7 744 #endif /* STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 745 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
<> 144:ef7eb2e8f9f7 746 || defined(STM32F412Zx) || defined(STM32F412Vx)
<> 144:ef7eb2e8f9f7 747 /* Delay after an RCC peripheral clock enabling */
<> 144:ef7eb2e8f9f7 748 tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
<> 144:ef7eb2e8f9f7 749 /* Configure and enable Bank1_SRAM2 */
<> 144:ef7eb2e8f9f7 750 FSMC_Bank1->BTCR[2] = 0x00001011;
<> 144:ef7eb2e8f9f7 751 FSMC_Bank1->BTCR[3] = 0x00000201;
<> 144:ef7eb2e8f9f7 752 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
<> 144:ef7eb2e8f9f7 753 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #endif /* DATA_IN_ExtSRAM */
<> 144:ef7eb2e8f9f7 756 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 757 STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
<> 144:ef7eb2e8f9f7 758 (void)(tmp);
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /** System Clock Configuration
<> 144:ef7eb2e8f9f7 763 */
<> 144:ef7eb2e8f9f7 764 #if USE_SYSCLOCK_168 != 0
<> 144:ef7eb2e8f9f7 765 /*
<> 144:ef7eb2e8f9f7 766 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
<> 144:ef7eb2e8f9f7 767 * and SYSCLK=168MHZ
<> 144:ef7eb2e8f9f7 768 */
<> 144:ef7eb2e8f9f7 769 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 770 {
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 773 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 774
AnnaBridge 167:e84263d55307 775 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 780 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 781 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 782 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 783 RCC_OscInitStruct.PLL.PLLM = 8;
<> 144:ef7eb2e8f9f7 784 RCC_OscInitStruct.PLL.PLLN = 336;
<> 144:ef7eb2e8f9f7 785 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
<> 144:ef7eb2e8f9f7 786 RCC_OscInitStruct.PLL.PLLQ = 7;
<> 144:ef7eb2e8f9f7 787 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
<> 144:ef7eb2e8f9f7 790 |RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 791 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
<> 144:ef7eb2e8f9f7 792 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
<> 144:ef7eb2e8f9f7 793 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
<> 144:ef7eb2e8f9f7 794 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
<> 144:ef7eb2e8f9f7 795 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 #elif USE_SYSCLOCK_180 != 0
<> 144:ef7eb2e8f9f7 803 /*
<> 144:ef7eb2e8f9f7 804 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
<> 144:ef7eb2e8f9f7 805 * and SYSCLK=180MHZ
<> 144:ef7eb2e8f9f7 806 */
<> 144:ef7eb2e8f9f7 807 void SetSysClock(void)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 RCC_OscInitTypeDef RCC_OscInitStruct;
<> 144:ef7eb2e8f9f7 811 RCC_ClkInitTypeDef RCC_ClkInitStruct;
<> 144:ef7eb2e8f9f7 812
AnnaBridge 167:e84263d55307 813 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 816
<> 144:ef7eb2e8f9f7 817 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
<> 144:ef7eb2e8f9f7 818 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 819 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 820 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
<> 144:ef7eb2e8f9f7 821 RCC_OscInitStruct.PLL.PLLM = 8;
<> 144:ef7eb2e8f9f7 822 RCC_OscInitStruct.PLL.PLLN = 360;
<> 144:ef7eb2e8f9f7 823 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
<> 144:ef7eb2e8f9f7 824 RCC_OscInitStruct.PLL.PLLQ = 7;
<> 144:ef7eb2e8f9f7 825 HAL_RCC_OscConfig(&RCC_OscInitStruct);
<> 144:ef7eb2e8f9f7 826
AnnaBridge 167:e84263d55307 827 HAL_PWREx_EnableOverDrive();
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
<> 144:ef7eb2e8f9f7 830 |RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 831 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
<> 144:ef7eb2e8f9f7 832 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
<> 144:ef7eb2e8f9f7 833 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
<> 144:ef7eb2e8f9f7 834 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
<> 144:ef7eb2e8f9f7 835 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 #endif
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /**
<> 144:ef7eb2e8f9f7 843 * @}
<> 144:ef7eb2e8f9f7 844 */
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /**
<> 144:ef7eb2e8f9f7 847 * @}
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @}
<> 144:ef7eb2e8f9f7 852 */
<> 144:ef7eb2e8f9f7 853 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/