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cmsis/core_cm0plus.h@167:e84263d55307, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:46:44 2017 +0100
- Revision:
- 167:e84263d55307
- Parent:
- 152:9a67f0b066fc
This updates the lib to the mbed lib v 145
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file core_cm0plus.h |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
AnnaBridge | 167:e84263d55307 | 4 | * @version V5.0.2 |
AnnaBridge | 167:e84263d55307 | 5 | * @date 13. February 2017 |
AnnaBridge | 167:e84263d55307 | 6 | ******************************************************************************/ |
AnnaBridge | 167:e84263d55307 | 7 | /* |
AnnaBridge | 167:e84263d55307 | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
AnnaBridge | 167:e84263d55307 | 9 | * |
AnnaBridge | 167:e84263d55307 | 10 | * SPDX-License-Identifier: Apache-2.0 |
<> | 144:ef7eb2e8f9f7 | 11 | * |
AnnaBridge | 167:e84263d55307 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
AnnaBridge | 167:e84263d55307 | 13 | * not use this file except in compliance with the License. |
AnnaBridge | 167:e84263d55307 | 14 | * You may obtain a copy of the License at |
AnnaBridge | 167:e84263d55307 | 15 | * |
AnnaBridge | 167:e84263d55307 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 17 | * |
AnnaBridge | 167:e84263d55307 | 18 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 167:e84263d55307 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
AnnaBridge | 167:e84263d55307 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 167:e84263d55307 | 21 | * See the License for the specific language governing permissions and |
AnnaBridge | 167:e84263d55307 | 22 | * limitations under the License. |
AnnaBridge | 167:e84263d55307 | 23 | */ |
<> | 144:ef7eb2e8f9f7 | 24 | |
AnnaBridge | 167:e84263d55307 | 25 | #if defined ( __ICCARM__ ) |
AnnaBridge | 167:e84263d55307 | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
AnnaBridge | 167:e84263d55307 | 27 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
AnnaBridge | 167:e84263d55307 | 28 | #pragma clang system_header /* treat file as system include file */ |
<> | 144:ef7eb2e8f9f7 | 29 | #endif |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | #ifndef __CORE_CM0PLUS_H_GENERIC |
<> | 144:ef7eb2e8f9f7 | 32 | #define __CORE_CM0PLUS_H_GENERIC |
<> | 144:ef7eb2e8f9f7 | 33 | |
AnnaBridge | 167:e84263d55307 | 34 | #include <stdint.h> |
AnnaBridge | 167:e84263d55307 | 35 | |
<> | 144:ef7eb2e8f9f7 | 36 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 37 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 38 | #endif |
<> | 144:ef7eb2e8f9f7 | 39 | |
AnnaBridge | 167:e84263d55307 | 40 | /** |
AnnaBridge | 167:e84263d55307 | 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
<> | 144:ef7eb2e8f9f7 | 42 | CMSIS violates the following MISRA-C:2004 rules: |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
<> | 144:ef7eb2e8f9f7 | 45 | Function definitions in header files are used to allow 'inlining'. |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
<> | 144:ef7eb2e8f9f7 | 48 | Unions are used for effective representation of core registers. |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
<> | 144:ef7eb2e8f9f7 | 51 | Function-like macros are used to allow more efficient code. |
<> | 144:ef7eb2e8f9f7 | 52 | */ |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 56 | * CMSIS definitions |
<> | 144:ef7eb2e8f9f7 | 57 | ******************************************************************************/ |
AnnaBridge | 167:e84263d55307 | 58 | /** |
AnnaBridge | 167:e84263d55307 | 59 | \ingroup Cortex-M0+ |
<> | 144:ef7eb2e8f9f7 | 60 | @{ |
<> | 144:ef7eb2e8f9f7 | 61 | */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
AnnaBridge | 167:e84263d55307 | 63 | /* CMSIS CM0+ definitions */ |
AnnaBridge | 167:e84263d55307 | 64 | #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ |
AnnaBridge | 167:e84263d55307 | 65 | #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ |
AnnaBridge | 167:e84263d55307 | 66 | #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ |
AnnaBridge | 167:e84263d55307 | 67 | __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
<> | 144:ef7eb2e8f9f7 | 68 | |
AnnaBridge | 167:e84263d55307 | 69 | #define __CORTEX_M (0U) /*!< Cortex-M Core */ |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | /** __FPU_USED indicates whether an FPU is used or not. |
<> | 144:ef7eb2e8f9f7 | 72 | This core does not support an FPU at all |
<> | 144:ef7eb2e8f9f7 | 73 | */ |
AnnaBridge | 167:e84263d55307 | 74 | #define __FPU_USED 0U |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | #if defined ( __CC_ARM ) |
<> | 144:ef7eb2e8f9f7 | 77 | #if defined __TARGET_FPU_VFP |
AnnaBridge | 167:e84263d55307 | 78 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
AnnaBridge | 167:e84263d55307 | 79 | #endif |
AnnaBridge | 167:e84263d55307 | 80 | |
AnnaBridge | 167:e84263d55307 | 81 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
AnnaBridge | 167:e84263d55307 | 82 | #if defined __ARM_PCS_VFP |
AnnaBridge | 167:e84263d55307 | 83 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 84 | #endif |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | #elif defined ( __GNUC__ ) |
<> | 144:ef7eb2e8f9f7 | 87 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
AnnaBridge | 167:e84263d55307 | 88 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 89 | #endif |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | #elif defined ( __ICCARM__ ) |
<> | 144:ef7eb2e8f9f7 | 92 | #if defined __ARMVFP__ |
AnnaBridge | 167:e84263d55307 | 93 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 94 | #endif |
<> | 144:ef7eb2e8f9f7 | 95 | |
AnnaBridge | 167:e84263d55307 | 96 | #elif defined ( __TI_ARM__ ) |
AnnaBridge | 167:e84263d55307 | 97 | #if defined __TI_VFP_SUPPORT__ |
AnnaBridge | 167:e84263d55307 | 98 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 99 | #endif |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | #elif defined ( __TASKING__ ) |
<> | 144:ef7eb2e8f9f7 | 102 | #if defined __FPU_VFP__ |
<> | 144:ef7eb2e8f9f7 | 103 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 104 | #endif |
<> | 144:ef7eb2e8f9f7 | 105 | |
AnnaBridge | 167:e84263d55307 | 106 | #elif defined ( __CSMC__ ) |
AnnaBridge | 167:e84263d55307 | 107 | #if ( __CSMC__ & 0x400U) |
<> | 144:ef7eb2e8f9f7 | 108 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 144:ef7eb2e8f9f7 | 109 | #endif |
AnnaBridge | 167:e84263d55307 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | #endif |
<> | 144:ef7eb2e8f9f7 | 112 | |
AnnaBridge | 167:e84263d55307 | 113 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
AnnaBridge | 167:e84263d55307 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 117 | } |
<> | 144:ef7eb2e8f9f7 | 118 | #endif |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | #endif /* __CORE_CM0PLUS_H_GENERIC */ |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | #ifndef __CMSIS_GENERIC |
<> | 144:ef7eb2e8f9f7 | 123 | |
<> | 144:ef7eb2e8f9f7 | 124 | #ifndef __CORE_CM0PLUS_H_DEPENDANT |
<> | 144:ef7eb2e8f9f7 | 125 | #define __CORE_CM0PLUS_H_DEPENDANT |
<> | 144:ef7eb2e8f9f7 | 126 | |
<> | 144:ef7eb2e8f9f7 | 127 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 128 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 129 | #endif |
<> | 144:ef7eb2e8f9f7 | 130 | |
<> | 144:ef7eb2e8f9f7 | 131 | /* check device defines and use defaults */ |
<> | 144:ef7eb2e8f9f7 | 132 | #if defined __CHECK_DEVICE_DEFINES |
<> | 144:ef7eb2e8f9f7 | 133 | #ifndef __CM0PLUS_REV |
AnnaBridge | 167:e84263d55307 | 134 | #define __CM0PLUS_REV 0x0000U |
<> | 144:ef7eb2e8f9f7 | 135 | #warning "__CM0PLUS_REV not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 136 | #endif |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | #ifndef __MPU_PRESENT |
AnnaBridge | 167:e84263d55307 | 139 | #define __MPU_PRESENT 0U |
<> | 144:ef7eb2e8f9f7 | 140 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 141 | #endif |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | #ifndef __VTOR_PRESENT |
AnnaBridge | 167:e84263d55307 | 144 | #define __VTOR_PRESENT 0U |
<> | 144:ef7eb2e8f9f7 | 145 | #warning "__VTOR_PRESENT not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 146 | #endif |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | #ifndef __NVIC_PRIO_BITS |
AnnaBridge | 167:e84263d55307 | 149 | #define __NVIC_PRIO_BITS 2U |
<> | 144:ef7eb2e8f9f7 | 150 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 151 | #endif |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | #ifndef __Vendor_SysTickConfig |
AnnaBridge | 167:e84263d55307 | 154 | #define __Vendor_SysTickConfig 0U |
<> | 144:ef7eb2e8f9f7 | 155 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
<> | 144:ef7eb2e8f9f7 | 156 | #endif |
<> | 144:ef7eb2e8f9f7 | 157 | #endif |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | /* IO definitions (access restrictions to peripheral registers) */ |
<> | 144:ef7eb2e8f9f7 | 160 | /** |
<> | 144:ef7eb2e8f9f7 | 161 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
<> | 144:ef7eb2e8f9f7 | 162 | |
<> | 144:ef7eb2e8f9f7 | 163 | <strong>IO Type Qualifiers</strong> are used |
<> | 144:ef7eb2e8f9f7 | 164 | \li to specify the access to peripheral variables. |
<> | 144:ef7eb2e8f9f7 | 165 | \li for automatic generation of peripheral register debug information. |
<> | 144:ef7eb2e8f9f7 | 166 | */ |
<> | 144:ef7eb2e8f9f7 | 167 | #ifdef __cplusplus |
AnnaBridge | 167:e84263d55307 | 168 | #define __I volatile /*!< Defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 169 | #else |
AnnaBridge | 167:e84263d55307 | 170 | #define __I volatile const /*!< Defines 'read only' permissions */ |
<> | 144:ef7eb2e8f9f7 | 171 | #endif |
AnnaBridge | 167:e84263d55307 | 172 | #define __O volatile /*!< Defines 'write only' permissions */ |
AnnaBridge | 167:e84263d55307 | 173 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
<> | 144:ef7eb2e8f9f7 | 174 | |
AnnaBridge | 167:e84263d55307 | 175 | /* following defines should be used for structure members */ |
AnnaBridge | 167:e84263d55307 | 176 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
AnnaBridge | 167:e84263d55307 | 177 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
AnnaBridge | 167:e84263d55307 | 178 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
<> | 150:02e0a0aed4ec | 179 | |
<> | 144:ef7eb2e8f9f7 | 180 | /*@} end of group Cortex-M0+ */ |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 185 | * Register Abstraction |
<> | 144:ef7eb2e8f9f7 | 186 | Core Register contain: |
<> | 144:ef7eb2e8f9f7 | 187 | - Core Register |
<> | 144:ef7eb2e8f9f7 | 188 | - Core NVIC Register |
<> | 144:ef7eb2e8f9f7 | 189 | - Core SCB Register |
<> | 144:ef7eb2e8f9f7 | 190 | - Core SysTick Register |
<> | 144:ef7eb2e8f9f7 | 191 | - Core MPU Register |
<> | 144:ef7eb2e8f9f7 | 192 | ******************************************************************************/ |
AnnaBridge | 167:e84263d55307 | 193 | /** |
AnnaBridge | 167:e84263d55307 | 194 | \defgroup CMSIS_core_register Defines and Type Definitions |
AnnaBridge | 167:e84263d55307 | 195 | \brief Type definitions and defines for Cortex-M processor based devices. |
<> | 144:ef7eb2e8f9f7 | 196 | */ |
<> | 144:ef7eb2e8f9f7 | 197 | |
AnnaBridge | 167:e84263d55307 | 198 | /** |
AnnaBridge | 167:e84263d55307 | 199 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 200 | \defgroup CMSIS_CORE Status and Control Registers |
AnnaBridge | 167:e84263d55307 | 201 | \brief Core Register type definitions. |
<> | 144:ef7eb2e8f9f7 | 202 | @{ |
<> | 144:ef7eb2e8f9f7 | 203 | */ |
<> | 144:ef7eb2e8f9f7 | 204 | |
AnnaBridge | 167:e84263d55307 | 205 | /** |
AnnaBridge | 167:e84263d55307 | 206 | \brief Union type to access the Application Program Status Register (APSR). |
<> | 144:ef7eb2e8f9f7 | 207 | */ |
<> | 144:ef7eb2e8f9f7 | 208 | typedef union |
<> | 144:ef7eb2e8f9f7 | 209 | { |
<> | 144:ef7eb2e8f9f7 | 210 | struct |
<> | 144:ef7eb2e8f9f7 | 211 | { |
AnnaBridge | 167:e84263d55307 | 212 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
AnnaBridge | 167:e84263d55307 | 213 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
AnnaBridge | 167:e84263d55307 | 214 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
AnnaBridge | 167:e84263d55307 | 215 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
AnnaBridge | 167:e84263d55307 | 216 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
AnnaBridge | 167:e84263d55307 | 217 | } b; /*!< Structure used for bit access */ |
AnnaBridge | 167:e84263d55307 | 218 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 219 | } APSR_Type; |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | /* APSR Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 222 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
<> | 144:ef7eb2e8f9f7 | 223 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
<> | 144:ef7eb2e8f9f7 | 224 | |
AnnaBridge | 167:e84263d55307 | 225 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
<> | 144:ef7eb2e8f9f7 | 226 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
<> | 144:ef7eb2e8f9f7 | 227 | |
AnnaBridge | 167:e84263d55307 | 228 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
<> | 144:ef7eb2e8f9f7 | 229 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
<> | 144:ef7eb2e8f9f7 | 230 | |
AnnaBridge | 167:e84263d55307 | 231 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
<> | 144:ef7eb2e8f9f7 | 232 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
<> | 144:ef7eb2e8f9f7 | 233 | |
<> | 144:ef7eb2e8f9f7 | 234 | |
AnnaBridge | 167:e84263d55307 | 235 | /** |
AnnaBridge | 167:e84263d55307 | 236 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
<> | 144:ef7eb2e8f9f7 | 237 | */ |
<> | 144:ef7eb2e8f9f7 | 238 | typedef union |
<> | 144:ef7eb2e8f9f7 | 239 | { |
<> | 144:ef7eb2e8f9f7 | 240 | struct |
<> | 144:ef7eb2e8f9f7 | 241 | { |
AnnaBridge | 167:e84263d55307 | 242 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
AnnaBridge | 167:e84263d55307 | 243 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
AnnaBridge | 167:e84263d55307 | 244 | } b; /*!< Structure used for bit access */ |
AnnaBridge | 167:e84263d55307 | 245 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 246 | } IPSR_Type; |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | /* IPSR Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 249 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
<> | 144:ef7eb2e8f9f7 | 250 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | |
AnnaBridge | 167:e84263d55307 | 253 | /** |
AnnaBridge | 167:e84263d55307 | 254 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
<> | 144:ef7eb2e8f9f7 | 255 | */ |
<> | 144:ef7eb2e8f9f7 | 256 | typedef union |
<> | 144:ef7eb2e8f9f7 | 257 | { |
<> | 144:ef7eb2e8f9f7 | 258 | struct |
<> | 144:ef7eb2e8f9f7 | 259 | { |
AnnaBridge | 167:e84263d55307 | 260 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
AnnaBridge | 167:e84263d55307 | 261 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
AnnaBridge | 167:e84263d55307 | 262 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
AnnaBridge | 167:e84263d55307 | 263 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
AnnaBridge | 167:e84263d55307 | 264 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
AnnaBridge | 167:e84263d55307 | 265 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
AnnaBridge | 167:e84263d55307 | 266 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
AnnaBridge | 167:e84263d55307 | 267 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
AnnaBridge | 167:e84263d55307 | 268 | } b; /*!< Structure used for bit access */ |
AnnaBridge | 167:e84263d55307 | 269 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 270 | } xPSR_Type; |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | /* xPSR Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 273 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
<> | 144:ef7eb2e8f9f7 | 274 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
<> | 144:ef7eb2e8f9f7 | 275 | |
AnnaBridge | 167:e84263d55307 | 276 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
<> | 144:ef7eb2e8f9f7 | 277 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
<> | 144:ef7eb2e8f9f7 | 278 | |
AnnaBridge | 167:e84263d55307 | 279 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
<> | 144:ef7eb2e8f9f7 | 280 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
<> | 144:ef7eb2e8f9f7 | 281 | |
AnnaBridge | 167:e84263d55307 | 282 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
<> | 144:ef7eb2e8f9f7 | 283 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
<> | 144:ef7eb2e8f9f7 | 284 | |
AnnaBridge | 167:e84263d55307 | 285 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
<> | 144:ef7eb2e8f9f7 | 286 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
<> | 144:ef7eb2e8f9f7 | 287 | |
AnnaBridge | 167:e84263d55307 | 288 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
<> | 144:ef7eb2e8f9f7 | 289 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | |
AnnaBridge | 167:e84263d55307 | 292 | /** |
AnnaBridge | 167:e84263d55307 | 293 | \brief Union type to access the Control Registers (CONTROL). |
<> | 144:ef7eb2e8f9f7 | 294 | */ |
<> | 144:ef7eb2e8f9f7 | 295 | typedef union |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | struct |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
AnnaBridge | 167:e84263d55307 | 300 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
AnnaBridge | 167:e84263d55307 | 301 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
AnnaBridge | 167:e84263d55307 | 302 | } b; /*!< Structure used for bit access */ |
AnnaBridge | 167:e84263d55307 | 303 | uint32_t w; /*!< Type used for word access */ |
<> | 144:ef7eb2e8f9f7 | 304 | } CONTROL_Type; |
<> | 144:ef7eb2e8f9f7 | 305 | |
<> | 144:ef7eb2e8f9f7 | 306 | /* CONTROL Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 307 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
<> | 144:ef7eb2e8f9f7 | 308 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
<> | 144:ef7eb2e8f9f7 | 309 | |
AnnaBridge | 167:e84263d55307 | 310 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
<> | 144:ef7eb2e8f9f7 | 311 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | /*@} end of group CMSIS_CORE */ |
<> | 144:ef7eb2e8f9f7 | 314 | |
<> | 144:ef7eb2e8f9f7 | 315 | |
AnnaBridge | 167:e84263d55307 | 316 | /** |
AnnaBridge | 167:e84263d55307 | 317 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 318 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
AnnaBridge | 167:e84263d55307 | 319 | \brief Type definitions for the NVIC Registers |
<> | 144:ef7eb2e8f9f7 | 320 | @{ |
<> | 144:ef7eb2e8f9f7 | 321 | */ |
<> | 144:ef7eb2e8f9f7 | 322 | |
AnnaBridge | 167:e84263d55307 | 323 | /** |
AnnaBridge | 167:e84263d55307 | 324 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
<> | 144:ef7eb2e8f9f7 | 325 | */ |
<> | 144:ef7eb2e8f9f7 | 326 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 327 | { |
AnnaBridge | 167:e84263d55307 | 328 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
AnnaBridge | 167:e84263d55307 | 329 | uint32_t RESERVED0[31U]; |
AnnaBridge | 167:e84263d55307 | 330 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
AnnaBridge | 167:e84263d55307 | 331 | uint32_t RSERVED1[31U]; |
AnnaBridge | 167:e84263d55307 | 332 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
AnnaBridge | 167:e84263d55307 | 333 | uint32_t RESERVED2[31U]; |
AnnaBridge | 167:e84263d55307 | 334 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
AnnaBridge | 167:e84263d55307 | 335 | uint32_t RESERVED3[31U]; |
AnnaBridge | 167:e84263d55307 | 336 | uint32_t RESERVED4[64U]; |
AnnaBridge | 167:e84263d55307 | 337 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
<> | 144:ef7eb2e8f9f7 | 338 | } NVIC_Type; |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /*@} end of group CMSIS_NVIC */ |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | |
AnnaBridge | 167:e84263d55307 | 343 | /** |
AnnaBridge | 167:e84263d55307 | 344 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 345 | \defgroup CMSIS_SCB System Control Block (SCB) |
AnnaBridge | 167:e84263d55307 | 346 | \brief Type definitions for the System Control Block Registers |
<> | 144:ef7eb2e8f9f7 | 347 | @{ |
<> | 144:ef7eb2e8f9f7 | 348 | */ |
<> | 144:ef7eb2e8f9f7 | 349 | |
AnnaBridge | 167:e84263d55307 | 350 | /** |
AnnaBridge | 167:e84263d55307 | 351 | \brief Structure type to access the System Control Block (SCB). |
<> | 144:ef7eb2e8f9f7 | 352 | */ |
<> | 144:ef7eb2e8f9f7 | 353 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 354 | { |
AnnaBridge | 167:e84263d55307 | 355 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
AnnaBridge | 167:e84263d55307 | 356 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
AnnaBridge | 167:e84263d55307 | 357 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
AnnaBridge | 167:e84263d55307 | 358 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
<> | 144:ef7eb2e8f9f7 | 359 | #else |
AnnaBridge | 167:e84263d55307 | 360 | uint32_t RESERVED0; |
<> | 144:ef7eb2e8f9f7 | 361 | #endif |
AnnaBridge | 167:e84263d55307 | 362 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
AnnaBridge | 167:e84263d55307 | 363 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
AnnaBridge | 167:e84263d55307 | 364 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
AnnaBridge | 167:e84263d55307 | 365 | uint32_t RESERVED1; |
AnnaBridge | 167:e84263d55307 | 366 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
AnnaBridge | 167:e84263d55307 | 367 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
<> | 144:ef7eb2e8f9f7 | 368 | } SCB_Type; |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | /* SCB CPUID Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 371 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
<> | 144:ef7eb2e8f9f7 | 372 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
<> | 144:ef7eb2e8f9f7 | 373 | |
AnnaBridge | 167:e84263d55307 | 374 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
<> | 144:ef7eb2e8f9f7 | 375 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
<> | 144:ef7eb2e8f9f7 | 376 | |
AnnaBridge | 167:e84263d55307 | 377 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
<> | 144:ef7eb2e8f9f7 | 378 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
<> | 144:ef7eb2e8f9f7 | 379 | |
AnnaBridge | 167:e84263d55307 | 380 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
<> | 144:ef7eb2e8f9f7 | 381 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
<> | 144:ef7eb2e8f9f7 | 382 | |
AnnaBridge | 167:e84263d55307 | 383 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
<> | 144:ef7eb2e8f9f7 | 384 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
<> | 144:ef7eb2e8f9f7 | 385 | |
<> | 144:ef7eb2e8f9f7 | 386 | /* SCB Interrupt Control State Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 387 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
<> | 144:ef7eb2e8f9f7 | 388 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 389 | |
AnnaBridge | 167:e84263d55307 | 390 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
<> | 144:ef7eb2e8f9f7 | 391 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 392 | |
AnnaBridge | 167:e84263d55307 | 393 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
<> | 144:ef7eb2e8f9f7 | 394 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
<> | 144:ef7eb2e8f9f7 | 395 | |
AnnaBridge | 167:e84263d55307 | 396 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
<> | 144:ef7eb2e8f9f7 | 397 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
<> | 144:ef7eb2e8f9f7 | 398 | |
AnnaBridge | 167:e84263d55307 | 399 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
<> | 144:ef7eb2e8f9f7 | 400 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
<> | 144:ef7eb2e8f9f7 | 401 | |
AnnaBridge | 167:e84263d55307 | 402 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
<> | 144:ef7eb2e8f9f7 | 403 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
<> | 144:ef7eb2e8f9f7 | 404 | |
AnnaBridge | 167:e84263d55307 | 405 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
<> | 144:ef7eb2e8f9f7 | 406 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
<> | 144:ef7eb2e8f9f7 | 407 | |
AnnaBridge | 167:e84263d55307 | 408 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
<> | 144:ef7eb2e8f9f7 | 409 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
<> | 144:ef7eb2e8f9f7 | 410 | |
AnnaBridge | 167:e84263d55307 | 411 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
<> | 144:ef7eb2e8f9f7 | 412 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
<> | 144:ef7eb2e8f9f7 | 413 | |
AnnaBridge | 167:e84263d55307 | 414 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
<> | 144:ef7eb2e8f9f7 | 415 | /* SCB Interrupt Control State Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 416 | #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ |
<> | 144:ef7eb2e8f9f7 | 417 | #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
<> | 144:ef7eb2e8f9f7 | 418 | #endif |
<> | 144:ef7eb2e8f9f7 | 419 | |
<> | 144:ef7eb2e8f9f7 | 420 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 421 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
<> | 144:ef7eb2e8f9f7 | 422 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
<> | 144:ef7eb2e8f9f7 | 423 | |
AnnaBridge | 167:e84263d55307 | 424 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
<> | 144:ef7eb2e8f9f7 | 425 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
<> | 144:ef7eb2e8f9f7 | 426 | |
AnnaBridge | 167:e84263d55307 | 427 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
<> | 144:ef7eb2e8f9f7 | 428 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
<> | 144:ef7eb2e8f9f7 | 429 | |
AnnaBridge | 167:e84263d55307 | 430 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
<> | 144:ef7eb2e8f9f7 | 431 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
<> | 144:ef7eb2e8f9f7 | 432 | |
AnnaBridge | 167:e84263d55307 | 433 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
<> | 144:ef7eb2e8f9f7 | 434 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
<> | 144:ef7eb2e8f9f7 | 435 | |
<> | 144:ef7eb2e8f9f7 | 436 | /* SCB System Control Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 437 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
<> | 144:ef7eb2e8f9f7 | 438 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
<> | 144:ef7eb2e8f9f7 | 439 | |
AnnaBridge | 167:e84263d55307 | 440 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
<> | 144:ef7eb2e8f9f7 | 441 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
<> | 144:ef7eb2e8f9f7 | 442 | |
AnnaBridge | 167:e84263d55307 | 443 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
<> | 144:ef7eb2e8f9f7 | 444 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
<> | 144:ef7eb2e8f9f7 | 445 | |
<> | 144:ef7eb2e8f9f7 | 446 | /* SCB Configuration Control Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 447 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
<> | 144:ef7eb2e8f9f7 | 448 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
<> | 144:ef7eb2e8f9f7 | 449 | |
AnnaBridge | 167:e84263d55307 | 450 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
<> | 144:ef7eb2e8f9f7 | 451 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
<> | 144:ef7eb2e8f9f7 | 452 | |
<> | 144:ef7eb2e8f9f7 | 453 | /* SCB System Handler Control and State Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 454 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
<> | 144:ef7eb2e8f9f7 | 455 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
<> | 144:ef7eb2e8f9f7 | 456 | |
<> | 144:ef7eb2e8f9f7 | 457 | /*@} end of group CMSIS_SCB */ |
<> | 144:ef7eb2e8f9f7 | 458 | |
<> | 144:ef7eb2e8f9f7 | 459 | |
AnnaBridge | 167:e84263d55307 | 460 | /** |
AnnaBridge | 167:e84263d55307 | 461 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 462 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
AnnaBridge | 167:e84263d55307 | 463 | \brief Type definitions for the System Timer Registers. |
<> | 144:ef7eb2e8f9f7 | 464 | @{ |
<> | 144:ef7eb2e8f9f7 | 465 | */ |
<> | 144:ef7eb2e8f9f7 | 466 | |
AnnaBridge | 167:e84263d55307 | 467 | /** |
AnnaBridge | 167:e84263d55307 | 468 | \brief Structure type to access the System Timer (SysTick). |
<> | 144:ef7eb2e8f9f7 | 469 | */ |
<> | 144:ef7eb2e8f9f7 | 470 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 471 | { |
AnnaBridge | 167:e84263d55307 | 472 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
AnnaBridge | 167:e84263d55307 | 473 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
AnnaBridge | 167:e84263d55307 | 474 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
AnnaBridge | 167:e84263d55307 | 475 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
<> | 144:ef7eb2e8f9f7 | 476 | } SysTick_Type; |
<> | 144:ef7eb2e8f9f7 | 477 | |
<> | 144:ef7eb2e8f9f7 | 478 | /* SysTick Control / Status Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 479 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
<> | 144:ef7eb2e8f9f7 | 480 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
<> | 144:ef7eb2e8f9f7 | 481 | |
AnnaBridge | 167:e84263d55307 | 482 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
<> | 144:ef7eb2e8f9f7 | 483 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
<> | 144:ef7eb2e8f9f7 | 484 | |
AnnaBridge | 167:e84263d55307 | 485 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
<> | 144:ef7eb2e8f9f7 | 486 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
<> | 144:ef7eb2e8f9f7 | 487 | |
AnnaBridge | 167:e84263d55307 | 488 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
<> | 144:ef7eb2e8f9f7 | 489 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | /* SysTick Reload Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 492 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
<> | 144:ef7eb2e8f9f7 | 493 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
<> | 144:ef7eb2e8f9f7 | 494 | |
<> | 144:ef7eb2e8f9f7 | 495 | /* SysTick Current Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 496 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
<> | 144:ef7eb2e8f9f7 | 497 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
<> | 144:ef7eb2e8f9f7 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | /* SysTick Calibration Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 500 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
<> | 144:ef7eb2e8f9f7 | 501 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
<> | 144:ef7eb2e8f9f7 | 502 | |
AnnaBridge | 167:e84263d55307 | 503 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
<> | 144:ef7eb2e8f9f7 | 504 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
<> | 144:ef7eb2e8f9f7 | 505 | |
AnnaBridge | 167:e84263d55307 | 506 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
<> | 144:ef7eb2e8f9f7 | 507 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
<> | 144:ef7eb2e8f9f7 | 508 | |
<> | 144:ef7eb2e8f9f7 | 509 | /*@} end of group CMSIS_SysTick */ |
<> | 144:ef7eb2e8f9f7 | 510 | |
AnnaBridge | 167:e84263d55307 | 511 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
AnnaBridge | 167:e84263d55307 | 512 | /** |
AnnaBridge | 167:e84263d55307 | 513 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 514 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
AnnaBridge | 167:e84263d55307 | 515 | \brief Type definitions for the Memory Protection Unit (MPU) |
<> | 144:ef7eb2e8f9f7 | 516 | @{ |
<> | 144:ef7eb2e8f9f7 | 517 | */ |
<> | 144:ef7eb2e8f9f7 | 518 | |
AnnaBridge | 167:e84263d55307 | 519 | /** |
AnnaBridge | 167:e84263d55307 | 520 | \brief Structure type to access the Memory Protection Unit (MPU). |
<> | 144:ef7eb2e8f9f7 | 521 | */ |
<> | 144:ef7eb2e8f9f7 | 522 | typedef struct |
<> | 144:ef7eb2e8f9f7 | 523 | { |
AnnaBridge | 167:e84263d55307 | 524 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
AnnaBridge | 167:e84263d55307 | 525 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
AnnaBridge | 167:e84263d55307 | 526 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
AnnaBridge | 167:e84263d55307 | 527 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
AnnaBridge | 167:e84263d55307 | 528 | __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
<> | 144:ef7eb2e8f9f7 | 529 | } MPU_Type; |
<> | 144:ef7eb2e8f9f7 | 530 | |
AnnaBridge | 167:e84263d55307 | 531 | /* MPU Type Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 532 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
<> | 144:ef7eb2e8f9f7 | 533 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 534 | |
AnnaBridge | 167:e84263d55307 | 535 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
<> | 144:ef7eb2e8f9f7 | 536 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 537 | |
AnnaBridge | 167:e84263d55307 | 538 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
<> | 144:ef7eb2e8f9f7 | 539 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
<> | 144:ef7eb2e8f9f7 | 540 | |
AnnaBridge | 167:e84263d55307 | 541 | /* MPU Control Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 542 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
<> | 144:ef7eb2e8f9f7 | 543 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 544 | |
AnnaBridge | 167:e84263d55307 | 545 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
<> | 144:ef7eb2e8f9f7 | 546 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
<> | 144:ef7eb2e8f9f7 | 547 | |
AnnaBridge | 167:e84263d55307 | 548 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
<> | 144:ef7eb2e8f9f7 | 549 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
<> | 144:ef7eb2e8f9f7 | 550 | |
AnnaBridge | 167:e84263d55307 | 551 | /* MPU Region Number Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 552 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
<> | 144:ef7eb2e8f9f7 | 553 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 554 | |
AnnaBridge | 167:e84263d55307 | 555 | /* MPU Region Base Address Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 556 | #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ |
<> | 144:ef7eb2e8f9f7 | 557 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
<> | 144:ef7eb2e8f9f7 | 558 | |
AnnaBridge | 167:e84263d55307 | 559 | #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ |
<> | 144:ef7eb2e8f9f7 | 560 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
<> | 144:ef7eb2e8f9f7 | 561 | |
AnnaBridge | 167:e84263d55307 | 562 | #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ |
<> | 144:ef7eb2e8f9f7 | 563 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
<> | 144:ef7eb2e8f9f7 | 564 | |
AnnaBridge | 167:e84263d55307 | 565 | /* MPU Region Attribute and Size Register Definitions */ |
AnnaBridge | 167:e84263d55307 | 566 | #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ |
<> | 144:ef7eb2e8f9f7 | 567 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
<> | 144:ef7eb2e8f9f7 | 568 | |
AnnaBridge | 167:e84263d55307 | 569 | #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ |
<> | 144:ef7eb2e8f9f7 | 570 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
<> | 144:ef7eb2e8f9f7 | 571 | |
AnnaBridge | 167:e84263d55307 | 572 | #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ |
<> | 144:ef7eb2e8f9f7 | 573 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
<> | 144:ef7eb2e8f9f7 | 574 | |
AnnaBridge | 167:e84263d55307 | 575 | #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ |
<> | 144:ef7eb2e8f9f7 | 576 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
<> | 144:ef7eb2e8f9f7 | 577 | |
AnnaBridge | 167:e84263d55307 | 578 | #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ |
<> | 144:ef7eb2e8f9f7 | 579 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
<> | 144:ef7eb2e8f9f7 | 580 | |
AnnaBridge | 167:e84263d55307 | 581 | #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ |
<> | 144:ef7eb2e8f9f7 | 582 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
<> | 144:ef7eb2e8f9f7 | 583 | |
AnnaBridge | 167:e84263d55307 | 584 | #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ |
<> | 144:ef7eb2e8f9f7 | 585 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
<> | 144:ef7eb2e8f9f7 | 586 | |
AnnaBridge | 167:e84263d55307 | 587 | #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ |
<> | 144:ef7eb2e8f9f7 | 588 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
<> | 144:ef7eb2e8f9f7 | 589 | |
AnnaBridge | 167:e84263d55307 | 590 | #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ |
<> | 144:ef7eb2e8f9f7 | 591 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
<> | 144:ef7eb2e8f9f7 | 592 | |
AnnaBridge | 167:e84263d55307 | 593 | #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ |
<> | 144:ef7eb2e8f9f7 | 594 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
<> | 144:ef7eb2e8f9f7 | 595 | |
<> | 144:ef7eb2e8f9f7 | 596 | /*@} end of group CMSIS_MPU */ |
<> | 144:ef7eb2e8f9f7 | 597 | #endif |
<> | 144:ef7eb2e8f9f7 | 598 | |
<> | 144:ef7eb2e8f9f7 | 599 | |
AnnaBridge | 167:e84263d55307 | 600 | /** |
AnnaBridge | 167:e84263d55307 | 601 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 602 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
AnnaBridge | 167:e84263d55307 | 603 | \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
AnnaBridge | 167:e84263d55307 | 604 | Therefore they are not covered by the Cortex-M0+ header file. |
<> | 144:ef7eb2e8f9f7 | 605 | @{ |
<> | 144:ef7eb2e8f9f7 | 606 | */ |
<> | 144:ef7eb2e8f9f7 | 607 | /*@} end of group CMSIS_CoreDebug */ |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | |
AnnaBridge | 167:e84263d55307 | 610 | /** |
AnnaBridge | 167:e84263d55307 | 611 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 612 | \defgroup CMSIS_core_bitfield Core register bit field macros |
AnnaBridge | 167:e84263d55307 | 613 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
<> | 144:ef7eb2e8f9f7 | 614 | @{ |
<> | 144:ef7eb2e8f9f7 | 615 | */ |
<> | 144:ef7eb2e8f9f7 | 616 | |
AnnaBridge | 167:e84263d55307 | 617 | /** |
AnnaBridge | 167:e84263d55307 | 618 | \brief Mask and shift a bit field value for use in a register bit range. |
AnnaBridge | 167:e84263d55307 | 619 | \param[in] field Name of the register bit field. |
AnnaBridge | 167:e84263d55307 | 620 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
AnnaBridge | 167:e84263d55307 | 621 | \return Masked and shifted value. |
AnnaBridge | 167:e84263d55307 | 622 | */ |
AnnaBridge | 167:e84263d55307 | 623 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
AnnaBridge | 167:e84263d55307 | 624 | |
AnnaBridge | 167:e84263d55307 | 625 | /** |
AnnaBridge | 167:e84263d55307 | 626 | \brief Mask and shift a register value to extract a bit filed value. |
AnnaBridge | 167:e84263d55307 | 627 | \param[in] field Name of the register bit field. |
AnnaBridge | 167:e84263d55307 | 628 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
AnnaBridge | 167:e84263d55307 | 629 | \return Masked and shifted bit field value. |
AnnaBridge | 167:e84263d55307 | 630 | */ |
AnnaBridge | 167:e84263d55307 | 631 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
AnnaBridge | 167:e84263d55307 | 632 | |
AnnaBridge | 167:e84263d55307 | 633 | /*@} end of group CMSIS_core_bitfield */ |
AnnaBridge | 167:e84263d55307 | 634 | |
AnnaBridge | 167:e84263d55307 | 635 | |
AnnaBridge | 167:e84263d55307 | 636 | /** |
AnnaBridge | 167:e84263d55307 | 637 | \ingroup CMSIS_core_register |
AnnaBridge | 167:e84263d55307 | 638 | \defgroup CMSIS_core_base Core Definitions |
AnnaBridge | 167:e84263d55307 | 639 | \brief Definitions for base addresses, unions, and structures. |
AnnaBridge | 167:e84263d55307 | 640 | @{ |
AnnaBridge | 167:e84263d55307 | 641 | */ |
AnnaBridge | 167:e84263d55307 | 642 | |
AnnaBridge | 167:e84263d55307 | 643 | /* Memory mapping of Core Hardware */ |
<> | 144:ef7eb2e8f9f7 | 644 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
AnnaBridge | 167:e84263d55307 | 645 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
AnnaBridge | 167:e84263d55307 | 646 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
<> | 144:ef7eb2e8f9f7 | 647 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
<> | 144:ef7eb2e8f9f7 | 648 | |
AnnaBridge | 167:e84263d55307 | 649 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
AnnaBridge | 167:e84263d55307 | 650 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
AnnaBridge | 167:e84263d55307 | 651 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
<> | 144:ef7eb2e8f9f7 | 652 | |
AnnaBridge | 167:e84263d55307 | 653 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
AnnaBridge | 167:e84263d55307 | 654 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
AnnaBridge | 167:e84263d55307 | 655 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
<> | 144:ef7eb2e8f9f7 | 656 | #endif |
<> | 144:ef7eb2e8f9f7 | 657 | |
<> | 144:ef7eb2e8f9f7 | 658 | /*@} */ |
<> | 144:ef7eb2e8f9f7 | 659 | |
<> | 144:ef7eb2e8f9f7 | 660 | |
<> | 144:ef7eb2e8f9f7 | 661 | |
<> | 144:ef7eb2e8f9f7 | 662 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 663 | * Hardware Abstraction Layer |
<> | 144:ef7eb2e8f9f7 | 664 | Core Function Interface contains: |
<> | 144:ef7eb2e8f9f7 | 665 | - Core NVIC Functions |
<> | 144:ef7eb2e8f9f7 | 666 | - Core SysTick Functions |
<> | 144:ef7eb2e8f9f7 | 667 | - Core Register Access Functions |
<> | 144:ef7eb2e8f9f7 | 668 | ******************************************************************************/ |
AnnaBridge | 167:e84263d55307 | 669 | /** |
AnnaBridge | 167:e84263d55307 | 670 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
<> | 144:ef7eb2e8f9f7 | 671 | */ |
<> | 144:ef7eb2e8f9f7 | 672 | |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | |
<> | 144:ef7eb2e8f9f7 | 675 | /* ########################## NVIC functions #################################### */ |
AnnaBridge | 167:e84263d55307 | 676 | /** |
AnnaBridge | 167:e84263d55307 | 677 | \ingroup CMSIS_Core_FunctionInterface |
AnnaBridge | 167:e84263d55307 | 678 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
AnnaBridge | 167:e84263d55307 | 679 | \brief Functions that manage interrupts and exceptions via the NVIC. |
AnnaBridge | 167:e84263d55307 | 680 | @{ |
<> | 144:ef7eb2e8f9f7 | 681 | */ |
<> | 144:ef7eb2e8f9f7 | 682 | |
AnnaBridge | 167:e84263d55307 | 683 | #ifdef CMSIS_NVIC_VIRTUAL |
AnnaBridge | 167:e84263d55307 | 684 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
AnnaBridge | 167:e84263d55307 | 685 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
AnnaBridge | 167:e84263d55307 | 686 | #endif |
AnnaBridge | 167:e84263d55307 | 687 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
AnnaBridge | 167:e84263d55307 | 688 | #else |
AnnaBridge | 167:e84263d55307 | 689 | /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ |
AnnaBridge | 167:e84263d55307 | 690 | /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ |
AnnaBridge | 167:e84263d55307 | 691 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
AnnaBridge | 167:e84263d55307 | 692 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
AnnaBridge | 167:e84263d55307 | 693 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
AnnaBridge | 167:e84263d55307 | 694 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
AnnaBridge | 167:e84263d55307 | 695 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
AnnaBridge | 167:e84263d55307 | 696 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
AnnaBridge | 167:e84263d55307 | 697 | /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ |
AnnaBridge | 167:e84263d55307 | 698 | #define NVIC_SetPriority __NVIC_SetPriority |
AnnaBridge | 167:e84263d55307 | 699 | #define NVIC_GetPriority __NVIC_GetPriority |
AnnaBridge | 167:e84263d55307 | 700 | #define NVIC_SystemReset __NVIC_SystemReset |
AnnaBridge | 167:e84263d55307 | 701 | #endif /* CMSIS_NVIC_VIRTUAL */ |
AnnaBridge | 167:e84263d55307 | 702 | |
AnnaBridge | 167:e84263d55307 | 703 | #ifdef CMSIS_VECTAB_VIRTUAL |
AnnaBridge | 167:e84263d55307 | 704 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
AnnaBridge | 167:e84263d55307 | 705 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
AnnaBridge | 167:e84263d55307 | 706 | #endif |
AnnaBridge | 167:e84263d55307 | 707 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
AnnaBridge | 167:e84263d55307 | 708 | #else |
AnnaBridge | 167:e84263d55307 | 709 | #define NVIC_SetVector __NVIC_SetVector |
AnnaBridge | 167:e84263d55307 | 710 | #define NVIC_GetVector __NVIC_GetVector |
AnnaBridge | 167:e84263d55307 | 711 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
AnnaBridge | 167:e84263d55307 | 712 | |
AnnaBridge | 167:e84263d55307 | 713 | #define NVIC_USER_IRQ_OFFSET 16 |
AnnaBridge | 167:e84263d55307 | 714 | |
AnnaBridge | 167:e84263d55307 | 715 | |
<> | 144:ef7eb2e8f9f7 | 716 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
<> | 144:ef7eb2e8f9f7 | 717 | /* The following MACROS handle generation of the register offset and byte masks */ |
<> | 144:ef7eb2e8f9f7 | 718 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
<> | 144:ef7eb2e8f9f7 | 719 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
<> | 144:ef7eb2e8f9f7 | 720 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
<> | 144:ef7eb2e8f9f7 | 721 | |
<> | 144:ef7eb2e8f9f7 | 722 | |
AnnaBridge | 167:e84263d55307 | 723 | /** |
AnnaBridge | 167:e84263d55307 | 724 | \brief Enable Interrupt |
AnnaBridge | 167:e84263d55307 | 725 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
AnnaBridge | 167:e84263d55307 | 726 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 727 | \note IRQn must not be negative. |
<> | 144:ef7eb2e8f9f7 | 728 | */ |
AnnaBridge | 167:e84263d55307 | 729 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 730 | { |
AnnaBridge | 167:e84263d55307 | 731 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 732 | { |
AnnaBridge | 167:e84263d55307 | 733 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
AnnaBridge | 167:e84263d55307 | 734 | } |
<> | 144:ef7eb2e8f9f7 | 735 | } |
<> | 144:ef7eb2e8f9f7 | 736 | |
<> | 144:ef7eb2e8f9f7 | 737 | |
AnnaBridge | 167:e84263d55307 | 738 | /** |
AnnaBridge | 167:e84263d55307 | 739 | \brief Get Interrupt Enable status |
AnnaBridge | 167:e84263d55307 | 740 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
AnnaBridge | 167:e84263d55307 | 741 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 742 | \return 0 Interrupt is not enabled. |
AnnaBridge | 167:e84263d55307 | 743 | \return 1 Interrupt is enabled. |
AnnaBridge | 167:e84263d55307 | 744 | \note IRQn must not be negative. |
<> | 144:ef7eb2e8f9f7 | 745 | */ |
AnnaBridge | 167:e84263d55307 | 746 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 747 | { |
AnnaBridge | 167:e84263d55307 | 748 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 749 | { |
AnnaBridge | 167:e84263d55307 | 750 | return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
AnnaBridge | 167:e84263d55307 | 751 | } |
AnnaBridge | 167:e84263d55307 | 752 | else |
AnnaBridge | 167:e84263d55307 | 753 | { |
AnnaBridge | 167:e84263d55307 | 754 | return(0U); |
AnnaBridge | 167:e84263d55307 | 755 | } |
<> | 144:ef7eb2e8f9f7 | 756 | } |
<> | 144:ef7eb2e8f9f7 | 757 | |
<> | 144:ef7eb2e8f9f7 | 758 | |
AnnaBridge | 167:e84263d55307 | 759 | /** |
AnnaBridge | 167:e84263d55307 | 760 | \brief Disable Interrupt |
AnnaBridge | 167:e84263d55307 | 761 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
AnnaBridge | 167:e84263d55307 | 762 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 763 | \note IRQn must not be negative. |
<> | 144:ef7eb2e8f9f7 | 764 | */ |
AnnaBridge | 167:e84263d55307 | 765 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 766 | { |
AnnaBridge | 167:e84263d55307 | 767 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 768 | { |
AnnaBridge | 167:e84263d55307 | 769 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
AnnaBridge | 167:e84263d55307 | 770 | __DSB(); |
AnnaBridge | 167:e84263d55307 | 771 | __ISB(); |
AnnaBridge | 167:e84263d55307 | 772 | } |
<> | 144:ef7eb2e8f9f7 | 773 | } |
<> | 144:ef7eb2e8f9f7 | 774 | |
<> | 144:ef7eb2e8f9f7 | 775 | |
AnnaBridge | 167:e84263d55307 | 776 | /** |
AnnaBridge | 167:e84263d55307 | 777 | \brief Get Pending Interrupt |
AnnaBridge | 167:e84263d55307 | 778 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
AnnaBridge | 167:e84263d55307 | 779 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 780 | \return 0 Interrupt status is not pending. |
AnnaBridge | 167:e84263d55307 | 781 | \return 1 Interrupt status is pending. |
AnnaBridge | 167:e84263d55307 | 782 | \note IRQn must not be negative. |
<> | 144:ef7eb2e8f9f7 | 783 | */ |
AnnaBridge | 167:e84263d55307 | 784 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 785 | { |
AnnaBridge | 167:e84263d55307 | 786 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 787 | { |
AnnaBridge | 167:e84263d55307 | 788 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
AnnaBridge | 167:e84263d55307 | 789 | } |
AnnaBridge | 167:e84263d55307 | 790 | else |
AnnaBridge | 167:e84263d55307 | 791 | { |
AnnaBridge | 167:e84263d55307 | 792 | return(0U); |
AnnaBridge | 167:e84263d55307 | 793 | } |
<> | 144:ef7eb2e8f9f7 | 794 | } |
<> | 144:ef7eb2e8f9f7 | 795 | |
<> | 144:ef7eb2e8f9f7 | 796 | |
AnnaBridge | 167:e84263d55307 | 797 | /** |
AnnaBridge | 167:e84263d55307 | 798 | \brief Set Pending Interrupt |
AnnaBridge | 167:e84263d55307 | 799 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
AnnaBridge | 167:e84263d55307 | 800 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 801 | \note IRQn must not be negative. |
<> | 144:ef7eb2e8f9f7 | 802 | */ |
AnnaBridge | 167:e84263d55307 | 803 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 804 | { |
AnnaBridge | 167:e84263d55307 | 805 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 806 | { |
AnnaBridge | 167:e84263d55307 | 807 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 144:ef7eb2e8f9f7 | 808 | } |
AnnaBridge | 167:e84263d55307 | 809 | } |
AnnaBridge | 167:e84263d55307 | 810 | |
AnnaBridge | 167:e84263d55307 | 811 | |
AnnaBridge | 167:e84263d55307 | 812 | /** |
AnnaBridge | 167:e84263d55307 | 813 | \brief Clear Pending Interrupt |
AnnaBridge | 167:e84263d55307 | 814 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
AnnaBridge | 167:e84263d55307 | 815 | \param [in] IRQn Device specific interrupt number. |
AnnaBridge | 167:e84263d55307 | 816 | \note IRQn must not be negative. |
AnnaBridge | 167:e84263d55307 | 817 | */ |
AnnaBridge | 167:e84263d55307 | 818 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
AnnaBridge | 167:e84263d55307 | 819 | { |
AnnaBridge | 167:e84263d55307 | 820 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 821 | { |
AnnaBridge | 167:e84263d55307 | 822 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 144:ef7eb2e8f9f7 | 823 | } |
<> | 144:ef7eb2e8f9f7 | 824 | } |
<> | 144:ef7eb2e8f9f7 | 825 | |
<> | 144:ef7eb2e8f9f7 | 826 | |
AnnaBridge | 167:e84263d55307 | 827 | /** |
AnnaBridge | 167:e84263d55307 | 828 | \brief Set Interrupt Priority |
AnnaBridge | 167:e84263d55307 | 829 | \details Sets the priority of a device specific interrupt or a processor exception. |
AnnaBridge | 167:e84263d55307 | 830 | The interrupt number can be positive to specify a device specific interrupt, |
AnnaBridge | 167:e84263d55307 | 831 | or negative to specify a processor exception. |
AnnaBridge | 167:e84263d55307 | 832 | \param [in] IRQn Interrupt number. |
AnnaBridge | 167:e84263d55307 | 833 | \param [in] priority Priority to set. |
AnnaBridge | 167:e84263d55307 | 834 | \note The priority cannot be set for every processor exception. |
AnnaBridge | 167:e84263d55307 | 835 | */ |
AnnaBridge | 167:e84263d55307 | 836 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
AnnaBridge | 167:e84263d55307 | 837 | { |
AnnaBridge | 167:e84263d55307 | 838 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 839 | { |
AnnaBridge | 167:e84263d55307 | 840 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
AnnaBridge | 167:e84263d55307 | 841 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
AnnaBridge | 167:e84263d55307 | 842 | } |
AnnaBridge | 167:e84263d55307 | 843 | else |
AnnaBridge | 167:e84263d55307 | 844 | { |
AnnaBridge | 167:e84263d55307 | 845 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
AnnaBridge | 167:e84263d55307 | 846 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
AnnaBridge | 167:e84263d55307 | 847 | } |
AnnaBridge | 167:e84263d55307 | 848 | } |
<> | 144:ef7eb2e8f9f7 | 849 | |
<> | 144:ef7eb2e8f9f7 | 850 | |
AnnaBridge | 167:e84263d55307 | 851 | /** |
AnnaBridge | 167:e84263d55307 | 852 | \brief Get Interrupt Priority |
AnnaBridge | 167:e84263d55307 | 853 | \details Reads the priority of a device specific interrupt or a processor exception. |
AnnaBridge | 167:e84263d55307 | 854 | The interrupt number can be positive to specify a device specific interrupt, |
AnnaBridge | 167:e84263d55307 | 855 | or negative to specify a processor exception. |
AnnaBridge | 167:e84263d55307 | 856 | \param [in] IRQn Interrupt number. |
AnnaBridge | 167:e84263d55307 | 857 | \return Interrupt Priority. |
AnnaBridge | 167:e84263d55307 | 858 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
<> | 144:ef7eb2e8f9f7 | 859 | */ |
AnnaBridge | 167:e84263d55307 | 860 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
<> | 144:ef7eb2e8f9f7 | 861 | { |
<> | 144:ef7eb2e8f9f7 | 862 | |
AnnaBridge | 167:e84263d55307 | 863 | if ((int32_t)(IRQn) >= 0) |
AnnaBridge | 167:e84263d55307 | 864 | { |
AnnaBridge | 167:e84263d55307 | 865 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
<> | 144:ef7eb2e8f9f7 | 866 | } |
AnnaBridge | 167:e84263d55307 | 867 | else |
AnnaBridge | 167:e84263d55307 | 868 | { |
AnnaBridge | 167:e84263d55307 | 869 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
<> | 144:ef7eb2e8f9f7 | 870 | } |
<> | 144:ef7eb2e8f9f7 | 871 | } |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | |
AnnaBridge | 167:e84263d55307 | 874 | /** |
AnnaBridge | 167:e84263d55307 | 875 | \brief Set Interrupt Vector |
AnnaBridge | 167:e84263d55307 | 876 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
AnnaBridge | 167:e84263d55307 | 877 | The interrupt number can be positive to specify a device specific interrupt, |
AnnaBridge | 167:e84263d55307 | 878 | or negative to specify a processor exception. |
AnnaBridge | 167:e84263d55307 | 879 | VTOR must been relocated to SRAM before. |
AnnaBridge | 167:e84263d55307 | 880 | If VTOR is not present address 0 must be mapped to SRAM. |
AnnaBridge | 167:e84263d55307 | 881 | \param [in] IRQn Interrupt number |
AnnaBridge | 167:e84263d55307 | 882 | \param [in] vector Address of interrupt handler function |
<> | 144:ef7eb2e8f9f7 | 883 | */ |
AnnaBridge | 167:e84263d55307 | 884 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
<> | 144:ef7eb2e8f9f7 | 885 | { |
AnnaBridge | 167:e84263d55307 | 886 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
AnnaBridge | 167:e84263d55307 | 887 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
AnnaBridge | 167:e84263d55307 | 888 | #else |
AnnaBridge | 167:e84263d55307 | 889 | uint32_t *vectors = (uint32_t *)0x0U; |
AnnaBridge | 167:e84263d55307 | 890 | #endif |
AnnaBridge | 167:e84263d55307 | 891 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
AnnaBridge | 167:e84263d55307 | 892 | } |
AnnaBridge | 167:e84263d55307 | 893 | |
AnnaBridge | 167:e84263d55307 | 894 | |
AnnaBridge | 167:e84263d55307 | 895 | /** |
AnnaBridge | 167:e84263d55307 | 896 | \brief Get Interrupt Vector |
AnnaBridge | 167:e84263d55307 | 897 | \details Reads an interrupt vector from interrupt vector table. |
AnnaBridge | 167:e84263d55307 | 898 | The interrupt number can be positive to specify a device specific interrupt, |
AnnaBridge | 167:e84263d55307 | 899 | or negative to specify a processor exception. |
AnnaBridge | 167:e84263d55307 | 900 | \param [in] IRQn Interrupt number. |
AnnaBridge | 167:e84263d55307 | 901 | \return Address of interrupt handler function |
AnnaBridge | 167:e84263d55307 | 902 | */ |
AnnaBridge | 167:e84263d55307 | 903 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
AnnaBridge | 167:e84263d55307 | 904 | { |
AnnaBridge | 167:e84263d55307 | 905 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
AnnaBridge | 167:e84263d55307 | 906 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
AnnaBridge | 167:e84263d55307 | 907 | #else |
AnnaBridge | 167:e84263d55307 | 908 | uint32_t *vectors = (uint32_t *)0x0U; |
AnnaBridge | 167:e84263d55307 | 909 | #endif |
AnnaBridge | 167:e84263d55307 | 910 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
AnnaBridge | 167:e84263d55307 | 911 | |
AnnaBridge | 167:e84263d55307 | 912 | } |
AnnaBridge | 167:e84263d55307 | 913 | |
AnnaBridge | 167:e84263d55307 | 914 | |
AnnaBridge | 167:e84263d55307 | 915 | /** |
AnnaBridge | 167:e84263d55307 | 916 | \brief System Reset |
AnnaBridge | 167:e84263d55307 | 917 | \details Initiates a system reset request to reset the MCU. |
AnnaBridge | 167:e84263d55307 | 918 | */ |
AnnaBridge | 167:e84263d55307 | 919 | __STATIC_INLINE void __NVIC_SystemReset(void) |
AnnaBridge | 167:e84263d55307 | 920 | { |
AnnaBridge | 167:e84263d55307 | 921 | __DSB(); /* Ensure all outstanding memory accesses included |
AnnaBridge | 167:e84263d55307 | 922 | buffered write are completed before reset */ |
<> | 144:ef7eb2e8f9f7 | 923 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
<> | 144:ef7eb2e8f9f7 | 924 | SCB_AIRCR_SYSRESETREQ_Msk); |
AnnaBridge | 167:e84263d55307 | 925 | __DSB(); /* Ensure completion of memory access */ |
AnnaBridge | 167:e84263d55307 | 926 | |
AnnaBridge | 167:e84263d55307 | 927 | for(;;) /* wait until reset */ |
AnnaBridge | 167:e84263d55307 | 928 | { |
AnnaBridge | 167:e84263d55307 | 929 | __NOP(); |
AnnaBridge | 167:e84263d55307 | 930 | } |
<> | 144:ef7eb2e8f9f7 | 931 | } |
<> | 144:ef7eb2e8f9f7 | 932 | |
<> | 144:ef7eb2e8f9f7 | 933 | /*@} end of CMSIS_Core_NVICFunctions */ |
<> | 144:ef7eb2e8f9f7 | 934 | |
<> | 144:ef7eb2e8f9f7 | 935 | |
AnnaBridge | 167:e84263d55307 | 936 | /* ########################## FPU functions #################################### */ |
AnnaBridge | 167:e84263d55307 | 937 | /** |
AnnaBridge | 167:e84263d55307 | 938 | \ingroup CMSIS_Core_FunctionInterface |
AnnaBridge | 167:e84263d55307 | 939 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
AnnaBridge | 167:e84263d55307 | 940 | \brief Function that provides FPU type. |
<> | 144:ef7eb2e8f9f7 | 941 | @{ |
<> | 144:ef7eb2e8f9f7 | 942 | */ |
<> | 144:ef7eb2e8f9f7 | 943 | |
AnnaBridge | 167:e84263d55307 | 944 | /** |
AnnaBridge | 167:e84263d55307 | 945 | \brief get FPU type |
AnnaBridge | 167:e84263d55307 | 946 | \details returns the FPU type |
AnnaBridge | 167:e84263d55307 | 947 | \returns |
AnnaBridge | 167:e84263d55307 | 948 | - \b 0: No FPU |
AnnaBridge | 167:e84263d55307 | 949 | - \b 1: Single precision FPU |
AnnaBridge | 167:e84263d55307 | 950 | - \b 2: Double + Single precision FPU |
AnnaBridge | 167:e84263d55307 | 951 | */ |
AnnaBridge | 167:e84263d55307 | 952 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
AnnaBridge | 167:e84263d55307 | 953 | { |
AnnaBridge | 167:e84263d55307 | 954 | return 0U; /* No FPU */ |
AnnaBridge | 167:e84263d55307 | 955 | } |
<> | 144:ef7eb2e8f9f7 | 956 | |
<> | 144:ef7eb2e8f9f7 | 957 | |
AnnaBridge | 167:e84263d55307 | 958 | /*@} end of CMSIS_Core_FpuFunctions */ |
AnnaBridge | 167:e84263d55307 | 959 | |
AnnaBridge | 167:e84263d55307 | 960 | |
<> | 144:ef7eb2e8f9f7 | 961 | |
AnnaBridge | 167:e84263d55307 | 962 | /* ################################## SysTick function ############################################ */ |
AnnaBridge | 167:e84263d55307 | 963 | /** |
AnnaBridge | 167:e84263d55307 | 964 | \ingroup CMSIS_Core_FunctionInterface |
AnnaBridge | 167:e84263d55307 | 965 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
AnnaBridge | 167:e84263d55307 | 966 | \brief Functions that configure the System. |
AnnaBridge | 167:e84263d55307 | 967 | @{ |
AnnaBridge | 167:e84263d55307 | 968 | */ |
<> | 144:ef7eb2e8f9f7 | 969 | |
AnnaBridge | 167:e84263d55307 | 970 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
<> | 144:ef7eb2e8f9f7 | 971 | |
AnnaBridge | 167:e84263d55307 | 972 | /** |
AnnaBridge | 167:e84263d55307 | 973 | \brief System Tick Configuration |
AnnaBridge | 167:e84263d55307 | 974 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
AnnaBridge | 167:e84263d55307 | 975 | Counter is in free running mode to generate periodic interrupts. |
AnnaBridge | 167:e84263d55307 | 976 | \param [in] ticks Number of ticks between two interrupts. |
AnnaBridge | 167:e84263d55307 | 977 | \return 0 Function succeeded. |
AnnaBridge | 167:e84263d55307 | 978 | \return 1 Function failed. |
AnnaBridge | 167:e84263d55307 | 979 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
AnnaBridge | 167:e84263d55307 | 980 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
AnnaBridge | 167:e84263d55307 | 981 | must contain a vendor-specific implementation of this function. |
<> | 144:ef7eb2e8f9f7 | 982 | */ |
<> | 144:ef7eb2e8f9f7 | 983 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
<> | 144:ef7eb2e8f9f7 | 984 | { |
AnnaBridge | 167:e84263d55307 | 985 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
AnnaBridge | 167:e84263d55307 | 986 | { |
AnnaBridge | 167:e84263d55307 | 987 | return (1UL); /* Reload value impossible */ |
AnnaBridge | 167:e84263d55307 | 988 | } |
<> | 144:ef7eb2e8f9f7 | 989 | |
<> | 144:ef7eb2e8f9f7 | 990 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
<> | 144:ef7eb2e8f9f7 | 991 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 992 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
<> | 144:ef7eb2e8f9f7 | 993 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
<> | 144:ef7eb2e8f9f7 | 994 | SysTick_CTRL_TICKINT_Msk | |
<> | 144:ef7eb2e8f9f7 | 995 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
<> | 144:ef7eb2e8f9f7 | 996 | return (0UL); /* Function successful */ |
<> | 144:ef7eb2e8f9f7 | 997 | } |
<> | 144:ef7eb2e8f9f7 | 998 | |
<> | 144:ef7eb2e8f9f7 | 999 | #endif |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | /*@} end of CMSIS_Core_SysTickFunctions */ |
<> | 144:ef7eb2e8f9f7 | 1002 | |
<> | 144:ef7eb2e8f9f7 | 1003 | |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | |
<> | 144:ef7eb2e8f9f7 | 1006 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 1007 | } |
<> | 144:ef7eb2e8f9f7 | 1008 | #endif |
<> | 144:ef7eb2e8f9f7 | 1009 | |
<> | 144:ef7eb2e8f9f7 | 1010 | #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
<> | 144:ef7eb2e8f9f7 | 1011 | |
<> | 144:ef7eb2e8f9f7 | 1012 | #endif /* __CMSIS_GENERIC */ |