Amit Gandhi / sensen_copy_2

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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/Changes_emlib.txt@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec
Child:
161:2cc1468da177
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ================ Revision history ============================================
<> 150:02e0a0aed4ec 2 5.0.0:
<> 150:02e0a0aed4ec 3 - em_core: New module, contains API for enabling/disabling interrupts
<> 150:02e0a0aed4ec 4 and implementing critical regions.
<> 150:02e0a0aed4ec 5 em_core replaces em_int which is deprecated and marked for removal in a
<> 150:02e0a0aed4ec 6 later release.
<> 150:02e0a0aed4ec 7 - em_emu: Added EMU_SetBiasMode() for Series 1 Configuration 1 devices.
<> 150:02e0a0aed4ec 8 - em_chip: Adding EMU_E210 errata fix in CHIP_Init().
<> 150:02e0a0aed4ec 9 - em_adc: Changed default value of negSel in ADC_INITSINGLE_DEFAULT
<> 150:02e0a0aed4ec 10 from adcNegSelAPORT0XCH1 to adcNegSelVSS.
<> 150:02e0a0aed4ec 11 - em_emu, em_cmu, em_chip, em_system: Added support for Series 1,
<> 150:02e0a0aed4ec 12 Configuration 2 parts (eg. EFR32MG12)
<> 150:02e0a0aed4ec 13 - em_gpio: Fixed GPIO_ExtIntConfig() to enable correct interrupt number on
<> 150:02e0a0aed4ec 14 Series 1 devices.
<> 150:02e0a0aed4ec 15 - em_ldma: Updated LDMA_Init() and LDMA_StartTransfer() to support pointers
<> 150:02e0a0aed4ec 16 to const memory.
<> 150:02e0a0aed4ec 17 - em_ldma: Adding LDMA_DESCRIPTOR_SINGLE_P2P_BYTE which can be used when
<> 150:02e0a0aed4ec 18 transfering bytes from one peripheral to another peripheral.
<> 150:02e0a0aed4ec 19 - em_i2c: Fixed bug that may clear IEN bits set by the user.
<> 150:02e0a0aed4ec 20 - em_emu: DCDC LN mode RCOBAND is now set based on LNFORCECCM.
<> 150:02e0a0aed4ec 21 - em_emu: Member dcdcLnCompCtrl added to EMU_DCDCInit_TypeDef. This parameter
<> 150:02e0a0aed4ec 22 allows configuraiton of 1uF or 4.7uF DCDC capacitor. 1uF is default for
<> 150:02e0a0aed4ec 23 Series 1 Device Configuration 1 while 4.7 is default for Series 1
<> 150:02e0a0aed4ec 24 Device Configuration 2 and later.
<> 150:02e0a0aed4ec 25 - Updated documentation with more code examples for em_assert, em_common,
<> 150:02e0a0aed4ec 26 em_cryotimer, em_gpcrc, em_ldma, em_msc, em_ramfunc, em_system, em_usart.
<> 150:02e0a0aed4ec 27
<> 150:02e0a0aed4ec 28 4.4.0:
<> 150:02e0a0aed4ec 29 - em_emu: Putting DCDC in bypass mode before entering EM4S.
<> 150:02e0a0aed4ec 30 - em_cmu: In the CMU_HFXOInit_TypeDef struct the following members have been
<> 150:02e0a0aed4ec 31 deprecated and are no longer in use: autoStartEm01, autoSelEm01, and
<> 150:02e0a0aed4ec 32 autoStartSelOnRacWakeup. Any application using the HFXO autostart feature
<> 150:02e0a0aed4ec 33 must use the CMU_HFXOAutostartEnable() function instead.
<> 150:02e0a0aed4ec 34 - em_emu: Updating DCDC LP comparator bias thresholds for EM2/3/4 according to
<> 150:02e0a0aed4ec 35 updated reference manual. The thresholds are compared to the
<> 150:02e0a0aed4ec 36 em234LoadCurrent_uA value of the EMU_DCDCInit_TypeDef struct.
<> 150:02e0a0aed4ec 37 - em_msc: Fix for errata FLASH_E201 - Potential program failure after power on
<> 150:02e0a0aed4ec 38 After a flash write the first word is checked to verify write operation. On
<> 150:02e0a0aed4ec 39 a verification failure the first word is re-programmed.
<> 150:02e0a0aed4ec 40 - em_adc: Enforcing at least 8 cycle aquisition time when reading ADC internal
<> 150:02e0a0aed4ec 41 temp sensor using a 1.25V reference on platform 2 generation 1 devices.
<> 150:02e0a0aed4ec 42 - em_adc: Setting GPBIASACC when initializing measurement of the ADC internal
<> 150:02e0a0aed4ec 43 temp sensor as documented in the reference manual.
<> 150:02e0a0aed4ec 44 - em_emu: Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H
<> 150:02e0a0aed4ec 45 - em_cmu: Added the possibility to configure external clock as HFXO
<> 150:02e0a0aed4ec 46 and LFXO source via the CMU_HFXOInit() and CMU_LFXOInit() functions.
<> 150:02e0a0aed4ec 47 - em_emu: Added EMU_EnterEM4H and EMU_EnterEM4S functions.
<> 150:02e0a0aed4ec 48 - Fixed shift bug in ADC_EM2ClockConfig_TypeDef.
<> 150:02e0a0aed4ec 49 - Added bounds check on ADC prescaler.
<> 150:02e0a0aed4ec 50 - Updated ADC_INITSCAN_DEFAULT to match ADC_ScanInputClear().
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 4.3.1:
<> 150:02e0a0aed4ec 53 - EFR32 and EFM32PG/JG em_cmu: Added automatic switching to HFXO
<> 150:02e0a0aed4ec 54 PEAKDETSHUNTOPTMODE=CMD mode after the first enable. This means automatic
<> 150:02e0a0aed4ec 55 peak detection and shunt current optimization runs at the first call to
<> 150:02e0a0aed4ec 56 CMU_OscillatorEnable(cmuOsc_HFXO, true, true) or
<> 150:02e0a0aed4ec 57 CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO) only.
<> 150:02e0a0aed4ec 58 Optimization can be restarted by calling CMU_OscillatorTuningOptimize(). This is
<> 150:02e0a0aed4ec 59 required if the temperature changes by more than 100degC.
<> 150:02e0a0aed4ec 60 - Added CMU_HFXOAutostartEnable() function to support automatic HFXO start and
<> 150:02e0a0aed4ec 61 select.
<> 150:02e0a0aed4ec 62 - Updated default timeouts for CMU_HFXOInit() to optimize HFXO startup
<> 150:02e0a0aed4ec 63 time. The startup time reduction depends on the oscillator specification.
<> 150:02e0a0aed4ec 64 The new defaults are safe for typical oscillator specifications.
<> 150:02e0a0aed4ec 65 - em_ldma: LDMA_StartTransfer() now only enable a DMA channel once.
<> 150:02e0a0aed4ec 66 - em_cmu: Fixed condtitional compilation bug in CMU_ClockSelectGet().
<> 150:02e0a0aed4ec 67 - em_usart: Fixed bug in USART_BaudrateCalc() function.
<> 150:02e0a0aed4ec 68 - em_usart: Improved corner cases in synchrounous baudrate calculation math.
<> 150:02e0a0aed4ec 69 - em_emu.c: EMU_DCDCLnRcoBandSet() calls EMU_DCDCOptimizeSlice() as the slice
<> 150:02e0a0aed4ec 70 configuration depends on RCO band.
<> 150:02e0a0aed4ec 71
<> 150:02e0a0aed4ec 72 4.3.0:
<> 150:02e0a0aed4ec 73 - em_cmu: Removed unused fields from CMU_HFXOInit_TypeDef. The removed fields
<> 150:02e0a0aed4ec 74 are regIshStartup and timeoutWarmSteady.
<> 150:02e0a0aed4ec 75 - em_rtc.h: Added RTC_CounterSet function for modifying the RTC Counter.
<> 150:02e0a0aed4ec 76 - em_burtc.c: Fixed bug when doing low frequency domain synchronization.
<> 150:02e0a0aed4ec 77 - em_gpio.c: Deprecated GPIO_IntConfig(), use new function GPIO_ExtIntConfig()
<> 150:02e0a0aed4ec 78 instead.
<> 150:02e0a0aed4ec 79 - Removed deprecated file em_part.h.
<> 150:02e0a0aed4ec 80 - em_dma.c: Replaced infinite loop on bus errors in default irq handler with
<> 150:02e0a0aed4ec 81 an assert.
<> 150:02e0a0aed4ec 82 - em_gpio.c: Use direct register write instead of BUS API in GPIO_PinModeSet
<> 150:02e0a0aed4ec 83 to prevent glitches.
<> 150:02e0a0aed4ec 84 - Fixed incorrect handling of CMU_CTRL_WSHFLE and CMU_HFPRESC_HFCLKLEPRESC in
<> 150:02e0a0aed4ec 85 em_cmu.c for EFM32 Pearl and Jade Gecko.
<> 150:02e0a0aed4ec 86 - Type enumerations cmuClock_HFLE and cmuSelect_HFCLKLE can now be used for
<> 150:02e0a0aed4ec 87 all families to select or reference the divided down HF clock for LE peripherals.
<> 150:02e0a0aed4ec 88 - Code size optimization in em_cmu.c.
<> 150:02e0a0aed4ec 89 - Added GPCRC support.
<> 150:02e0a0aed4ec 90 - Added support for WARNSEL, WINSEL and WDOGRSTDIS to em_wdog. Added interrupt
<> 150:02e0a0aed4ec 91 functions. Added support for multiple WDOG instances. Deprecated functions
<> 150:02e0a0aed4ec 92 WDOG_Enable(), WDOG_Feed(), WDOG_Init() and WDOG_Lock().
<> 150:02e0a0aed4ec 93 - GPIO_EM4GetPinWakeupCause() now returns the content of the EM4WU field from
<> 150:02e0a0aed4ec 94 the GPIO_IF register for platform 2 devices.
<> 150:02e0a0aed4ec 95 - Added function GPIO_SlewrateSet() to set slewrate for GPIO ports.
<> 150:02e0a0aed4ec 96 - Added fix for GPIO_E201 in CHIP_Init().
<> 150:02e0a0aed4ec 97 - Added function CMU_HFRCOBandGet() and CMU_HFRCOBandSet() for platform 2.
<> 150:02e0a0aed4ec 98 Functions with the same names are present for platform 1, but the parameter
<> 150:02e0a0aed4ec 99 and return types are different. Platform 1 and 2 also do not support the same
<> 150:02e0a0aed4ec 100 HFRCO/AUXHFRCO frequencies.
<> 150:02e0a0aed4ec 101 - Added HFLE wait-state control to CMU_HFRCOBandSet(). This is a bug on
<> 150:02e0a0aed4ec 102 EFM32 Wonder Gecko only as HFLE DIV4 is required at 24MHz, in between the 28HMz
<> 150:02e0a0aed4ec 103 and 21MHz HFRCO bands.
<> 150:02e0a0aed4ec 104 - Fixed reset-cause XMASKs for platform 2, gen 1 parts. Improved
<> 150:02e0a0aed4ec 105 documentation in em_rmu.c.
<> 150:02e0a0aed4ec 106 - Added support for configuring IrDA on USART1 for EFM32 Happy Gecko. The
<> 150:02e0a0aed4ec 107 function USART_InitIrDA() is deprecated, and replaced by USARTn_InitIrDA().
<> 150:02e0a0aed4ec 108 - Added module em_ramfunc. Fixed issue with calls from em_msc RAM code to Flash.
<> 150:02e0a0aed4ec 109 - Updated current limiter threshold equations for LNCLIMILIMSEL, LPCLIMILIMSEL
<> 150:02e0a0aed4ec 110 and DCDCZDETCTRL.
<> 150:02e0a0aed4ec 111 - Member type EMU_DcdcLnTransientMode_TypeDef in EMU_DCDCInit_TypeDef changed to
<> 150:02e0a0aed4ec 112 EMU_DcdcLnReverseCurrentControl_TypeDef to enable support for reverse current
<> 150:02e0a0aed4ec 113 limiter.
<> 150:02e0a0aed4ec 114 - EM2/3 current consumption optimization: Default value
<> 150:02e0a0aed4ec 115 emuDcdcAnaPeripheralPower_AVDD in EMU_DCDCINIT_DEFAULT for EFR32
<> 150:02e0a0aed4ec 116 changed to emuDcdcAnaPeripheralPower_DCDC.
<> 150:02e0a0aed4ec 117 - EM2/3 current consumption optimization: DCDC_LP_NFET_CNT updated to 7
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119 4.2.3:
<> 150:02e0a0aed4ec 120 - Added DMA and LDMA functions to enable/disable channel requests.
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 4.2.2:
<> 150:02e0a0aed4ec 123 - em_gpio.c: Use direct register write instead of BUS API in GPIO_PinModeSet
<> 150:02e0a0aed4ec 124 to prevent glitches.
<> 150:02e0a0aed4ec 125
<> 144:ef7eb2e8f9f7 126 4.2.1:
<> 144:ef7eb2e8f9f7 127 - Added errata fix for an issue that may cause BOD resets in EM2 when using
<> 144:ef7eb2e8f9f7 128 DCDC-to-DVDD mode. The fix is implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 129 - Added function EMU_DCDCPowerOff() for boards with physically disconnected DCDC.
<> 144:ef7eb2e8f9f7 130 - Current consumption is optimized for DCDC bypass mode. This update is
<> 144:ef7eb2e8f9f7 131 implemented in EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 4.2.0:
<> 144:ef7eb2e8f9f7 134 - Updated I2C clock divider equation for platform 2 parts. Added constraints
<> 144:ef7eb2e8f9f7 135 to HFPER clock frequency in I2C_BusFreqSet().
<> 144:ef7eb2e8f9f7 136 - EMU EMU_EM23VregMode_TypeDef replaced with a bool.
<> 144:ef7eb2e8f9f7 137 - Added support for GPIO alternate drive strength and alternate control modes.
<> 144:ef7eb2e8f9f7 138 - DCDC setup is simplified. More tuning and optimization settings added to
<> 144:ef7eb2e8f9f7 139 EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 140 - Added member pinRetentionMode to EMU_EM4Init_TypeDef.
<> 144:ef7eb2e8f9f7 141 - Added function EMU_UnlatchPinRetention() to support unlatching of pin
<> 144:ef7eb2e8f9f7 142 retention in EM4H/S.
<> 144:ef7eb2e8f9f7 143 - Fixed bug in ADC_InitScan() which caused a overwrite of single conversion
<> 144:ef7eb2e8f9f7 144 mode calibration values.
<> 150:02e0a0aed4ec 145 - Added support for CRYPTO module on EFM32 Pearl and Jade Gecko (em_crypto.c/h).
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 4.1.1:
<> 144:ef7eb2e8f9f7 148 - EMU_DCDCInit() updated with new parameters for EM2 and 3. Current consumption
<> 150:02e0a0aed4ec 149 with DCDC at expected levels for EFR32 and EFM32 Pearl and Jade Gecko.
<> 144:ef7eb2e8f9f7 150 - EMU_DCDCInit_TypeDef updated with more parameters. EMU_DcdcLpcmpBiasMode_TypeDef
<> 144:ef7eb2e8f9f7 151 is removed.
<> 144:ef7eb2e8f9f7 152 - More assertions added to EMU_DCDCInit().
<> 144:ef7eb2e8f9f7 153 - HFXO default parameters updated.
<> 144:ef7eb2e8f9f7 154 - ADC defaults updated.
<> 144:ef7eb2e8f9f7 155 - RMU pin mode set fixed.
<> 144:ef7eb2e8f9f7 156 - Added missing define for cmuSelect_ULFRCO.
<> 144:ef7eb2e8f9f7 157 - Added missing functions for handling peripheral interrupts.
<> 144:ef7eb2e8f9f7 158 - Added support for VMON.
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 4.1.0:
<> 150:02e0a0aed4ec 161 - New signature for RMU_ResetControl() function.
<> 144:ef7eb2e8f9f7 162 - The typedef EMU_EM23Init_TypeDef which is a parameter to EMU_EM23Init()
<> 144:ef7eb2e8f9f7 163 has got a new definition.
<> 150:02e0a0aed4ec 164 - Initial support _SILICON_LABS_32B_PLATFORM_2 devices added.
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 4.0.0:
<> 144:ef7eb2e8f9f7 167 - Use ARM CMSIS version 4.2.0.
<> 144:ef7eb2e8f9f7 168 - New style version macros in em_version.h.
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 3.20.14:
<> 144:ef7eb2e8f9f7 171 - USB release only.
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 3.20.13:
<> 144:ef7eb2e8f9f7 174 - Added new style family #defines in em_system.h, including EZR32 families.
<> 144:ef7eb2e8f9f7 175 - Fixed I2C_FREQ_STANDARD_MAX macros.
<> 144:ef7eb2e8f9f7 176 - Fixed bug in MSC_WriteWord which called internal functions that were linked
<> 144:ef7eb2e8f9f7 177 to flash for armgcc. All subsequent calls of MSC_WriteWord should now be
<> 150:02e0a0aed4ec 178 linked to RAM for all supported compilers. The internals of MSC_WriteWord()
<> 144:ef7eb2e8f9f7 179 will check the global variable SystemCoreClock in order to make sure the
<> 144:ef7eb2e8f9f7 180 frequency is high enough for flash operations. If the core clock frequency
<> 144:ef7eb2e8f9f7 181 is changed, software is responsible for calling MSC_Init or
<> 144:ef7eb2e8f9f7 182 SystemCoreClockGet in order to set the SystemCoreClock variable to the
<> 144:ef7eb2e8f9f7 183 correct value.
<> 144:ef7eb2e8f9f7 184 - Added errata fix IDAC_101.
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 3.20.12:
<> 144:ef7eb2e8f9f7 187 - Added errata fix EMU_108.
<> 144:ef7eb2e8f9f7 188 - #ifdef's now use register defines instead of a mix of register and family defines.
<> 144:ef7eb2e8f9f7 189 - Added a case for when there are only 4 DMA channels available:
<> 144:ef7eb2e8f9f7 190 Alignment was (correctly) defined at 7 bit, but got asserted for 8 bit, leading
<> 144:ef7eb2e8f9f7 191 to unpredictable tripped asserts.
<> 144:ef7eb2e8f9f7 192 - Added USART_INITPRSTRIGGER_DEFAULT defined structure to support HWCONF.
<> 144:ef7eb2e8f9f7 193 - Added support for LFC clock tree.
<> 144:ef7eb2e8f9f7 194 - Added CMU_USHFRCOBandSet() and CMU_USHFRCOBandGet().
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 3.20.10:
<> 144:ef7eb2e8f9f7 197 - Maintenance release, no changes.
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 3.20.9:
<> 144:ef7eb2e8f9f7 200 - Added support for Happy Gecko including support for the new oscillator USHFRCO.
<> 144:ef7eb2e8f9f7 201 - Added MSC_WriteWordFast() function. This flash write function has a similar
<> 144:ef7eb2e8f9f7 202 performance as the old MSC_WriteWord(), but it disables interrupts and
<> 144:ef7eb2e8f9f7 203 requires a core clock frequency of at least 14MHz. The new MSC_WriteWord()
<> 144:ef7eb2e8f9f7 204 is slower, but it does not disable interrupts and may be called with core
<> 144:ef7eb2e8f9f7 205 clock frequencies down to 1MHz.
<> 144:ef7eb2e8f9f7 206 - Fixed a bug in EMU_EnterEM4() that set other EM4 configuration bits to 0
<> 144:ef7eb2e8f9f7 207 on EM4 entry.
<> 144:ef7eb2e8f9f7 208 - Added EMU_EM23Init().
<> 144:ef7eb2e8f9f7 209 - Fixed a bug in CMU_FlashWaitStateControl() where it failed to set the
<> 144:ef7eb2e8f9f7 210 required wait-state configuration if the MSC is locked.
<> 144:ef7eb2e8f9f7 211 - Added EMU interrupt handling functions.
<> 144:ef7eb2e8f9f7 212 - BURTC_Reset() changed to use async reset RMU_CTRL_BURSTEN instead of
<> 144:ef7eb2e8f9f7 213 reset value writeback. This makes the function independent of a selected
<> 144:ef7eb2e8f9f7 214 and enabled clock.
<> 144:ef7eb2e8f9f7 215 - BURTC_Sync() now returns without waiting for BURTC->SYNCBUSY to clear
<> 144:ef7eb2e8f9f7 216 when no clock is selected in BURTC_CTRL_CLKSEL.
<> 144:ef7eb2e8f9f7 217 - Fixed assertion bug in ACMP_ChannelSet() that checked the negSel parameter
<> 144:ef7eb2e8f9f7 218 against the wrong upper bound.
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 3.20.7:
<> 144:ef7eb2e8f9f7 221 - Fixed CMU_MAX_FREQ_HFLE macro for Wonder family.
<> 144:ef7eb2e8f9f7 222 - Fixed MSC_WriteWord() bug.
<> 144:ef7eb2e8f9f7 223 - Added syncbusy wait in RTC_Reset() for Gecko family.
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 3.20.6:
<> 144:ef7eb2e8f9f7 226 - Corrected fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 3.20.5:
<> 144:ef7eb2e8f9f7 229 - Updated license texts.
<> 144:ef7eb2e8f9f7 230 - Removed unnecessary fix for Wonder Gecko.
<> 144:ef7eb2e8f9f7 231 - Updated LFXO temperature compensation in CHIP_Init().
<> 144:ef7eb2e8f9f7 232 - Changed LESENSE_ScanStart, LESENSE_ScanStop, LESENSE_DecoderStart,
<> 144:ef7eb2e8f9f7 233 LESENSE_ResultBufferClear() and LESENSE_Reset() functions to wait until
<> 144:ef7eb2e8f9f7 234 CMD register writes complete in order to make sure CMD register writes do
<> 144:ef7eb2e8f9f7 235 not break each other, and for register values to be consistent when
<> 144:ef7eb2e8f9f7 236 returning from functions that write to the CMD register.
<> 144:ef7eb2e8f9f7 237 - Added fix for Errata EMU_E107.
<> 144:ef7eb2e8f9f7 238 - Added family to SYSTEM_ChipRevision_TypeDef.
<> 144:ef7eb2e8f9f7 239 - Fixed bug in function AES_OFB128 which failed on Zero Gecko.
<> 144:ef7eb2e8f9f7 240 - Fixed RMU_ResetCauseGet() to return correct reset causes.
<> 144:ef7eb2e8f9f7 241 - Fixed bug in RTC_CounterReset() which failed to reset counter immediately
<> 144:ef7eb2e8f9f7 242 after return on Gecko devices.
<> 144:ef7eb2e8f9f7 243 - Added static inline non-blocking USART receive functions (USART_Rx...).
<> 144:ef7eb2e8f9f7 244 - Added function SYSTEM_GetFamily().
<> 144:ef7eb2e8f9f7 245 - Added function DAC_ChannelOutputSet().
<> 144:ef7eb2e8f9f7 246 - Fixed MSC_WriteWord() to not use WDOUBLE if LPWRITE is set.
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 3.20.2:
<> 144:ef7eb2e8f9f7 249 - Fixed bug regarding when MEMINFO in DEVINFO was introduced.
<> 144:ef7eb2e8f9f7 250 The correct crossover is production revision 18.
<> 144:ef7eb2e8f9f7 251 - Fixed bug in WDOG_Feed() which does not feed the watchdog if the watchdog
<> 144:ef7eb2e8f9f7 252 is disabled. Previously, the watchdog was broken after WDOG_Feed() fed it
<> 144:ef7eb2e8f9f7 253 when it was disabled.
<> 144:ef7eb2e8f9f7 254 - Fixed issue in em_i2c.c, which should set the NACK bit in the I2C CMD
<> 144:ef7eb2e8f9f7 255 register for the next to last byte received. The exception is when only
<> 144:ef7eb2e8f9f7 256 one byte is to be received. Then the NACK bit must be set like the
<> 144:ef7eb2e8f9f7 257 previous code was doing.
<> 144:ef7eb2e8f9f7 258 - Added function BURTC_ClockFreqGet() in order to determine clock frequency
<> 144:ef7eb2e8f9f7 259 of BURTC.
<> 144:ef7eb2e8f9f7 260 - Fixed bug in BURTC_Reset() which made a subsequent call to BURTC_Init hang.
<> 144:ef7eb2e8f9f7 261 - Added support for the IDAC module on the Zero Gecko family, em_idac.c/h.
<> 144:ef7eb2e8f9f7 262 - Fixed bug in DAC_PrescaleCalc() which could return higher values than
<> 144:ef7eb2e8f9f7 263 the maximum prescaler value. The fix makes sure to return the max prescaler
<> 144:ef7eb2e8f9f7 264 value resulting in possible higher DAC frequency than requested.
<> 144:ef7eb2e8f9f7 265 - Fixed I2C_BusFreqSet to use documented values for Nlow and Nhigh values,
<> 144:ef7eb2e8f9f7 266 and do not decrement the div(isor) by one according to the formula because
<> 144:ef7eb2e8f9f7 267 this resulted in higher I2C bus frequencies than desired.
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 3.20.0:
<> 144:ef7eb2e8f9f7 270 - LEUART: Added LEUART_TxDmaInEM2Enable() and LEUART_RxDmaInEM2Enable() for
<> 144:ef7eb2e8f9f7 271 enabling and disabling DMA LEUART RX and Tx in EM2 support.
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 3.0.3:
<> 144:ef7eb2e8f9f7 274 - Internal release for testing Wonder Gecko support.
<> 144:ef7eb2e8f9f7 275 - SYSTEM: Added function to enable/disable FPU access on Wonder parts,
<> 144:ef7eb2e8f9f7 276 SYSTEM_FpuAccessModeSet().
<> 144:ef7eb2e8f9f7 277 - USART: Added USART_SpiTransfer() function.
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 3.0.2:
<> 144:ef7eb2e8f9f7 280 - MSC: In MSC_WriteWord(), added support for double word write cycle support
<> 144:ef7eb2e8f9f7 281 (WDOUBLE) on devices with more than 512KiBytes of Flash memory. This can
<> 144:ef7eb2e8f9f7 282 almost double the speed of the MSC_WriteWord function for large data sizes.
<> 144:ef7eb2e8f9f7 283 - MSC: In MSC_ErasePage(), added support for devices with Flash page size
<> 144:ef7eb2e8f9f7 284 larger than 512 bytes, like Giant and Leopard Gecko.
<> 144:ef7eb2e8f9f7 285 - CMU: Fixed bug in CMU_ClockDivSet(). Clear HFLE and HFCORECLKLEDIV flags when
<> 144:ef7eb2e8f9f7 286 the core runs at frequencies up to 32MHz.
<> 144:ef7eb2e8f9f7 287 - CMU: Fixed bug in CMU_ClockEnable(): Set the HFLE and HFCORECLKLEDIV flags
<> 144:ef7eb2e8f9f7 288 when the CORE clock runs at frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 289 - CMU: Fixed bug in CMU_ClockSelectSet(): Set HFLE and DIV4 factor for peripheral
<> 144:ef7eb2e8f9f7 290 clock if HFCORE clock for LE is enabled and the CORE clock runs at
<> 144:ef7eb2e8f9f7 291 frequencies higher than 32MHz.
<> 144:ef7eb2e8f9f7 292 - BITBAND: Added BITBAND_PeripheralRead() and BITBAND_SRAMRead() functions.
<> 144:ef7eb2e8f9f7 293 - DMA: Added #ifndef EXCLUDE_DEFAULT_DMA_IRQ_HANDLER around DMA_IRQHandler in
<> 144:ef7eb2e8f9f7 294 order for the user to implement a custom IRQ handler or run without a DMA
<> 144:ef7eb2e8f9f7 295 IRQ handler by defining EXCLUDE_DEFAULT_DMA_IRQ_HANDLER with the -D compiler
<> 144:ef7eb2e8f9f7 296 option.
<> 144:ef7eb2e8f9f7 297 - BURTC: In functions BURTC_Init() and BURTC_CompareSet(), moved SYNCBUSY
<> 144:ef7eb2e8f9f7 298 loops in front of modifications of registers COMP0 and LPMODE.
<> 144:ef7eb2e8f9f7 299 - MSC: Fixed ram_code section error on Keil toolchain.
<> 144:ef7eb2e8f9f7 300 - MSC: Removed uneeded code from MSC init and deinit which would have no
<> 144:ef7eb2e8f9f7 301 effect (Big thanks to Martin Schreiber for reporting this bug!).
<> 144:ef7eb2e8f9f7 302 - System: Added access functions for reading some values out of the Device
<> 144:ef7eb2e8f9f7 303 Information page.
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 3.0.1:
<> 144:ef7eb2e8f9f7 306 - LFXO fix for Giant family.
<> 144:ef7eb2e8f9f7 307 - USART: Fix for EFM32TG108Fxx which does not have USART0.
<> 144:ef7eb2e8f9f7 308 - EBI: The write to the CTRL register now happens before the ROUTE registers
<> 144:ef7eb2e8f9f7 309 are set. This avoids potential glitches.
<> 144:ef7eb2e8f9f7 310 - LESENSE: Fix issue when using lesenseAltExMapACMP.
<> 144:ef7eb2e8f9f7 311 - TIMER: Fix compilation on devices where ADC is not available.
<> 144:ef7eb2e8f9f7 312 - LCD: Fix bug where Aloc field would not be set to 0.
<> 144:ef7eb2e8f9f7 313 - BURTC: Fix Reset function by adding reset of COMP0 register and removing
<> 144:ef7eb2e8f9f7 314 reset of POWERDOWN register. The POWERDOWN register cannot be used to
<> 144:ef7eb2e8f9f7 315 power up the blocks after it has been powered down.
<> 144:ef7eb2e8f9f7 316 - CMU: Fixed bug where ClockDivSet, ClockDivGet and ClockFreqGet didn't work for
<> 144:ef7eb2e8f9f7 317 cmuClock_LCDpre clock. Also corrected 3 wrongly typed constants.
<> 144:ef7eb2e8f9f7 318 - CMU: Fixed bug where LFBE field in LFCLKSEL was not cleared before setting
<> 144:ef7eb2e8f9f7 319 bit-value.
<> 144:ef7eb2e8f9f7 320 - CMU: Fixed bug with CMU_ClockSelectGet. Did not give correct return value
<> 144:ef7eb2e8f9f7 321 for cmuClock_LFB.
<> 144:ef7eb2e8f9f7 322 - I2C: Fixed bug where I2C_Init would set divisor depending on the previous
<> 144:ef7eb2e8f9f7 323 master/slave configuration, not the one set in the initialization.
<> 144:ef7eb2e8f9f7 324 - I2C: Fixed issue in the function I2C_BusFreqSet (called by I2C_Init). The
<> 144:ef7eb2e8f9f7 325 input parameter 'I2C_ClockHLR_TypeDef type' was not in use. The fix enables
<> 144:ef7eb2e8f9f7 326 the parameter to add support for 'i2cClockHLRAsymetric' and 'i2cClockHLRFast'
<> 144:ef7eb2e8f9f7 327 modes. In order to use 'i2cClockHLRAsymetric' and 'i2cClockHLRFast' the
<> 144:ef7eb2e8f9f7 328 frequency of the HFPER clock may need to be increased.
<> 144:ef7eb2e8f9f7 329 - OPAMP: Fixed bug in the function OPAMP_Enable where an incorrect register
<> 144:ef7eb2e8f9f7 330 was used when setting the OPA2 calibration value.
<> 144:ef7eb2e8f9f7 331 - LEUART: Fixed issue in LEUART_BaudrateSet when a high clock frequency and a
<> 144:ef7eb2e8f9f7 332 low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 333 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 334 range.
<> 144:ef7eb2e8f9f7 335 - USART: Fixed issue in USART_BaudrateAsyncSet when a high clock frequency and
<> 144:ef7eb2e8f9f7 336 a low baudrate can overflow the clock divisor register (CLKDIV). The fix uses
<> 144:ef7eb2e8f9f7 337 an assert statement to check whether the calculated clock divisor is out of
<> 144:ef7eb2e8f9f7 338 range.
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 3.0.0:
<> 144:ef7eb2e8f9f7 341 - efm32lib renamed emlib, as it will include support for non-EFM32 devices
<> 144:ef7eb2e8f9f7 342 in the future
<> 144:ef7eb2e8f9f7 343 - Added CMSIS_V3 compatibility fixes, and use of CMSIS_V3 definitions
<> 144:ef7eb2e8f9f7 344 - See Device/Changes-EnergyMicro.txt for detailed path changes
<> 144:ef7eb2e8f9f7 345 - New prefixes of all files, efm32_<peripherqal>.c/h to em_<peripheral>.c/h
<> 144:ef7eb2e8f9f7 346 - New names for readme and changes files
<> 144:ef7eb2e8f9f7 347 - RMU - BUMODERST not masked away when EM4 bits has been set
<> 144:ef7eb2e8f9f7 348 - CMU - CMU_LFClkGet now accounts for ULFRCO bit for Tiny Gecko
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 2.4.1:
<> 144:ef7eb2e8f9f7 351 - New, open source friendly license
<> 144:ef7eb2e8f9f7 352 - Fixed BURTC initialization hang if init->enable was false
<> 144:ef7eb2e8f9f7 353 - Fixed CMU issue with USBC and USB checks not being used correctly
<> 144:ef7eb2e8f9f7 354 - Added CMU feature, missing TIMER3 support
<> 144:ef7eb2e8f9f7 355 - Improved accuracy of SPI mode for USART baudrate calculation
<> 144:ef7eb2e8f9f7 356 - Corrected USBC HFCLKNODIV setting to comply with new header file defines
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 2.4.0:
<> 144:ef7eb2e8f9f7 359 - Added efm32_version.h defining software version number
<> 144:ef7eb2e8f9f7 360 - Added BURTC support for Giant and Leopard Gecko
<> 144:ef7eb2e8f9f7 361 - Added RMU_ResetControl for BU reset flag
<> 144:ef7eb2e8f9f7 362 - Added some missing features to EMU for back up domain and EM4 support
<> 144:ef7eb2e8f9f7 363 - ADC TimebaseCalc(), Giant/Leopard Gecko have max 5 bits in TIMEBASE field
<> 144:ef7eb2e8f9f7 364 - Removed EMU Backup Power Domain threshold setings from EMU_BUPDInit, added
<> 144:ef7eb2e8f9f7 365 EMU_BUThresRangeSet() and EMU_BUThresholdSet() API calls. Threshold values
<> 144:ef7eb2e8f9f7 366 are factory calibrated and should not usually be overridden by the user.
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 2.3.2:
<> 144:ef7eb2e8f9f7 369 - Added Tiny Gecko and Giant Gecko support in RMU for new reset causes
<> 144:ef7eb2e8f9f7 370 - CMU_ClockFreqGet will now report correct clock rates if HFLE is set (/4)
<> 144:ef7eb2e8f9f7 371 - Added Giant Gecko specific MSC_MassErase(), erase entire flash
<> 144:ef7eb2e8f9f7 372 - Added Giant Gecko specific MSC_BusStrategy (inline) function
<> 144:ef7eb2e8f9f7 373 - MSC_Init() will now configure TIMEBASE correctly according to AUXHFRCO clock
<> 144:ef7eb2e8f9f7 374 rate for Tiny Gecko and Giant Gecko
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 2.3.0:
<> 144:ef7eb2e8f9f7 377 - USART - Added USART_InitPrsTrigger to initialize USART PRS triggered
<> 144:ef7eb2e8f9f7 378 transmissions.
<> 144:ef7eb2e8f9f7 379 - CMU - numerous updates, now supports full clock tree of Giant/Tiny Gecko
<> 144:ef7eb2e8f9f7 380 - CMU_ClockDivSet/Get will now use real dividend and not logarithmic values
<> 144:ef7eb2e8f9f7 381 as earlier. Prior enumerated values have been kept for backward compatibility.
<> 144:ef7eb2e8f9f7 382 - Added support for CMU HFLE and DIV4 factor for core clock for LE
<> 144:ef7eb2e8f9f7 383 peripherals
<> 144:ef7eb2e8f9f7 384 - Added support for alternate LCD segment animation range for Giant Gecko
<> 144:ef7eb2e8f9f7 385 - Fixed bug: Don't enable VCMP low power reference until after warm up,
<> 144:ef7eb2e8f9f7 386 allow biasprog value of 0 in VCMP_Init()
<> 144:ef7eb2e8f9f7 387 - Added support for ALTMAP (256MB address map) in EBI_BankAddress()
<> 144:ef7eb2e8f9f7 388 - TIMER_Init() will now reset CNT value
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 2.2.2:
<> 144:ef7eb2e8f9f7 391 - Added DAC0 channel 0 and 1 to ACMP for Tiny and Giant devices
<> 144:ef7eb2e8f9f7 392 - Fixed bug in CMU for MSC WAITSTATE configuration, leading to too high wait
<> 144:ef7eb2e8f9f7 393 states depending on clock rate
<> 144:ef7eb2e8f9f7 394 - Fixed bug in CMU for UART1 clock enable
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 2.2.1:
<> 144:ef7eb2e8f9f7 397 - UART_Reset() and LEUART_Reset() will now reset ROUTE register as well, this
<> 144:ef7eb2e8f9f7 398 will mean GPIO pins will not be driven after this call. Take care to ensure
<> 144:ef7eb2e8f9f7 399 that GPIO ROUTE register is configured after calls to *UART_Init*Sync
<> 144:ef7eb2e8f9f7 400 - Fixed problems with EFM_ASSERT when using UART in USART API
<> 144:ef7eb2e8f9f7 401 - Added Giant Gecko support for EBI (new modes and TFT direct drive)
<> 144:ef7eb2e8f9f7 402 - Added Giant Gecko support for CMU 2 WAIT STATES, and I2C1
<> 144:ef7eb2e8f9f7 403 - Added Giant Gecko support for UART1 in CMU
<> 144:ef7eb2e8f9f7 404 - Added Giant Gecko support for DMA LOOP and 2D Copy operations
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 2.1.0:
<> 144:ef7eb2e8f9f7 407 - EMU_Restore will now disable HFRCO if it was not enabled when entering
<> 144:ef7eb2e8f9f7 408 an Energy Mode
<> 144:ef7eb2e8f9f7 409 - Run time changes only applies to Gecko devices, filter out Tiny and Giant
<> 144:ef7eb2e8f9f7 410 for CHIP_Init();
<> 144:ef7eb2e8f9f7 411 - Added const specificers to various initialization structures, to ensure
<> 144:ef7eb2e8f9f7 412 they can reside in flash instead of SRAM
<> 144:ef7eb2e8f9f7 413 - Bugfix in efm32_i2c.c, keep returning i2cTransferInProgress until done
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 2.0.1:
<> 144:ef7eb2e8f9f7 416 - Changed enum OPAMP_PosSel_TypeDef. Enum value opaPosSelOpaIn changed from
<> 144:ef7eb2e8f9f7 417 DAC_OPA0MUX_POSSEL_OPA1IN to DAC_OPA0MUX_POSSEL_OPA0INP.
<> 144:ef7eb2e8f9f7 418 - Bugfix in efm32_lesense.h, LESENSE_ChClk_TypeDef now contains unshifted
<> 144:ef7eb2e8f9f7 419 values, fixed the implementation in efm32_lesense.c where the bug prevented
<> 144:ef7eb2e8f9f7 420 the sampleClk to be set to AUXHFRCO.
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 2.0.0:
<> 144:ef7eb2e8f9f7 423 - USART_Init-functions now calls USART_Reset() which will also disable/reset
<> 144:ef7eb2e8f9f7 424 interrupt
<> 144:ef7eb2e8f9f7 425 - USART_BaudrateSyncSet() now asserts on invalid oversample configuration
<> 144:ef7eb2e8f9f7 426 - Added initialization of parity bit in LEUART_Init()
<> 144:ef7eb2e8f9f7 427 - Added Tiny Gecko support for CMU, ULFRCO, LESENSE clocks and continuous
<> 144:ef7eb2e8f9f7 428 calibration
<> 144:ef7eb2e8f9f7 429 - Added Tiny Gecko support for GPIO, EM4 pin retention and wake up support
<> 144:ef7eb2e8f9f7 430 - Added Tiny Gecko support for I2S, SPI auto TX mode on USART
<> 144:ef7eb2e8f9f7 431 - Added Tiny Gecko support for CACHE mesasurements for MSC module
<> 144:ef7eb2e8f9f7 432 - Added Tiny Gecko support for LCD module (with no HIGH segment registers)
<> 144:ef7eb2e8f9f7 433 - Added Tiny Gecko support for TIMER, PWM 2x, (DT lock not supported)
<> 144:ef7eb2e8f9f7 434 - Added Tiny Gecko support for LESENSE module
<> 144:ef7eb2e8f9f7 435 - Added Tiny Gecko support for PRS input in PCNT
<> 144:ef7eb2e8f9f7 436 - Added Tiny Gecko support for async signals in PRS, PRS_SourceAsyncSignalSet()
<> 144:ef7eb2e8f9f7 437 - Initial support for some Giant Gecko features, where overlapping with Tiny
<> 144:ef7eb2e8f9f7 438 - Removed LPFEN / LPFREQ support from DAC
<> 144:ef7eb2e8f9f7 439 - Fixed comments around interrupt functions, making it clear it is bitwise
<> 144:ef7eb2e8f9f7 440 logical or interrupt flags
<> 144:ef7eb2e8f9f7 441 - Fixed PCNT initialization for external clock configurations, making sure
<> 144:ef7eb2e8f9f7 442 config is synchronized at startup to 3 clocks. Note fix only works for
<> 144:ef7eb2e8f9f7 443 >revC EFM32G devices.
<> 144:ef7eb2e8f9f7 444 - Fixed efm32_cmu.c, EFM_ASSERT statement for LEUART clock div logic was
<> 144:ef7eb2e8f9f7 445 inverted
<> 144:ef7eb2e8f9f7 446 - Fixed ADC_InitScan, PRSSEL shift value corrected
<> 144:ef7eb2e8f9f7 447 - Fixed CMU_ClockFreqGet for devices that do not have I2C
<> 144:ef7eb2e8f9f7 448 - Fixed I2C_TransferInit for devices with more than one I2C-bus (Giant Gecko)
<> 144:ef7eb2e8f9f7 449 - Changed ACMP_Disable() implementation, now only disables the ACMP instance
<> 144:ef7eb2e8f9f7 450 by clearing the EN bit in the CTRL register
<> 144:ef7eb2e8f9f7 451 - Removed ACMP_DisableNoReset() function
<> 144:ef7eb2e8f9f7 452 - Fixed ACMP_Init(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 453 "enaReq" for ACMP_Init_TypeDef to control, fixed the EFM_ASSERT of the
<> 144:ef7eb2e8f9f7 454 biasprog parameter
<> 144:ef7eb2e8f9f7 455 - Added default configuration macro ACMP_INIT_DEFAULT for ACMP_Init_TypeDef
<> 144:ef7eb2e8f9f7 456 - Fixed ACMP_CapsenseInit(), removed automatic enabling, added new structure member
<> 144:ef7eb2e8f9f7 457 "enaReq" for ACMP_CapsenseInit_TypeDef to control, fixed the EFM_ASSERT of
<> 144:ef7eb2e8f9f7 458 the biasprog parameter
<> 144:ef7eb2e8f9f7 459 - Changed the name of the default configuration macro for
<> 144:ef7eb2e8f9f7 460 ACMP_CapsenseInit_TypeDef to ACMP_CAPSENSE_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 461 - Added RTC_Reset and RTC_CounterReset functions for RTC
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 1.3.0:
<> 144:ef7eb2e8f9f7 464 - MSC is automatically enabled/disabled when using the MSC API. This saves
<> 144:ef7eb2e8f9f7 465 power, and reduces errors due to not calling MSC_Init().
<> 144:ef7eb2e8f9f7 466 - Added API for controlling Cortex-M3 MPU (memory protection unit)
<> 144:ef7eb2e8f9f7 467 - Adjusted bit fields to comply with latest CMSIS release, see EFM_CMSIS
<> 144:ef7eb2e8f9f7 468 changes file for details
<> 144:ef7eb2e8f9f7 469 - Fixed issue with bit mask clearing in ACMP
<> 144:ef7eb2e8f9f7 470 - Functions ACMP_Enable and ACMP_DisableNoReset added
<> 144:ef7eb2e8f9f7 471 - Added comment about rev.C chips in PCNT, CMD_LTOPBIM not neccessary any more
<> 144:ef7eb2e8f9f7 472 - Added missing instance validity asserts to peripherals (ACMP, LEUART, USART)
<> 144:ef7eb2e8f9f7 473 - Fixed UART0 check in CMU_ClockFreqGet()
<> 144:ef7eb2e8f9f7 474 - Fixed command sync for PCNT before setting TOPB value during init
<> 144:ef7eb2e8f9f7 475 - Fixed instance validity check macro in PCNT
<> 144:ef7eb2e8f9f7 476 - Fixed TIMER_Reset() removed write to unimplemented timer channel registers
<> 144:ef7eb2e8f9f7 477 - Fixed EFM_ASSERT statements in ACMP, VCMP
<> 144:ef7eb2e8f9f7 478 - General code style update: added missing curly braces, default cases, etc.
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 1.2.1:
<> 144:ef7eb2e8f9f7 481 - Feature complete efm32lib, now also includes peripheral API for modules
<> 144:ef7eb2e8f9f7 482 AES,PCNT,MSC,ACMP,VCMP,LCD,EBI
<> 144:ef7eb2e8f9f7 483 - Fixed _TIMER_CC_CTRL_ICEDGE flags for correct timer configuration
<> 144:ef7eb2e8f9f7 484 - Fixed ADC calibration of Single and Scan mode of operation
<> 144:ef7eb2e8f9f7 485 - Added PCNT (ChipRev A/B PCNT0 errata NOT supported) and AES support
<> 144:ef7eb2e8f9f7 486 - Fixed conditional inclusion in efm32_emu.h
<> 144:ef7eb2e8f9f7 487 - Fixed code for LEUART0 for devices with multiple LEUARTs.
<> 144:ef7eb2e8f9f7 488 - Fixed incorrect setting of DOUT for GPIO configuration
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 1.1.4
<> 144:ef7eb2e8f9f7 491 - Fix for TIMER_INIT_DEFAULT
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 1.1.3:
<> 144:ef7eb2e8f9f7 494 - Added ADC, DAC, LETIMER, PRS, TIMER (except DTI) support
<> 144:ef7eb2e8f9f7 495 - Added utility for fetching chip revision (efm32_system.c/h)
<> 144:ef7eb2e8f9f7 496 - Removed RTC instance ref in API, only one RTC will be supported
<> 144:ef7eb2e8f9f7 497 (Affects also define in efm32_cmu.h)
<> 144:ef7eb2e8f9f7 498 - Added default init struct macros for LEUART, USART
<> 144:ef7eb2e8f9f7 499 - Added msbf parameter in USART synchronous init struct, USART_InitSync_TypeDef.
<> 144:ef7eb2e8f9f7 500 - Updated reset for I2C, USART, LEUART to also reset IEN register.
<> 144:ef7eb2e8f9f7 501 - Corrected fault in GPIO_PortOutSet()
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 1.1.2:
<> 144:ef7eb2e8f9f7 504 - Corrected minor issues in EMU, EM3 mode when restoring clocks
<> 144:ef7eb2e8f9f7 505 - Corrected RMU reset cause checking
<> 144:ef7eb2e8f9f7 506 - Changed GPIO enumerator symbols to start with gpio (from GPIO_)
<> 144:ef7eb2e8f9f7 507 - Changed CMU and WDOG enum typedefs to start with CMU_/WDOG_ (from cmu/wdog)
<> 144:ef7eb2e8f9f7 508 - Added USART/UART, LEUART, DMA, I2C support
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 1.1.1:
<> 144:ef7eb2e8f9f7 511 - First version including support for CMU, DBG, EMU, GPIO, RTC, WDOG