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targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | ;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** |
<> | 144:ef7eb2e8f9f7 | 2 | ;* File Name : startup_stm32f411xe.s |
<> | 144:ef7eb2e8f9f7 | 3 | ;* Author : MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 4 | ;* Version : V2.1.0 |
<> | 144:ef7eb2e8f9f7 | 5 | ;* Date : 19-June-2014 |
<> | 144:ef7eb2e8f9f7 | 6 | ;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. |
<> | 144:ef7eb2e8f9f7 | 7 | ;* This module performs: |
<> | 144:ef7eb2e8f9f7 | 8 | ;* - Set the initial SP |
<> | 144:ef7eb2e8f9f7 | 9 | ;* - Set the initial PC == Reset_Handler |
<> | 144:ef7eb2e8f9f7 | 10 | ;* - Set the vector table entries with the exceptions ISR address |
<> | 144:ef7eb2e8f9f7 | 11 | ;* - Branches to __main in the C library (which eventually |
<> | 144:ef7eb2e8f9f7 | 12 | ;* calls main()). |
<> | 144:ef7eb2e8f9f7 | 13 | ;* After Reset the CortexM4 processor is in Thread mode, |
<> | 144:ef7eb2e8f9f7 | 14 | ;* priority is Privileged, and the Stack is set to Main. |
<> | 144:ef7eb2e8f9f7 | 15 | ;* <<< Use Configuration Wizard in Context Menu >>> |
<> | 144:ef7eb2e8f9f7 | 16 | ;******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 17 | ; |
<> | 144:ef7eb2e8f9f7 | 18 | ;* Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 19 | ;* are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 20 | ;* 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 21 | ;* this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 22 | ;* 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 23 | ;* this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 24 | ;* and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 25 | ;* 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 26 | ;* may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 27 | ;* without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 28 | ;* |
<> | 144:ef7eb2e8f9f7 | 29 | ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 30 | ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 31 | ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 32 | ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 33 | ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 34 | ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 35 | ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 36 | ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 37 | ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 38 | ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 39 | ; |
<> | 144:ef7eb2e8f9f7 | 40 | ;******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | ; Amount of memory (in bytes) allocated for Stack |
<> | 144:ef7eb2e8f9f7 | 43 | ; Tailor this value to your application needs |
<> | 144:ef7eb2e8f9f7 | 44 | ; <h> Stack Configuration |
<> | 144:ef7eb2e8f9f7 | 45 | ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
<> | 144:ef7eb2e8f9f7 | 46 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 47 | |
<> | 144:ef7eb2e8f9f7 | 48 | Stack_Size EQU 0x00000400 |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | AREA STACK, NOINIT, READWRITE, ALIGN=3 |
<> | 144:ef7eb2e8f9f7 | 51 | EXPORT __initial_sp |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | Stack_Mem SPACE Stack_Size |
<> | 144:ef7eb2e8f9f7 | 54 | __initial_sp EQU 0x20020000 ; Top of RAM |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | ; <h> Heap Configuration |
<> | 144:ef7eb2e8f9f7 | 58 | ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
<> | 144:ef7eb2e8f9f7 | 59 | ; </h> |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | Heap_Size EQU 0x00000400 |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
<> | 144:ef7eb2e8f9f7 | 64 | EXPORT __heap_base |
<> | 144:ef7eb2e8f9f7 | 65 | EXPORT __heap_limit |
<> | 144:ef7eb2e8f9f7 | 66 | |
<> | 144:ef7eb2e8f9f7 | 67 | __heap_base |
<> | 144:ef7eb2e8f9f7 | 68 | Heap_Mem SPACE Heap_Size |
<> | 144:ef7eb2e8f9f7 | 69 | __heap_limit EQU (__initial_sp - Stack_Size) |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | PRESERVE8 |
<> | 144:ef7eb2e8f9f7 | 72 | THUMB |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | ; Vector Table Mapped to Address 0 at Reset |
<> | 144:ef7eb2e8f9f7 | 76 | AREA RESET, DATA, READONLY |
<> | 144:ef7eb2e8f9f7 | 77 | EXPORT __Vectors |
<> | 144:ef7eb2e8f9f7 | 78 | EXPORT __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 79 | EXPORT __Vectors_Size |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | __Vectors DCD __initial_sp ; Top of Stack |
<> | 144:ef7eb2e8f9f7 | 82 | DCD Reset_Handler ; Reset Handler |
<> | 144:ef7eb2e8f9f7 | 83 | DCD NMI_Handler ; NMI Handler |
<> | 144:ef7eb2e8f9f7 | 84 | DCD HardFault_Handler ; Hard Fault Handler |
<> | 144:ef7eb2e8f9f7 | 85 | DCD MemManage_Handler ; MPU Fault Handler |
<> | 144:ef7eb2e8f9f7 | 86 | DCD BusFault_Handler ; Bus Fault Handler |
<> | 144:ef7eb2e8f9f7 | 87 | DCD UsageFault_Handler ; Usage Fault Handler |
<> | 144:ef7eb2e8f9f7 | 88 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 89 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 90 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 91 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 92 | DCD SVC_Handler ; SVCall Handler |
<> | 144:ef7eb2e8f9f7 | 93 | DCD DebugMon_Handler ; Debug Monitor Handler |
<> | 144:ef7eb2e8f9f7 | 94 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 95 | DCD PendSV_Handler ; PendSV Handler |
<> | 144:ef7eb2e8f9f7 | 96 | DCD SysTick_Handler ; SysTick Handler |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | ; External Interrupts |
<> | 144:ef7eb2e8f9f7 | 99 | DCD WWDG_IRQHandler ; Window WatchDog |
<> | 144:ef7eb2e8f9f7 | 100 | DCD PVD_IRQHandler ; PVD through EXTI Line detection |
<> | 144:ef7eb2e8f9f7 | 101 | DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line |
<> | 144:ef7eb2e8f9f7 | 102 | DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line |
<> | 144:ef7eb2e8f9f7 | 103 | DCD FLASH_IRQHandler ; FLASH |
<> | 144:ef7eb2e8f9f7 | 104 | DCD RCC_IRQHandler ; RCC |
<> | 144:ef7eb2e8f9f7 | 105 | DCD EXTI0_IRQHandler ; EXTI Line0 |
<> | 144:ef7eb2e8f9f7 | 106 | DCD EXTI1_IRQHandler ; EXTI Line1 |
<> | 144:ef7eb2e8f9f7 | 107 | DCD EXTI2_IRQHandler ; EXTI Line2 |
<> | 144:ef7eb2e8f9f7 | 108 | DCD EXTI3_IRQHandler ; EXTI Line3 |
<> | 144:ef7eb2e8f9f7 | 109 | DCD EXTI4_IRQHandler ; EXTI Line4 |
<> | 144:ef7eb2e8f9f7 | 110 | DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 |
<> | 144:ef7eb2e8f9f7 | 111 | DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 |
<> | 144:ef7eb2e8f9f7 | 112 | DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 |
<> | 144:ef7eb2e8f9f7 | 113 | DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 |
<> | 144:ef7eb2e8f9f7 | 114 | DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 |
<> | 144:ef7eb2e8f9f7 | 115 | DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 |
<> | 144:ef7eb2e8f9f7 | 116 | DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 |
<> | 144:ef7eb2e8f9f7 | 117 | DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s |
<> | 144:ef7eb2e8f9f7 | 118 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 119 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 120 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 121 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 122 | DCD EXTI9_5_IRQHandler ; External Line[9:5]s |
<> | 144:ef7eb2e8f9f7 | 123 | DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 |
<> | 144:ef7eb2e8f9f7 | 124 | DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 |
<> | 144:ef7eb2e8f9f7 | 125 | DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 |
<> | 144:ef7eb2e8f9f7 | 126 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare |
<> | 144:ef7eb2e8f9f7 | 127 | DCD TIM2_IRQHandler ; TIM2 |
<> | 144:ef7eb2e8f9f7 | 128 | DCD TIM3_IRQHandler ; TIM3 |
<> | 144:ef7eb2e8f9f7 | 129 | DCD TIM4_IRQHandler ; TIM4 |
<> | 144:ef7eb2e8f9f7 | 130 | DCD I2C1_EV_IRQHandler ; I2C1 Event |
<> | 144:ef7eb2e8f9f7 | 131 | DCD I2C1_ER_IRQHandler ; I2C1 Error |
<> | 144:ef7eb2e8f9f7 | 132 | DCD I2C2_EV_IRQHandler ; I2C2 Event |
<> | 144:ef7eb2e8f9f7 | 133 | DCD I2C2_ER_IRQHandler ; I2C2 Error |
<> | 144:ef7eb2e8f9f7 | 134 | DCD SPI1_IRQHandler ; SPI1 |
<> | 144:ef7eb2e8f9f7 | 135 | DCD SPI2_IRQHandler ; SPI2 |
<> | 144:ef7eb2e8f9f7 | 136 | DCD USART1_IRQHandler ; USART1 |
<> | 144:ef7eb2e8f9f7 | 137 | DCD USART2_IRQHandler ; USART2 |
<> | 144:ef7eb2e8f9f7 | 138 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 139 | DCD EXTI15_10_IRQHandler ; External Line[15:10]s |
<> | 144:ef7eb2e8f9f7 | 140 | DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line |
<> | 144:ef7eb2e8f9f7 | 141 | DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line |
<> | 144:ef7eb2e8f9f7 | 142 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 143 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 144 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 145 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 146 | DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 |
<> | 144:ef7eb2e8f9f7 | 147 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 148 | DCD SDIO_IRQHandler ; SDIO |
<> | 144:ef7eb2e8f9f7 | 149 | DCD TIM5_IRQHandler ; TIM5 |
<> | 144:ef7eb2e8f9f7 | 150 | DCD SPI3_IRQHandler ; SPI3 |
<> | 144:ef7eb2e8f9f7 | 151 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 152 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 153 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 154 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 155 | DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 |
<> | 144:ef7eb2e8f9f7 | 156 | DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 |
<> | 144:ef7eb2e8f9f7 | 157 | DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 |
<> | 144:ef7eb2e8f9f7 | 158 | DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 |
<> | 144:ef7eb2e8f9f7 | 159 | DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 |
<> | 144:ef7eb2e8f9f7 | 160 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 161 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 162 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 163 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 164 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 165 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 166 | DCD OTG_FS_IRQHandler ; USB OTG FS |
<> | 144:ef7eb2e8f9f7 | 167 | DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 |
<> | 144:ef7eb2e8f9f7 | 168 | DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 |
<> | 144:ef7eb2e8f9f7 | 169 | DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 |
<> | 144:ef7eb2e8f9f7 | 170 | DCD USART6_IRQHandler ; USART6 |
<> | 144:ef7eb2e8f9f7 | 171 | DCD I2C3_EV_IRQHandler ; I2C3 event |
<> | 144:ef7eb2e8f9f7 | 172 | DCD I2C3_ER_IRQHandler ; I2C3 error |
<> | 144:ef7eb2e8f9f7 | 173 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 174 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 175 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 176 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 177 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 178 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 179 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 180 | DCD FPU_IRQHandler ; FPU |
<> | 144:ef7eb2e8f9f7 | 181 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 182 | DCD 0 ; Reserved |
<> | 144:ef7eb2e8f9f7 | 183 | DCD SPI4_IRQHandler ; SPI4 |
<> | 144:ef7eb2e8f9f7 | 184 | DCD SPI5_IRQHandler ; SPI5 |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | __Vectors_End |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | __Vectors_Size EQU __Vectors_End - __Vectors |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | AREA |.text|, CODE, READONLY |
<> | 144:ef7eb2e8f9f7 | 191 | |
<> | 144:ef7eb2e8f9f7 | 192 | ; Reset handler |
<> | 144:ef7eb2e8f9f7 | 193 | Reset_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 194 | EXPORT Reset_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 195 | IMPORT SystemInit |
<> | 144:ef7eb2e8f9f7 | 196 | IMPORT __main |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | LDR R0, =SystemInit |
<> | 144:ef7eb2e8f9f7 | 199 | BLX R0 |
<> | 144:ef7eb2e8f9f7 | 200 | LDR R0, =__main |
<> | 144:ef7eb2e8f9f7 | 201 | BX R0 |
<> | 144:ef7eb2e8f9f7 | 202 | ENDP |
<> | 144:ef7eb2e8f9f7 | 203 | |
<> | 144:ef7eb2e8f9f7 | 204 | ; Dummy Exception Handlers (infinite loops which can be modified) |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | NMI_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 207 | EXPORT NMI_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 208 | B . |
<> | 144:ef7eb2e8f9f7 | 209 | ENDP |
<> | 144:ef7eb2e8f9f7 | 210 | HardFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 211 | PROC |
<> | 144:ef7eb2e8f9f7 | 212 | EXPORT HardFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 213 | B . |
<> | 144:ef7eb2e8f9f7 | 214 | ENDP |
<> | 144:ef7eb2e8f9f7 | 215 | MemManage_Handler\ |
<> | 144:ef7eb2e8f9f7 | 216 | PROC |
<> | 144:ef7eb2e8f9f7 | 217 | EXPORT MemManage_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 218 | B . |
<> | 144:ef7eb2e8f9f7 | 219 | ENDP |
<> | 144:ef7eb2e8f9f7 | 220 | BusFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 221 | PROC |
<> | 144:ef7eb2e8f9f7 | 222 | EXPORT BusFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 223 | B . |
<> | 144:ef7eb2e8f9f7 | 224 | ENDP |
<> | 144:ef7eb2e8f9f7 | 225 | UsageFault_Handler\ |
<> | 144:ef7eb2e8f9f7 | 226 | PROC |
<> | 144:ef7eb2e8f9f7 | 227 | EXPORT UsageFault_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 228 | B . |
<> | 144:ef7eb2e8f9f7 | 229 | ENDP |
<> | 144:ef7eb2e8f9f7 | 230 | SVC_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 231 | EXPORT SVC_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 232 | B . |
<> | 144:ef7eb2e8f9f7 | 233 | ENDP |
<> | 144:ef7eb2e8f9f7 | 234 | DebugMon_Handler\ |
<> | 144:ef7eb2e8f9f7 | 235 | PROC |
<> | 144:ef7eb2e8f9f7 | 236 | EXPORT DebugMon_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 237 | B . |
<> | 144:ef7eb2e8f9f7 | 238 | ENDP |
<> | 144:ef7eb2e8f9f7 | 239 | PendSV_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 240 | EXPORT PendSV_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 241 | B . |
<> | 144:ef7eb2e8f9f7 | 242 | ENDP |
<> | 144:ef7eb2e8f9f7 | 243 | SysTick_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 244 | EXPORT SysTick_Handler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 245 | B . |
<> | 144:ef7eb2e8f9f7 | 246 | ENDP |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | Default_Handler PROC |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | EXPORT WWDG_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 251 | EXPORT PVD_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 252 | EXPORT TAMP_STAMP_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 253 | EXPORT RTC_WKUP_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 254 | EXPORT FLASH_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 255 | EXPORT RCC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 256 | EXPORT EXTI0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 257 | EXPORT EXTI1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 258 | EXPORT EXTI2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 259 | EXPORT EXTI3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 260 | EXPORT EXTI4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 261 | EXPORT DMA1_Stream0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 262 | EXPORT DMA1_Stream1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 263 | EXPORT DMA1_Stream2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 264 | EXPORT DMA1_Stream3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 265 | EXPORT DMA1_Stream4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 266 | EXPORT DMA1_Stream5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 267 | EXPORT DMA1_Stream6_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 268 | EXPORT ADC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 269 | EXPORT EXTI9_5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 270 | EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 271 | EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 272 | EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 273 | EXPORT TIM1_CC_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 274 | EXPORT TIM2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 275 | EXPORT TIM3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 276 | EXPORT TIM4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 277 | EXPORT I2C1_EV_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 278 | EXPORT I2C1_ER_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 279 | EXPORT I2C2_EV_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 280 | EXPORT I2C2_ER_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 281 | EXPORT SPI1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 282 | EXPORT SPI2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 283 | EXPORT USART1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 284 | EXPORT USART2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 285 | EXPORT EXTI15_10_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 286 | EXPORT RTC_Alarm_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 287 | EXPORT OTG_FS_WKUP_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 288 | EXPORT DMA1_Stream7_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 289 | EXPORT SDIO_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 290 | EXPORT TIM5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 291 | EXPORT SPI3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 292 | EXPORT DMA2_Stream0_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 293 | EXPORT DMA2_Stream1_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 294 | EXPORT DMA2_Stream2_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 295 | EXPORT DMA2_Stream3_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 296 | EXPORT DMA2_Stream4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 297 | EXPORT OTG_FS_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 298 | EXPORT DMA2_Stream5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 299 | EXPORT DMA2_Stream6_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 300 | EXPORT DMA2_Stream7_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 301 | EXPORT USART6_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 302 | EXPORT I2C3_EV_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 303 | EXPORT I2C3_ER_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 304 | EXPORT FPU_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 305 | EXPORT SPI4_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 306 | EXPORT SPI5_IRQHandler [WEAK] |
<> | 144:ef7eb2e8f9f7 | 307 | |
<> | 144:ef7eb2e8f9f7 | 308 | WWDG_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 309 | PVD_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 310 | TAMP_STAMP_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 311 | RTC_WKUP_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 312 | FLASH_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 313 | RCC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 314 | EXTI0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 315 | EXTI1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 316 | EXTI2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 317 | EXTI3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 318 | EXTI4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 319 | DMA1_Stream0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 320 | DMA1_Stream1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 321 | DMA1_Stream2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 322 | DMA1_Stream3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 323 | DMA1_Stream4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 324 | DMA1_Stream5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 325 | DMA1_Stream6_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 326 | ADC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 327 | EXTI9_5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 328 | TIM1_BRK_TIM9_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 329 | TIM1_UP_TIM10_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 330 | TIM1_TRG_COM_TIM11_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 331 | TIM1_CC_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 332 | TIM2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 333 | TIM3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 334 | TIM4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 335 | I2C1_EV_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 336 | I2C1_ER_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 337 | I2C2_EV_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 338 | I2C2_ER_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 339 | SPI1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 340 | SPI2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 341 | USART1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 342 | USART2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 343 | EXTI15_10_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 344 | RTC_Alarm_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 345 | OTG_FS_WKUP_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 346 | DMA1_Stream7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 347 | SDIO_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 348 | TIM5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 349 | SPI3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 350 | DMA2_Stream0_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 351 | DMA2_Stream1_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 352 | DMA2_Stream2_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 353 | DMA2_Stream3_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 354 | DMA2_Stream4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 355 | OTG_FS_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 356 | DMA2_Stream5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 357 | DMA2_Stream6_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 358 | DMA2_Stream7_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 359 | USART6_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 360 | I2C3_EV_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 361 | I2C3_ER_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 362 | FPU_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 363 | SPI4_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 364 | SPI5_IRQHandler |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | B . |
<> | 144:ef7eb2e8f9f7 | 367 | |
<> | 144:ef7eb2e8f9f7 | 368 | ENDP |
<> | 144:ef7eb2e8f9f7 | 369 | |
<> | 144:ef7eb2e8f9f7 | 370 | ALIGN |
<> | 144:ef7eb2e8f9f7 | 371 | END |
<> | 144:ef7eb2e8f9f7 | 372 | |
<> | 144:ef7eb2e8f9f7 | 373 | ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** |