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targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /* mbed Microcontroller Library |
<> | 149:156823d33999 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 149:156823d33999 | 3 | * |
<> | 149:156823d33999 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 149:156823d33999 | 5 | * you may not use this file except in compliance with the License. |
<> | 149:156823d33999 | 6 | * You may obtain a copy of the License at |
<> | 149:156823d33999 | 7 | * |
<> | 149:156823d33999 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 149:156823d33999 | 9 | * |
<> | 149:156823d33999 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 149:156823d33999 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 149:156823d33999 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 149:156823d33999 | 13 | * See the License for the specific language governing permissions and |
<> | 149:156823d33999 | 14 | * limitations under the License. |
<> | 149:156823d33999 | 15 | */ |
<> | 149:156823d33999 | 16 | #include "mbed_assert.h" |
<> | 149:156823d33999 | 17 | #include "pwmout_api.h" |
<> | 149:156823d33999 | 18 | #include "cmsis.h" |
<> | 149:156823d33999 | 19 | #include "pinmap.h" |
<> | 149:156823d33999 | 20 | #include "RZ_A1_Init.h" |
<> | 149:156823d33999 | 21 | #include "cpg_iodefine.h" |
<> | 149:156823d33999 | 22 | #include "pwm_iodefine.h" |
<> | 149:156823d33999 | 23 | #include "gpio_addrdefine.h" |
<> | 149:156823d33999 | 24 | |
<> | 149:156823d33999 | 25 | #define MTU2_PWM_NUM 22 |
<> | 149:156823d33999 | 26 | #define MTU2_PWM_SIGNAL 2 |
<> | 149:156823d33999 | 27 | #define MTU2_PWM_OFFSET 0x20 |
<> | 149:156823d33999 | 28 | |
<> | 149:156823d33999 | 29 | // PORT ID, PWM ID, Pin function |
<> | 149:156823d33999 | 30 | static const PinMap PinMap_PWM[] = { |
<> | 149:156823d33999 | 31 | {P2_1 , MTU2_PWM0_PIN , 6}, |
<> | 149:156823d33999 | 32 | {P2_11 , MTU2_PWM1_PIN , 5}, |
<> | 149:156823d33999 | 33 | {P3_8 , MTU2_PWM2_PIN , 6}, |
<> | 149:156823d33999 | 34 | {P3_10 , MTU2_PWM3_PIN , 6}, |
<> | 149:156823d33999 | 35 | {P4_0 , MTU2_PWM4_PIN , 2}, |
<> | 149:156823d33999 | 36 | {P4_4 , MTU2_PWM5_PIN , 3}, |
<> | 149:156823d33999 | 37 | {P4_6 , MTU2_PWM6_PIN , 3}, |
<> | 149:156823d33999 | 38 | {P5_0 , MTU2_PWM7_PIN , 6}, |
<> | 149:156823d33999 | 39 | {P5_3 , MTU2_PWM8_PIN , 6}, |
<> | 149:156823d33999 | 40 | {P5_5 , MTU2_PWM9_PIN , 6}, |
<> | 149:156823d33999 | 41 | {P7_2 , MTU2_PWM10_PIN , 7}, |
<> | 149:156823d33999 | 42 | {P7_4 , MTU2_PWM11_PIN , 7}, |
<> | 149:156823d33999 | 43 | {P7_6 , MTU2_PWM12_PIN , 7}, |
<> | 149:156823d33999 | 44 | {P7_10 , MTU2_PWM13_PIN , 7}, |
<> | 149:156823d33999 | 45 | {P7_12 , MTU2_PWM14_PIN , 7}, |
<> | 149:156823d33999 | 46 | {P7_14 , MTU2_PWM15_PIN , 7}, |
<> | 149:156823d33999 | 47 | {P8_8 , MTU2_PWM16_PIN , 5}, |
<> | 149:156823d33999 | 48 | {P8_10 , MTU2_PWM17_PIN , 4}, |
<> | 149:156823d33999 | 49 | {P8_12 , MTU2_PWM18_PIN , 4}, |
<> | 149:156823d33999 | 50 | {P8_14 , MTU2_PWM19_PIN , 4}, |
<> | 149:156823d33999 | 51 | {P11_0 , MTU2_PWM20_PIN , 2}, |
<> | 149:156823d33999 | 52 | {P11_2 , MTU2_PWM21_PIN , 2}, |
<> | 149:156823d33999 | 53 | {P4_4 , PWM0_PIN , 4}, |
<> | 149:156823d33999 | 54 | {P3_2 , PWM1_PIN , 7}, |
<> | 149:156823d33999 | 55 | {P4_6 , PWM2_PIN , 4}, |
<> | 149:156823d33999 | 56 | {P4_7 , PWM3_PIN , 4}, |
<> | 149:156823d33999 | 57 | {P8_14 , PWM4_PIN , 6}, |
<> | 149:156823d33999 | 58 | {P8_15 , PWM5_PIN , 6}, |
<> | 149:156823d33999 | 59 | {P8_13 , PWM6_PIN , 6}, |
<> | 149:156823d33999 | 60 | {P8_11 , PWM7_PIN , 6}, |
<> | 149:156823d33999 | 61 | {P8_8 , PWM8_PIN , 6}, |
<> | 149:156823d33999 | 62 | {P10_0 , PWM9_PIN , 3}, |
<> | 149:156823d33999 | 63 | {P8_12 , PWM10_PIN , 6}, |
<> | 149:156823d33999 | 64 | {P8_9 , PWM11_PIN , 6}, |
<> | 149:156823d33999 | 65 | {P8_10 , PWM12_PIN , 6}, |
<> | 149:156823d33999 | 66 | {P4_5 , PWM13_PIN , 4}, |
<> | 149:156823d33999 | 67 | {NC , NC , 0} |
<> | 149:156823d33999 | 68 | }; |
<> | 149:156823d33999 | 69 | |
<> | 149:156823d33999 | 70 | static const PWMType PORT[] = { |
<> | 149:156823d33999 | 71 | PWM2E, // PWM0_PIN |
<> | 149:156823d33999 | 72 | PWM2C, // PWM1_PIN |
<> | 149:156823d33999 | 73 | PWM2G, // PWM2_PIN |
<> | 149:156823d33999 | 74 | PWM2H, // PWM3_PIN |
<> | 149:156823d33999 | 75 | PWM1G, // PWM4_PIN |
<> | 149:156823d33999 | 76 | PWM1H, // PWM5_PIN |
<> | 149:156823d33999 | 77 | PWM1F, // PWM6_PIN |
<> | 149:156823d33999 | 78 | PWM1D, // PWM7_PIN |
<> | 149:156823d33999 | 79 | PWM1A, // PWM8_PIN |
<> | 149:156823d33999 | 80 | PWM2A, // PWM9_PIN |
<> | 149:156823d33999 | 81 | PWM1E, // PWM10_PIN |
<> | 149:156823d33999 | 82 | PWM1B, // PWM11_PIN |
<> | 149:156823d33999 | 83 | PWM1C, // PWM12_PIN |
<> | 149:156823d33999 | 84 | PWM2F, // PWM13_PIN |
<> | 149:156823d33999 | 85 | }; |
<> | 149:156823d33999 | 86 | |
<> | 149:156823d33999 | 87 | static const MTU2_PWMType MTU2_PORT[] = { |
<> | 149:156823d33999 | 88 | TIOC2A, // MTU2_PWM0_PIN |
<> | 149:156823d33999 | 89 | TIOC1A, // MTU2_PWM1_PIN |
<> | 149:156823d33999 | 90 | TIOC4A, // MTU2_PWM2_PIN |
<> | 149:156823d33999 | 91 | TIOC4C, // MTU2_PWM3_PIN |
<> | 149:156823d33999 | 92 | TIOC0A, // MTU2_PWM4_PIN |
<> | 149:156823d33999 | 93 | TIOC4A, // MTU2_PWM5_PIN |
<> | 149:156823d33999 | 94 | TIOC4C, // MTU2_PWM6_PIN |
<> | 149:156823d33999 | 95 | TIOC0A, // MTU2_PWM7_PIN |
<> | 149:156823d33999 | 96 | TIOC3C, // MTU2_PWM8_PIN |
<> | 149:156823d33999 | 97 | TIOC0C, // MTU2_PWM9_PIN |
<> | 149:156823d33999 | 98 | TIOC0C, // MTU2_PWM10_PIN |
<> | 149:156823d33999 | 99 | TIOC1A, // MTU2_PWM11_PIN |
<> | 149:156823d33999 | 100 | TIOC2A, // MTU2_PWM12_PIN |
<> | 149:156823d33999 | 101 | TIOC3C, // MTU2_PWM13_PIN |
<> | 149:156823d33999 | 102 | TIOC4A, // MTU2_PWM14_PIN |
<> | 149:156823d33999 | 103 | TIOC4C, // MTU2_PWM15_PIN |
<> | 149:156823d33999 | 104 | TIOC1A, // MTU2_PWM16_PIN |
<> | 149:156823d33999 | 105 | TIOC3A, // MTU2_PWM17_PIN |
<> | 149:156823d33999 | 106 | TIOC3C, // MTU2_PWM18_PIN |
<> | 149:156823d33999 | 107 | TIOC2A, // MTU2_PWM19_PIN |
<> | 149:156823d33999 | 108 | TIOC4A, // MTU2_PWM20_PIN |
<> | 149:156823d33999 | 109 | TIOC4C, // MTU2_PWM21_PIN |
<> | 149:156823d33999 | 110 | }; |
<> | 149:156823d33999 | 111 | |
<> | 149:156823d33999 | 112 | static __IO uint16_t *PWM_MATCH[] = { |
<> | 149:156823d33999 | 113 | &PWMPWBFR_2E, // PWM0_PIN |
<> | 149:156823d33999 | 114 | &PWMPWBFR_2C, // PWM1_PIN |
<> | 149:156823d33999 | 115 | &PWMPWBFR_2G, // PWM2_PIN |
<> | 149:156823d33999 | 116 | &PWMPWBFR_2G, // PWM3_PIN |
<> | 149:156823d33999 | 117 | &PWMPWBFR_1G, // PWM4_PIN |
<> | 149:156823d33999 | 118 | &PWMPWBFR_1G, // PWM5_PIN |
<> | 149:156823d33999 | 119 | &PWMPWBFR_1E, // PWM6_PIN |
<> | 149:156823d33999 | 120 | &PWMPWBFR_1C, // PWM7_PIN |
<> | 149:156823d33999 | 121 | &PWMPWBFR_1A, // PWM8_PIN |
<> | 149:156823d33999 | 122 | &PWMPWBFR_2A, // PWM9_PIN |
<> | 149:156823d33999 | 123 | &PWMPWBFR_1E, // PWM10_PIN |
<> | 149:156823d33999 | 124 | &PWMPWBFR_1A, // PWM11_PIN |
<> | 149:156823d33999 | 125 | &PWMPWBFR_1C, // PWM12_PIN |
<> | 149:156823d33999 | 126 | &PWMPWBFR_2E, // PWM13_PIN |
<> | 149:156823d33999 | 127 | }; |
<> | 149:156823d33999 | 128 | |
<> | 149:156823d33999 | 129 | static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { |
<> | 149:156823d33999 | 130 | { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN |
<> | 149:156823d33999 | 131 | { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN |
<> | 149:156823d33999 | 132 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN |
<> | 149:156823d33999 | 133 | { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN |
<> | 149:156823d33999 | 134 | { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN |
<> | 149:156823d33999 | 135 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN |
<> | 149:156823d33999 | 136 | { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN |
<> | 149:156823d33999 | 137 | { &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN |
<> | 149:156823d33999 | 138 | { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN |
<> | 149:156823d33999 | 139 | { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN |
<> | 149:156823d33999 | 140 | { &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN |
<> | 149:156823d33999 | 141 | { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN |
<> | 149:156823d33999 | 142 | { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN |
<> | 149:156823d33999 | 143 | { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN |
<> | 149:156823d33999 | 144 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN |
<> | 149:156823d33999 | 145 | { &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN |
<> | 149:156823d33999 | 146 | { &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN |
<> | 149:156823d33999 | 147 | { &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN |
<> | 149:156823d33999 | 148 | { &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN |
<> | 149:156823d33999 | 149 | { &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN |
<> | 149:156823d33999 | 150 | { &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN |
<> | 149:156823d33999 | 151 | { &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN |
<> | 149:156823d33999 | 152 | }; |
<> | 149:156823d33999 | 153 | |
<> | 149:156823d33999 | 154 | static __IO uint8_t *TCR_MATCH[] = { |
<> | 149:156823d33999 | 155 | &MTU2TCR_0, |
<> | 149:156823d33999 | 156 | &MTU2TCR_1, |
<> | 149:156823d33999 | 157 | &MTU2TCR_2, |
<> | 149:156823d33999 | 158 | &MTU2TCR_3, |
<> | 149:156823d33999 | 159 | &MTU2TCR_4, |
<> | 149:156823d33999 | 160 | }; |
<> | 149:156823d33999 | 161 | |
<> | 149:156823d33999 | 162 | static __IO uint8_t *TIORH_MATCH[] = { |
<> | 149:156823d33999 | 163 | &MTU2TIORH_0, |
<> | 149:156823d33999 | 164 | &MTU2TIOR_1, |
<> | 149:156823d33999 | 165 | &MTU2TIOR_2, |
<> | 149:156823d33999 | 166 | &MTU2TIORH_3, |
<> | 149:156823d33999 | 167 | &MTU2TIORH_4, |
<> | 149:156823d33999 | 168 | }; |
<> | 149:156823d33999 | 169 | |
<> | 149:156823d33999 | 170 | static __IO uint8_t *TIORL_MATCH[] = { |
<> | 149:156823d33999 | 171 | &MTU2TIORL_0, |
<> | 149:156823d33999 | 172 | NULL, |
<> | 149:156823d33999 | 173 | NULL, |
<> | 149:156823d33999 | 174 | &MTU2TIORL_3, |
<> | 149:156823d33999 | 175 | &MTU2TIORL_4, |
<> | 149:156823d33999 | 176 | }; |
<> | 149:156823d33999 | 177 | |
<> | 149:156823d33999 | 178 | static __IO uint16_t *TGRA_MATCH[] = { |
<> | 149:156823d33999 | 179 | &MTU2TGRA_0, |
<> | 149:156823d33999 | 180 | &MTU2TGRA_1, |
<> | 149:156823d33999 | 181 | &MTU2TGRA_2, |
<> | 149:156823d33999 | 182 | &MTU2TGRA_3, |
<> | 149:156823d33999 | 183 | &MTU2TGRA_4, |
<> | 149:156823d33999 | 184 | }; |
<> | 149:156823d33999 | 185 | |
<> | 149:156823d33999 | 186 | static __IO uint16_t *TGRC_MATCH[] = { |
<> | 149:156823d33999 | 187 | &MTU2TGRC_0, |
<> | 149:156823d33999 | 188 | NULL, |
<> | 149:156823d33999 | 189 | NULL, |
<> | 149:156823d33999 | 190 | &MTU2TGRC_3, |
<> | 149:156823d33999 | 191 | &MTU2TGRC_4, |
<> | 149:156823d33999 | 192 | }; |
<> | 149:156823d33999 | 193 | |
<> | 149:156823d33999 | 194 | static __IO uint8_t *TMDR_MATCH[] = { |
<> | 149:156823d33999 | 195 | &MTU2TMDR_0, |
<> | 149:156823d33999 | 196 | &MTU2TMDR_1, |
<> | 149:156823d33999 | 197 | &MTU2TMDR_2, |
<> | 149:156823d33999 | 198 | &MTU2TMDR_3, |
<> | 149:156823d33999 | 199 | &MTU2TMDR_4, |
<> | 149:156823d33999 | 200 | }; |
<> | 149:156823d33999 | 201 | |
<> | 149:156823d33999 | 202 | static int MAX_PERIOD[] = { |
<> | 149:156823d33999 | 203 | 125000, |
<> | 149:156823d33999 | 204 | 503000, |
<> | 149:156823d33999 | 205 | 2000000, |
<> | 149:156823d33999 | 206 | 2000000, |
<> | 149:156823d33999 | 207 | 2000000, |
<> | 149:156823d33999 | 208 | }; |
<> | 149:156823d33999 | 209 | |
<> | 149:156823d33999 | 210 | typedef enum { |
<> | 149:156823d33999 | 211 | MTU2_PULSE = 0, |
<> | 149:156823d33999 | 212 | MTU2_PERIOD |
<> | 149:156823d33999 | 213 | } MTU2Signal; |
<> | 149:156823d33999 | 214 | |
<> | 149:156823d33999 | 215 | static uint16_t init_period_ch1 = 0; |
<> | 149:156823d33999 | 216 | static uint16_t init_period_ch2 = 0; |
<> | 149:156823d33999 | 217 | static uint16_t init_mtu2_period_ch[5] = {0}; |
<> | 149:156823d33999 | 218 | static int32_t period_ch1 = 1; |
<> | 149:156823d33999 | 219 | static int32_t period_ch2 = 1; |
<> | 149:156823d33999 | 220 | static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; |
<> | 149:156823d33999 | 221 | |
<> | 149:156823d33999 | 222 | void pwmout_init(pwmout_t* obj, PinName pin) { |
<> | 149:156823d33999 | 223 | // determine the channel |
<> | 149:156823d33999 | 224 | PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); |
<> | 149:156823d33999 | 225 | MBED_ASSERT(pwm != (PWMName)NC); |
<> | 149:156823d33999 | 226 | |
<> | 149:156823d33999 | 227 | if (pwm >= MTU2_PWM_OFFSET) { |
<> | 149:156823d33999 | 228 | /* PWM by MTU2 */ |
<> | 149:156823d33999 | 229 | int tmp_pwm; |
<> | 149:156823d33999 | 230 | |
<> | 149:156823d33999 | 231 | // power on |
<> | 149:156823d33999 | 232 | CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33); |
<> | 149:156823d33999 | 233 | |
<> | 149:156823d33999 | 234 | obj->pwm = pwm; |
<> | 149:156823d33999 | 235 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
<> | 149:156823d33999 | 236 | if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) { |
<> | 149:156823d33999 | 237 | obj->ch = 4; |
<> | 149:156823d33999 | 238 | MTU2TOER |= 0x36; |
<> | 149:156823d33999 | 239 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) { |
<> | 149:156823d33999 | 240 | obj->ch = 3; |
<> | 149:156823d33999 | 241 | MTU2TOER |= 0x09; |
<> | 149:156823d33999 | 242 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) { |
<> | 149:156823d33999 | 243 | obj->ch = 2; |
<> | 149:156823d33999 | 244 | } else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) { |
<> | 149:156823d33999 | 245 | obj->ch = 1; |
<> | 149:156823d33999 | 246 | } else { |
<> | 149:156823d33999 | 247 | obj->ch = 0; |
<> | 149:156823d33999 | 248 | } |
<> | 149:156823d33999 | 249 | // Wire pinout |
<> | 149:156823d33999 | 250 | pinmap_pinout(pin, PinMap_PWM); |
<> | 149:156823d33999 | 251 | |
<> | 149:156823d33999 | 252 | int bitmask = 1 << (pin & 0xf); |
<> | 149:156823d33999 | 253 | |
<> | 149:156823d33999 | 254 | *PMSR(PINGROUP(pin)) = (bitmask << 16) | 0; |
<> | 149:156823d33999 | 255 | |
<> | 149:156823d33999 | 256 | // default duty 0.0f |
<> | 149:156823d33999 | 257 | pwmout_write(obj, 0); |
<> | 149:156823d33999 | 258 | if (init_mtu2_period_ch[obj->ch] == 0) { |
<> | 149:156823d33999 | 259 | // default period 1ms |
<> | 149:156823d33999 | 260 | pwmout_period_us(obj, 1000); |
<> | 149:156823d33999 | 261 | init_mtu2_period_ch[obj->ch] = 1; |
<> | 149:156823d33999 | 262 | } |
<> | 149:156823d33999 | 263 | } else { |
<> | 149:156823d33999 | 264 | /* PWM */ |
<> | 149:156823d33999 | 265 | // power on |
<> | 149:156823d33999 | 266 | CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); |
<> | 149:156823d33999 | 267 | |
<> | 149:156823d33999 | 268 | obj->pwm = pwm; |
<> | 149:156823d33999 | 269 | if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) { |
<> | 149:156823d33999 | 270 | obj->ch = 2; |
<> | 149:156823d33999 | 271 | PWMPWPR_2_BYTE_L = 0x00; |
<> | 149:156823d33999 | 272 | } else { |
<> | 149:156823d33999 | 273 | obj->ch = 1; |
<> | 149:156823d33999 | 274 | PWMPWPR_1_BYTE_L = 0x00; |
<> | 149:156823d33999 | 275 | } |
<> | 149:156823d33999 | 276 | |
<> | 149:156823d33999 | 277 | // Wire pinout |
<> | 149:156823d33999 | 278 | pinmap_pinout(pin, PinMap_PWM); |
<> | 149:156823d33999 | 279 | |
<> | 149:156823d33999 | 280 | // default to 491us: standard for servos, and fine for e.g. brightness control |
<> | 149:156823d33999 | 281 | pwmout_write(obj, 0); |
<> | 149:156823d33999 | 282 | if ((obj->ch == 2) && (init_period_ch2 == 0)) { |
<> | 149:156823d33999 | 283 | pwmout_period_us(obj, 491); |
<> | 149:156823d33999 | 284 | init_period_ch2 = 1; |
<> | 149:156823d33999 | 285 | } |
<> | 149:156823d33999 | 286 | if ((obj->ch == 1) && (init_period_ch1 == 0)) { |
<> | 149:156823d33999 | 287 | pwmout_period_us(obj, 491); |
<> | 149:156823d33999 | 288 | init_period_ch1 = 1; |
<> | 149:156823d33999 | 289 | } |
<> | 149:156823d33999 | 290 | } |
<> | 149:156823d33999 | 291 | } |
<> | 149:156823d33999 | 292 | |
<> | 149:156823d33999 | 293 | void pwmout_free(pwmout_t* obj) { |
<> | 149:156823d33999 | 294 | pwmout_write(obj, 0); |
<> | 149:156823d33999 | 295 | } |
<> | 149:156823d33999 | 296 | |
<> | 149:156823d33999 | 297 | void pwmout_write(pwmout_t* obj, float value) { |
<> | 149:156823d33999 | 298 | uint32_t wk_cycle; |
<> | 149:156823d33999 | 299 | uint16_t v; |
<> | 149:156823d33999 | 300 | |
<> | 149:156823d33999 | 301 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
<> | 149:156823d33999 | 302 | /* PWM by MTU2 */ |
<> | 149:156823d33999 | 303 | int tmp_pwm; |
<> | 149:156823d33999 | 304 | |
<> | 149:156823d33999 | 305 | if (value < 0.0f) { |
<> | 149:156823d33999 | 306 | value = 0.0f; |
<> | 149:156823d33999 | 307 | } else if (value > 1.0f) { |
<> | 149:156823d33999 | 308 | value = 1.0f; |
<> | 149:156823d33999 | 309 | } else { |
<> | 149:156823d33999 | 310 | // Do Nothing |
<> | 149:156823d33999 | 311 | } |
<> | 149:156823d33999 | 312 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
<> | 149:156823d33999 | 313 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
<> | 149:156823d33999 | 314 | // set channel match to percentage |
<> | 149:156823d33999 | 315 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); |
<> | 149:156823d33999 | 316 | } else { |
<> | 149:156823d33999 | 317 | /* PWM */ |
<> | 149:156823d33999 | 318 | if (value < 0.0f) { |
<> | 149:156823d33999 | 319 | value = 0.0f; |
<> | 149:156823d33999 | 320 | } else if (value > 1.0f) { |
<> | 149:156823d33999 | 321 | value = 1.0f; |
<> | 149:156823d33999 | 322 | } else { |
<> | 149:156823d33999 | 323 | // Do Nothing |
<> | 149:156823d33999 | 324 | } |
<> | 149:156823d33999 | 325 | |
<> | 149:156823d33999 | 326 | if (obj->ch == 2) { |
<> | 149:156823d33999 | 327 | wk_cycle = PWMPWCYR_2 & 0x03ff; |
<> | 149:156823d33999 | 328 | } else { |
<> | 149:156823d33999 | 329 | wk_cycle = PWMPWCYR_1 & 0x03ff; |
<> | 149:156823d33999 | 330 | } |
<> | 149:156823d33999 | 331 | |
<> | 149:156823d33999 | 332 | // set channel match to percentage |
<> | 149:156823d33999 | 333 | v = (uint16_t)((float)wk_cycle * value); |
<> | 149:156823d33999 | 334 | *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); |
<> | 149:156823d33999 | 335 | } |
<> | 149:156823d33999 | 336 | } |
<> | 149:156823d33999 | 337 | |
<> | 149:156823d33999 | 338 | float pwmout_read(pwmout_t* obj) { |
<> | 149:156823d33999 | 339 | uint32_t wk_cycle; |
<> | 149:156823d33999 | 340 | float value; |
<> | 149:156823d33999 | 341 | |
<> | 149:156823d33999 | 342 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
<> | 149:156823d33999 | 343 | /* PWM by MTU2 */ |
<> | 149:156823d33999 | 344 | uint32_t wk_pulse; |
<> | 149:156823d33999 | 345 | int tmp_pwm; |
<> | 149:156823d33999 | 346 | |
<> | 149:156823d33999 | 347 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
<> | 149:156823d33999 | 348 | wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
<> | 149:156823d33999 | 349 | wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; |
<> | 149:156823d33999 | 350 | value = ((float)wk_pulse / (float)wk_cycle); |
<> | 149:156823d33999 | 351 | } else { |
<> | 149:156823d33999 | 352 | /* PWM */ |
<> | 149:156823d33999 | 353 | if (obj->ch == 2) { |
<> | 149:156823d33999 | 354 | wk_cycle = PWMPWCYR_2 & 0x03ff; |
<> | 149:156823d33999 | 355 | } else { |
<> | 149:156823d33999 | 356 | wk_cycle = PWMPWCYR_1 & 0x03ff; |
<> | 149:156823d33999 | 357 | } |
<> | 149:156823d33999 | 358 | value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); |
<> | 149:156823d33999 | 359 | } |
<> | 149:156823d33999 | 360 | |
<> | 149:156823d33999 | 361 | return (value > 1.0f) ? (1.0f) : (value); |
<> | 149:156823d33999 | 362 | } |
<> | 149:156823d33999 | 363 | |
<> | 149:156823d33999 | 364 | void pwmout_period(pwmout_t* obj, float seconds) { |
<> | 149:156823d33999 | 365 | pwmout_period_us(obj, seconds * 1000000.0f); |
<> | 149:156823d33999 | 366 | } |
<> | 149:156823d33999 | 367 | |
<> | 149:156823d33999 | 368 | void pwmout_period_ms(pwmout_t* obj, int ms) { |
<> | 149:156823d33999 | 369 | pwmout_period_us(obj, ms * 1000); |
<> | 149:156823d33999 | 370 | } |
<> | 149:156823d33999 | 371 | |
<> | 149:156823d33999 | 372 | static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ |
<> | 149:156823d33999 | 373 | uint16_t wk_pwmpbfr; |
<> | 149:156823d33999 | 374 | float value; |
<> | 149:156823d33999 | 375 | uint16_t v; |
<> | 149:156823d33999 | 376 | |
<> | 149:156823d33999 | 377 | wk_pwmpbfr = *p_pwmpbfr; |
<> | 149:156823d33999 | 378 | value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle); |
<> | 149:156823d33999 | 379 | v = (uint16_t)((float)new_cycle * value); |
<> | 149:156823d33999 | 380 | *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); |
<> | 149:156823d33999 | 381 | } |
<> | 149:156823d33999 | 382 | |
<> | 149:156823d33999 | 383 | static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ |
<> | 149:156823d33999 | 384 | uint16_t wk_pwmpbfr; |
<> | 149:156823d33999 | 385 | float value; |
<> | 149:156823d33999 | 386 | |
<> | 149:156823d33999 | 387 | wk_pwmpbfr = *p_pwmpbfr; |
<> | 149:156823d33999 | 388 | value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); |
<> | 149:156823d33999 | 389 | *p_pwmpbfr = (uint16_t)((float)new_cycle * value); |
<> | 149:156823d33999 | 390 | } |
<> | 149:156823d33999 | 391 | |
<> | 149:156823d33999 | 392 | // Set the PWM period, keeping the duty cycle the same. |
<> | 149:156823d33999 | 393 | void pwmout_period_us(pwmout_t* obj, int us) { |
<> | 149:156823d33999 | 394 | uint64_t wk_cycle_mtu2; |
<> | 149:156823d33999 | 395 | uint32_t pclk_base; |
<> | 149:156823d33999 | 396 | uint32_t wk_cycle; |
<> | 149:156823d33999 | 397 | uint32_t wk_cks = 0; |
<> | 149:156823d33999 | 398 | uint16_t wk_last_cycle; |
<> | 149:156823d33999 | 399 | int max_us = 0; |
<> | 149:156823d33999 | 400 | |
<> | 149:156823d33999 | 401 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
<> | 149:156823d33999 | 402 | /* PWM by MTU2 */ |
<> | 149:156823d33999 | 403 | int tmp_pwm; |
<> | 149:156823d33999 | 404 | uint8_t tmp_tcr_up; |
<> | 149:156823d33999 | 405 | uint8_t tmp_tstr_sp; |
<> | 149:156823d33999 | 406 | uint8_t tmp_tstr_st; |
<> | 149:156823d33999 | 407 | |
<> | 149:156823d33999 | 408 | max_us = MAX_PERIOD[obj->ch]; |
<> | 149:156823d33999 | 409 | if (us > max_us) { |
<> | 149:156823d33999 | 410 | us = max_us; |
<> | 149:156823d33999 | 411 | } else if (us < 1) { |
<> | 149:156823d33999 | 412 | us = 1; |
<> | 149:156823d33999 | 413 | } else { |
<> | 149:156823d33999 | 414 | // Do Nothing |
<> | 149:156823d33999 | 415 | } |
<> | 149:156823d33999 | 416 | |
<> | 149:156823d33999 | 417 | if (RZ_A1_IsClockMode0() == false) { |
<> | 149:156823d33999 | 418 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK; |
<> | 149:156823d33999 | 419 | } else { |
<> | 149:156823d33999 | 420 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK; |
<> | 149:156823d33999 | 421 | } |
<> | 149:156823d33999 | 422 | |
<> | 149:156823d33999 | 423 | wk_cycle_mtu2 = (uint64_t)pclk_base * us; |
<> | 149:156823d33999 | 424 | while (wk_cycle_mtu2 >= 65535000000) { |
<> | 149:156823d33999 | 425 | if ((obj->ch == 1) && (wk_cks == 3)) { |
<> | 149:156823d33999 | 426 | wk_cks+=2; |
<> | 149:156823d33999 | 427 | } else if ((obj->ch == 2) && (wk_cks == 3)) { |
<> | 149:156823d33999 | 428 | wk_cycle_mtu2 >>= 2; |
<> | 149:156823d33999 | 429 | wk_cks+=3; |
<> | 149:156823d33999 | 430 | } |
<> | 149:156823d33999 | 431 | wk_cycle_mtu2 >>= 2; |
<> | 149:156823d33999 | 432 | wk_cks++; |
<> | 149:156823d33999 | 433 | } |
<> | 149:156823d33999 | 434 | wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); |
<> | 149:156823d33999 | 435 | |
<> | 149:156823d33999 | 436 | tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); |
<> | 149:156823d33999 | 437 | if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { |
<> | 149:156823d33999 | 438 | tmp_tcr_up = 0xC0; |
<> | 149:156823d33999 | 439 | } else { |
<> | 149:156823d33999 | 440 | tmp_tcr_up = 0x40; |
<> | 149:156823d33999 | 441 | } |
<> | 149:156823d33999 | 442 | if ((obj->ch == 4) || (obj->ch == 3)) { |
<> | 149:156823d33999 | 443 | tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3))); |
<> | 149:156823d33999 | 444 | tmp_tstr_st = (1 << (obj->ch + 3)); |
<> | 149:156823d33999 | 445 | } else { |
<> | 149:156823d33999 | 446 | tmp_tstr_sp = ~(0x38 | (1 << obj->ch)); |
<> | 149:156823d33999 | 447 | tmp_tstr_st = (1 << obj->ch); |
<> | 149:156823d33999 | 448 | } |
<> | 149:156823d33999 | 449 | // Counter Stop |
<> | 149:156823d33999 | 450 | MTU2TSTR &= tmp_tstr_sp; |
<> | 149:156823d33999 | 451 | wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; |
<> | 149:156823d33999 | 452 | *TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks; |
<> | 149:156823d33999 | 453 | *TIORH_MATCH[obj->ch] = 0x21; |
<> | 149:156823d33999 | 454 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { |
<> | 149:156823d33999 | 455 | *TIORL_MATCH[obj->ch] = 0x21; |
<> | 149:156823d33999 | 456 | } |
<> | 149:156823d33999 | 457 | *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period |
<> | 149:156823d33999 | 458 | |
<> | 149:156823d33999 | 459 | // Set duty again(TGRA) |
<> | 149:156823d33999 | 460 | set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 461 | if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) { |
<> | 149:156823d33999 | 462 | // Set duty again(TGRC) |
<> | 149:156823d33999 | 463 | set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 464 | } |
<> | 149:156823d33999 | 465 | *TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1 |
<> | 149:156823d33999 | 466 | |
<> | 149:156823d33999 | 467 | // Counter Start |
<> | 149:156823d33999 | 468 | MTU2TSTR |= tmp_tstr_st; |
<> | 149:156823d33999 | 469 | // Save for future use |
<> | 149:156823d33999 | 470 | mtu2_period_ch[obj->ch] = us; |
<> | 149:156823d33999 | 471 | } else { |
<> | 149:156823d33999 | 472 | /* PWM */ |
<> | 149:156823d33999 | 473 | if (us > 491) { |
<> | 149:156823d33999 | 474 | us = 491; |
<> | 149:156823d33999 | 475 | } else if (us < 1) { |
<> | 149:156823d33999 | 476 | us = 1; |
<> | 149:156823d33999 | 477 | } else { |
<> | 149:156823d33999 | 478 | // Do Nothing |
<> | 149:156823d33999 | 479 | } |
<> | 149:156823d33999 | 480 | |
<> | 149:156823d33999 | 481 | if (RZ_A1_IsClockMode0() == false) { |
<> | 149:156823d33999 | 482 | pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000; |
<> | 149:156823d33999 | 483 | } else { |
<> | 149:156823d33999 | 484 | pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000; |
<> | 149:156823d33999 | 485 | } |
<> | 149:156823d33999 | 486 | |
<> | 149:156823d33999 | 487 | wk_cycle = pclk_base * us; |
<> | 149:156823d33999 | 488 | while (wk_cycle >= 102350) { |
<> | 149:156823d33999 | 489 | wk_cycle >>= 1; |
<> | 149:156823d33999 | 490 | wk_cks++; |
<> | 149:156823d33999 | 491 | } |
<> | 149:156823d33999 | 492 | wk_cycle = (wk_cycle + 50) / 100; |
<> | 149:156823d33999 | 493 | |
<> | 149:156823d33999 | 494 | if (obj->ch == 2) { |
<> | 149:156823d33999 | 495 | wk_last_cycle = PWMPWCYR_2 & 0x03ff; |
<> | 149:156823d33999 | 496 | PWMPWCR_2_BYTE_L = 0xc0 | wk_cks; |
<> | 149:156823d33999 | 497 | PWMPWCYR_2 = (uint16_t)wk_cycle; |
<> | 149:156823d33999 | 498 | |
<> | 149:156823d33999 | 499 | // Set duty again |
<> | 149:156823d33999 | 500 | set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 501 | set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 502 | set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 503 | set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 504 | |
<> | 149:156823d33999 | 505 | // Counter Start |
<> | 149:156823d33999 | 506 | PWMPWCR_2_BYTE_L |= 0x08; |
<> | 149:156823d33999 | 507 | |
<> | 149:156823d33999 | 508 | // Save for future use |
<> | 149:156823d33999 | 509 | period_ch2 = us; |
<> | 149:156823d33999 | 510 | } else { |
<> | 149:156823d33999 | 511 | wk_last_cycle = PWMPWCYR_1 & 0x03ff; |
<> | 149:156823d33999 | 512 | PWMPWCR_1_BYTE_L = 0xc0 | wk_cks; |
<> | 149:156823d33999 | 513 | PWMPWCYR_1 = (uint16_t)wk_cycle; |
<> | 149:156823d33999 | 514 | |
<> | 149:156823d33999 | 515 | // Set duty again |
<> | 149:156823d33999 | 516 | set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 517 | set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 518 | set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 519 | set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle); |
<> | 149:156823d33999 | 520 | |
<> | 149:156823d33999 | 521 | // Counter Start |
<> | 149:156823d33999 | 522 | PWMPWCR_1_BYTE_L |= 0x08; |
<> | 149:156823d33999 | 523 | |
<> | 149:156823d33999 | 524 | // Save for future use |
<> | 149:156823d33999 | 525 | period_ch1 = us; |
<> | 149:156823d33999 | 526 | } |
<> | 149:156823d33999 | 527 | } |
<> | 149:156823d33999 | 528 | } |
<> | 149:156823d33999 | 529 | |
<> | 149:156823d33999 | 530 | void pwmout_pulsewidth(pwmout_t* obj, float seconds) { |
<> | 149:156823d33999 | 531 | pwmout_pulsewidth_us(obj, seconds * 1000000.0f); |
<> | 149:156823d33999 | 532 | } |
<> | 149:156823d33999 | 533 | |
<> | 149:156823d33999 | 534 | void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { |
<> | 149:156823d33999 | 535 | pwmout_pulsewidth_us(obj, ms * 1000); |
<> | 149:156823d33999 | 536 | } |
<> | 149:156823d33999 | 537 | |
<> | 149:156823d33999 | 538 | void pwmout_pulsewidth_us(pwmout_t* obj, int us) { |
<> | 149:156823d33999 | 539 | float value = 0; |
<> | 149:156823d33999 | 540 | |
<> | 149:156823d33999 | 541 | if (obj->pwm >= MTU2_PWM_OFFSET) { |
<> | 149:156823d33999 | 542 | /* PWM by MTU2 */ |
<> | 149:156823d33999 | 543 | if (mtu2_period_ch[obj->ch] != 0) { |
<> | 149:156823d33999 | 544 | value = (float)us / (float)mtu2_period_ch[obj->ch]; |
<> | 149:156823d33999 | 545 | } |
<> | 149:156823d33999 | 546 | } else { |
<> | 149:156823d33999 | 547 | /* PWM */ |
<> | 149:156823d33999 | 548 | if (obj->ch == 2) { |
<> | 149:156823d33999 | 549 | if (period_ch2 != 0) { |
<> | 149:156823d33999 | 550 | value = (float)us / (float)period_ch2; |
<> | 149:156823d33999 | 551 | } |
<> | 149:156823d33999 | 552 | } else { |
<> | 149:156823d33999 | 553 | if (period_ch1 != 0) { |
<> | 149:156823d33999 | 554 | value = (float)us / (float)period_ch1; |
<> | 149:156823d33999 | 555 | } |
<> | 149:156823d33999 | 556 | } |
<> | 149:156823d33999 | 557 | } |
<> | 149:156823d33999 | 558 | pwmout_write(obj, value); |
<> | 149:156823d33999 | 559 | } |