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targets/TARGET_ONSEMI/TARGET_NCS36510/spi_ipc7207_map.h@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file spi_ipc7207_map.h |
<> | 144:ef7eb2e8f9f7 | 4 | * @brief SPI IPC 7207 HW register map |
<> | 144:ef7eb2e8f9f7 | 5 | * @internal |
<> | 144:ef7eb2e8f9f7 | 6 | * @author ON Semiconductor |
<> | 144:ef7eb2e8f9f7 | 7 | * $Rev: 2110 $ |
<> | 144:ef7eb2e8f9f7 | 8 | * $Date: 2013-07-16 20:13:03 +0530 (Tue, 16 Jul 2013) $ |
<> | 144:ef7eb2e8f9f7 | 9 | ****************************************************************************** |
<> | 147:30b64687e01f | 10 | * Copyright 2016 Semiconductor Components Industries LLC (d/b/a ON Semiconductor). |
<> | 147:30b64687e01f | 11 | * All rights reserved. This software and/or documentation is licensed by ON Semiconductor |
<> | 147:30b64687e01f | 12 | * under limited terms and conditions. The terms and conditions pertaining to the software |
<> | 147:30b64687e01f | 13 | * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf |
<> | 147:30b64687e01f | 14 | * (ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software) and |
<> | 147:30b64687e01f | 15 | * if applicable the software license agreement. Do not use this software and/or |
<> | 147:30b64687e01f | 16 | * documentation unless you have carefully read and you agree to the limited terms and |
<> | 147:30b64687e01f | 17 | * conditions. By using this software and/or documentation, you agree to the limited |
<> | 147:30b64687e01f | 18 | * terms and conditions. |
<> | 144:ef7eb2e8f9f7 | 19 | * |
<> | 144:ef7eb2e8f9f7 | 20 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
<> | 144:ef7eb2e8f9f7 | 21 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 23 | * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, |
<> | 144:ef7eb2e8f9f7 | 24 | * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
<> | 144:ef7eb2e8f9f7 | 25 | * @endinternal |
<> | 144:ef7eb2e8f9f7 | 26 | * |
<> | 144:ef7eb2e8f9f7 | 27 | * @ingroup spi_ipc7207 |
<> | 144:ef7eb2e8f9f7 | 28 | * |
<> | 144:ef7eb2e8f9f7 | 29 | * @details |
<> | 144:ef7eb2e8f9f7 | 30 | * <p> |
<> | 144:ef7eb2e8f9f7 | 31 | * SPI HW register map description |
<> | 144:ef7eb2e8f9f7 | 32 | * </p> |
<> | 144:ef7eb2e8f9f7 | 33 | * |
<> | 144:ef7eb2e8f9f7 | 34 | * <h1> Reference document(s) </h1> |
<> | 144:ef7eb2e8f9f7 | 35 | * <p> |
<> | 144:ef7eb2e8f9f7 | 36 | * <a href="../pdf/IPC7207_SPI_APB_DS_v1P2.pdf" target="_blank"> |
<> | 144:ef7eb2e8f9f7 | 37 | * IPC7207 APB SPI Design Specification v1.2 </a> |
<> | 144:ef7eb2e8f9f7 | 38 | * </p> |
<> | 144:ef7eb2e8f9f7 | 39 | */ |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | #ifndef SPI_IPC7207_MAP_H_ |
<> | 144:ef7eb2e8f9f7 | 42 | #define SPI_IPC7207_MAP_H_ |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | #include "architecture.h" |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /** SPI HW Structure Overlay */ |
<> | 144:ef7eb2e8f9f7 | 47 | typedef struct { |
<> | 144:ef7eb2e8f9f7 | 48 | __O uint32_t TX_DATA; |
<> | 144:ef7eb2e8f9f7 | 49 | __I uint32_t RX_DATA; |
<> | 144:ef7eb2e8f9f7 | 50 | __IO uint32_t FDIV; |
<> | 144:ef7eb2e8f9f7 | 51 | union { |
<> | 144:ef7eb2e8f9f7 | 52 | struct { |
<> | 144:ef7eb2e8f9f7 | 53 | __IO uint32_t ENABLE :1; /**< SPI port enable: 0 = disable , 1 = enable */ |
<> | 144:ef7eb2e8f9f7 | 54 | __IO uint32_t SAMPLING_EDGE :1; /**< SDI sampling edge: 0 = opposite to SDO edge / 1 = same as SDO edge */ |
<> | 144:ef7eb2e8f9f7 | 55 | __IO uint32_t ENDIAN :1; /**< Bits endianness: 0 = LSB first (little-endian) / 1 = MSB first (big-endian) */ |
<> | 144:ef7eb2e8f9f7 | 56 | __IO uint32_t CPHA :1; /**< Clock phase: 0 = SDO set before first SCLK edge / 1 = SDO set after first SCLK edge */ |
<> | 144:ef7eb2e8f9f7 | 57 | __IO uint32_t CPOL :1; /**< Clock polarity: 0 = active high / 1 = active low */ |
<> | 144:ef7eb2e8f9f7 | 58 | __IO uint32_t MODE :1; /**< Device mode: 0 = slave mode / 1 = master mode */ |
<> | 144:ef7eb2e8f9f7 | 59 | __IO uint32_t WORD_WIDTH :2; /**< Word width: 0 = 8b / 1 = 16b / 2 = 32b / 3 = reserved */ |
<> | 144:ef7eb2e8f9f7 | 60 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 61 | __IO uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 62 | } CONTROL; |
<> | 144:ef7eb2e8f9f7 | 63 | union { |
<> | 144:ef7eb2e8f9f7 | 64 | struct { |
<> | 144:ef7eb2e8f9f7 | 65 | __I uint32_t XFER_IP :1; /**< Transfer in progress: 0 = No transfer in progress / 1 = transfer in progress */ |
<> | 144:ef7eb2e8f9f7 | 66 | __I uint32_t XFER_ERROR :1;/**< Transfer error: 0 = no error / 1 = SPI Overflow or Underflow */ |
<> | 144:ef7eb2e8f9f7 | 67 | __I uint32_t TX_EMPTY :1; /**< Transmit FIFO/buffer empty flag: 0 = not empty / 1 = empty */ |
<> | 144:ef7eb2e8f9f7 | 68 | __I uint32_t TX_HALF :1; /**< Transmit FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */ |
<> | 144:ef7eb2e8f9f7 | 69 | __I uint32_t TX_FULL :1; /**< Transmit FIFO/buffer full flag: 0 = not full / 1 = full */ |
<> | 144:ef7eb2e8f9f7 | 70 | __I uint32_t RX_EMPTY :1; /**< Receive FIFO/buffer empty flag: 0 = not empty / 1 = empty */ |
<> | 144:ef7eb2e8f9f7 | 71 | __I uint32_t RX_HALF :1; /**< Receive FIFO/buffer "half full" flag: 0 = (< half full) / 1 = (>= half full) */ |
<> | 144:ef7eb2e8f9f7 | 72 | __I uint32_t RX_FULL :1; /**< Receive FIFO/buffer full flag: 0 = not full / 1 = full */ |
<> | 144:ef7eb2e8f9f7 | 73 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 74 | __I uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 75 | } STATUS; |
<> | 144:ef7eb2e8f9f7 | 76 | union { |
<> | 144:ef7eb2e8f9f7 | 77 | struct { |
<> | 144:ef7eb2e8f9f7 | 78 | __IO uint32_t SS_ENABLE :4; /**< Slave Select (x4): 0 = disable / 1 = enable */ |
<> | 144:ef7eb2e8f9f7 | 79 | __IO uint32_t SS_BURST :1; /**< Slave Select burst mode (maintain SS active if TXFIFO not empty) */ |
<> | 144:ef7eb2e8f9f7 | 80 | } BITS; |
<> | 144:ef7eb2e8f9f7 | 81 | __IO uint32_t WORD; |
<> | 144:ef7eb2e8f9f7 | 82 | } SLAVE_SELECT; |
<> | 144:ef7eb2e8f9f7 | 83 | __IO uint32_t SLAVE_SELECT_POLARITY; /**< Slave Select polarity for up to 4 slaves:0 = active low / 1 = active high */ |
<> | 144:ef7eb2e8f9f7 | 84 | __IO uint32_t IRQ_ENABLE; /**< IRQ (x8) enable: 0 = disable / 1 = enable */ |
<> | 144:ef7eb2e8f9f7 | 85 | __I uint32_t IRQ_STATUS; /**< IRQ (x8) status: 0 = no IRQ occurred / 1 = IRQ occurred */ |
<> | 144:ef7eb2e8f9f7 | 86 | __O uint32_t IRQ_CLEAR; /**< IRQ (x8) clearing: write 1 to clear IRQ */ |
<> | 144:ef7eb2e8f9f7 | 87 | __IO uint32_t TX_WATERMARK; /**< Transmit FIFO Watermark: Defines level of RX Half Full Flag */ |
<> | 144:ef7eb2e8f9f7 | 88 | __IO uint32_t RX_WATERMARK; /**< Receive FIFO Watermark: Defines level of TX Half Full Flag */ |
<> | 144:ef7eb2e8f9f7 | 89 | __I uint32_t TX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of TX FIFO. */ |
<> | 144:ef7eb2e8f9f7 | 90 | __I uint32_t RX_FIFO_LEVEL; /**< Transmit FIFO Level: Indicates actual fill level of RX FIFO. */ |
<> | 144:ef7eb2e8f9f7 | 91 | } SpiIpc7207Reg_t, *SpiIpc7207Reg_pt; |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | #endif /* SPI_IPC7207_MAP_H_ */ |