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targets/TARGET_NXP/TARGET_LPC15XX/can_api.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 156:95d6b41a828b
- Child:
- 167:e84263d55307
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | |
<> | 144:ef7eb2e8f9f7 | 17 | #include "can_api.h" |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | #include <math.h> |
<> | 144:ef7eb2e8f9f7 | 23 | #include <string.h> |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | /* Handy defines */ |
<> | 156:95d6b41a828b | 26 | #define RX_MSG_OBJ_COUNT 31 |
<> | 156:95d6b41a828b | 27 | #define TX_MSG_OBJ_COUNT 1 |
<> | 144:ef7eb2e8f9f7 | 28 | #define DLC_MAX 8 |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | #define ID_STD_MASK 0x07FF |
<> | 144:ef7eb2e8f9f7 | 31 | #define ID_EXT_MASK 0x1FFFFFFF |
<> | 144:ef7eb2e8f9f7 | 32 | #define DLC_MASK 0x0F |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #define CANIFn_ARB2_DIR (1UL << 13) |
<> | 144:ef7eb2e8f9f7 | 35 | #define CANIFn_ARB2_XTD (1UL << 14) |
<> | 144:ef7eb2e8f9f7 | 36 | #define CANIFn_ARB2_MSGVAL (1UL << 15) |
<> | 144:ef7eb2e8f9f7 | 37 | #define CANIFn_MSK2_MXTD (1UL << 15) |
<> | 144:ef7eb2e8f9f7 | 38 | #define CANIFn_MSK2_MDIR (1UL << 14) |
<> | 144:ef7eb2e8f9f7 | 39 | #define CANIFn_MCTRL_EOB (1UL << 7) |
<> | 144:ef7eb2e8f9f7 | 40 | #define CANIFn_MCTRL_TXRQST (1UL << 8) |
<> | 144:ef7eb2e8f9f7 | 41 | #define CANIFn_MCTRL_RMTEN (1UL << 9) |
<> | 144:ef7eb2e8f9f7 | 42 | #define CANIFn_MCTRL_RXIE (1UL << 10) |
<> | 144:ef7eb2e8f9f7 | 43 | #define CANIFn_MCTRL_TXIE (1UL << 11) |
<> | 144:ef7eb2e8f9f7 | 44 | #define CANIFn_MCTRL_UMASK (1UL << 12) |
<> | 144:ef7eb2e8f9f7 | 45 | #define CANIFn_MCTRL_INTPND (1UL << 13) |
<> | 144:ef7eb2e8f9f7 | 46 | #define CANIFn_MCTRL_MSGLST (1UL << 14) |
<> | 144:ef7eb2e8f9f7 | 47 | #define CANIFn_MCTRL_NEWDAT (1UL << 15) |
<> | 144:ef7eb2e8f9f7 | 48 | #define CANIFn_CMDMSK_DATA_B (1UL << 0) |
<> | 144:ef7eb2e8f9f7 | 49 | #define CANIFn_CMDMSK_DATA_A (1UL << 1) |
<> | 144:ef7eb2e8f9f7 | 50 | #define CANIFn_CMDMSK_TXRQST (1UL << 2) |
<> | 144:ef7eb2e8f9f7 | 51 | #define CANIFn_CMDMSK_NEWDAT (1UL << 2) |
<> | 144:ef7eb2e8f9f7 | 52 | #define CANIFn_CMDMSK_CLRINTPND (1UL << 3) |
<> | 144:ef7eb2e8f9f7 | 53 | #define CANIFn_CMDMSK_CTRL (1UL << 4) |
<> | 144:ef7eb2e8f9f7 | 54 | #define CANIFn_CMDMSK_ARB (1UL << 5) |
<> | 144:ef7eb2e8f9f7 | 55 | #define CANIFn_CMDMSK_MASK (1UL << 6) |
<> | 144:ef7eb2e8f9f7 | 56 | #define CANIFn_CMDMSK_WR (1UL << 7) |
<> | 144:ef7eb2e8f9f7 | 57 | #define CANIFn_CMDMSK_RD (0UL << 7) |
<> | 144:ef7eb2e8f9f7 | 58 | #define CANIFn_CMDREQ_BUSY (1UL << 15) |
<> | 144:ef7eb2e8f9f7 | 59 | |
<> | 156:95d6b41a828b | 60 | #define CANSTAT_TXOK (1 << 3) // Transmitted a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller. |
<> | 156:95d6b41a828b | 61 | #define CANSTAT_RXOK (1 << 4) // Received a message successfully This bit must be reset by the CPU. It is never reset by the CAN controller. |
<> | 156:95d6b41a828b | 62 | #define CANSTAT_EPASS (1 << 5) // Error passive |
<> | 156:95d6b41a828b | 63 | #define CANSTAT_EWARN (1 << 6) // Warning status |
<> | 156:95d6b41a828b | 64 | #define CANSTAT_BOFF (1 << 7) // Busoff status |
<> | 156:95d6b41a828b | 65 | |
<> | 144:ef7eb2e8f9f7 | 66 | #define CANCNTL_INIT (1 << 0) // Initialization |
<> | 144:ef7eb2e8f9f7 | 67 | #define CANCNTL_IE (1 << 1) // Module interrupt enable |
<> | 144:ef7eb2e8f9f7 | 68 | #define CANCNTL_SIE (1 << 2) // Status change interrupt enable |
<> | 144:ef7eb2e8f9f7 | 69 | #define CANCNTL_EIE (1 << 3) // Error interrupt enable |
<> | 144:ef7eb2e8f9f7 | 70 | #define CANCNTL_DAR (1 << 5) // Disable automatic retransmission |
<> | 144:ef7eb2e8f9f7 | 71 | #define CANCNTL_CCE (1 << 6) // Configuration change enable |
<> | 144:ef7eb2e8f9f7 | 72 | #define CANCNTL_TEST (1 << 7) // Test mode enable |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | #define CANTEST_BASIC (1 << 2) // Basic mode |
<> | 144:ef7eb2e8f9f7 | 75 | #define CANTEST_SILENT (1 << 3) // Silent mode |
<> | 144:ef7eb2e8f9f7 | 76 | #define CANTEST_LBACK (1 << 4) // Loop back mode |
<> | 144:ef7eb2e8f9f7 | 77 | #define CANTEST_TX_MASK 0x0060 // Control of CAN_TXD pins |
<> | 144:ef7eb2e8f9f7 | 78 | #define CANTEST_TX_SHIFT 5 |
<> | 144:ef7eb2e8f9f7 | 79 | #define CANTEST_RX (1 << 7) // Monitors the actual value of the CAN_RXD pin. |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | static uint32_t can_irq_id = 0; |
<> | 144:ef7eb2e8f9f7 | 82 | static can_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 156:95d6b41a828b | 84 | #define IRQ_ENABLE_TX (1 << 0) |
<> | 156:95d6b41a828b | 85 | #define IRQ_ENABLE_RX (1 << 1) |
<> | 156:95d6b41a828b | 86 | #define IRQ_ENABLE_EW (1 << 2) |
<> | 156:95d6b41a828b | 87 | #define IRQ_ENABLE_EP (1 << 3) |
<> | 156:95d6b41a828b | 88 | #define IRQ_ENABLE_BE (1 << 4) |
<> | 156:95d6b41a828b | 89 | #define IRQ_ENABLE_STATUS (IRQ_ENABLE_TX | IRQ_ENABLE_RX) |
<> | 156:95d6b41a828b | 90 | #define IRQ_ENABLE_ERROR (IRQ_ENABLE_EW | IRQ_ENABLE_EP | IRQ_ENABLE_BE) |
<> | 156:95d6b41a828b | 91 | #define IRQ_ENABLE_ANY (IRQ_ENABLE_STATUS | IRQ_ENABLE_ERROR) |
<> | 156:95d6b41a828b | 92 | static uint32_t enabled_irqs = 0; |
<> | 156:95d6b41a828b | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | static inline void can_disable(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 95 | LPC_C_CAN0->CANCNTL |= 0x1; |
<> | 144:ef7eb2e8f9f7 | 96 | } |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | static inline void can_enable(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 99 | if (LPC_C_CAN0->CANCNTL & 0x1) { |
<> | 144:ef7eb2e8f9f7 | 100 | LPC_C_CAN0->CANCNTL &= ~(0x1); |
<> | 144:ef7eb2e8f9f7 | 101 | } |
<> | 144:ef7eb2e8f9f7 | 102 | } |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | int can_mode(can_t *obj, CanMode mode) { |
<> | 144:ef7eb2e8f9f7 | 105 | int success = 0; |
<> | 144:ef7eb2e8f9f7 | 106 | switch (mode) { |
<> | 144:ef7eb2e8f9f7 | 107 | case MODE_RESET: |
<> | 144:ef7eb2e8f9f7 | 108 | LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST; |
<> | 144:ef7eb2e8f9f7 | 109 | can_disable(obj); |
<> | 144:ef7eb2e8f9f7 | 110 | success = 1; |
<> | 144:ef7eb2e8f9f7 | 111 | break; |
<> | 144:ef7eb2e8f9f7 | 112 | case MODE_NORMAL: |
<> | 144:ef7eb2e8f9f7 | 113 | LPC_C_CAN0->CANCNTL &=~CANCNTL_TEST; |
<> | 144:ef7eb2e8f9f7 | 114 | can_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 115 | success = 1; |
<> | 144:ef7eb2e8f9f7 | 116 | break; |
<> | 144:ef7eb2e8f9f7 | 117 | case MODE_SILENT: |
<> | 144:ef7eb2e8f9f7 | 118 | LPC_C_CAN0->CANCNTL |= CANCNTL_TEST; |
<> | 144:ef7eb2e8f9f7 | 119 | LPC_C_CAN0->CANTEST |= CANTEST_SILENT; |
<> | 144:ef7eb2e8f9f7 | 120 | LPC_C_CAN0->CANTEST &=~ CANTEST_LBACK; |
<> | 144:ef7eb2e8f9f7 | 121 | success = 1; |
<> | 144:ef7eb2e8f9f7 | 122 | break; |
<> | 144:ef7eb2e8f9f7 | 123 | case MODE_TEST_LOCAL: |
<> | 144:ef7eb2e8f9f7 | 124 | LPC_C_CAN0->CANCNTL |= CANCNTL_TEST; |
<> | 144:ef7eb2e8f9f7 | 125 | LPC_C_CAN0->CANTEST &=~CANTEST_SILENT; |
<> | 144:ef7eb2e8f9f7 | 126 | LPC_C_CAN0->CANTEST |= CANTEST_LBACK; |
<> | 144:ef7eb2e8f9f7 | 127 | success = 1; |
<> | 144:ef7eb2e8f9f7 | 128 | break; |
<> | 144:ef7eb2e8f9f7 | 129 | case MODE_TEST_SILENT: |
<> | 144:ef7eb2e8f9f7 | 130 | LPC_C_CAN0->CANCNTL |= CANCNTL_TEST; |
<> | 144:ef7eb2e8f9f7 | 131 | LPC_C_CAN0->CANTEST |= (CANTEST_LBACK | CANTEST_SILENT); |
<> | 144:ef7eb2e8f9f7 | 132 | success = 1; |
<> | 144:ef7eb2e8f9f7 | 133 | break; |
<> | 144:ef7eb2e8f9f7 | 134 | case MODE_TEST_GLOBAL: |
<> | 144:ef7eb2e8f9f7 | 135 | default: |
<> | 144:ef7eb2e8f9f7 | 136 | success = 0; |
<> | 144:ef7eb2e8f9f7 | 137 | break; |
<> | 144:ef7eb2e8f9f7 | 138 | } |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | return success; |
<> | 144:ef7eb2e8f9f7 | 141 | } |
<> | 144:ef7eb2e8f9f7 | 142 | |
<> | 144:ef7eb2e8f9f7 | 143 | int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { |
<> | 144:ef7eb2e8f9f7 | 144 | uint16_t i; |
<> | 144:ef7eb2e8f9f7 | 145 | |
<> | 144:ef7eb2e8f9f7 | 146 | // Find first free message object |
<> | 144:ef7eb2e8f9f7 | 147 | if (handle == 0) { |
<> | 144:ef7eb2e8f9f7 | 148 | uint32_t msgval = LPC_C_CAN0->CANMSGV1 | (LPC_C_CAN0->CANMSGV2 << 16); |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | // Find first free messagebox |
<> | 144:ef7eb2e8f9f7 | 151 | for (i = 0; i < 32; i++) { |
<> | 144:ef7eb2e8f9f7 | 152 | if ((msgval & (1 << i)) == 0) { |
<> | 144:ef7eb2e8f9f7 | 153 | handle = i+1; |
<> | 144:ef7eb2e8f9f7 | 154 | break; |
<> | 144:ef7eb2e8f9f7 | 155 | } |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | } |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 156:95d6b41a828b | 159 | if (handle > 0 && handle <= 32) { |
<> | 144:ef7eb2e8f9f7 | 160 | if (format == CANExtended) { |
<> | 144:ef7eb2e8f9f7 | 161 | // Mark message valid, Direction = TX, Extended Frame, Set Identifier and mask everything |
<> | 144:ef7eb2e8f9f7 | 162 | LPC_C_CAN0->CANIF1_ARB1 = (id & 0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 163 | LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | ((id >> 16) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 164 | LPC_C_CAN0->CANIF1_MSK1 = (mask & 0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 165 | LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD /*| CANIFn_MSK2_MDIR*/ | ((mask >> 16) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 166 | } else { |
<> | 144:ef7eb2e8f9f7 | 167 | // Mark message valid, Direction = TX, Set Identifier and mask everything |
<> | 144:ef7eb2e8f9f7 | 168 | LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | ((id << 2) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 169 | LPC_C_CAN0->CANIF1_MSK2 = /*CANIFn_MSK2_MDIR |*/ ((mask << 2) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | // Use mask, single message object and set DLC |
<> | 156:95d6b41a828b | 173 | LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_EOB | (DLC_MAX & 0xF); |
<> | 144:ef7eb2e8f9f7 | 174 | |
<> | 144:ef7eb2e8f9f7 | 175 | // Transfer all fields to message object |
<> | 144:ef7eb2e8f9f7 | 176 | LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL; |
<> | 144:ef7eb2e8f9f7 | 177 | |
<> | 144:ef7eb2e8f9f7 | 178 | // Start Transfer to given message number |
<> | 144:ef7eb2e8f9f7 | 179 | LPC_C_CAN0->CANIF1_CMDREQ = (handle & 0x3F); |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | // Wait until transfer to message ram complete - TODO: maybe not block?? |
<> | 144:ef7eb2e8f9f7 | 182 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 183 | } |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | return handle; |
<> | 144:ef7eb2e8f9f7 | 186 | } |
<> | 144:ef7eb2e8f9f7 | 187 | |
<> | 144:ef7eb2e8f9f7 | 188 | static inline void can_irq() { |
<> | 156:95d6b41a828b | 189 | uint32_t intid = LPC_C_CAN0->CANINT & 0xFFFF; |
<> | 156:95d6b41a828b | 190 | |
<> | 156:95d6b41a828b | 191 | if (intid == 0x8000) { |
<> | 156:95d6b41a828b | 192 | uint32_t status = LPC_C_CAN0->CANSTAT; |
<> | 156:95d6b41a828b | 193 | // Note that since it's impossible to tell which specific status caused |
<> | 156:95d6b41a828b | 194 | // the interrupt to fire, this just fires them all. |
<> | 156:95d6b41a828b | 195 | // In particular, EWARN is not mutually exclusive with the others and |
<> | 156:95d6b41a828b | 196 | // may fire multiple times with other status transitions, including |
<> | 156:95d6b41a828b | 197 | // transmit and receive completion (if enabled). Ignoring EWARN with a |
<> | 156:95d6b41a828b | 198 | // priority system (i.e. blocking EWARN interrupts if EPASS or BOFF is |
<> | 156:95d6b41a828b | 199 | // set) may discard some EWARN interrupts. |
<> | 156:95d6b41a828b | 200 | if (status & CANSTAT_BOFF) { |
<> | 156:95d6b41a828b | 201 | if (enabled_irqs & IRQ_ENABLE_BE) { |
<> | 156:95d6b41a828b | 202 | irq_handler(can_irq_id, IRQ_BUS); |
<> | 156:95d6b41a828b | 203 | } |
<> | 156:95d6b41a828b | 204 | } |
<> | 156:95d6b41a828b | 205 | if (status & CANSTAT_EPASS) { |
<> | 156:95d6b41a828b | 206 | if (enabled_irqs & IRQ_ENABLE_EP) { |
<> | 156:95d6b41a828b | 207 | irq_handler(can_irq_id, IRQ_PASSIVE); |
<> | 156:95d6b41a828b | 208 | } |
<> | 156:95d6b41a828b | 209 | } |
<> | 156:95d6b41a828b | 210 | if (status & CANSTAT_EWARN) { |
<> | 156:95d6b41a828b | 211 | if (enabled_irqs & IRQ_ENABLE_EW) { |
<> | 156:95d6b41a828b | 212 | irq_handler(can_irq_id, IRQ_ERROR); |
<> | 156:95d6b41a828b | 213 | } |
<> | 156:95d6b41a828b | 214 | } |
<> | 156:95d6b41a828b | 215 | if ((status & CANSTAT_RXOK) != 0) { |
<> | 156:95d6b41a828b | 216 | LPC_C_CAN0->CANSTAT &= ~CANSTAT_RXOK; |
<> | 156:95d6b41a828b | 217 | irq_handler(can_irq_id, IRQ_RX); |
<> | 156:95d6b41a828b | 218 | } |
<> | 156:95d6b41a828b | 219 | if ((status & CANSTAT_TXOK) != 0) { |
<> | 156:95d6b41a828b | 220 | LPC_C_CAN0->CANSTAT &= ~CANSTAT_TXOK; |
<> | 156:95d6b41a828b | 221 | irq_handler(can_irq_id, IRQ_TX); |
<> | 156:95d6b41a828b | 222 | } |
<> | 156:95d6b41a828b | 223 | } |
<> | 144:ef7eb2e8f9f7 | 224 | } |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | // Register CAN object's irq handler |
<> | 144:ef7eb2e8f9f7 | 227 | void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) { |
<> | 144:ef7eb2e8f9f7 | 228 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 229 | can_irq_id = id; |
<> | 144:ef7eb2e8f9f7 | 230 | } |
<> | 144:ef7eb2e8f9f7 | 231 | |
<> | 144:ef7eb2e8f9f7 | 232 | // Unregister CAN object's irq handler |
<> | 144:ef7eb2e8f9f7 | 233 | void can_irq_free(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 234 | LPC_C_CAN0->CANCNTL &= ~(1UL << 1); // Disable Interrupts :) |
<> | 144:ef7eb2e8f9f7 | 235 | can_irq_id = 0; |
<> | 144:ef7eb2e8f9f7 | 236 | NVIC_DisableIRQ(C_CAN0_IRQn); |
<> | 144:ef7eb2e8f9f7 | 237 | } |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | // Clear or set a irq |
<> | 144:ef7eb2e8f9f7 | 240 | void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) { |
<> | 156:95d6b41a828b | 241 | uint32_t mask_enable; |
<> | 156:95d6b41a828b | 242 | switch (type) { |
<> | 156:95d6b41a828b | 243 | case IRQ_RX: |
<> | 156:95d6b41a828b | 244 | mask_enable = IRQ_ENABLE_RX; |
<> | 156:95d6b41a828b | 245 | break; |
<> | 156:95d6b41a828b | 246 | case IRQ_TX: |
<> | 156:95d6b41a828b | 247 | mask_enable = IRQ_ENABLE_TX; |
<> | 156:95d6b41a828b | 248 | break; |
<> | 156:95d6b41a828b | 249 | case IRQ_BUS: |
<> | 156:95d6b41a828b | 250 | mask_enable = IRQ_ENABLE_BE; |
<> | 156:95d6b41a828b | 251 | break; |
<> | 156:95d6b41a828b | 252 | case IRQ_PASSIVE: |
<> | 156:95d6b41a828b | 253 | mask_enable = IRQ_ENABLE_EP; |
<> | 156:95d6b41a828b | 254 | break; |
<> | 156:95d6b41a828b | 255 | case IRQ_ERROR: |
<> | 156:95d6b41a828b | 256 | mask_enable = IRQ_ENABLE_EW; |
<> | 156:95d6b41a828b | 257 | break; |
<> | 156:95d6b41a828b | 258 | default: |
<> | 156:95d6b41a828b | 259 | return; |
<> | 156:95d6b41a828b | 260 | } |
<> | 156:95d6b41a828b | 261 | |
<> | 156:95d6b41a828b | 262 | if (enable) { |
<> | 156:95d6b41a828b | 263 | enabled_irqs = enabled_irqs | mask_enable; |
<> | 156:95d6b41a828b | 264 | } else { |
<> | 156:95d6b41a828b | 265 | enabled_irqs = enabled_irqs & ~mask_enable; |
<> | 156:95d6b41a828b | 266 | } |
<> | 156:95d6b41a828b | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | // Put CAN in Reset Mode and enable interrupt |
<> | 144:ef7eb2e8f9f7 | 269 | can_disable(obj); |
<> | 156:95d6b41a828b | 270 | if (!(enabled_irqs & IRQ_ENABLE_ANY)) { |
<> | 156:95d6b41a828b | 271 | LPC_C_CAN0->CANCNTL &= ~(1UL << 1 | 1UL << 2 | 1UL << 3); |
<> | 144:ef7eb2e8f9f7 | 272 | } else { |
<> | 156:95d6b41a828b | 273 | LPC_C_CAN0->CANCNTL |= 1UL << 1; |
<> | 156:95d6b41a828b | 274 | // Use status interrupts instead of message interrupts to avoid |
<> | 156:95d6b41a828b | 275 | // stomping over potential filter configurations. |
<> | 156:95d6b41a828b | 276 | if (enabled_irqs & IRQ_ENABLE_STATUS) { |
<> | 156:95d6b41a828b | 277 | LPC_C_CAN0->CANCNTL |= 1UL << 2; |
<> | 156:95d6b41a828b | 278 | } else { |
<> | 156:95d6b41a828b | 279 | LPC_C_CAN0->CANCNTL &= ~(1UL << 2); |
<> | 156:95d6b41a828b | 280 | } |
<> | 156:95d6b41a828b | 281 | if (enabled_irqs & IRQ_ENABLE_ERROR) { |
<> | 156:95d6b41a828b | 282 | LPC_C_CAN0->CANCNTL |= 1UL << 3; |
<> | 156:95d6b41a828b | 283 | } else { |
<> | 156:95d6b41a828b | 284 | LPC_C_CAN0->CANCNTL &= ~(1UL << 3); |
<> | 156:95d6b41a828b | 285 | } |
<> | 144:ef7eb2e8f9f7 | 286 | } |
<> | 156:95d6b41a828b | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | // Take it out of reset... |
<> | 144:ef7eb2e8f9f7 | 289 | can_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | // Enable NVIC if at least 1 interrupt is active |
<> | 144:ef7eb2e8f9f7 | 292 | NVIC_SetVector(C_CAN0_IRQn, (uint32_t) &can_irq); |
<> | 144:ef7eb2e8f9f7 | 293 | NVIC_EnableIRQ(C_CAN0_IRQn); |
<> | 144:ef7eb2e8f9f7 | 294 | } |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | // This table has the sampling points as close to 75% as possible. The first |
<> | 144:ef7eb2e8f9f7 | 297 | // value is TSEG1, the second TSEG2. |
<> | 144:ef7eb2e8f9f7 | 298 | static const int timing_pts[23][2] = { |
<> | 144:ef7eb2e8f9f7 | 299 | {0x0, 0x0}, // 2, 50% |
<> | 144:ef7eb2e8f9f7 | 300 | {0x1, 0x0}, // 3, 67% |
<> | 144:ef7eb2e8f9f7 | 301 | {0x2, 0x0}, // 4, 75% |
<> | 144:ef7eb2e8f9f7 | 302 | {0x3, 0x0}, // 5, 80% |
<> | 144:ef7eb2e8f9f7 | 303 | {0x3, 0x1}, // 6, 67% |
<> | 144:ef7eb2e8f9f7 | 304 | {0x4, 0x1}, // 7, 71% |
<> | 144:ef7eb2e8f9f7 | 305 | {0x5, 0x1}, // 8, 75% |
<> | 144:ef7eb2e8f9f7 | 306 | {0x6, 0x1}, // 9, 78% |
<> | 144:ef7eb2e8f9f7 | 307 | {0x6, 0x2}, // 10, 70% |
<> | 144:ef7eb2e8f9f7 | 308 | {0x7, 0x2}, // 11, 73% |
<> | 144:ef7eb2e8f9f7 | 309 | {0x8, 0x2}, // 12, 75% |
<> | 144:ef7eb2e8f9f7 | 310 | {0x9, 0x2}, // 13, 77% |
<> | 144:ef7eb2e8f9f7 | 311 | {0x9, 0x3}, // 14, 71% |
<> | 144:ef7eb2e8f9f7 | 312 | {0xA, 0x3}, // 15, 73% |
<> | 144:ef7eb2e8f9f7 | 313 | {0xB, 0x3}, // 16, 75% |
<> | 144:ef7eb2e8f9f7 | 314 | {0xC, 0x3}, // 17, 76% |
<> | 144:ef7eb2e8f9f7 | 315 | {0xD, 0x3}, // 18, 78% |
<> | 144:ef7eb2e8f9f7 | 316 | {0xD, 0x4}, // 19, 74% |
<> | 144:ef7eb2e8f9f7 | 317 | {0xE, 0x4}, // 20, 75% |
<> | 144:ef7eb2e8f9f7 | 318 | {0xF, 0x4}, // 21, 76% |
<> | 144:ef7eb2e8f9f7 | 319 | {0xF, 0x5}, // 22, 73% |
<> | 144:ef7eb2e8f9f7 | 320 | {0xF, 0x6}, // 23, 70% |
<> | 144:ef7eb2e8f9f7 | 321 | {0xF, 0x7}, // 24, 67% |
<> | 144:ef7eb2e8f9f7 | 322 | }; |
<> | 144:ef7eb2e8f9f7 | 323 | |
<> | 144:ef7eb2e8f9f7 | 324 | static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) { |
<> | 144:ef7eb2e8f9f7 | 325 | uint32_t btr; |
<> | 144:ef7eb2e8f9f7 | 326 | uint32_t clkdiv = 1; |
<> | 144:ef7eb2e8f9f7 | 327 | uint16_t brp = 0; |
<> | 144:ef7eb2e8f9f7 | 328 | uint32_t calcbit; |
<> | 144:ef7eb2e8f9f7 | 329 | uint32_t bitwidth; |
<> | 144:ef7eb2e8f9f7 | 330 | int hit = 0; |
<> | 144:ef7eb2e8f9f7 | 331 | int bits = 0; |
<> | 144:ef7eb2e8f9f7 | 332 | |
<> | 144:ef7eb2e8f9f7 | 333 | bitwidth = sclk / cclk; |
<> | 144:ef7eb2e8f9f7 | 334 | |
<> | 144:ef7eb2e8f9f7 | 335 | brp = bitwidth / 0x18; |
<> | 144:ef7eb2e8f9f7 | 336 | while ((!hit) && (brp < bitwidth / 4)) { |
<> | 144:ef7eb2e8f9f7 | 337 | brp++; |
<> | 144:ef7eb2e8f9f7 | 338 | for (bits = 22; bits > 0; bits--) { |
<> | 144:ef7eb2e8f9f7 | 339 | calcbit = (bits + 3) * (brp + 1); |
<> | 144:ef7eb2e8f9f7 | 340 | if (calcbit == bitwidth) { |
<> | 144:ef7eb2e8f9f7 | 341 | hit = 1; |
<> | 144:ef7eb2e8f9f7 | 342 | break; |
<> | 144:ef7eb2e8f9f7 | 343 | } |
<> | 144:ef7eb2e8f9f7 | 344 | } |
<> | 144:ef7eb2e8f9f7 | 345 | } |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | clkdiv = clkdiv - 1; |
<> | 144:ef7eb2e8f9f7 | 348 | |
<> | 144:ef7eb2e8f9f7 | 349 | if (hit) { |
<> | 144:ef7eb2e8f9f7 | 350 | btr = (timing_pts[bits][1] & 0x7) << 12 |
<> | 144:ef7eb2e8f9f7 | 351 | | (timing_pts[bits][0] & 0xf) << 8 |
<> | 144:ef7eb2e8f9f7 | 352 | | (psjw & 0x3) << 6 |
<> | 144:ef7eb2e8f9f7 | 353 | | (brp & 0x3F); |
<> | 144:ef7eb2e8f9f7 | 354 | btr = btr | (clkdiv << 16); |
<> | 144:ef7eb2e8f9f7 | 355 | } else { |
<> | 144:ef7eb2e8f9f7 | 356 | btr = 0; |
<> | 144:ef7eb2e8f9f7 | 357 | } |
<> | 144:ef7eb2e8f9f7 | 358 | |
<> | 144:ef7eb2e8f9f7 | 359 | return btr; |
<> | 144:ef7eb2e8f9f7 | 360 | } |
<> | 144:ef7eb2e8f9f7 | 361 | |
<> | 144:ef7eb2e8f9f7 | 362 | |
<> | 144:ef7eb2e8f9f7 | 363 | int can_config_rxmsgobj(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 364 | uint16_t i = 0; |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | // Make sure the interface is available |
<> | 144:ef7eb2e8f9f7 | 367 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 368 | |
<> | 144:ef7eb2e8f9f7 | 369 | // Mark message valid, Direction = RX, Don't care about anything else |
<> | 144:ef7eb2e8f9f7 | 370 | LPC_C_CAN0->CANIF1_ARB1 = 0; |
<> | 144:ef7eb2e8f9f7 | 371 | LPC_C_CAN0->CANIF1_ARB2 = 0; |
<> | 144:ef7eb2e8f9f7 | 372 | LPC_C_CAN0->CANIF1_MCTRL = 0; |
<> | 144:ef7eb2e8f9f7 | 373 | |
<> | 156:95d6b41a828b | 374 | for ( i = 1; i <= RX_MSG_OBJ_COUNT; i++ ) { |
<> | 144:ef7eb2e8f9f7 | 375 | // Transfer arb and control fields to message object |
<> | 156:95d6b41a828b | 376 | LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL; |
<> | 144:ef7eb2e8f9f7 | 377 | |
<> | 144:ef7eb2e8f9f7 | 378 | // Start Transfer to given message number |
<> | 144:ef7eb2e8f9f7 | 379 | LPC_C_CAN0->CANIF1_CMDREQ = (i & 0x3F); |
<> | 144:ef7eb2e8f9f7 | 380 | |
<> | 144:ef7eb2e8f9f7 | 381 | // Wait until transfer to message ram complete - TODO: maybe not block?? |
<> | 144:ef7eb2e8f9f7 | 382 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | |
<> | 144:ef7eb2e8f9f7 | 385 | // Accept all messages |
<> | 144:ef7eb2e8f9f7 | 386 | can_filter(obj, 0, 0, CANStandard, 1); |
<> | 144:ef7eb2e8f9f7 | 387 | |
<> | 144:ef7eb2e8f9f7 | 388 | return 1; |
<> | 144:ef7eb2e8f9f7 | 389 | } |
<> | 144:ef7eb2e8f9f7 | 390 | |
<> | 156:95d6b41a828b | 391 | int can_config_txmsgobj(can_t *obj) { |
<> | 156:95d6b41a828b | 392 | uint16_t i = 0; |
<> | 156:95d6b41a828b | 393 | |
<> | 156:95d6b41a828b | 394 | // Make sure the interface is available |
<> | 156:95d6b41a828b | 395 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 156:95d6b41a828b | 396 | |
<> | 156:95d6b41a828b | 397 | // Mark message valid, Direction = TX, Don't care about anything else |
<> | 156:95d6b41a828b | 398 | LPC_C_CAN0->CANIF1_ARB1 = 0; |
<> | 156:95d6b41a828b | 399 | LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_DIR; |
<> | 156:95d6b41a828b | 400 | LPC_C_CAN0->CANIF1_MCTRL = 0; |
<> | 156:95d6b41a828b | 401 | |
<> | 156:95d6b41a828b | 402 | for ( i = RX_MSG_OBJ_COUNT + 1; i <= (TX_MSG_OBJ_COUNT + RX_MSG_OBJ_COUNT); i++ ) |
<> | 156:95d6b41a828b | 403 | { |
<> | 156:95d6b41a828b | 404 | // Transfer arb and control fields to message object |
<> | 156:95d6b41a828b | 405 | LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL; |
<> | 156:95d6b41a828b | 406 | // In a union with CANIF1_CMDMSK_R |
<> | 156:95d6b41a828b | 407 | |
<> | 156:95d6b41a828b | 408 | // Start Transfer to given message number |
<> | 156:95d6b41a828b | 409 | LPC_C_CAN0->CANIF1_CMDREQ = i & 0x3F; |
<> | 156:95d6b41a828b | 410 | |
<> | 156:95d6b41a828b | 411 | // Wait until transfer to message ram complete - TODO: maybe not block?? |
<> | 156:95d6b41a828b | 412 | while( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 156:95d6b41a828b | 413 | } |
<> | 156:95d6b41a828b | 414 | |
<> | 156:95d6b41a828b | 415 | return 1; |
<> | 156:95d6b41a828b | 416 | } |
<> | 156:95d6b41a828b | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | void can_init(can_t *obj, PinName rd, PinName td) { |
<> | 144:ef7eb2e8f9f7 | 420 | // Enable power and clock |
<> | 144:ef7eb2e8f9f7 | 421 | LPC_SYSCON->SYSAHBCLKCTRL1 |= (1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 422 | LPC_SYSCON->PRESETCTRL1 |= (1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 423 | LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 424 | |
<> | 144:ef7eb2e8f9f7 | 425 | // Enable Initialization mode |
<> | 144:ef7eb2e8f9f7 | 426 | if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) { |
<> | 144:ef7eb2e8f9f7 | 427 | LPC_C_CAN0->CANCNTL |= (1UL << 0); |
<> | 144:ef7eb2e8f9f7 | 428 | } |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | LPC_SWM->PINASSIGN[6] &= ~(0x00FFFF00L); |
<> | 144:ef7eb2e8f9f7 | 431 | LPC_SWM->PINASSIGN[6] |= (rd << 16) | (td << 8); |
<> | 144:ef7eb2e8f9f7 | 432 | |
<> | 144:ef7eb2e8f9f7 | 433 | can_frequency(obj, 100000); |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | // Resume operation |
<> | 144:ef7eb2e8f9f7 | 436 | LPC_C_CAN0->CANCNTL &= ~(1UL << 0); |
<> | 144:ef7eb2e8f9f7 | 437 | while ( LPC_C_CAN0->CANCNTL & (1UL << 0) ); |
<> | 144:ef7eb2e8f9f7 | 438 | |
<> | 144:ef7eb2e8f9f7 | 439 | // Initialize RX message object |
<> | 144:ef7eb2e8f9f7 | 440 | can_config_rxmsgobj(obj); |
<> | 156:95d6b41a828b | 441 | // Initialize TX message object |
<> | 156:95d6b41a828b | 442 | can_config_txmsgobj(obj); |
<> | 144:ef7eb2e8f9f7 | 443 | } |
<> | 144:ef7eb2e8f9f7 | 444 | |
<> | 144:ef7eb2e8f9f7 | 445 | void can_free(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 446 | LPC_SYSCON->SYSAHBCLKCTRL1 &= ~(1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 447 | LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 448 | } |
<> | 144:ef7eb2e8f9f7 | 449 | |
<> | 144:ef7eb2e8f9f7 | 450 | int can_frequency(can_t *obj, int f) { |
<> | 144:ef7eb2e8f9f7 | 451 | int btr = can_speed(SystemCoreClock, (unsigned int)f, 1); |
<> | 144:ef7eb2e8f9f7 | 452 | int clkdiv = (btr >> 16) & 0x0F; |
<> | 144:ef7eb2e8f9f7 | 453 | btr = btr & 0xFFFF; |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | if (btr > 0) { |
<> | 144:ef7eb2e8f9f7 | 456 | // Set the bit clock |
<> | 144:ef7eb2e8f9f7 | 457 | LPC_C_CAN0->CANCNTL |= (1UL << 6 | 1UL << 0); // set CCE and INIT |
<> | 144:ef7eb2e8f9f7 | 458 | LPC_C_CAN0->CANCLKDIV = clkdiv; |
<> | 144:ef7eb2e8f9f7 | 459 | LPC_C_CAN0->CANBT = btr; |
<> | 144:ef7eb2e8f9f7 | 460 | LPC_C_CAN0->CANBRPE = 0x0000; |
<> | 144:ef7eb2e8f9f7 | 461 | LPC_C_CAN0->CANCNTL &= ~(1UL << 6 | 1UL << 0); // clear CCE and INIT |
<> | 144:ef7eb2e8f9f7 | 462 | return 1; |
<> | 144:ef7eb2e8f9f7 | 463 | } |
<> | 144:ef7eb2e8f9f7 | 464 | return 0; |
<> | 144:ef7eb2e8f9f7 | 465 | } |
<> | 144:ef7eb2e8f9f7 | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | int can_write(can_t *obj, CAN_Message msg, int cc) { |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | // Make sure controller is enabled |
<> | 144:ef7eb2e8f9f7 | 470 | can_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 471 | |
<> | 156:95d6b41a828b | 472 | // Find first message object that isn't pending to send |
<> | 156:95d6b41a828b | 473 | uint16_t msgnum = 0; |
<> | 156:95d6b41a828b | 474 | uint32_t txPending = (LPC_C_CAN0->CANTXREQ1 & 0xFF) | (LPC_C_CAN0->CANTXREQ2 << 16); |
<> | 156:95d6b41a828b | 475 | uint16_t i = 0; |
<> | 156:95d6b41a828b | 476 | for(i = RX_MSG_OBJ_COUNT; i < 32; i++) { |
<> | 156:95d6b41a828b | 477 | if ((txPending & (1 << i)) == 0) { |
<> | 156:95d6b41a828b | 478 | msgnum = i+1; |
<> | 156:95d6b41a828b | 479 | break; |
<> | 156:95d6b41a828b | 480 | } |
<> | 156:95d6b41a828b | 481 | } |
<> | 156:95d6b41a828b | 482 | |
<> | 156:95d6b41a828b | 483 | // If no messageboxes are available, stop and return failure |
<> | 156:95d6b41a828b | 484 | if (msgnum == 0) { |
<> | 156:95d6b41a828b | 485 | return 0; |
<> | 156:95d6b41a828b | 486 | } |
<> | 156:95d6b41a828b | 487 | |
<> | 144:ef7eb2e8f9f7 | 488 | // Make sure the interface is available |
<> | 144:ef7eb2e8f9f7 | 489 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 490 | |
<> | 144:ef7eb2e8f9f7 | 491 | // Set the direction bit based on the message type |
<> | 144:ef7eb2e8f9f7 | 492 | uint32_t direction = 0; |
<> | 144:ef7eb2e8f9f7 | 493 | if (msg.type == CANData) { |
<> | 144:ef7eb2e8f9f7 | 494 | direction = CANIFn_ARB2_DIR; |
<> | 144:ef7eb2e8f9f7 | 495 | } |
<> | 144:ef7eb2e8f9f7 | 496 | |
<> | 144:ef7eb2e8f9f7 | 497 | if (msg.format == CANExtended) { |
<> | 144:ef7eb2e8f9f7 | 498 | // Mark message valid, Extended Frame, Set Identifier and mask everything |
<> | 144:ef7eb2e8f9f7 | 499 | LPC_C_CAN0->CANIF1_ARB1 = (msg.id & 0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 500 | LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | CANIFn_ARB2_XTD | direction | ((msg.id >> 16) & 0x1FFFF); |
<> | 144:ef7eb2e8f9f7 | 501 | LPC_C_CAN0->CANIF1_MSK1 = (ID_EXT_MASK & 0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 502 | LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MXTD | CANIFn_MSK2_MDIR | ((ID_EXT_MASK >> 16) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 503 | } else { |
<> | 144:ef7eb2e8f9f7 | 504 | // Mark message valid, Set Identifier and mask everything |
<> | 144:ef7eb2e8f9f7 | 505 | LPC_C_CAN0->CANIF1_ARB2 = CANIFn_ARB2_MSGVAL | direction | ((msg.id << 2) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 506 | LPC_C_CAN0->CANIF1_MSK2 = CANIFn_MSK2_MDIR | ((ID_STD_MASK << 2) & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 507 | } |
<> | 144:ef7eb2e8f9f7 | 508 | |
<> | 144:ef7eb2e8f9f7 | 509 | // Use mask, request transmission, single message object and set DLC |
<> | 144:ef7eb2e8f9f7 | 510 | LPC_C_CAN0->CANIF1_MCTRL = CANIFn_MCTRL_UMASK | CANIFn_MCTRL_TXRQST | CANIFn_MCTRL_EOB | (msg.len & 0xF); |
<> | 144:ef7eb2e8f9f7 | 511 | |
<> | 144:ef7eb2e8f9f7 | 512 | LPC_C_CAN0->CANIF1_DA1 = ((msg.data[1] & 0xFF) << 8) | (msg.data[0] & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 513 | LPC_C_CAN0->CANIF1_DA2 = ((msg.data[3] & 0xFF) << 8) | (msg.data[2] & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 514 | LPC_C_CAN0->CANIF1_DB1 = ((msg.data[5] & 0xFF) << 8) | (msg.data[4] & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 515 | LPC_C_CAN0->CANIF1_DB2 = ((msg.data[7] & 0xFF) << 8) | (msg.data[6] & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | // Transfer all fields to message object |
<> | 144:ef7eb2e8f9f7 | 518 | LPC_C_CAN0->CANIF1_CMDMSK_W = CANIFn_CMDMSK_WR | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B; |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | // Start Transfer to given message number |
<> | 144:ef7eb2e8f9f7 | 521 | LPC_C_CAN0->CANIF1_CMDREQ = (msgnum & 0x3F); |
<> | 144:ef7eb2e8f9f7 | 522 | |
<> | 144:ef7eb2e8f9f7 | 523 | // Wait until transfer to message ram complete - TODO: maybe not block?? |
<> | 144:ef7eb2e8f9f7 | 524 | while ( LPC_C_CAN0->CANIF1_CMDREQ & CANIFn_CMDREQ_BUSY); |
<> | 144:ef7eb2e8f9f7 | 525 | |
<> | 144:ef7eb2e8f9f7 | 526 | // Wait until TXOK is set, then clear it - TODO: maybe not block |
<> | 144:ef7eb2e8f9f7 | 527 | //while ( !(LPC_C_CAN0->STAT & CANSTAT_TXOK) ); |
<> | 144:ef7eb2e8f9f7 | 528 | LPC_C_CAN0->CANSTAT &= ~(1UL << 3); |
<> | 144:ef7eb2e8f9f7 | 529 | |
<> | 144:ef7eb2e8f9f7 | 530 | return 1; |
<> | 144:ef7eb2e8f9f7 | 531 | } |
<> | 144:ef7eb2e8f9f7 | 532 | |
<> | 144:ef7eb2e8f9f7 | 533 | int can_read(can_t *obj, CAN_Message *msg, int handle) { |
<> | 144:ef7eb2e8f9f7 | 534 | uint16_t i; |
<> | 144:ef7eb2e8f9f7 | 535 | |
<> | 144:ef7eb2e8f9f7 | 536 | // Make sure controller is enabled |
<> | 144:ef7eb2e8f9f7 | 537 | can_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 538 | |
<> | 144:ef7eb2e8f9f7 | 539 | // Find first message object with new data |
<> | 144:ef7eb2e8f9f7 | 540 | if (handle == 0) { |
<> | 144:ef7eb2e8f9f7 | 541 | uint32_t newdata = LPC_C_CAN0->CANND1 | (LPC_C_CAN0->CANND2 << 16); |
<> | 144:ef7eb2e8f9f7 | 542 | // Find first free messagebox |
<> | 156:95d6b41a828b | 543 | for (i = 0; i < RX_MSG_OBJ_COUNT; i++) { |
<> | 144:ef7eb2e8f9f7 | 544 | if (newdata & (1 << i)) { |
<> | 144:ef7eb2e8f9f7 | 545 | handle = i+1; |
<> | 144:ef7eb2e8f9f7 | 546 | break; |
<> | 144:ef7eb2e8f9f7 | 547 | } |
<> | 144:ef7eb2e8f9f7 | 548 | } |
<> | 144:ef7eb2e8f9f7 | 549 | } |
<> | 144:ef7eb2e8f9f7 | 550 | |
<> | 156:95d6b41a828b | 551 | if (handle > 0 && handle <= 32) { |
<> | 144:ef7eb2e8f9f7 | 552 | // Wait until message interface is free |
<> | 144:ef7eb2e8f9f7 | 553 | while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 554 | |
<> | 144:ef7eb2e8f9f7 | 555 | // Transfer all fields to message object |
<> | 144:ef7eb2e8f9f7 | 556 | LPC_C_CAN0->CANIF2_CMDMSK_W = CANIFn_CMDMSK_RD | CANIFn_CMDMSK_MASK | CANIFn_CMDMSK_ARB | CANIFn_CMDMSK_CTRL | CANIFn_CMDMSK_CLRINTPND | CANIFn_CMDMSK_TXRQST | CANIFn_CMDMSK_DATA_A | CANIFn_CMDMSK_DATA_B; |
<> | 144:ef7eb2e8f9f7 | 557 | |
<> | 144:ef7eb2e8f9f7 | 558 | // Start Transfer from given message number |
<> | 144:ef7eb2e8f9f7 | 559 | LPC_C_CAN0->CANIF2_CMDREQ = (handle & 0x3F); |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | // Wait until transfer to message ram complete |
<> | 144:ef7eb2e8f9f7 | 562 | while ( LPC_C_CAN0->CANIF2_CMDREQ & CANIFn_CMDREQ_BUSY ); |
<> | 144:ef7eb2e8f9f7 | 563 | |
<> | 144:ef7eb2e8f9f7 | 564 | if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_XTD) { |
<> | 144:ef7eb2e8f9f7 | 565 | msg->format = CANExtended; |
<> | 144:ef7eb2e8f9f7 | 566 | msg->id = (LPC_C_CAN0->CANIF2_ARB1 & 0x1FFF) << 16; |
<> | 144:ef7eb2e8f9f7 | 567 | msg->id |= (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF); |
<> | 144:ef7eb2e8f9f7 | 568 | } else { |
<> | 144:ef7eb2e8f9f7 | 569 | msg->format = CANStandard; |
<> | 144:ef7eb2e8f9f7 | 570 | msg->id = (LPC_C_CAN0->CANIF2_ARB2 & 0x1FFF) >> 2; |
<> | 144:ef7eb2e8f9f7 | 571 | } |
<> | 144:ef7eb2e8f9f7 | 572 | |
<> | 144:ef7eb2e8f9f7 | 573 | if (LPC_C_CAN0->CANIF2_ARB2 & CANIFn_ARB2_DIR) { |
<> | 144:ef7eb2e8f9f7 | 574 | msg->type = CANRemote; |
<> | 144:ef7eb2e8f9f7 | 575 | } |
<> | 144:ef7eb2e8f9f7 | 576 | else { |
<> | 144:ef7eb2e8f9f7 | 577 | msg->type = CANData; |
<> | 144:ef7eb2e8f9f7 | 578 | } |
<> | 144:ef7eb2e8f9f7 | 579 | |
<> | 144:ef7eb2e8f9f7 | 580 | msg->len = (LPC_C_CAN0->CANIF2_MCTRL & 0xF); // TODO: If > 8, len = 8 |
<> | 144:ef7eb2e8f9f7 | 581 | msg->data[0] = ((LPC_C_CAN0->CANIF2_DA1 >> 0) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 582 | msg->data[1] = ((LPC_C_CAN0->CANIF2_DA1 >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 583 | msg->data[2] = ((LPC_C_CAN0->CANIF2_DA2 >> 0) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 584 | msg->data[3] = ((LPC_C_CAN0->CANIF2_DA2 >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 585 | msg->data[4] = ((LPC_C_CAN0->CANIF2_DB1 >> 0) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 586 | msg->data[5] = ((LPC_C_CAN0->CANIF2_DB1 >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 587 | msg->data[6] = ((LPC_C_CAN0->CANIF2_DB2 >> 0) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 588 | msg->data[7] = ((LPC_C_CAN0->CANIF2_DB2 >> 8) & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 589 | |
<> | 144:ef7eb2e8f9f7 | 590 | LPC_C_CAN0->CANSTAT &= ~(1UL << 4); |
<> | 144:ef7eb2e8f9f7 | 591 | return 1; |
<> | 144:ef7eb2e8f9f7 | 592 | } |
<> | 144:ef7eb2e8f9f7 | 593 | return 0; |
<> | 144:ef7eb2e8f9f7 | 594 | } |
<> | 144:ef7eb2e8f9f7 | 595 | |
<> | 144:ef7eb2e8f9f7 | 596 | void can_reset(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 597 | LPC_SYSCON->PRESETCTRL1 &= ~(1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 598 | LPC_C_CAN0->CANSTAT = 0; |
<> | 144:ef7eb2e8f9f7 | 599 | can_config_rxmsgobj(obj); |
<> | 156:95d6b41a828b | 600 | can_config_txmsgobj(obj); |
<> | 156:95d6b41a828b | 601 | |
<> | 156:95d6b41a828b | 602 | can_enable(obj); // clears a bus-off condition if necessary |
<> | 144:ef7eb2e8f9f7 | 603 | } |
<> | 144:ef7eb2e8f9f7 | 604 | |
<> | 144:ef7eb2e8f9f7 | 605 | unsigned char can_rderror(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 606 | return ((LPC_C_CAN0->CANEC >> 8) & 0x7F); |
<> | 144:ef7eb2e8f9f7 | 607 | } |
<> | 144:ef7eb2e8f9f7 | 608 | |
<> | 144:ef7eb2e8f9f7 | 609 | unsigned char can_tderror(can_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 610 | return (LPC_C_CAN0->CANEC & 0xFF); |
<> | 144:ef7eb2e8f9f7 | 611 | } |
<> | 144:ef7eb2e8f9f7 | 612 | |
<> | 144:ef7eb2e8f9f7 | 613 | void can_monitor(can_t *obj, int silent) { |
<> | 144:ef7eb2e8f9f7 | 614 | if (silent) { |
<> | 144:ef7eb2e8f9f7 | 615 | LPC_C_CAN0->CANCNTL |= (1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 616 | LPC_C_CAN0->CANTEST |= (1UL << 3); |
<> | 144:ef7eb2e8f9f7 | 617 | } else { |
<> | 144:ef7eb2e8f9f7 | 618 | LPC_C_CAN0->CANCNTL &= ~(1UL << 7); |
<> | 144:ef7eb2e8f9f7 | 619 | LPC_C_CAN0->CANTEST &= ~(1UL << 3); |
<> | 144:ef7eb2e8f9f7 | 620 | } |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | if (!(LPC_C_CAN0->CANCNTL & (1UL << 0))) { |
<> | 144:ef7eb2e8f9f7 | 623 | LPC_C_CAN0->CANCNTL |= (1UL << 0); |
<> | 144:ef7eb2e8f9f7 | 624 | } |
<> | 144:ef7eb2e8f9f7 | 625 | } |