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targets/TARGET_NXP/TARGET_LPC11XX_11CXX/spi_api.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
- Child:
- 167:e84263d55307
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 17 | #include <math.h> |
<> | 144:ef7eb2e8f9f7 | 18 | #include "spi_api.h" |
<> | 144:ef7eb2e8f9f7 | 19 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 21 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | static const PinMap PinMap_SPI_SCLK[] = { |
<> | 144:ef7eb2e8f9f7 | 24 | {P0_6 , SPI_0, 0x02}, |
<> | 144:ef7eb2e8f9f7 | 25 | // {P0_10, SPI_0, 0x02}, -- should be mapped to SWCLK only |
<> | 144:ef7eb2e8f9f7 | 26 | {P2_11, SPI_0, 0x01}, |
<> | 144:ef7eb2e8f9f7 | 27 | {P2_1 , SPI_1, 0x02}, |
<> | 144:ef7eb2e8f9f7 | 28 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 29 | }; |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | static const PinMap PinMap_SPI_MOSI[] = { |
<> | 144:ef7eb2e8f9f7 | 32 | {P0_9 , SPI_0, 0x01}, |
<> | 144:ef7eb2e8f9f7 | 33 | {P2_3 , SPI_1, 0x02}, |
<> | 144:ef7eb2e8f9f7 | 34 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 35 | }; |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | static const PinMap PinMap_SPI_MISO[] = { |
<> | 144:ef7eb2e8f9f7 | 38 | {P0_8 , SPI_0, 0x01}, |
<> | 144:ef7eb2e8f9f7 | 39 | {P2_2 , SPI_1, 0x02}, |
<> | 144:ef7eb2e8f9f7 | 40 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 41 | }; |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | static const PinMap PinMap_SPI_SSEL[] = { |
<> | 144:ef7eb2e8f9f7 | 44 | {P0_2 , SPI_0, 0x01}, |
<> | 144:ef7eb2e8f9f7 | 45 | {P2_0 , SPI_1, 0x02}, |
<> | 144:ef7eb2e8f9f7 | 46 | {NC , NC , 0} |
<> | 144:ef7eb2e8f9f7 | 47 | }; |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | static inline int ssp_disable(spi_t *obj); |
<> | 144:ef7eb2e8f9f7 | 50 | static inline int ssp_enable(spi_t *obj); |
<> | 144:ef7eb2e8f9f7 | 51 | |
<> | 144:ef7eb2e8f9f7 | 52 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { |
<> | 144:ef7eb2e8f9f7 | 53 | // determine the SPI to use |
<> | 144:ef7eb2e8f9f7 | 54 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 55 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 56 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 57 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 58 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
<> | 144:ef7eb2e8f9f7 | 59 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | obj->spi = (LPC_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl); |
<> | 144:ef7eb2e8f9f7 | 62 | MBED_ASSERT((int)obj->spi != NC); |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | // enable power and clocking |
<> | 144:ef7eb2e8f9f7 | 65 | switch ((int)obj->spi) { |
<> | 144:ef7eb2e8f9f7 | 66 | case SPI_0: |
<> | 144:ef7eb2e8f9f7 | 67 | LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 11; |
<> | 144:ef7eb2e8f9f7 | 68 | LPC_SYSCON->SSP0CLKDIV = 0x01; |
<> | 144:ef7eb2e8f9f7 | 69 | LPC_SYSCON->PRESETCTRL |= 1 << 0; |
<> | 144:ef7eb2e8f9f7 | 70 | if (sclk == P0_6) { |
<> | 144:ef7eb2e8f9f7 | 71 | LPC_IOCON->SCK_LOC = 0x02; |
<> | 144:ef7eb2e8f9f7 | 72 | } |
<> | 144:ef7eb2e8f9f7 | 73 | else { |
<> | 144:ef7eb2e8f9f7 | 74 | LPC_IOCON->SCK_LOC = 0x01; |
<> | 144:ef7eb2e8f9f7 | 75 | } |
<> | 144:ef7eb2e8f9f7 | 76 | break; |
<> | 144:ef7eb2e8f9f7 | 77 | case SPI_1: |
<> | 144:ef7eb2e8f9f7 | 78 | LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 18; |
<> | 144:ef7eb2e8f9f7 | 79 | LPC_SYSCON->SSP1CLKDIV = 0x01; |
<> | 144:ef7eb2e8f9f7 | 80 | LPC_SYSCON->PRESETCTRL |= 1 << 2; |
<> | 144:ef7eb2e8f9f7 | 81 | LPC_IOCON->SCK1_LOC = 0x00; |
<> | 144:ef7eb2e8f9f7 | 82 | LPC_IOCON->MISO1_LOC = 0x00; |
<> | 144:ef7eb2e8f9f7 | 83 | LPC_IOCON->MOSI1_LOC = 0x00; |
<> | 144:ef7eb2e8f9f7 | 84 | if (ssel != NC) { |
<> | 144:ef7eb2e8f9f7 | 85 | LPC_IOCON->SSEL1_LOC = 0x00; |
<> | 144:ef7eb2e8f9f7 | 86 | } |
<> | 144:ef7eb2e8f9f7 | 87 | break; |
<> | 144:ef7eb2e8f9f7 | 88 | } |
<> | 144:ef7eb2e8f9f7 | 89 | |
<> | 144:ef7eb2e8f9f7 | 90 | // pin out the spi pins |
<> | 144:ef7eb2e8f9f7 | 91 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
<> | 144:ef7eb2e8f9f7 | 92 | pinmap_pinout(miso, PinMap_SPI_MISO); |
<> | 144:ef7eb2e8f9f7 | 93 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
<> | 144:ef7eb2e8f9f7 | 94 | if (ssel != NC) { |
<> | 144:ef7eb2e8f9f7 | 95 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
<> | 144:ef7eb2e8f9f7 | 96 | } |
<> | 144:ef7eb2e8f9f7 | 97 | } |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | void spi_free(spi_t *obj) {} |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | void spi_format(spi_t *obj, int bits, int mode, int slave) { |
<> | 144:ef7eb2e8f9f7 | 102 | MBED_ASSERT((bits >= 4 && bits <= 16) || (mode >= 0 && mode <= 3)); |
<> | 144:ef7eb2e8f9f7 | 103 | ssp_disable(obj); |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | int polarity = (mode & 0x2) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 106 | int phase = (mode & 0x1) ? 1 : 0; |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | // set it up |
<> | 144:ef7eb2e8f9f7 | 109 | int DSS = bits - 1; // DSS (data select size) |
<> | 144:ef7eb2e8f9f7 | 110 | int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity |
<> | 144:ef7eb2e8f9f7 | 111 | int SPH = (phase) ? 1 : 0; // SPH - clock out phase |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | int FRF = 0; // FRF (frame format) = SPI |
<> | 144:ef7eb2e8f9f7 | 114 | uint32_t tmp = obj->spi->CR0; |
<> | 144:ef7eb2e8f9f7 | 115 | tmp &= ~(0xFFFF); |
<> | 144:ef7eb2e8f9f7 | 116 | tmp |= DSS << 0 |
<> | 144:ef7eb2e8f9f7 | 117 | | FRF << 4 |
<> | 144:ef7eb2e8f9f7 | 118 | | SPO << 6 |
<> | 144:ef7eb2e8f9f7 | 119 | | SPH << 7; |
<> | 144:ef7eb2e8f9f7 | 120 | obj->spi->CR0 = tmp; |
<> | 144:ef7eb2e8f9f7 | 121 | |
<> | 144:ef7eb2e8f9f7 | 122 | tmp = obj->spi->CR1; |
<> | 144:ef7eb2e8f9f7 | 123 | tmp &= ~(0xD); |
<> | 144:ef7eb2e8f9f7 | 124 | tmp |= 0 << 0 // LBM - loop back mode - off |
<> | 144:ef7eb2e8f9f7 | 125 | | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave |
<> | 144:ef7eb2e8f9f7 | 126 | | 0 << 3; // SOD - slave output disable - na |
<> | 144:ef7eb2e8f9f7 | 127 | obj->spi->CR1 = tmp; |
<> | 144:ef7eb2e8f9f7 | 128 | |
<> | 144:ef7eb2e8f9f7 | 129 | ssp_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 130 | } |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | void spi_frequency(spi_t *obj, int hz) { |
<> | 144:ef7eb2e8f9f7 | 133 | ssp_disable(obj); |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | uint32_t PCLK = SystemCoreClock; |
<> | 144:ef7eb2e8f9f7 | 136 | |
<> | 144:ef7eb2e8f9f7 | 137 | int prescaler; |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | for (prescaler = 2; prescaler <= 254; prescaler += 2) { |
<> | 144:ef7eb2e8f9f7 | 140 | int prescale_hz = PCLK / prescaler; |
<> | 144:ef7eb2e8f9f7 | 141 | |
<> | 144:ef7eb2e8f9f7 | 142 | // calculate the divider |
<> | 144:ef7eb2e8f9f7 | 143 | int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | // check we can support the divider |
<> | 144:ef7eb2e8f9f7 | 146 | if (divider < 256) { |
<> | 144:ef7eb2e8f9f7 | 147 | // prescaler |
<> | 144:ef7eb2e8f9f7 | 148 | obj->spi->CPSR = prescaler; |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | // divider |
<> | 144:ef7eb2e8f9f7 | 151 | obj->spi->CR0 &= ~(0xFFFF << 8); |
<> | 144:ef7eb2e8f9f7 | 152 | obj->spi->CR0 |= (divider - 1) << 8; |
<> | 144:ef7eb2e8f9f7 | 153 | ssp_enable(obj); |
<> | 144:ef7eb2e8f9f7 | 154 | return; |
<> | 144:ef7eb2e8f9f7 | 155 | } |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | error("Couldn't setup requested SPI frequency"); |
<> | 144:ef7eb2e8f9f7 | 158 | } |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | static inline int ssp_disable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 161 | return obj->spi->CR1 &= ~(1 << 1); |
<> | 144:ef7eb2e8f9f7 | 162 | } |
<> | 144:ef7eb2e8f9f7 | 163 | |
<> | 144:ef7eb2e8f9f7 | 164 | static inline int ssp_enable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 165 | return obj->spi->CR1 |= (1 << 1); |
<> | 144:ef7eb2e8f9f7 | 166 | } |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | static inline int ssp_readable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 169 | return obj->spi->SR & (1 << 2); |
<> | 144:ef7eb2e8f9f7 | 170 | } |
<> | 144:ef7eb2e8f9f7 | 171 | |
<> | 144:ef7eb2e8f9f7 | 172 | static inline int ssp_writeable(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 173 | return obj->spi->SR & (1 << 1); |
<> | 144:ef7eb2e8f9f7 | 174 | } |
<> | 144:ef7eb2e8f9f7 | 175 | |
<> | 144:ef7eb2e8f9f7 | 176 | static inline void ssp_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 177 | while (!ssp_writeable(obj)); |
<> | 144:ef7eb2e8f9f7 | 178 | obj->spi->DR = value; |
<> | 144:ef7eb2e8f9f7 | 179 | } |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | static inline int ssp_read(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 182 | while (!ssp_readable(obj)); |
<> | 144:ef7eb2e8f9f7 | 183 | return obj->spi->DR; |
<> | 144:ef7eb2e8f9f7 | 184 | } |
<> | 144:ef7eb2e8f9f7 | 185 | |
<> | 144:ef7eb2e8f9f7 | 186 | static inline int ssp_busy(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 187 | return (obj->spi->SR & (1 << 4)) ? (1) : (0); |
<> | 144:ef7eb2e8f9f7 | 188 | } |
<> | 144:ef7eb2e8f9f7 | 189 | |
<> | 144:ef7eb2e8f9f7 | 190 | int spi_master_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 191 | ssp_write(obj, value); |
<> | 144:ef7eb2e8f9f7 | 192 | return ssp_read(obj); |
<> | 144:ef7eb2e8f9f7 | 193 | } |
<> | 144:ef7eb2e8f9f7 | 194 | |
<> | 144:ef7eb2e8f9f7 | 195 | int spi_slave_receive(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 196 | return ssp_readable(obj) ? (1) : (0); |
<> | 144:ef7eb2e8f9f7 | 197 | } |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 144:ef7eb2e8f9f7 | 199 | int spi_slave_read(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 200 | return obj->spi->DR & 0xFFFF; |
<> | 144:ef7eb2e8f9f7 | 201 | } |
<> | 144:ef7eb2e8f9f7 | 202 | |
<> | 144:ef7eb2e8f9f7 | 203 | void spi_slave_write(spi_t *obj, int value) { |
<> | 144:ef7eb2e8f9f7 | 204 | while (ssp_writeable(obj) == 0) ; |
<> | 144:ef7eb2e8f9f7 | 205 | obj->spi->DR = value; |
<> | 144:ef7eb2e8f9f7 | 206 | } |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | int spi_busy(spi_t *obj) { |
<> | 144:ef7eb2e8f9f7 | 209 | return ssp_busy(obj); |
<> | 144:ef7eb2e8f9f7 | 210 | } |