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targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 157:ff67d9f36b67
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 157:ff67d9f36b67 | 1 | /** |
<> | 157:ff67d9f36b67 | 2 | * @file |
<> | 157:ff67d9f36b67 | 3 | * @brief Peripheral Management Unit (PMU) Function Implementations. |
<> | 157:ff67d9f36b67 | 4 | */ |
<> | 157:ff67d9f36b67 | 5 | /* ***************************************************************************** |
<> | 157:ff67d9f36b67 | 6 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
<> | 157:ff67d9f36b67 | 7 | * |
<> | 157:ff67d9f36b67 | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
<> | 157:ff67d9f36b67 | 9 | * copy of this software and associated documentation files (the "Software"), |
<> | 157:ff67d9f36b67 | 10 | * to deal in the Software without restriction, including without limitation |
<> | 157:ff67d9f36b67 | 11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
<> | 157:ff67d9f36b67 | 12 | * and/or sell copies of the Software, and to permit persons to whom the |
<> | 157:ff67d9f36b67 | 13 | * Software is furnished to do so, subject to the following conditions: |
<> | 157:ff67d9f36b67 | 14 | * |
<> | 157:ff67d9f36b67 | 15 | * The above copyright notice and this permission notice shall be included |
<> | 157:ff67d9f36b67 | 16 | * in all copies or substantial portions of the Software. |
<> | 157:ff67d9f36b67 | 17 | * |
<> | 157:ff67d9f36b67 | 18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
<> | 157:ff67d9f36b67 | 19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
<> | 157:ff67d9f36b67 | 20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
<> | 157:ff67d9f36b67 | 21 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
<> | 157:ff67d9f36b67 | 22 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
<> | 157:ff67d9f36b67 | 23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
<> | 157:ff67d9f36b67 | 24 | * OTHER DEALINGS IN THE SOFTWARE. |
<> | 157:ff67d9f36b67 | 25 | * |
<> | 157:ff67d9f36b67 | 26 | * Except as contained in this notice, the name of Maxim Integrated |
<> | 157:ff67d9f36b67 | 27 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
<> | 157:ff67d9f36b67 | 28 | * Products, Inc. Branding Policy. |
<> | 157:ff67d9f36b67 | 29 | * |
<> | 157:ff67d9f36b67 | 30 | * The mere transfer of this software does not imply any licenses |
<> | 157:ff67d9f36b67 | 31 | * of trade secrets, proprietary technology, copyrights, patents, |
<> | 157:ff67d9f36b67 | 32 | * trademarks, maskwork rights, or any other form of intellectual |
<> | 157:ff67d9f36b67 | 33 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
<> | 157:ff67d9f36b67 | 34 | * ownership rights. |
<> | 157:ff67d9f36b67 | 35 | * |
<> | 157:ff67d9f36b67 | 36 | * $Date: 2016-09-08 17:44:03 -0500 (Thu, 08 Sep 2016) $ |
<> | 157:ff67d9f36b67 | 37 | * $Revision: 24328 $ |
<> | 157:ff67d9f36b67 | 38 | * |
<> | 157:ff67d9f36b67 | 39 | **************************************************************************** */ |
<> | 157:ff67d9f36b67 | 40 | |
<> | 157:ff67d9f36b67 | 41 | /* **** Includes **** */ |
<> | 157:ff67d9f36b67 | 42 | #include <stdio.h> |
<> | 157:ff67d9f36b67 | 43 | #include <stddef.h> |
<> | 157:ff67d9f36b67 | 44 | #include "mxc_config.h" |
<> | 157:ff67d9f36b67 | 45 | #include "mxc_assert.h" |
<> | 157:ff67d9f36b67 | 46 | #include "pmu.h" |
<> | 157:ff67d9f36b67 | 47 | /** |
<> | 157:ff67d9f36b67 | 48 | * @ingroup pmuGroup |
<> | 157:ff67d9f36b67 | 49 | * @{ |
<> | 157:ff67d9f36b67 | 50 | */ |
<> | 157:ff67d9f36b67 | 51 | |
<> | 157:ff67d9f36b67 | 52 | #if (MXC_PMU_REV == 0) |
<> | 157:ff67d9f36b67 | 53 | /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */ |
<> | 157:ff67d9f36b67 | 54 | #include "clkman_regs.h" |
<> | 157:ff67d9f36b67 | 55 | /* Channel 5 infinite loop program */ |
<> | 157:ff67d9f36b67 | 56 | static const uint32_t pmu_0[] = { |
<> | 157:ff67d9f36b67 | 57 | PMU_JUMP(0, 0, (uint32_t)pmu_0) |
<> | 157:ff67d9f36b67 | 58 | }; |
<> | 157:ff67d9f36b67 | 59 | #endif |
<> | 157:ff67d9f36b67 | 60 | |
<> | 157:ff67d9f36b67 | 61 | /* **** Local Function Prototypes **** */ |
<> | 157:ff67d9f36b67 | 62 | static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int); |
<> | 157:ff67d9f36b67 | 63 | |
<> | 157:ff67d9f36b67 | 64 | |
<> | 157:ff67d9f36b67 | 65 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 66 | void PMU_Handler(void) |
<> | 157:ff67d9f36b67 | 67 | { |
<> | 157:ff67d9f36b67 | 68 | int channel; |
<> | 157:ff67d9f36b67 | 69 | uint32_t cfg1, cfg2; |
<> | 157:ff67d9f36b67 | 70 | mxc_pmu_regs_t *MXC_PMUn; |
<> | 157:ff67d9f36b67 | 71 | |
<> | 157:ff67d9f36b67 | 72 | for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) { |
<> | 157:ff67d9f36b67 | 73 | MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 74 | |
<> | 157:ff67d9f36b67 | 75 | if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) { |
<> | 157:ff67d9f36b67 | 76 | cfg1 = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 77 | /* Since any set flags will be cleared by the write-back below, mask them off */ |
<> | 157:ff67d9f36b67 | 78 | cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT); |
<> | 157:ff67d9f36b67 | 79 | |
<> | 157:ff67d9f36b67 | 80 | /* Clear the interrupt flag */ |
<> | 157:ff67d9f36b67 | 81 | MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT; |
<> | 157:ff67d9f36b67 | 82 | |
<> | 157:ff67d9f36b67 | 83 | if (callbacks[channel]) { |
<> | 157:ff67d9f36b67 | 84 | callbacks[channel](cfg1); |
<> | 157:ff67d9f36b67 | 85 | } |
<> | 157:ff67d9f36b67 | 86 | } |
<> | 157:ff67d9f36b67 | 87 | } |
<> | 157:ff67d9f36b67 | 88 | } |
<> | 157:ff67d9f36b67 | 89 | |
<> | 157:ff67d9f36b67 | 90 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 91 | int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback) |
<> | 157:ff67d9f36b67 | 92 | { |
<> | 157:ff67d9f36b67 | 93 | if(channel >= MXC_CFG_PMU_CHANNELS) |
<> | 157:ff67d9f36b67 | 94 | return E_BAD_PARAM; |
<> | 157:ff67d9f36b67 | 95 | |
<> | 157:ff67d9f36b67 | 96 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 97 | uint32_t cfg = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 98 | |
<> | 157:ff67d9f36b67 | 99 | /* is this channel already running? */ |
<> | 157:ff67d9f36b67 | 100 | if (cfg & MXC_F_PMU_CFG_ENABLE) { |
<> | 157:ff67d9f36b67 | 101 | return E_BUSY; |
<> | 157:ff67d9f36b67 | 102 | } |
<> | 157:ff67d9f36b67 | 103 | |
<> | 157:ff67d9f36b67 | 104 | #if (MXC_PMU_REV == 0) |
<> | 157:ff67d9f36b67 | 105 | /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */ |
<> | 157:ff67d9f36b67 | 106 | if (channel == 5) { |
<> | 157:ff67d9f36b67 | 107 | /* Channel 5 is used for the work-around */ |
<> | 157:ff67d9f36b67 | 108 | return E_BUSY; |
<> | 157:ff67d9f36b67 | 109 | } |
<> | 157:ff67d9f36b67 | 110 | /* Select always-ON clock for PMU */ |
<> | 157:ff67d9f36b67 | 111 | MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER; |
<> | 157:ff67d9f36b67 | 112 | /* Start channel 5 with infinite-loop program */ |
<> | 157:ff67d9f36b67 | 113 | MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */ |
<> | 157:ff67d9f36b67 | 114 | MXC_PMU5->dscadr = (uint32_t)pmu_0; |
<> | 157:ff67d9f36b67 | 115 | MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS); |
<> | 157:ff67d9f36b67 | 116 | #endif |
<> | 157:ff67d9f36b67 | 117 | /* Set callback */ |
<> | 157:ff67d9f36b67 | 118 | callbacks[channel] = callback; |
<> | 157:ff67d9f36b67 | 119 | |
<> | 157:ff67d9f36b67 | 120 | /* Set start op-code */ |
<> | 157:ff67d9f36b67 | 121 | MXC_PMUn->dscadr = (uint32_t)program_address; |
<> | 157:ff67d9f36b67 | 122 | |
<> | 157:ff67d9f36b67 | 123 | /* Configure the channel */ |
<> | 157:ff67d9f36b67 | 124 | cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS); |
<> | 157:ff67d9f36b67 | 125 | |
<> | 157:ff67d9f36b67 | 126 | /* Enable if necessary */ |
<> | 157:ff67d9f36b67 | 127 | if (callback) { |
<> | 157:ff67d9f36b67 | 128 | cfg |= MXC_F_PMU_CFG_INT_EN; |
<> | 157:ff67d9f36b67 | 129 | } else { |
<> | 157:ff67d9f36b67 | 130 | cfg &= ~MXC_F_PMU_CFG_INT_EN; |
<> | 157:ff67d9f36b67 | 131 | } |
<> | 157:ff67d9f36b67 | 132 | |
<> | 157:ff67d9f36b67 | 133 | /* Start the channel */ |
<> | 157:ff67d9f36b67 | 134 | cfg |= MXC_F_PMU_CFG_ENABLE; |
<> | 157:ff67d9f36b67 | 135 | |
<> | 157:ff67d9f36b67 | 136 | /*If any W1C flags are set, this write will clear them */ |
<> | 157:ff67d9f36b67 | 137 | MXC_PMUn->cfg = cfg; |
<> | 157:ff67d9f36b67 | 138 | |
<> | 157:ff67d9f36b67 | 139 | return E_NO_ERROR; |
<> | 157:ff67d9f36b67 | 140 | } |
<> | 157:ff67d9f36b67 | 141 | |
<> | 157:ff67d9f36b67 | 142 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 143 | void PMU_Stop(unsigned int channel) |
<> | 157:ff67d9f36b67 | 144 | { |
<> | 157:ff67d9f36b67 | 145 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 146 | uint32_t cfg = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 147 | |
<> | 157:ff67d9f36b67 | 148 | /* Since any set flags will be cleared by the write-back below, mask them off */ |
<> | 157:ff67d9f36b67 | 149 | cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); |
<> | 157:ff67d9f36b67 | 150 | |
<> | 157:ff67d9f36b67 | 151 | /* Clear the enable bit to stop the channel */ |
<> | 157:ff67d9f36b67 | 152 | cfg &= ~MXC_F_PMU_CFG_ENABLE; |
<> | 157:ff67d9f36b67 | 153 | |
<> | 157:ff67d9f36b67 | 154 | MXC_PMUn->cfg = cfg; |
<> | 157:ff67d9f36b67 | 155 | |
<> | 157:ff67d9f36b67 | 156 | /* Remove callback */ |
<> | 157:ff67d9f36b67 | 157 | callbacks[channel] = NULL; |
<> | 157:ff67d9f36b67 | 158 | |
<> | 157:ff67d9f36b67 | 159 | #if (MXC_PMU_REV == 0) |
<> | 157:ff67d9f36b67 | 160 | /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */ |
<> | 157:ff67d9f36b67 | 161 | /* Check channels 0-4 for any running channels. If none found, stop channel 5 */ |
<> | 157:ff67d9f36b67 | 162 | if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && |
<> | 157:ff67d9f36b67 | 163 | (MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && |
<> | 157:ff67d9f36b67 | 164 | (MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && |
<> | 157:ff67d9f36b67 | 165 | (MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 && |
<> | 157:ff67d9f36b67 | 166 | (MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) { |
<> | 157:ff67d9f36b67 | 167 | MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; |
<> | 157:ff67d9f36b67 | 168 | } |
<> | 157:ff67d9f36b67 | 169 | #endif |
<> | 157:ff67d9f36b67 | 170 | |
<> | 157:ff67d9f36b67 | 171 | } |
<> | 157:ff67d9f36b67 | 172 | |
<> | 157:ff67d9f36b67 | 173 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 174 | int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value) |
<> | 157:ff67d9f36b67 | 175 | { |
<> | 157:ff67d9f36b67 | 176 | if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1) |
<> | 157:ff67d9f36b67 | 177 | return E_BAD_PARAM; |
<> | 157:ff67d9f36b67 | 178 | |
<> | 157:ff67d9f36b67 | 179 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 180 | |
<> | 157:ff67d9f36b67 | 181 | if (counter == 0) { |
<> | 157:ff67d9f36b67 | 182 | MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS); |
<> | 157:ff67d9f36b67 | 183 | } else { |
<> | 157:ff67d9f36b67 | 184 | MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS); |
<> | 157:ff67d9f36b67 | 185 | } |
<> | 157:ff67d9f36b67 | 186 | |
<> | 157:ff67d9f36b67 | 187 | return E_NO_ERROR; |
<> | 157:ff67d9f36b67 | 188 | } |
<> | 157:ff67d9f36b67 | 189 | |
<> | 157:ff67d9f36b67 | 190 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 191 | int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks) |
<> | 157:ff67d9f36b67 | 192 | { |
<> | 157:ff67d9f36b67 | 193 | if(channel >= MXC_CFG_PMU_CHANNELS) |
<> | 157:ff67d9f36b67 | 194 | return E_BAD_PARAM; |
<> | 157:ff67d9f36b67 | 195 | |
<> | 157:ff67d9f36b67 | 196 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 197 | uint32_t cfg = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 198 | |
<> | 157:ff67d9f36b67 | 199 | /* Since any set flags will be cleared by the write-back below, mask them off */ |
<> | 157:ff67d9f36b67 | 200 | cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); |
<> | 157:ff67d9f36b67 | 201 | |
<> | 157:ff67d9f36b67 | 202 | /* Adjust timeout settings */ |
<> | 157:ff67d9f36b67 | 203 | cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL); |
<> | 157:ff67d9f36b67 | 204 | cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) | |
<> | 157:ff67d9f36b67 | 205 | ((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL); |
<> | 157:ff67d9f36b67 | 206 | |
<> | 157:ff67d9f36b67 | 207 | MXC_PMUn->cfg = cfg; |
<> | 157:ff67d9f36b67 | 208 | |
<> | 157:ff67d9f36b67 | 209 | return E_NO_ERROR; |
<> | 157:ff67d9f36b67 | 210 | } |
<> | 157:ff67d9f36b67 | 211 | |
<> | 157:ff67d9f36b67 | 212 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 213 | uint32_t PMU_GetFlags(unsigned int channel) |
<> | 157:ff67d9f36b67 | 214 | { |
<> | 157:ff67d9f36b67 | 215 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 216 | uint32_t cfg = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 217 | |
<> | 157:ff67d9f36b67 | 218 | /* Mask off configuration bits leaving only flag bits */ |
<> | 157:ff67d9f36b67 | 219 | cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL | |
<> | 157:ff67d9f36b67 | 220 | MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE); |
<> | 157:ff67d9f36b67 | 221 | |
<> | 157:ff67d9f36b67 | 222 | return cfg; |
<> | 157:ff67d9f36b67 | 223 | } |
<> | 157:ff67d9f36b67 | 224 | |
<> | 157:ff67d9f36b67 | 225 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 226 | void PMU_ClearFlags(unsigned int channel, unsigned int mask) |
<> | 157:ff67d9f36b67 | 227 | { |
<> | 157:ff67d9f36b67 | 228 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 229 | uint32_t cfg = MXC_PMUn->cfg; |
<> | 157:ff67d9f36b67 | 230 | |
<> | 157:ff67d9f36b67 | 231 | /* Since any set flags will be cleared by the write-back below, mask them off */ |
<> | 157:ff67d9f36b67 | 232 | cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT); |
<> | 157:ff67d9f36b67 | 233 | |
<> | 157:ff67d9f36b67 | 234 | /* Now, apply the caller-supplied bits to clear */ |
<> | 157:ff67d9f36b67 | 235 | cfg |= mask; |
<> | 157:ff67d9f36b67 | 236 | |
<> | 157:ff67d9f36b67 | 237 | MXC_PMUn->cfg = cfg; |
<> | 157:ff67d9f36b67 | 238 | } |
<> | 157:ff67d9f36b67 | 239 | |
<> | 157:ff67d9f36b67 | 240 | /* ************************************************************************* */ |
<> | 157:ff67d9f36b67 | 241 | uint32_t PMU_IsActive(unsigned int channel) |
<> | 157:ff67d9f36b67 | 242 | { |
<> | 157:ff67d9f36b67 | 243 | mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel]; |
<> | 157:ff67d9f36b67 | 244 | return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE); |
<> | 157:ff67d9f36b67 | 245 | } |
<> | 157:ff67d9f36b67 | 246 | /**@} end of ingroup pmuGroup */ |