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targets/TARGET_Maxim/TARGET_MAX32625/mxc/pmu.h@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

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<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-06-21 16:14:41 -0500 (Tue, 21 Jun 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 23446 $
<> 150:02e0a0aed4ec 34 *
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 /**
<> 150:02e0a0aed4ec 38 * @file pmu.h
<> 150:02e0a0aed4ec 39 * @addtogroup pmu Peripheral Management Unit
<> 150:02e0a0aed4ec 40 * @{
<> 150:02e0a0aed4ec 41 * @brief This is the API for the peripheral management unit.
<> 150:02e0a0aed4ec 42 */
<> 150:02e0a0aed4ec 43
<> 150:02e0a0aed4ec 44 #ifndef _PMU_H_
<> 150:02e0a0aed4ec 45 #define _PMU_H_
<> 150:02e0a0aed4ec 46
<> 150:02e0a0aed4ec 47 #include "pmu_regs.h"
<> 150:02e0a0aed4ec 48
<> 150:02e0a0aed4ec 49 #ifdef __cplusplus
<> 150:02e0a0aed4ec 50 extern "C" {
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 /// @brief Defines Clock scale used for Timeout
<> 150:02e0a0aed4ec 54 typedef enum {
<> 150:02e0a0aed4ec 55 PMU_PS_SEL_DISABLE = MXC_V_PMU_CFG_PS_SEL_DISABLE, // Timeout disabled
<> 150:02e0a0aed4ec 56 PMU_PS_SEL_DIV_2_8 = MXC_V_PMU_CFG_PS_SEL_DIV_2_8, // Timeout clk = PMU clock / 2^8 = 256
<> 150:02e0a0aed4ec 57 PMU_PS_SEL_DIV_2_16 = MXC_V_PMU_CFG_PS_SEL_DIV_2_16, // Timeout clk = PMU clock / 2^16 = 65536
<> 150:02e0a0aed4ec 58 PMU_PS_SEL_DIV_2_24 = MXC_V_PMU_CFG_PS_SEL_DIV_2_24 // Timeout clk = PMU clock / 2^24 = 16777216
<> 150:02e0a0aed4ec 59 }pmu_ps_sel_t;
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 /// @brief Defines the number of clk ticks for timeout duration
<> 150:02e0a0aed4ec 62 typedef enum {
<> 150:02e0a0aed4ec 63 PMU_TO_SEL_TICKS_4 = MXC_V_PMU_CFG_TO_SEL_TICKS_4, //timeout = 4 * Timeout clk period
<> 150:02e0a0aed4ec 64 PMU_TO_SEL_TICKS_8 = MXC_V_PMU_CFG_TO_SEL_TICKS_8, //timeout = 8 * Timeout clk period
<> 150:02e0a0aed4ec 65 PMU_TO_SEL_TICKS_16 = MXC_V_PMU_CFG_TO_SEL_TICKS_16, //timeout = 16 * Timeout clk period
<> 150:02e0a0aed4ec 66 PMU_TO_SEL_TICKS_32 = MXC_V_PMU_CFG_TO_SEL_TICKS_32, //timeout = 32 * Timeout clk period
<> 150:02e0a0aed4ec 67 PMU_TO_SEL_TICKS_64 = MXC_V_PMU_CFG_TO_SEL_TICKS_64, //timeout = 64 * Timeout clk period
<> 150:02e0a0aed4ec 68 PMU_TO_SEL_TICKS_128 = MXC_V_PMU_CFG_TO_SEL_TICKS_128, //timeout = 128 * Timeout clk period
<> 150:02e0a0aed4ec 69 PMU_TO_SEL_TICKS_256 = MXC_V_PMU_CFG_TO_SEL_TICKS_256, //timeout = 256 * Timeout clk period
<> 150:02e0a0aed4ec 70 PMU_TO_SEL_TICKS_512 = MXC_V_PMU_CFG_TO_SEL_TICKS_512 //timeout = 512 * Timeout clk period
<> 150:02e0a0aed4ec 71 }pmu_to_sel_t;
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73
<> 150:02e0a0aed4ec 74 /* The macros like the one below are designed to help build static PMU programs
<> 150:02e0a0aed4ec 75 * as arrays of 32bit words.
<> 150:02e0a0aed4ec 76 */
<> 150:02e0a0aed4ec 77 #define PMU_IS(interrupt, stop) ((!!interrupt) << PMU_INT_POS) | ((!!stop) << PMU_STOP_POS)
<> 150:02e0a0aed4ec 78
<> 150:02e0a0aed4ec 79 typedef struct pmu_move_des_t {
<> 150:02e0a0aed4ec 80 uint32_t op_code : 3; /* 0x0 */
<> 150:02e0a0aed4ec 81 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 82 uint32_t stop : 1;
<> 150:02e0a0aed4ec 83 uint32_t read_size : 2;
<> 150:02e0a0aed4ec 84 uint32_t read_inc : 1;
<> 150:02e0a0aed4ec 85 uint32_t write_size : 2;
<> 150:02e0a0aed4ec 86 uint32_t write_inc : 1;
<> 150:02e0a0aed4ec 87 uint32_t cont : 1;
<> 150:02e0a0aed4ec 88 uint32_t length : 20;
<> 150:02e0a0aed4ec 89
<> 150:02e0a0aed4ec 90 uint32_t write_address;
<> 150:02e0a0aed4ec 91 uint32_t read_address;
<> 150:02e0a0aed4ec 92 } pmu_move_des_t;
<> 150:02e0a0aed4ec 93 #define PMU_MOVE(i, s, rs, ri, ws, wi, c, length, wa, ra) \
<> 150:02e0a0aed4ec 94 (PMU_MOVE_OP | PMU_IS(i,s) | ((rs & 3) << PMU_MOVE_READS_POS) | ((!!ri) << PMU_MOVE_READI_POS) | \
<> 150:02e0a0aed4ec 95 ((ws & 3) << PMU_MOVE_WRITES_POS) | ((!!wi) << PMU_MOVE_WRITEI_POS) | ((!!c) << PMU_MOVE_CONT_POS) | ((length & 0xFFFFF) << PMU_MOVE_LEN_POS)), wa, ra
<> 150:02e0a0aed4ec 96
<> 150:02e0a0aed4ec 97 /* new_value = value | (old_value & ~ mask) */
<> 150:02e0a0aed4ec 98 typedef struct pmu_write_des_t {
<> 150:02e0a0aed4ec 99 uint32_t op_code : 3; /* 0x1 */
<> 150:02e0a0aed4ec 100 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 101 uint32_t stop : 1;
<> 150:02e0a0aed4ec 102 uint32_t : 3;
<> 150:02e0a0aed4ec 103 uint32_t write_method : 4;
<> 150:02e0a0aed4ec 104 uint32_t : 20;
<> 150:02e0a0aed4ec 105
<> 150:02e0a0aed4ec 106 uint32_t write_address;
<> 150:02e0a0aed4ec 107 uint32_t value;
<> 150:02e0a0aed4ec 108 uint32_t mask;
<> 150:02e0a0aed4ec 109 } pmu_write_des_t;
<> 150:02e0a0aed4ec 110 #define PMU_WRITE(i, s, wm, a, v, m) (PMU_WRITE_OP | PMU_IS(i,s) | ((wm & 0xF) << PMU_WRITE_METHOD_POS)), a, v, m
<> 150:02e0a0aed4ec 111
<> 150:02e0a0aed4ec 112 typedef struct pmu_wait_des_t {
<> 150:02e0a0aed4ec 113 uint32_t op_code : 3; /* 0x2 */
<> 150:02e0a0aed4ec 114 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 115 uint32_t stop : 1;
<> 150:02e0a0aed4ec 116 uint32_t wait : 1;
<> 150:02e0a0aed4ec 117 uint32_t sel : 1;
<> 150:02e0a0aed4ec 118 uint32_t : 25;
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 uint32_t mask1;
<> 150:02e0a0aed4ec 121 uint32_t mask2;
<> 150:02e0a0aed4ec 122 uint32_t wait_count;
<> 150:02e0a0aed4ec 123 } pmu_wait_des_t;
<> 150:02e0a0aed4ec 124 #define PMU_WAIT(i, s, sel, m1, m2, cnt) (PMU_WAIT_OP | PMU_IS(i,s) | ((cnt>0)?(1<<PMU_WAIT_WAIT_POS):0) | ((!!sel) << PMU_WAIT_SEL_POS)), \
<> 150:02e0a0aed4ec 125 m1, m2, cnt
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 typedef struct pmu_jump_des_t {
<> 150:02e0a0aed4ec 128 uint32_t op_code : 3; /* 0x3 */
<> 150:02e0a0aed4ec 129 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 130 uint32_t stop : 1;
<> 150:02e0a0aed4ec 131 uint32_t : 27;
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 uint32_t address;
<> 150:02e0a0aed4ec 134 } pmu_jump_des_t;
<> 150:02e0a0aed4ec 135 #define PMU_JUMP(i, s, a) (PMU_JUMP_OP | PMU_IS(i,s)), a
<> 150:02e0a0aed4ec 136
<> 150:02e0a0aed4ec 137 typedef struct pmu_loop_des_t {
<> 150:02e0a0aed4ec 138 uint32_t op_code : 3; /* 0x4 */
<> 150:02e0a0aed4ec 139 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 140 uint32_t stop : 1;
<> 150:02e0a0aed4ec 141 uint32_t sel_counter : 1;
<> 150:02e0a0aed4ec 142 uint32_t : 26;
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 uint32_t address;
<> 150:02e0a0aed4ec 145 } pmu_loop_des_t;
<> 150:02e0a0aed4ec 146 #define PMU_LOOP(i, s, c, a) (PMU_LOOP_OP | PMU_IS(i,s) | ((!!c) << PMU_LOOP_SEL_COUNTER_POS)), a
<> 150:02e0a0aed4ec 147
<> 150:02e0a0aed4ec 148 typedef struct pmu_poll_des_t {
<> 150:02e0a0aed4ec 149 uint32_t op_code : 3; /* 0x5 */
<> 150:02e0a0aed4ec 150 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 151 uint32_t stop : 1;
<> 150:02e0a0aed4ec 152 uint32_t : 2;
<> 150:02e0a0aed4ec 153 uint32_t and : 1;
<> 150:02e0a0aed4ec 154 uint32_t : 24;
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 uint32_t poll_addr;
<> 150:02e0a0aed4ec 157 uint32_t data;
<> 150:02e0a0aed4ec 158 uint32_t mask;
<> 150:02e0a0aed4ec 159 uint32_t poll_interval;
<> 150:02e0a0aed4ec 160 } pmu_poll_des_t;
<> 150:02e0a0aed4ec 161 #define PMU_POLL(i, s, a, adr, d, m, per) (PMU_POLL_OP | PMU_IS(i,s) | ((!!a) << PMU_POLL_AND_POS)), adr, d, m, per
<> 150:02e0a0aed4ec 162
<> 150:02e0a0aed4ec 163 typedef struct pmu_branch_des_t {
<> 150:02e0a0aed4ec 164 uint32_t op_code : 3; /* 0x6 */
<> 150:02e0a0aed4ec 165 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 166 uint32_t stop : 1;
<> 150:02e0a0aed4ec 167 uint32_t : 2;
<> 150:02e0a0aed4ec 168 uint32_t and : 1;
<> 150:02e0a0aed4ec 169 uint32_t type : 3;
<> 150:02e0a0aed4ec 170 uint32_t : 21;
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172 uint32_t poll_addr;
<> 150:02e0a0aed4ec 173 uint32_t data;
<> 150:02e0a0aed4ec 174 uint32_t mask;
<> 150:02e0a0aed4ec 175 uint32_t address;
<> 150:02e0a0aed4ec 176 } pmu_branch_des_t;
<> 150:02e0a0aed4ec 177 #define PMU_BRANCH(i, s, a, t, adr, d, m, badr) \
<> 150:02e0a0aed4ec 178 (PMU_BRANCH_OP | PMU_IS(i,s) | ((!!a) << PMU_BRANCH_AND_POS)| ((t & 7) << PMU_BRANCH_TYPE_POS)), adr, d, m, badr
<> 150:02e0a0aed4ec 179
<> 150:02e0a0aed4ec 180 typedef struct pmu_transfer_des_t {
<> 150:02e0a0aed4ec 181 uint32_t op_code : 3; /* 0x7 */
<> 150:02e0a0aed4ec 182 uint32_t interrupt : 1;
<> 150:02e0a0aed4ec 183 uint32_t stop : 1;
<> 150:02e0a0aed4ec 184 uint32_t read_size : 2;
<> 150:02e0a0aed4ec 185 uint32_t read_inc : 1;
<> 150:02e0a0aed4ec 186 uint32_t write_size : 2;
<> 150:02e0a0aed4ec 187 uint32_t write_inc : 1;
<> 150:02e0a0aed4ec 188 uint32_t : 1;
<> 150:02e0a0aed4ec 189 uint32_t tx_length : 20;
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 uint32_t write_address;
<> 150:02e0a0aed4ec 192 uint32_t read_address;
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194 uint32_t int_mask : 25; /* valid int_mask is from 0 - 24 */
<> 150:02e0a0aed4ec 195 uint32_t : 1;
<> 150:02e0a0aed4ec 196 uint32_t burst_size : 6;
<> 150:02e0a0aed4ec 197 } pmu_transfer_des_t;
<> 150:02e0a0aed4ec 198 #define PMU_TRANSFER(i, s, rs, ri, ws, wi, l, wa, ra, imsk, b) \
<> 150:02e0a0aed4ec 199 (PMU_TRANSFER_OP | PMU_IS(i,s) | ((rs & 3) << PMU_TX_READS_POS) | ((!!ri) << PMU_TX_READI_POS) | \
<> 150:02e0a0aed4ec 200 ((ws & 3) << PMU_TX_WRITES_POS) | ((!!wi) << PMU_TX_WRITEI_POS) | ((l & 0xFFFFF) << PMU_TX_LEN_POS)), wa, ra, \
<> 150:02e0a0aed4ec 201 ((imsk) | ((b & 0x3F) << PMU_TX_BS_POS))
<> 150:02e0a0aed4ec 202
<> 150:02e0a0aed4ec 203 /**
<> 150:02e0a0aed4ec 204 * @brief Type alias \c pmu_callback with function signature: \code void (*pmu_callback)(int pmu_status) \endcode
<> 150:02e0a0aed4ec 205 * @details The callback function will be called for every opcode that has
<> 150:02e0a0aed4ec 206 * the interrupt bit set. If NULL, the channel interrupt will not
<> 150:02e0a0aed4ec 207 * be enabled. The callback function argument is a status bit
<> 150:02e0a0aed4ec 208 * indicating the status of the PMU program.
<> 150:02e0a0aed4ec 209 * @param pmu_status The callback function argument is a status bit indicating
<> 150:02e0a0aed4ec 210 * the status of the PMU program.
<> 150:02e0a0aed4ec 211 */
<> 150:02e0a0aed4ec 212 typedef void (*pmu_callback)(int pmu_status);
<> 150:02e0a0aed4ec 213
<> 150:02e0a0aed4ec 214 /**
<> 150:02e0a0aed4ec 215 * @brief Start a PMU program on a channel
<> 150:02e0a0aed4ec 216 * @param channel Channel to start
<> 150:02e0a0aed4ec 217 * @param program_address Pointer to the first opcode of the PMU program
<> 150:02e0a0aed4ec 218 * @param callback Callback function of the signature \c pmu_callback
<> 150:02e0a0aed4ec 219 * @param arg Pointer to be passed to the interrupt callback function.
<> 150:02e0a0aed4ec 220 * @returns E_NO_ERROR if everything is successful, error if unsuccessful.
<> 150:02e0a0aed4ec 221 */
<> 150:02e0a0aed4ec 222 int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback);
<> 150:02e0a0aed4ec 223
<> 150:02e0a0aed4ec 224 /**
<> 150:02e0a0aed4ec 225 * @brief Set a loop counter value on a channel
<> 150:02e0a0aed4ec 226 * @param channel Channel number to set the value on
<> 150:02e0a0aed4ec 227 * @param counter_num Counter number for the channel (0 or 1)
<> 150:02e0a0aed4ec 228 * @param value Loop count value
<> 150:02e0a0aed4ec 229 * @returns E_NO_ERROR if everything is successful, error if unsuccessful.
<> 150:02e0a0aed4ec 230 */
<> 150:02e0a0aed4ec 231 int PMU_SetCounter(unsigned int channel, unsigned int counter_num, uint16_t value);
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233 /**
<> 150:02e0a0aed4ec 234 * @brief Stop a running channel. This will clear the enable bit on the channel
<> 150:02e0a0aed4ec 235 * and stop the running PMU program at the current opcode. The callback
<> 150:02e0a0aed4ec 236 * function is not called.
<> 150:02e0a0aed4ec 237 * @param channel Channel to stop
<> 150:02e0a0aed4ec 238 */
<> 150:02e0a0aed4ec 239 void PMU_Stop(unsigned int channel);
<> 150:02e0a0aed4ec 240
<> 150:02e0a0aed4ec 241 /**
<> 150:02e0a0aed4ec 242 * @brief Function to handle PMU interrupts. This function can be called from
<> 150:02e0a0aed4ec 243 * the PMU interrupt service routine, or periodically from the
<> 150:02e0a0aed4ec 244 * application if interrupts are not enabled.
<> 150:02e0a0aed4ec 245 */
<> 150:02e0a0aed4ec 246 void PMU_Handler(void);
<> 150:02e0a0aed4ec 247
<> 150:02e0a0aed4ec 248 /**
<> 150:02e0a0aed4ec 249 * @brief Set the AHB bus operation timeout on a channel
<> 150:02e0a0aed4ec 250 * @param channel Selected PMU channel
<> 150:02e0a0aed4ec 251 * @param timeoutClkScale Clk scale use for timeout clk
<> 150:02e0a0aed4ec 252 * @param timeoutTicks Number of ticks for timeout duration
<> 150:02e0a0aed4ec 253 * @returns E_NO_ERROR if everything is successful, error if unsuccessful.
<> 150:02e0a0aed4ec 254 */
<> 150:02e0a0aed4ec 255 int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks);
<> 150:02e0a0aed4ec 256
<> 150:02e0a0aed4ec 257 /**
<> 150:02e0a0aed4ec 258 * @brief Gets the PMU channel's flags
<> 150:02e0a0aed4ec 259 * @param channel Selected PMU channel
<> 150:02e0a0aed4ec 260 * @return 0 = flags not set, non-zero = flags
<> 150:02e0a0aed4ec 261 */
<> 150:02e0a0aed4ec 262 uint32_t PMU_GetFlags(unsigned int channel);
<> 150:02e0a0aed4ec 263
<> 150:02e0a0aed4ec 264 /**
<> 150:02e0a0aed4ec 265 * @brief Clear the PMU channel's flags based on the mask
<> 150:02e0a0aed4ec 266 * @param channel Selected PMU channel
<> 150:02e0a0aed4ec 267 * @param mask bits of the flags to clear
<> 150:02e0a0aed4ec 268 */
<> 150:02e0a0aed4ec 269 void PMU_ClearFlags(unsigned int channel, unsigned int mask);
<> 150:02e0a0aed4ec 270
<> 150:02e0a0aed4ec 271 /**
<> 150:02e0a0aed4ec 272 * @brief Determines if the PMU channel is running
<> 150:02e0a0aed4ec 273 * @param channel Selected PMU channel
<> 150:02e0a0aed4ec 274 * @return 0 = channel is off, non-zero = channel is running
<> 150:02e0a0aed4ec 275 */
<> 150:02e0a0aed4ec 276 uint32_t PMU_IsActive(unsigned int channel);
<> 150:02e0a0aed4ec 277
<> 150:02e0a0aed4ec 278 /**
<> 150:02e0a0aed4ec 279 * @}
<> 150:02e0a0aed4ec 280 */
<> 150:02e0a0aed4ec 281
<> 150:02e0a0aed4ec 282 #ifdef __cplusplus
<> 150:02e0a0aed4ec 283 }
<> 150:02e0a0aed4ec 284 #endif
<> 150:02e0a0aed4ec 285
<> 150:02e0a0aed4ec 286 #endif /* _PMU_H_ */