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targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_sys.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 150:02e0a0aed4ec
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 150:02e0a0aed4ec | 1 | /******************************************************************************* |
<> | 150:02e0a0aed4ec | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
<> | 150:02e0a0aed4ec | 3 | * |
<> | 150:02e0a0aed4ec | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
<> | 150:02e0a0aed4ec | 5 | * copy of this software and associated documentation files (the "Software"), |
<> | 150:02e0a0aed4ec | 6 | * to deal in the Software without restriction, including without limitation |
<> | 150:02e0a0aed4ec | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
<> | 150:02e0a0aed4ec | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
<> | 150:02e0a0aed4ec | 9 | * Software is furnished to do so, subject to the following conditions: |
<> | 150:02e0a0aed4ec | 10 | * |
<> | 150:02e0a0aed4ec | 11 | * The above copyright notice and this permission notice shall be included |
<> | 150:02e0a0aed4ec | 12 | * in all copies or substantial portions of the Software. |
<> | 150:02e0a0aed4ec | 13 | * |
<> | 150:02e0a0aed4ec | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
<> | 150:02e0a0aed4ec | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
<> | 150:02e0a0aed4ec | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
<> | 150:02e0a0aed4ec | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
<> | 150:02e0a0aed4ec | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
<> | 150:02e0a0aed4ec | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
<> | 150:02e0a0aed4ec | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
<> | 150:02e0a0aed4ec | 21 | * |
<> | 150:02e0a0aed4ec | 22 | * Except as contained in this notice, the name of Maxim Integrated |
<> | 150:02e0a0aed4ec | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
<> | 150:02e0a0aed4ec | 24 | * Products, Inc. Branding Policy. |
<> | 150:02e0a0aed4ec | 25 | * |
<> | 150:02e0a0aed4ec | 26 | * The mere transfer of this software does not imply any licenses |
<> | 150:02e0a0aed4ec | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
<> | 150:02e0a0aed4ec | 28 | * trademarks, maskwork rights, or any other form of intellectual |
<> | 150:02e0a0aed4ec | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
<> | 150:02e0a0aed4ec | 30 | * ownership rights. |
<> | 150:02e0a0aed4ec | 31 | * |
<> | 150:02e0a0aed4ec | 32 | * $Date: 2016-06-17 13:05:03 -0500 (Fri, 17 Jun 2016) $ |
<> | 150:02e0a0aed4ec | 33 | * $Revision: 23367 $ |
<> | 150:02e0a0aed4ec | 34 | * |
<> | 150:02e0a0aed4ec | 35 | ******************************************************************************/ |
<> | 150:02e0a0aed4ec | 36 | |
<> | 150:02e0a0aed4ec | 37 | #include <stddef.h> |
<> | 150:02e0a0aed4ec | 38 | #include "mxc_config.h" |
<> | 150:02e0a0aed4ec | 39 | #include "mxc_assert.h" |
<> | 150:02e0a0aed4ec | 40 | #include "mxc_sys.h" |
<> | 150:02e0a0aed4ec | 41 | #include "ioman.h" |
<> | 150:02e0a0aed4ec | 42 | #include "clkman.h" |
<> | 150:02e0a0aed4ec | 43 | #include "pwrseq_regs.h" |
<> | 150:02e0a0aed4ec | 44 | #include "pwrman_regs.h" |
<> | 150:02e0a0aed4ec | 45 | #include "spix_regs.h" |
<> | 150:02e0a0aed4ec | 46 | #include "trim_regs.h" |
<> | 150:02e0a0aed4ec | 47 | |
<> | 150:02e0a0aed4ec | 48 | /***** Definitions *****/ |
<> | 150:02e0a0aed4ec | 49 | #define SYS_RTC_CLK 32768UL |
<> | 150:02e0a0aed4ec | 50 | |
<> | 150:02e0a0aed4ec | 51 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 52 | uint32_t SYS_GetFreq(uint32_t clk_scale) |
<> | 150:02e0a0aed4ec | 53 | { |
<> | 150:02e0a0aed4ec | 54 | uint32_t freq; |
<> | 150:02e0a0aed4ec | 55 | unsigned int clkdiv; |
<> | 150:02e0a0aed4ec | 56 | |
<> | 150:02e0a0aed4ec | 57 | if (clk_scale == MXC_V_CLKMAN_CLK_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 58 | freq = 0; |
<> | 150:02e0a0aed4ec | 59 | } else { |
<> | 150:02e0a0aed4ec | 60 | clkdiv = 1 << (clk_scale - 1); |
<> | 150:02e0a0aed4ec | 61 | freq = SystemCoreClock / clkdiv; |
<> | 150:02e0a0aed4ec | 62 | } |
<> | 150:02e0a0aed4ec | 63 | |
<> | 150:02e0a0aed4ec | 64 | return freq; |
<> | 150:02e0a0aed4ec | 65 | } |
<> | 150:02e0a0aed4ec | 66 | |
<> | 150:02e0a0aed4ec | 67 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 68 | uint32_t SYS_CPU_GetFreq(void) |
<> | 150:02e0a0aed4ec | 69 | { |
<> | 150:02e0a0aed4ec | 70 | return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_CPU)); |
<> | 150:02e0a0aed4ec | 71 | } |
<> | 150:02e0a0aed4ec | 72 | |
<> | 150:02e0a0aed4ec | 73 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 74 | int SYS_ADC_Init(void) |
<> | 150:02e0a0aed4ec | 75 | { |
<> | 150:02e0a0aed4ec | 76 | /* Power up the ADC AFE, enable clocks */ |
<> | 150:02e0a0aed4ec | 77 | MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED; |
<> | 150:02e0a0aed4ec | 78 | MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE; |
<> | 150:02e0a0aed4ec | 79 | |
<> | 150:02e0a0aed4ec | 80 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 81 | } |
<> | 150:02e0a0aed4ec | 82 | |
<> | 150:02e0a0aed4ec | 83 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 84 | int SYS_AES_Init(void) |
<> | 150:02e0a0aed4ec | 85 | { |
<> | 150:02e0a0aed4ec | 86 | /* Set up clocks for AES block */ |
<> | 150:02e0a0aed4ec | 87 | /* Enable crypto ring oscillator, which is used by all TPU components (AES, uMAA, etc.) */ |
<> | 150:02e0a0aed4ec | 88 | CLKMAN_CryptoClockEnable(1); |
<> | 150:02e0a0aed4ec | 89 | |
<> | 150:02e0a0aed4ec | 90 | /* Change prescaler to /1 */ |
<> | 150:02e0a0aed4ec | 91 | CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_AES, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 92 | |
<> | 150:02e0a0aed4ec | 93 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 94 | } |
<> | 150:02e0a0aed4ec | 95 | |
<> | 150:02e0a0aed4ec | 96 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 97 | int SYS_GPIO_Init(void) |
<> | 150:02e0a0aed4ec | 98 | { |
<> | 150:02e0a0aed4ec | 99 | if (CLKMAN_GetClkScale(CLKMAN_CLK_GPIO) == CLKMAN_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 100 | CLKMAN_SetClkScale(CLKMAN_CLK_GPIO, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 101 | } |
<> | 150:02e0a0aed4ec | 102 | |
<> | 150:02e0a0aed4ec | 103 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 104 | } |
<> | 150:02e0a0aed4ec | 105 | |
<> | 150:02e0a0aed4ec | 106 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 107 | int SYS_UART_Init(mxc_uart_regs_t *uart, const uart_cfg_t *uart_cfg, const sys_cfg_uart_t *sys_cfg) |
<> | 150:02e0a0aed4ec | 108 | { |
<> | 150:02e0a0aed4ec | 109 | static int subsequent_call = 0; |
<> | 150:02e0a0aed4ec | 110 | int err, idx; |
<> | 150:02e0a0aed4ec | 111 | clkman_scale_t clk_scale; |
<> | 150:02e0a0aed4ec | 112 | uint32_t min_baud; |
<> | 150:02e0a0aed4ec | 113 | |
<> | 150:02e0a0aed4ec | 114 | if(sys_cfg == NULL) |
<> | 150:02e0a0aed4ec | 115 | return E_NULL_PTR; |
<> | 150:02e0a0aed4ec | 116 | |
<> | 150:02e0a0aed4ec | 117 | if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 118 | CLKMAN_SetClkScale(CLKMAN_CLK_UART, sys_cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 119 | } else if (!subsequent_call) { |
<> | 150:02e0a0aed4ec | 120 | /* This clock divider is shared amongst all UARTs. Only change it if it |
<> | 150:02e0a0aed4ec | 121 | * hasn't already been configured. UART_Init() will check for validity |
<> | 150:02e0a0aed4ec | 122 | * for this baudrate. |
<> | 150:02e0a0aed4ec | 123 | */ |
<> | 150:02e0a0aed4ec | 124 | subsequent_call = 1; |
<> | 150:02e0a0aed4ec | 125 | |
<> | 150:02e0a0aed4ec | 126 | /* Setup the clock divider for the given baud rate */ |
<> | 150:02e0a0aed4ec | 127 | clk_scale = CLKMAN_SCALE_DISABLED; |
<> | 150:02e0a0aed4ec | 128 | do { |
<> | 150:02e0a0aed4ec | 129 | min_baud = ((SystemCoreClock >> clk_scale++) / (16 * (MXC_F_UART_BAUD_BAUD_DIVISOR >> MXC_F_UART_BAUD_BAUD_DIVISOR_POS))); |
<> | 150:02e0a0aed4ec | 130 | } while (uart_cfg->baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO); |
<> | 150:02e0a0aed4ec | 131 | |
<> | 150:02e0a0aed4ec | 132 | /* check if baud rate cannot be reached */ |
<> | 150:02e0a0aed4ec | 133 | if(uart_cfg->baud < min_baud) |
<> | 150:02e0a0aed4ec | 134 | return E_BAD_STATE; |
<> | 150:02e0a0aed4ec | 135 | |
<> | 150:02e0a0aed4ec | 136 | CLKMAN_SetClkScale(CLKMAN_CLK_UART, clk_scale); |
<> | 150:02e0a0aed4ec | 137 | } |
<> | 150:02e0a0aed4ec | 138 | |
<> | 150:02e0a0aed4ec | 139 | if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 140 | return err; |
<> | 150:02e0a0aed4ec | 141 | } |
<> | 150:02e0a0aed4ec | 142 | |
<> | 150:02e0a0aed4ec | 143 | /* Reset the peripheral */ |
<> | 150:02e0a0aed4ec | 144 | idx = MXC_UART_GET_IDX(uart); |
<> | 150:02e0a0aed4ec | 145 | MXC_PWRMAN->peripheral_reset |= (MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx); |
<> | 150:02e0a0aed4ec | 146 | MXC_PWRMAN->peripheral_reset &= ~((MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 << idx)); |
<> | 150:02e0a0aed4ec | 147 | |
<> | 150:02e0a0aed4ec | 148 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 149 | } |
<> | 150:02e0a0aed4ec | 150 | |
<> | 150:02e0a0aed4ec | 151 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 152 | int SYS_UART_Shutdown(mxc_uart_regs_t *uart) |
<> | 150:02e0a0aed4ec | 153 | { |
<> | 150:02e0a0aed4ec | 154 | int err; |
<> | 150:02e0a0aed4ec | 155 | int idx = MXC_UART_GET_IDX(uart); |
<> | 150:02e0a0aed4ec | 156 | ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_UART(idx, 0, 0, 0, 0, 0, 0); |
<> | 150:02e0a0aed4ec | 157 | |
<> | 150:02e0a0aed4ec | 158 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 159 | return err; |
<> | 150:02e0a0aed4ec | 160 | } |
<> | 150:02e0a0aed4ec | 161 | |
<> | 150:02e0a0aed4ec | 162 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 163 | } |
<> | 150:02e0a0aed4ec | 164 | |
<> | 150:02e0a0aed4ec | 165 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 166 | uint32_t SYS_UART_GetFreq(mxc_uart_regs_t *uart) |
<> | 150:02e0a0aed4ec | 167 | { |
<> | 150:02e0a0aed4ec | 168 | return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_UART)); |
<> | 150:02e0a0aed4ec | 169 | } |
<> | 150:02e0a0aed4ec | 170 | |
<> | 150:02e0a0aed4ec | 171 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 172 | int SYS_I2CM_Init(mxc_i2cm_regs_t *i2cm, const sys_cfg_i2cm_t *cfg) |
<> | 150:02e0a0aed4ec | 173 | { |
<> | 150:02e0a0aed4ec | 174 | int err; |
<> | 150:02e0a0aed4ec | 175 | |
<> | 150:02e0a0aed4ec | 176 | if(cfg == NULL) |
<> | 150:02e0a0aed4ec | 177 | return E_NULL_PTR; |
<> | 150:02e0a0aed4ec | 178 | |
<> | 150:02e0a0aed4ec | 179 | CLKMAN_SetClkScale(CLKMAN_CLK_I2CM, cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 180 | MXC_CLKMAN->i2c_timer_ctrl = 1; |
<> | 150:02e0a0aed4ec | 181 | |
<> | 150:02e0a0aed4ec | 182 | if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 183 | return err; |
<> | 150:02e0a0aed4ec | 184 | } |
<> | 150:02e0a0aed4ec | 185 | |
<> | 150:02e0a0aed4ec | 186 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 187 | } |
<> | 150:02e0a0aed4ec | 188 | |
<> | 150:02e0a0aed4ec | 189 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 190 | int SYS_I2CM_Shutdown(mxc_i2cm_regs_t *i2cm) |
<> | 150:02e0a0aed4ec | 191 | { |
<> | 150:02e0a0aed4ec | 192 | int err; |
<> | 150:02e0a0aed4ec | 193 | int idx = MXC_I2CM_GET_IDX(i2cm); |
<> | 150:02e0a0aed4ec | 194 | ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_I2CM(idx, 0, 0); |
<> | 150:02e0a0aed4ec | 195 | |
<> | 150:02e0a0aed4ec | 196 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 197 | return err; |
<> | 150:02e0a0aed4ec | 198 | } |
<> | 150:02e0a0aed4ec | 199 | |
<> | 150:02e0a0aed4ec | 200 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 201 | } |
<> | 150:02e0a0aed4ec | 202 | |
<> | 150:02e0a0aed4ec | 203 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 204 | uint32_t SYS_I2CM_GetFreq(mxc_i2cm_regs_t *i2cm) |
<> | 150:02e0a0aed4ec | 205 | { |
<> | 150:02e0a0aed4ec | 206 | return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_I2CM)); |
<> | 150:02e0a0aed4ec | 207 | } |
<> | 150:02e0a0aed4ec | 208 | |
<> | 150:02e0a0aed4ec | 209 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 210 | int SYS_I2CS_Init(mxc_i2cs_regs_t *i2cs, const sys_cfg_i2cs_t *cfg) |
<> | 150:02e0a0aed4ec | 211 | { |
<> | 150:02e0a0aed4ec | 212 | int err; |
<> | 150:02e0a0aed4ec | 213 | |
<> | 150:02e0a0aed4ec | 214 | if(cfg == NULL) |
<> | 150:02e0a0aed4ec | 215 | return E_NULL_PTR; |
<> | 150:02e0a0aed4ec | 216 | |
<> | 150:02e0a0aed4ec | 217 | CLKMAN_SetClkScale(CLKMAN_CLK_I2CS, cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 218 | MXC_CLKMAN->i2c_timer_ctrl = 1; |
<> | 150:02e0a0aed4ec | 219 | |
<> | 150:02e0a0aed4ec | 220 | if ((err = IOMAN_Config(&cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 221 | return err; |
<> | 150:02e0a0aed4ec | 222 | } |
<> | 150:02e0a0aed4ec | 223 | |
<> | 150:02e0a0aed4ec | 224 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 225 | } |
<> | 150:02e0a0aed4ec | 226 | |
<> | 150:02e0a0aed4ec | 227 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 228 | int SYS_I2CS_Shutdown(mxc_i2cs_regs_t *i2cs) |
<> | 150:02e0a0aed4ec | 229 | { |
<> | 150:02e0a0aed4ec | 230 | int err; |
<> | 150:02e0a0aed4ec | 231 | ioman_cfg_t io_cfg = (ioman_cfg_t)IOMAN_I2CS(0, 0); |
<> | 150:02e0a0aed4ec | 232 | |
<> | 150:02e0a0aed4ec | 233 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 234 | return err; |
<> | 150:02e0a0aed4ec | 235 | } |
<> | 150:02e0a0aed4ec | 236 | |
<> | 150:02e0a0aed4ec | 237 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 238 | } |
<> | 150:02e0a0aed4ec | 239 | |
<> | 150:02e0a0aed4ec | 240 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 241 | uint32_t SYS_I2CS_GetFreq(mxc_i2cs_regs_t *i2cs) |
<> | 150:02e0a0aed4ec | 242 | { |
<> | 150:02e0a0aed4ec | 243 | uint32_t freq, clkdiv; |
<> | 150:02e0a0aed4ec | 244 | |
<> | 150:02e0a0aed4ec | 245 | if (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) == MXC_V_CLKMAN_CLK_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 246 | freq = 0; |
<> | 150:02e0a0aed4ec | 247 | } else { |
<> | 150:02e0a0aed4ec | 248 | clkdiv = 1 << (CLKMAN_GetClkScale(CLKMAN_CLK_I2CS) - 1); |
<> | 150:02e0a0aed4ec | 249 | freq = (SystemCoreClock / clkdiv); |
<> | 150:02e0a0aed4ec | 250 | } |
<> | 150:02e0a0aed4ec | 251 | |
<> | 150:02e0a0aed4ec | 252 | return freq; |
<> | 150:02e0a0aed4ec | 253 | } |
<> | 150:02e0a0aed4ec | 254 | |
<> | 150:02e0a0aed4ec | 255 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 256 | int SYS_SPIM_Init(mxc_spim_regs_t *spim, const spim_cfg_t *spim_cfg, const sys_cfg_spim_t *sys_cfg) |
<> | 150:02e0a0aed4ec | 257 | { |
<> | 150:02e0a0aed4ec | 258 | int err, idx; |
<> | 150:02e0a0aed4ec | 259 | clkman_scale_t clk_scale; |
<> | 150:02e0a0aed4ec | 260 | uint32_t max_baud; |
<> | 150:02e0a0aed4ec | 261 | |
<> | 150:02e0a0aed4ec | 262 | if(sys_cfg == NULL) |
<> | 150:02e0a0aed4ec | 263 | return E_NULL_PTR; |
<> | 150:02e0a0aed4ec | 264 | |
<> | 150:02e0a0aed4ec | 265 | idx = MXC_SPIM_GET_IDX(spim); |
<> | 150:02e0a0aed4ec | 266 | |
<> | 150:02e0a0aed4ec | 267 | if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 268 | if(spim_cfg->baud > ((SystemCoreClock >> (sys_cfg->clk_scale - 1))/2)) { |
<> | 150:02e0a0aed4ec | 269 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 270 | } |
<> | 150:02e0a0aed4ec | 271 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), sys_cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 272 | } else { |
<> | 150:02e0a0aed4ec | 273 | |
<> | 150:02e0a0aed4ec | 274 | if(spim_cfg->baud > (SystemCoreClock/2)) { |
<> | 150:02e0a0aed4ec | 275 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 276 | } |
<> | 150:02e0a0aed4ec | 277 | |
<> | 150:02e0a0aed4ec | 278 | /* Setup the clock divider for the given baud rate */ |
<> | 150:02e0a0aed4ec | 279 | clk_scale = CLKMAN_SCALE_DISABLED; |
<> | 150:02e0a0aed4ec | 280 | do { |
<> | 150:02e0a0aed4ec | 281 | max_baud = ((SystemCoreClock >> clk_scale++) / 2); |
<> | 150:02e0a0aed4ec | 282 | } while (spim_cfg->baud < max_baud && clk_scale < CLKMAN_SCALE_AUTO); |
<> | 150:02e0a0aed4ec | 283 | |
<> | 150:02e0a0aed4ec | 284 | if(clk_scale == CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 285 | clk_scale--; |
<> | 150:02e0a0aed4ec | 286 | } |
<> | 150:02e0a0aed4ec | 287 | |
<> | 150:02e0a0aed4ec | 288 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx), clk_scale); |
<> | 150:02e0a0aed4ec | 289 | } |
<> | 150:02e0a0aed4ec | 290 | |
<> | 150:02e0a0aed4ec | 291 | if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 292 | return err; |
<> | 150:02e0a0aed4ec | 293 | } |
<> | 150:02e0a0aed4ec | 294 | |
<> | 150:02e0a0aed4ec | 295 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 296 | } |
<> | 150:02e0a0aed4ec | 297 | |
<> | 150:02e0a0aed4ec | 298 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 299 | int SYS_SPIM_Shutdown(mxc_spim_regs_t *spim) |
<> | 150:02e0a0aed4ec | 300 | { |
<> | 150:02e0a0aed4ec | 301 | int err; |
<> | 150:02e0a0aed4ec | 302 | int idx = MXC_SPIM_GET_IDX(spim); |
<> | 150:02e0a0aed4ec | 303 | ioman_cfg_t io_cfg; |
<> | 150:02e0a0aed4ec | 304 | |
<> | 150:02e0a0aed4ec | 305 | switch(idx) { |
<> | 150:02e0a0aed4ec | 306 | case 0: |
<> | 150:02e0a0aed4ec | 307 | io_cfg = (ioman_cfg_t)IOMAN_SPIM0(0, 0, 0, 0, 0, 0, 0, 0); |
<> | 150:02e0a0aed4ec | 308 | break; |
<> | 150:02e0a0aed4ec | 309 | case 1: |
<> | 150:02e0a0aed4ec | 310 | io_cfg = (ioman_cfg_t)IOMAN_SPIM1(0, 0, 0, 0, 0, 0); |
<> | 150:02e0a0aed4ec | 311 | break; |
<> | 150:02e0a0aed4ec | 312 | case 2: |
<> | 150:02e0a0aed4ec | 313 | io_cfg = (ioman_cfg_t)IOMAN_SPIM2(0, 0, 0, 0, 0, 0, 0, 0); |
<> | 150:02e0a0aed4ec | 314 | break; |
<> | 150:02e0a0aed4ec | 315 | default: |
<> | 150:02e0a0aed4ec | 316 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 317 | } |
<> | 150:02e0a0aed4ec | 318 | |
<> | 150:02e0a0aed4ec | 319 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 320 | return err; |
<> | 150:02e0a0aed4ec | 321 | } |
<> | 150:02e0a0aed4ec | 322 | |
<> | 150:02e0a0aed4ec | 323 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 324 | } |
<> | 150:02e0a0aed4ec | 325 | |
<> | 150:02e0a0aed4ec | 326 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 327 | uint32_t SYS_SPIM_GetFreq(mxc_spim_regs_t *spim) |
<> | 150:02e0a0aed4ec | 328 | { |
<> | 150:02e0a0aed4ec | 329 | int idx = MXC_SPIM_GET_IDX(spim); |
<> | 150:02e0a0aed4ec | 330 | return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIM0 + idx))); |
<> | 150:02e0a0aed4ec | 331 | } |
<> | 150:02e0a0aed4ec | 332 | |
<> | 150:02e0a0aed4ec | 333 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 334 | int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud) |
<> | 150:02e0a0aed4ec | 335 | { |
<> | 150:02e0a0aed4ec | 336 | int err; |
<> | 150:02e0a0aed4ec | 337 | clkman_scale_t clk_scale; |
<> | 150:02e0a0aed4ec | 338 | uint32_t min_baud; |
<> | 150:02e0a0aed4ec | 339 | |
<> | 150:02e0a0aed4ec | 340 | if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 341 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), sys_cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 342 | } else { |
<> | 150:02e0a0aed4ec | 343 | /* Setup the clock divider for the given baud rate */ |
<> | 150:02e0a0aed4ec | 344 | clk_scale = CLKMAN_SCALE_DISABLED; |
<> | 150:02e0a0aed4ec | 345 | do { |
<> | 150:02e0a0aed4ec | 346 | min_baud = ((SystemCoreClock >> clk_scale++) / (2 * |
<> | 150:02e0a0aed4ec | 347 | (MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK >> MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS))); |
<> | 150:02e0a0aed4ec | 348 | } while (baud < min_baud && clk_scale < CLKMAN_SCALE_AUTO); |
<> | 150:02e0a0aed4ec | 349 | |
<> | 150:02e0a0aed4ec | 350 | /* check if baud rate cannot be reached */ |
<> | 150:02e0a0aed4ec | 351 | if(baud < min_baud) |
<> | 150:02e0a0aed4ec | 352 | return E_BAD_STATE; |
<> | 150:02e0a0aed4ec | 353 | |
<> | 150:02e0a0aed4ec | 354 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX), clk_scale); |
<> | 150:02e0a0aed4ec | 355 | } |
<> | 150:02e0a0aed4ec | 356 | |
<> | 150:02e0a0aed4ec | 357 | if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 358 | return err; |
<> | 150:02e0a0aed4ec | 359 | } |
<> | 150:02e0a0aed4ec | 360 | |
<> | 150:02e0a0aed4ec | 361 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 362 | } |
<> | 150:02e0a0aed4ec | 363 | |
<> | 150:02e0a0aed4ec | 364 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 365 | int SYS_SPIX_Shutdown(void) |
<> | 150:02e0a0aed4ec | 366 | { |
<> | 150:02e0a0aed4ec | 367 | int err; |
<> | 150:02e0a0aed4ec | 368 | ioman_cfg_t io_cfg = IOMAN_SPIX(0, 0, 0, 0, 0, 0); |
<> | 150:02e0a0aed4ec | 369 | |
<> | 150:02e0a0aed4ec | 370 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 371 | return err; |
<> | 150:02e0a0aed4ec | 372 | } |
<> | 150:02e0a0aed4ec | 373 | |
<> | 150:02e0a0aed4ec | 374 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 375 | } |
<> | 150:02e0a0aed4ec | 376 | |
<> | 150:02e0a0aed4ec | 377 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 378 | uint32_t SYS_SPIX_GetFreq(void) |
<> | 150:02e0a0aed4ec | 379 | { |
<> | 150:02e0a0aed4ec | 380 | return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIX))); |
<> | 150:02e0a0aed4ec | 381 | } |
<> | 150:02e0a0aed4ec | 382 | |
<> | 150:02e0a0aed4ec | 383 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 384 | int SYS_SPIS_Init(const sys_cfg_spis_t *sys_cfg) |
<> | 150:02e0a0aed4ec | 385 | { |
<> | 150:02e0a0aed4ec | 386 | int err; |
<> | 150:02e0a0aed4ec | 387 | |
<> | 150:02e0a0aed4ec | 388 | if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 389 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIS), sys_cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 390 | } else { |
<> | 150:02e0a0aed4ec | 391 | CLKMAN_SetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIS), CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 392 | } |
<> | 150:02e0a0aed4ec | 393 | |
<> | 150:02e0a0aed4ec | 394 | if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 395 | return err; |
<> | 150:02e0a0aed4ec | 396 | } |
<> | 150:02e0a0aed4ec | 397 | |
<> | 150:02e0a0aed4ec | 398 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 399 | } |
<> | 150:02e0a0aed4ec | 400 | |
<> | 150:02e0a0aed4ec | 401 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 402 | int SYS_SPIS_Shutdown(mxc_spis_regs_t *spis) |
<> | 150:02e0a0aed4ec | 403 | { |
<> | 150:02e0a0aed4ec | 404 | int err; |
<> | 150:02e0a0aed4ec | 405 | ioman_cfg_t io_cfg = IOMAN_SPIS(0, 0, 0); |
<> | 150:02e0a0aed4ec | 406 | |
<> | 150:02e0a0aed4ec | 407 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 408 | return err; |
<> | 150:02e0a0aed4ec | 409 | } |
<> | 150:02e0a0aed4ec | 410 | |
<> | 150:02e0a0aed4ec | 411 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 412 | } |
<> | 150:02e0a0aed4ec | 413 | |
<> | 150:02e0a0aed4ec | 414 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 415 | uint32_t SYS_SPIS_GetFreq(mxc_spis_regs_t *spis) |
<> | 150:02e0a0aed4ec | 416 | { |
<> | 150:02e0a0aed4ec | 417 | return SYS_GetFreq(CLKMAN_GetClkScale((clkman_clk_t)(CLKMAN_CLK_SPIS))); |
<> | 150:02e0a0aed4ec | 418 | } |
<> | 150:02e0a0aed4ec | 419 | |
<> | 150:02e0a0aed4ec | 420 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 421 | int SYS_OWM_Init(mxc_owm_regs_t *owm, const sys_cfg_owm_t *sys_cfg) |
<> | 150:02e0a0aed4ec | 422 | { |
<> | 150:02e0a0aed4ec | 423 | int err; |
<> | 150:02e0a0aed4ec | 424 | |
<> | 150:02e0a0aed4ec | 425 | if(sys_cfg == NULL) |
<> | 150:02e0a0aed4ec | 426 | return E_NULL_PTR; |
<> | 150:02e0a0aed4ec | 427 | |
<> | 150:02e0a0aed4ec | 428 | if (sys_cfg->clk_scale != CLKMAN_SCALE_AUTO) { |
<> | 150:02e0a0aed4ec | 429 | CLKMAN_SetClkScale(CLKMAN_CLK_OWM, sys_cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 430 | } else { |
<> | 150:02e0a0aed4ec | 431 | CLKMAN_SetClkScale(CLKMAN_CLK_OWM, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 432 | } |
<> | 150:02e0a0aed4ec | 433 | |
<> | 150:02e0a0aed4ec | 434 | if ((err = IOMAN_Config(&sys_cfg->io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 435 | return err; |
<> | 150:02e0a0aed4ec | 436 | } |
<> | 150:02e0a0aed4ec | 437 | |
<> | 150:02e0a0aed4ec | 438 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 439 | } |
<> | 150:02e0a0aed4ec | 440 | |
<> | 150:02e0a0aed4ec | 441 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 442 | int SYS_OWM_Shutdown(mxc_owm_regs_t *owm) |
<> | 150:02e0a0aed4ec | 443 | { |
<> | 150:02e0a0aed4ec | 444 | int err; |
<> | 150:02e0a0aed4ec | 445 | |
<> | 150:02e0a0aed4ec | 446 | ioman_cfg_t io_cfg = IOMAN_OWM(0, 0); |
<> | 150:02e0a0aed4ec | 447 | |
<> | 150:02e0a0aed4ec | 448 | if ((err = IOMAN_Config(&io_cfg)) != E_NO_ERROR) { |
<> | 150:02e0a0aed4ec | 449 | return err; |
<> | 150:02e0a0aed4ec | 450 | } |
<> | 150:02e0a0aed4ec | 451 | |
<> | 150:02e0a0aed4ec | 452 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 453 | } |
<> | 150:02e0a0aed4ec | 454 | |
<> | 150:02e0a0aed4ec | 455 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 456 | uint32_t SYS_OWM_GetFreq(mxc_owm_regs_t *owm) |
<> | 150:02e0a0aed4ec | 457 | { |
<> | 150:02e0a0aed4ec | 458 | return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_OWM)); |
<> | 150:02e0a0aed4ec | 459 | } |
<> | 150:02e0a0aed4ec | 460 | |
<> | 150:02e0a0aed4ec | 461 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 462 | uint32_t SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr) |
<> | 150:02e0a0aed4ec | 463 | { |
<> | 150:02e0a0aed4ec | 464 | return SystemCoreClock; |
<> | 150:02e0a0aed4ec | 465 | } |
<> | 150:02e0a0aed4ec | 466 | |
<> | 150:02e0a0aed4ec | 467 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 468 | int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t *cfg) |
<> | 150:02e0a0aed4ec | 469 | { |
<> | 150:02e0a0aed4ec | 470 | int pin, gpio_index, tmr_index; |
<> | 150:02e0a0aed4ec | 471 | |
<> | 150:02e0a0aed4ec | 472 | if (cfg != NULL) { |
<> | 150:02e0a0aed4ec | 473 | /* Make sure the given GPIO mapps to the given TMR */ |
<> | 150:02e0a0aed4ec | 474 | for (pin = 0; pin < MXC_GPIO_MAX_PINS_PER_PORT; pin++) { |
<> | 150:02e0a0aed4ec | 475 | if(cfg->mask & (1 << pin)) { |
<> | 150:02e0a0aed4ec | 476 | gpio_index = (MXC_GPIO_MAX_PINS_PER_PORT * cfg->port) + pin; |
<> | 150:02e0a0aed4ec | 477 | tmr_index = gpio_index % MXC_CFG_TMR_INSTANCES; |
<> | 150:02e0a0aed4ec | 478 | |
<> | 150:02e0a0aed4ec | 479 | if(tmr_index == MXC_TMR_GET_IDX(tmr)) |
<> | 150:02e0a0aed4ec | 480 | return GPIO_Config(cfg); |
<> | 150:02e0a0aed4ec | 481 | else |
<> | 150:02e0a0aed4ec | 482 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 483 | } |
<> | 150:02e0a0aed4ec | 484 | } |
<> | 150:02e0a0aed4ec | 485 | |
<> | 150:02e0a0aed4ec | 486 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 487 | |
<> | 150:02e0a0aed4ec | 488 | } else { |
<> | 150:02e0a0aed4ec | 489 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 490 | } |
<> | 150:02e0a0aed4ec | 491 | } |
<> | 150:02e0a0aed4ec | 492 | |
<> | 150:02e0a0aed4ec | 493 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 494 | uint32_t SYS_SysTick_GetFreq(void) |
<> | 150:02e0a0aed4ec | 495 | { |
<> | 150:02e0a0aed4ec | 496 | /* Determine is using internal (SystemCoreClock) or external (32768) clock */ |
<> | 150:02e0a0aed4ec | 497 | if ( (SysTick->CTRL & SysTick_CTRL_CLKSOURCE_Msk) || !(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { |
<> | 150:02e0a0aed4ec | 498 | return SystemCoreClock; |
<> | 150:02e0a0aed4ec | 499 | } else { |
<> | 150:02e0a0aed4ec | 500 | return SYS_RTC_CLK; |
<> | 150:02e0a0aed4ec | 501 | } |
<> | 150:02e0a0aed4ec | 502 | } |
<> | 150:02e0a0aed4ec | 503 | |
<> | 150:02e0a0aed4ec | 504 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 505 | uint32_t SYS_PT_GetFreq(void) |
<> | 150:02e0a0aed4ec | 506 | { |
<> | 150:02e0a0aed4ec | 507 | return SYS_GetFreq(CLKMAN_GetClkScale(CLKMAN_CLK_PT)); |
<> | 150:02e0a0aed4ec | 508 | } |
<> | 150:02e0a0aed4ec | 509 | |
<> | 150:02e0a0aed4ec | 510 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 511 | void SYS_PT_Init(sys_pt_clk_scale clk_scale) |
<> | 150:02e0a0aed4ec | 512 | { |
<> | 150:02e0a0aed4ec | 513 | /* setup clock divider for pulse train clock */ |
<> | 150:02e0a0aed4ec | 514 | CLKMAN_SetClkScale(CLKMAN_CLK_PT, clk_scale); |
<> | 150:02e0a0aed4ec | 515 | } |
<> | 150:02e0a0aed4ec | 516 | |
<> | 150:02e0a0aed4ec | 517 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 518 | int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg) |
<> | 150:02e0a0aed4ec | 519 | { |
<> | 150:02e0a0aed4ec | 520 | int pt_index; |
<> | 150:02e0a0aed4ec | 521 | |
<> | 150:02e0a0aed4ec | 522 | /* Make sure the given GPIO mapps to the given PT */ |
<> | 150:02e0a0aed4ec | 523 | pt_index = MXC_PT_GET_IDX(pt); |
<> | 150:02e0a0aed4ec | 524 | if(pt_index < 0) { |
<> | 150:02e0a0aed4ec | 525 | return E_NOT_SUPPORTED; |
<> | 150:02e0a0aed4ec | 526 | } |
<> | 150:02e0a0aed4ec | 527 | |
<> | 150:02e0a0aed4ec | 528 | /* Even number port */ |
<> | 150:02e0a0aed4ec | 529 | if(cfg->port%2 == 0) { |
<> | 150:02e0a0aed4ec | 530 | /* Pin number should match PT number */ |
<> | 150:02e0a0aed4ec | 531 | if(!(cfg->mask & (0x1 << pt_index))) { |
<> | 150:02e0a0aed4ec | 532 | return E_NOT_SUPPORTED; |
<> | 150:02e0a0aed4ec | 533 | } |
<> | 150:02e0a0aed4ec | 534 | } else { |
<> | 150:02e0a0aed4ec | 535 | /* Pin number+8 should match PT */ |
<> | 150:02e0a0aed4ec | 536 | if(!((cfg->mask << 8) & (0x1 << pt_index))) { |
<> | 150:02e0a0aed4ec | 537 | return E_NOT_SUPPORTED; |
<> | 150:02e0a0aed4ec | 538 | } |
<> | 150:02e0a0aed4ec | 539 | } |
<> | 150:02e0a0aed4ec | 540 | |
<> | 150:02e0a0aed4ec | 541 | return GPIO_Config(cfg); |
<> | 150:02e0a0aed4ec | 542 | } |
<> | 150:02e0a0aed4ec | 543 | |
<> | 150:02e0a0aed4ec | 544 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 545 | void SYS_USB_Enable(uint8_t enable) |
<> | 150:02e0a0aed4ec | 546 | { |
<> | 150:02e0a0aed4ec | 547 | /* Enable USB clock */ |
<> | 150:02e0a0aed4ec | 548 | CLKMAN_ClockGate(CLKMAN_USB_CLOCK, enable); |
<> | 150:02e0a0aed4ec | 549 | |
<> | 150:02e0a0aed4ec | 550 | if(enable) { |
<> | 150:02e0a0aed4ec | 551 | /* Enable USB Power */ |
<> | 150:02e0a0aed4ec | 552 | MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED; |
<> | 150:02e0a0aed4ec | 553 | } else { |
<> | 150:02e0a0aed4ec | 554 | /* Disable USB Power */ |
<> | 150:02e0a0aed4ec | 555 | MXC_PWRMAN->pwr_rst_ctrl &= ~MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED; |
<> | 150:02e0a0aed4ec | 556 | } |
<> | 150:02e0a0aed4ec | 557 | } |
<> | 150:02e0a0aed4ec | 558 | |
<> | 150:02e0a0aed4ec | 559 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 560 | int SYS_SysTick_Config(uint32_t ticks, int clk_src) |
<> | 150:02e0a0aed4ec | 561 | { |
<> | 150:02e0a0aed4ec | 562 | |
<> | 150:02e0a0aed4ec | 563 | if(ticks == 0) |
<> | 150:02e0a0aed4ec | 564 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 565 | |
<> | 150:02e0a0aed4ec | 566 | /* If SystemClock, call default CMSIS config and return */ |
<> | 150:02e0a0aed4ec | 567 | if (clk_src) { |
<> | 150:02e0a0aed4ec | 568 | return SysTick_Config(ticks); |
<> | 150:02e0a0aed4ec | 569 | } else { |
<> | 150:02e0a0aed4ec | 570 | /* External clock source requested |
<> | 150:02e0a0aed4ec | 571 | enable RTC clock in run mode*/ |
<> | 150:02e0a0aed4ec | 572 | MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN); |
<> | 150:02e0a0aed4ec | 573 | |
<> | 150:02e0a0aed4ec | 574 | /* Disable SysTick Timer */ |
<> | 150:02e0a0aed4ec | 575 | SysTick->CTRL = 0; |
<> | 150:02e0a0aed4ec | 576 | /* Check reload value for valid */ |
<> | 150:02e0a0aed4ec | 577 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) { |
<> | 150:02e0a0aed4ec | 578 | /* Reload value impossible */ |
<> | 150:02e0a0aed4ec | 579 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 580 | } |
<> | 150:02e0a0aed4ec | 581 | /* set reload register */ |
<> | 150:02e0a0aed4ec | 582 | SysTick->LOAD = ticks - 1; |
<> | 150:02e0a0aed4ec | 583 | |
<> | 150:02e0a0aed4ec | 584 | /* set Priority for Systick Interrupt */ |
<> | 150:02e0a0aed4ec | 585 | NVIC_SetPriority(SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); |
<> | 150:02e0a0aed4ec | 586 | |
<> | 150:02e0a0aed4ec | 587 | /* Load the SysTick Counter Value */ |
<> | 150:02e0a0aed4ec | 588 | SysTick->VAL = 0; |
<> | 150:02e0a0aed4ec | 589 | |
<> | 150:02e0a0aed4ec | 590 | /* Enable SysTick IRQ and SysTick Timer leaving clock source as external */ |
<> | 150:02e0a0aed4ec | 591 | SysTick->CTRL = SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; |
<> | 150:02e0a0aed4ec | 592 | |
<> | 150:02e0a0aed4ec | 593 | /* Function successful */ |
<> | 150:02e0a0aed4ec | 594 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 595 | } |
<> | 150:02e0a0aed4ec | 596 | } |
<> | 150:02e0a0aed4ec | 597 | |
<> | 150:02e0a0aed4ec | 598 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 599 | int SYS_SysTick_Delay(uint32_t ticks) |
<> | 150:02e0a0aed4ec | 600 | { |
<> | 150:02e0a0aed4ec | 601 | uint32_t cur_ticks, num_full, num_remain, previous_ticks, num_subtract, i; |
<> | 150:02e0a0aed4ec | 602 | uint32_t reload, value, ctrl; /* save/restore variables */ |
<> | 150:02e0a0aed4ec | 603 | |
<> | 150:02e0a0aed4ec | 604 | if(ticks == 0) |
<> | 150:02e0a0aed4ec | 605 | return E_BAD_PARAM; |
<> | 150:02e0a0aed4ec | 606 | |
<> | 150:02e0a0aed4ec | 607 | /* If SysTick is not enabled we can take it for our delay */ |
<> | 150:02e0a0aed4ec | 608 | if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)) { |
<> | 150:02e0a0aed4ec | 609 | |
<> | 150:02e0a0aed4ec | 610 | /* Save current state in case it's disabled but already configured, restore at return.*/ |
<> | 150:02e0a0aed4ec | 611 | reload = SysTick->LOAD; |
<> | 150:02e0a0aed4ec | 612 | value = SysTick->VAL; |
<> | 150:02e0a0aed4ec | 613 | ctrl = SysTick->CTRL; |
<> | 150:02e0a0aed4ec | 614 | |
<> | 150:02e0a0aed4ec | 615 | /* get the number of ticks less than max RELOAD. */ |
<> | 150:02e0a0aed4ec | 616 | num_remain = ticks % SysTick_LOAD_RELOAD_Msk; |
<> | 150:02e0a0aed4ec | 617 | |
<> | 150:02e0a0aed4ec | 618 | /* if ticks is < Max SysTick Reload num_full will be 0, otherwise it will |
<> | 150:02e0a0aed4ec | 619 | give us the number of max SysTicks cycles required */ |
<> | 150:02e0a0aed4ec | 620 | num_full = (ticks - 1) / SysTick_LOAD_RELOAD_Msk; |
<> | 150:02e0a0aed4ec | 621 | |
<> | 150:02e0a0aed4ec | 622 | /* Do the required full systick countdowns */ |
<> | 150:02e0a0aed4ec | 623 | if (num_full) { |
<> | 150:02e0a0aed4ec | 624 | /* load the max count value into systick */ |
<> | 150:02e0a0aed4ec | 625 | SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; |
<> | 150:02e0a0aed4ec | 626 | /* load the starting value */ |
<> | 150:02e0a0aed4ec | 627 | SysTick->VAL = 0; |
<> | 150:02e0a0aed4ec | 628 | /*enable SysTick counter with SystemClock source internal, immediately forces LOAD register into VAL register */ |
<> | 150:02e0a0aed4ec | 629 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; |
<> | 150:02e0a0aed4ec | 630 | /* CountFlag will get set when VAL reaches zero */ |
<> | 150:02e0a0aed4ec | 631 | for (i = num_full; i > 0; i--) { |
<> | 150:02e0a0aed4ec | 632 | do { |
<> | 150:02e0a0aed4ec | 633 | cur_ticks = SysTick->CTRL; |
<> | 150:02e0a0aed4ec | 634 | } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); |
<> | 150:02e0a0aed4ec | 635 | } |
<> | 150:02e0a0aed4ec | 636 | /* Disable systick */ |
<> | 150:02e0a0aed4ec | 637 | SysTick->CTRL = 0; |
<> | 150:02e0a0aed4ec | 638 | } |
<> | 150:02e0a0aed4ec | 639 | /* Now handle the remainder of ticks */ |
<> | 150:02e0a0aed4ec | 640 | if (num_remain) { |
<> | 150:02e0a0aed4ec | 641 | SysTick->LOAD = num_remain; |
<> | 150:02e0a0aed4ec | 642 | SysTick->VAL = 0; |
<> | 150:02e0a0aed4ec | 643 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; |
<> | 150:02e0a0aed4ec | 644 | /* wait for countflag to get set */ |
<> | 150:02e0a0aed4ec | 645 | do { |
<> | 150:02e0a0aed4ec | 646 | cur_ticks = SysTick->CTRL; |
<> | 150:02e0a0aed4ec | 647 | } while (!(cur_ticks & SysTick_CTRL_COUNTFLAG_Msk)); |
<> | 150:02e0a0aed4ec | 648 | /* Disable systick */ |
<> | 150:02e0a0aed4ec | 649 | SysTick->CTRL = 0; |
<> | 150:02e0a0aed4ec | 650 | } |
<> | 150:02e0a0aed4ec | 651 | |
<> | 150:02e0a0aed4ec | 652 | /* restore original state of SysTick and return */ |
<> | 150:02e0a0aed4ec | 653 | SysTick->LOAD = reload; |
<> | 150:02e0a0aed4ec | 654 | SysTick->VAL = value; |
<> | 150:02e0a0aed4ec | 655 | SysTick->CTRL = ctrl; |
<> | 150:02e0a0aed4ec | 656 | |
<> | 150:02e0a0aed4ec | 657 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 658 | |
<> | 150:02e0a0aed4ec | 659 | } else { |
<> | 150:02e0a0aed4ec | 660 | /* SysTick is enabled |
<> | 150:02e0a0aed4ec | 661 | When SysTick is enabled count flag can not be used |
<> | 150:02e0a0aed4ec | 662 | and the reload can not be changed. |
<> | 150:02e0a0aed4ec | 663 | Do not read the CTRL register -> clears count flag */ |
<> | 150:02e0a0aed4ec | 664 | |
<> | 150:02e0a0aed4ec | 665 | /* Get the reload value for wrap/reload case */ |
<> | 150:02e0a0aed4ec | 666 | reload = SysTick->LOAD; |
<> | 150:02e0a0aed4ec | 667 | |
<> | 150:02e0a0aed4ec | 668 | /* Read the starting systick value */ |
<> | 150:02e0a0aed4ec | 669 | previous_ticks = SysTick->VAL; |
<> | 150:02e0a0aed4ec | 670 | |
<> | 150:02e0a0aed4ec | 671 | do { |
<> | 150:02e0a0aed4ec | 672 | /* get current SysTick value */ |
<> | 150:02e0a0aed4ec | 673 | cur_ticks = SysTick->VAL; |
<> | 150:02e0a0aed4ec | 674 | /* Check for wrap/reload of timer countval */ |
<> | 150:02e0a0aed4ec | 675 | if (cur_ticks > previous_ticks) { |
<> | 150:02e0a0aed4ec | 676 | /* subtract count to 0 (previous_ticks) and wrap (reload value - cur_ticks) */ |
<> | 150:02e0a0aed4ec | 677 | num_subtract = (previous_ticks + (reload - cur_ticks)); |
<> | 150:02e0a0aed4ec | 678 | } else { |
<> | 150:02e0a0aed4ec | 679 | /* standard case (no wrap) |
<> | 150:02e0a0aed4ec | 680 | subtract off the number of ticks since last pass */ |
<> | 150:02e0a0aed4ec | 681 | num_subtract = (previous_ticks - cur_ticks); |
<> | 150:02e0a0aed4ec | 682 | } |
<> | 150:02e0a0aed4ec | 683 | /* check to see if we are done. */ |
<> | 150:02e0a0aed4ec | 684 | if (num_subtract >= ticks) |
<> | 150:02e0a0aed4ec | 685 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 686 | else |
<> | 150:02e0a0aed4ec | 687 | ticks -= num_subtract; |
<> | 150:02e0a0aed4ec | 688 | /* cur_ticks becomes previous_ticks for next timer read. */ |
<> | 150:02e0a0aed4ec | 689 | previous_ticks = cur_ticks; |
<> | 150:02e0a0aed4ec | 690 | } while (ticks > 0); |
<> | 150:02e0a0aed4ec | 691 | /* Should not ever be reached */ |
<> | 150:02e0a0aed4ec | 692 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 693 | } |
<> | 150:02e0a0aed4ec | 694 | } |
<> | 150:02e0a0aed4ec | 695 | |
<> | 150:02e0a0aed4ec | 696 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 697 | int SYS_RTC_Init(void) |
<> | 150:02e0a0aed4ec | 698 | { |
<> | 150:02e0a0aed4ec | 699 | /* Enable power for RTC for all LPx states */ |
<> | 150:02e0a0aed4ec | 700 | MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | |
<> | 150:02e0a0aed4ec | 701 | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP); |
<> | 150:02e0a0aed4ec | 702 | |
<> | 150:02e0a0aed4ec | 703 | /* Enable clock to synchronizers */ |
<> | 150:02e0a0aed4ec | 704 | CLKMAN_SetClkScale(CLKMAN_CLK_SYNC, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 705 | |
<> | 150:02e0a0aed4ec | 706 | return E_NO_ERROR; |
<> | 150:02e0a0aed4ec | 707 | } |
<> | 150:02e0a0aed4ec | 708 | |
<> | 150:02e0a0aed4ec | 709 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 710 | void SYS_IOMAN_UseVDDIO(const gpio_cfg_t *cfg) |
<> | 150:02e0a0aed4ec | 711 | { |
<> | 150:02e0a0aed4ec | 712 | unsigned int startbit = (cfg->port * 8); |
<> | 150:02e0a0aed4ec | 713 | volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32); |
<> | 150:02e0a0aed4ec | 714 | *use_vddioh_reg &= ~cfg->mask << (startbit % 32); |
<> | 150:02e0a0aed4ec | 715 | } |
<> | 150:02e0a0aed4ec | 716 | |
<> | 150:02e0a0aed4ec | 717 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 718 | void SYS_IOMAN_UseVDDIOH(const gpio_cfg_t *cfg) |
<> | 150:02e0a0aed4ec | 719 | { |
<> | 150:02e0a0aed4ec | 720 | unsigned int startbit = (cfg->port * 8); |
<> | 150:02e0a0aed4ec | 721 | volatile uint32_t *use_vddioh_reg = &MXC_IOMAN->use_vddioh_0 + (startbit / 32); |
<> | 150:02e0a0aed4ec | 722 | *use_vddioh_reg |= cfg->mask << (startbit % 32); |
<> | 150:02e0a0aed4ec | 723 | } |
<> | 150:02e0a0aed4ec | 724 | |
<> | 150:02e0a0aed4ec | 725 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 726 | void SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t *cfg) |
<> | 150:02e0a0aed4ec | 727 | { |
<> | 150:02e0a0aed4ec | 728 | |
<> | 150:02e0a0aed4ec | 729 | if(cfg->clk == CLKMAN_WDT_SELECT_NANO_RING_OSCILLATOR) { |
<> | 150:02e0a0aed4ec | 730 | /*enable nanoring in run mode */ |
<> | 150:02e0a0aed4ec | 731 | MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_NREN_RUN); |
<> | 150:02e0a0aed4ec | 732 | } else if(cfg->clk == CLKMAN_WDT_SELECT_32KHZ_RTC_OSCILLATOR) { |
<> | 150:02e0a0aed4ec | 733 | /*enabled RTC in run mode */ |
<> | 150:02e0a0aed4ec | 734 | MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN); |
<> | 150:02e0a0aed4ec | 735 | } |
<> | 150:02e0a0aed4ec | 736 | |
<> | 150:02e0a0aed4ec | 737 | if(wdt == MXC_WDT0) { |
<> | 150:02e0a0aed4ec | 738 | /*select clock source */ |
<> | 150:02e0a0aed4ec | 739 | CLKMAN_WdtClkSelect(0, cfg->clk); |
<> | 150:02e0a0aed4ec | 740 | |
<> | 150:02e0a0aed4ec | 741 | /*Set scale of clock (only used for system clock as source) */ |
<> | 150:02e0a0aed4ec | 742 | CLKMAN_SetClkScale(CLKMAN_CLK_WDT0, cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 743 | |
<> | 150:02e0a0aed4ec | 744 | /*Enable clock */ |
<> | 150:02e0a0aed4ec | 745 | CLKMAN_ClockGate(CLKMAN_WDT0_CLOCK, 1); |
<> | 150:02e0a0aed4ec | 746 | } else if (wdt == MXC_WDT1) { |
<> | 150:02e0a0aed4ec | 747 | /*select clock source */ |
<> | 150:02e0a0aed4ec | 748 | CLKMAN_WdtClkSelect(1, cfg->clk); |
<> | 150:02e0a0aed4ec | 749 | |
<> | 150:02e0a0aed4ec | 750 | /*Set scale of clock (only used for system clock as source) */ |
<> | 150:02e0a0aed4ec | 751 | CLKMAN_SetClkScale(CLKMAN_CLK_WDT1, cfg->clk_scale); |
<> | 150:02e0a0aed4ec | 752 | |
<> | 150:02e0a0aed4ec | 753 | /*Enable clock */ |
<> | 150:02e0a0aed4ec | 754 | CLKMAN_ClockGate(CLKMAN_WDT1_CLOCK, 1); |
<> | 150:02e0a0aed4ec | 755 | } |
<> | 150:02e0a0aed4ec | 756 | } |
<> | 150:02e0a0aed4ec | 757 | |
<> | 150:02e0a0aed4ec | 758 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 759 | void SYS_PRNG_Init(void) |
<> | 150:02e0a0aed4ec | 760 | { |
<> | 150:02e0a0aed4ec | 761 | /* Start crypto ring, unconditionally */ |
<> | 150:02e0a0aed4ec | 762 | CLKMAN_CryptoClockEnable(1); |
<> | 150:02e0a0aed4ec | 763 | |
<> | 150:02e0a0aed4ec | 764 | /* If we find the dividers in anything other than off, don't touch them */ |
<> | 150:02e0a0aed4ec | 765 | if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_PRNG) == CLKMAN_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 766 | /* Div 1 mode */ |
<> | 150:02e0a0aed4ec | 767 | CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_PRNG, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 768 | } |
<> | 150:02e0a0aed4ec | 769 | |
<> | 150:02e0a0aed4ec | 770 | if (CLKMAN_GetClkScale(CLKMAN_CLK_PRNG) == CLKMAN_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 771 | /* Div 1 mode */ |
<> | 150:02e0a0aed4ec | 772 | CLKMAN_SetClkScale(CLKMAN_CLK_PRNG, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 773 | } |
<> | 150:02e0a0aed4ec | 774 | } |
<> | 150:02e0a0aed4ec | 775 | |
<> | 150:02e0a0aed4ec | 776 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 777 | void SYS_MAA_Init(void) |
<> | 150:02e0a0aed4ec | 778 | { |
<> | 150:02e0a0aed4ec | 779 | /* Start crypto ring, unconditionally */ |
<> | 150:02e0a0aed4ec | 780 | CLKMAN_CryptoClockEnable(1); |
<> | 150:02e0a0aed4ec | 781 | |
<> | 150:02e0a0aed4ec | 782 | /* If we find the dividers in anything other than off, don't touch them */ |
<> | 150:02e0a0aed4ec | 783 | if (CLKMAN_GetClkScale(CLKMAN_CRYPTO_CLK_MAA) == CLKMAN_SCALE_DISABLED) { |
<> | 150:02e0a0aed4ec | 784 | /* Div 1 mode */ |
<> | 150:02e0a0aed4ec | 785 | CLKMAN_SetClkScale(CLKMAN_CRYPTO_CLK_MAA, CLKMAN_SCALE_DIV_1); |
<> | 150:02e0a0aed4ec | 786 | } |
<> | 150:02e0a0aed4ec | 787 | } |
<> | 150:02e0a0aed4ec | 788 | |
<> | 150:02e0a0aed4ec | 789 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 790 | uint32_t SYS_SRAM_GetSize(void) |
<> | 150:02e0a0aed4ec | 791 | { |
<> | 150:02e0a0aed4ec | 792 | uint32_t memSize; |
<> | 150:02e0a0aed4ec | 793 | |
<> | 150:02e0a0aed4ec | 794 | /* Read TRIM value*/ |
<> | 150:02e0a0aed4ec | 795 | int SRAMtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_SRAM) >> MXC_F_TRIM_REG10_MEM_SIZE_SRAM_POS; |
<> | 150:02e0a0aed4ec | 796 | |
<> | 150:02e0a0aed4ec | 797 | /* Decode trim value into memory size in bytes */ |
<> | 150:02e0a0aed4ec | 798 | switch(SRAMtrim) { |
<> | 150:02e0a0aed4ec | 799 | case MXC_V_TRIM_REG10_MEM_SRAM_THREE_FOURTHS_SIZE: |
<> | 150:02e0a0aed4ec | 800 | memSize = (MXC_SRAM_FULL_MEM_SIZE >> 2) * 3; |
<> | 150:02e0a0aed4ec | 801 | break; |
<> | 150:02e0a0aed4ec | 802 | |
<> | 150:02e0a0aed4ec | 803 | case MXC_V_TRIM_REG10_MEM_SRAM_HALF_SIZE: |
<> | 150:02e0a0aed4ec | 804 | memSize = MXC_SRAM_FULL_MEM_SIZE >> 1; |
<> | 150:02e0a0aed4ec | 805 | break; |
<> | 150:02e0a0aed4ec | 806 | |
<> | 150:02e0a0aed4ec | 807 | default: /* other values are FULL size */ |
<> | 150:02e0a0aed4ec | 808 | memSize = MXC_SRAM_FULL_MEM_SIZE; |
<> | 150:02e0a0aed4ec | 809 | break; |
<> | 150:02e0a0aed4ec | 810 | } |
<> | 150:02e0a0aed4ec | 811 | |
<> | 150:02e0a0aed4ec | 812 | /* Returns size in bytes */ |
<> | 150:02e0a0aed4ec | 813 | return memSize; |
<> | 150:02e0a0aed4ec | 814 | } |
<> | 150:02e0a0aed4ec | 815 | |
<> | 150:02e0a0aed4ec | 816 | /******************************************************************************/ |
<> | 150:02e0a0aed4ec | 817 | uint32_t SYS_FLASH_GetSize(void) |
<> | 150:02e0a0aed4ec | 818 | { |
<> | 150:02e0a0aed4ec | 819 | uint32_t memSize; |
<> | 150:02e0a0aed4ec | 820 | |
<> | 150:02e0a0aed4ec | 821 | /* Read TRIM value */ |
<> | 150:02e0a0aed4ec | 822 | int FLASHtrim = (MXC_TRIM->reg10_mem_size & MXC_F_TRIM_REG10_MEM_SIZE_FLASH) >> MXC_F_TRIM_REG10_MEM_SIZE_FLASH_POS; |
<> | 150:02e0a0aed4ec | 823 | |
<> | 150:02e0a0aed4ec | 824 | /* Decode trim value into memory size in bytes*/ |
<> | 150:02e0a0aed4ec | 825 | switch(FLASHtrim) { |
<> | 150:02e0a0aed4ec | 826 | case MXC_V_TRIM_REG10_MEM_FLASH_THREE_FOURTHS_SIZE: |
<> | 150:02e0a0aed4ec | 827 | memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2) * 3; |
<> | 150:02e0a0aed4ec | 828 | break; |
<> | 150:02e0a0aed4ec | 829 | case MXC_V_TRIM_REG10_MEM_FLASH_HALF_SIZE: |
<> | 150:02e0a0aed4ec | 830 | memSize = (MXC_FLASH_FULL_MEM_SIZE >> 1); |
<> | 150:02e0a0aed4ec | 831 | break; |
<> | 150:02e0a0aed4ec | 832 | case MXC_V_TRIM_REG10_MEM_FLASH_THREE_EIGHTHS_SIZE: |
<> | 150:02e0a0aed4ec | 833 | memSize = (MXC_FLASH_FULL_MEM_SIZE >> 3) * 3; |
<> | 150:02e0a0aed4ec | 834 | break; |
<> | 150:02e0a0aed4ec | 835 | case MXC_V_TRIM_REG10_MEM_FLASH_FOURTH_SIZE: |
<> | 150:02e0a0aed4ec | 836 | memSize = (MXC_FLASH_FULL_MEM_SIZE >> 2); |
<> | 150:02e0a0aed4ec | 837 | break; |
<> | 150:02e0a0aed4ec | 838 | default: /* other values are FULL size */ |
<> | 150:02e0a0aed4ec | 839 | memSize = MXC_FLASH_FULL_MEM_SIZE; |
<> | 150:02e0a0aed4ec | 840 | break; |
<> | 150:02e0a0aed4ec | 841 | } |
<> | 150:02e0a0aed4ec | 842 | |
<> | 150:02e0a0aed4ec | 843 | /* Returns size in bytes */ |
<> | 150:02e0a0aed4ec | 844 | return memSize; |
<> | 150:02e0a0aed4ec | 845 | } |