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targets/TARGET_Maxim/TARGET_MAX32625/device/uart_regs.h@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_UART_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_UART_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t ctrl; /* 0x0000 UART Control Register */
<> 150:02e0a0aed4ec 66 __IO uint32_t baud; /* 0x0004 UART Baud Control Register */
<> 150:02e0a0aed4ec 67 __IO uint32_t tx_fifo_ctrl; /* 0x0008 UART TX FIFO Control Register */
<> 150:02e0a0aed4ec 68 __IO uint32_t rx_fifo_ctrl; /* 0x000C UART RX FIFO Control Register */
<> 150:02e0a0aed4ec 69 __IO uint32_t md_ctrl; /* 0x0010 UART Multidrop Control Register */
<> 150:02e0a0aed4ec 70 __IO uint32_t intfl; /* 0x0014 UART Interrupt Flags */
<> 150:02e0a0aed4ec 71 __IO uint32_t inten; /* 0x0018 UART Interrupt Enable/Disable Controls */
<> 150:02e0a0aed4ec 72 #if (MXC_UART_REV > 0)
<> 150:02e0a0aed4ec 73 __I uint32_t idle; /* 0x001C UART Idle Status */
<> 150:02e0a0aed4ec 74 #endif
<> 150:02e0a0aed4ec 75 } mxc_uart_regs_t;
<> 150:02e0a0aed4ec 76
<> 150:02e0a0aed4ec 77
<> 150:02e0a0aed4ec 78 /* Offset Register Description
<> 150:02e0a0aed4ec 79 ============= ============================================================================ */
<> 150:02e0a0aed4ec 80 typedef struct {
<> 150:02e0a0aed4ec 81 union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */
<> 150:02e0a0aed4ec 82 __IO uint8_t tx;
<> 150:02e0a0aed4ec 83 __IO uint8_t tx_8[2048];
<> 150:02e0a0aed4ec 84 __IO uint16_t tx_16[1024];
<> 150:02e0a0aed4ec 85 __IO uint32_t tx_32[512];
<> 150:02e0a0aed4ec 86 };
<> 150:02e0a0aed4ec 87 union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */
<> 150:02e0a0aed4ec 88 __IO uint8_t rx;
<> 150:02e0a0aed4ec 89 __IO uint8_t rx_8[2048];
<> 150:02e0a0aed4ec 90 __IO uint16_t rx_16[1024];
<> 150:02e0a0aed4ec 91 __IO uint32_t rx_32[512];
<> 150:02e0a0aed4ec 92 };
<> 150:02e0a0aed4ec 93 } mxc_uart_fifo_regs_t;
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95
<> 150:02e0a0aed4ec 96 /*
<> 150:02e0a0aed4ec 97 Register offsets for module UART.
<> 150:02e0a0aed4ec 98 */
<> 150:02e0a0aed4ec 99
<> 150:02e0a0aed4ec 100 #define MXC_R_UART_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 101 #define MXC_R_UART_OFFS_BAUD ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 102 #define MXC_R_UART_OFFS_TX_FIFO_CTRL ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 103 #define MXC_R_UART_OFFS_RX_FIFO_CTRL ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 104 #define MXC_R_UART_OFFS_MD_CTRL ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 105 #define MXC_R_UART_OFFS_INTFL ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 106 #define MXC_R_UART_OFFS_INTEN ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 107 #define MXC_R_UART_FIFO_OFFS_TX ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 108 #define MXC_R_UART_FIFO_OFFS_RX ((uint32_t)0x00000800UL)
<> 150:02e0a0aed4ec 109
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 /*
<> 150:02e0a0aed4ec 112 Field positions and masks for module UART.
<> 150:02e0a0aed4ec 113 */
<> 150:02e0a0aed4ec 114
<> 150:02e0a0aed4ec 115 #define MXC_F_UART_CTRL_UART_EN_POS 0
<> 150:02e0a0aed4ec 116 #define MXC_F_UART_CTRL_UART_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_UART_EN_POS))
<> 150:02e0a0aed4ec 117 #define MXC_F_UART_CTRL_RX_FIFO_EN_POS 1
<> 150:02e0a0aed4ec 118 #define MXC_F_UART_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 119 #define MXC_F_UART_CTRL_TX_FIFO_EN_POS 2
<> 150:02e0a0aed4ec 120 #define MXC_F_UART_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_EN_POS))
<> 150:02e0a0aed4ec 121 #define MXC_F_UART_CTRL_DATA_SIZE_POS 4
<> 150:02e0a0aed4ec 122 #define MXC_F_UART_CTRL_DATA_SIZE ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 150:02e0a0aed4ec 123 #define MXC_F_UART_CTRL_EXTRA_STOP_POS 8
<> 150:02e0a0aed4ec 124 #define MXC_F_UART_CTRL_EXTRA_STOP ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_EXTRA_STOP_POS))
<> 150:02e0a0aed4ec 125 #define MXC_F_UART_CTRL_PARITY_POS 12
<> 150:02e0a0aed4ec 126 #define MXC_F_UART_CTRL_PARITY ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_PARITY_POS))
<> 150:02e0a0aed4ec 127 #define MXC_F_UART_CTRL_CTS_EN_POS 16
<> 150:02e0a0aed4ec 128 #define MXC_F_UART_CTRL_CTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_EN_POS))
<> 150:02e0a0aed4ec 129 #define MXC_F_UART_CTRL_CTS_POLARITY_POS 17
<> 150:02e0a0aed4ec 130 #define MXC_F_UART_CTRL_CTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_CTS_POLARITY_POS))
<> 150:02e0a0aed4ec 131 #define MXC_F_UART_CTRL_RTS_EN_POS 18
<> 150:02e0a0aed4ec 132 #define MXC_F_UART_CTRL_RTS_EN ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_EN_POS))
<> 150:02e0a0aed4ec 133 #define MXC_F_UART_CTRL_RTS_POLARITY_POS 19
<> 150:02e0a0aed4ec 134 #define MXC_F_UART_CTRL_RTS_POLARITY ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RTS_POLARITY_POS))
<> 150:02e0a0aed4ec 135 #define MXC_F_UART_CTRL_RTS_LEVEL_POS 20
<> 150:02e0a0aed4ec 136 #define MXC_F_UART_CTRL_RTS_LEVEL ((uint32_t)(0x0000003FUL << MXC_F_UART_CTRL_RTS_LEVEL_POS))
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 #define MXC_F_UART_BAUD_BAUD_DIVISOR_POS 0
<> 150:02e0a0aed4ec 139 #define MXC_F_UART_BAUD_BAUD_DIVISOR ((uint32_t)(0x000000FFUL << MXC_F_UART_BAUD_BAUD_DIVISOR_POS))
<> 150:02e0a0aed4ec 140 #define MXC_F_UART_BAUD_BAUD_MODE_POS 8
<> 150:02e0a0aed4ec 141 #define MXC_F_UART_BAUD_BAUD_MODE ((uint32_t)(0x00000003UL << MXC_F_UART_BAUD_BAUD_MODE_POS))
<> 150:02e0a0aed4ec 142
<> 150:02e0a0aed4ec 143 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS 0
<> 150:02e0a0aed4ec 144 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_ENTRY_POS))
<> 150:02e0a0aed4ec 145 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS 16
<> 150:02e0a0aed4ec 146 #define MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_TX_FIFO_CTRL_FIFO_AE_LVL_POS))
<> 150:02e0a0aed4ec 147
<> 150:02e0a0aed4ec 148 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS 0
<> 150:02e0a0aed4ec 149 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY ((uint32_t)(0x0000003FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_ENTRY_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS 16
<> 150:02e0a0aed4ec 151 #define MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_UART_RX_FIFO_CTRL_FIFO_AF_LVL_POS))
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS 0
<> 150:02e0a0aed4ec 154 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_POS))
<> 150:02e0a0aed4ec 155 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS 8
<> 150:02e0a0aed4ec 156 #define MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK ((uint32_t)(0x000000FFUL << MXC_F_UART_MD_CTRL_SLAVE_ADDR_MSK_POS))
<> 150:02e0a0aed4ec 157 #define MXC_F_UART_MD_CTRL_MD_MSTR_POS 16
<> 150:02e0a0aed4ec 158 #define MXC_F_UART_MD_CTRL_MD_MSTR ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_MD_MSTR_POS))
<> 150:02e0a0aed4ec 159 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS 17
<> 150:02e0a0aed4ec 160 #define MXC_F_UART_MD_CTRL_TX_ADDR_MARK ((uint32_t)(0x00000001UL << MXC_F_UART_MD_CTRL_TX_ADDR_MARK_POS))
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 #define MXC_F_UART_INTFL_TX_DONE_POS 0
<> 150:02e0a0aed4ec 163 #define MXC_F_UART_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_DONE_POS))
<> 150:02e0a0aed4ec 164 #define MXC_F_UART_INTFL_TX_UNSTALLED_POS 1
<> 150:02e0a0aed4ec 165 #define MXC_F_UART_INTFL_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_UNSTALLED_POS))
<> 150:02e0a0aed4ec 166 #define MXC_F_UART_INTFL_TX_FIFO_AE_POS 2
<> 150:02e0a0aed4ec 167 #define MXC_F_UART_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 168 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS 3
<> 150:02e0a0aed4ec 169 #define MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY_POS))
<> 150:02e0a0aed4ec 170 #define MXC_F_UART_INTFL_RX_STALLED_POS 4
<> 150:02e0a0aed4ec 171 #define MXC_F_UART_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_STALLED_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_UART_INTFL_RX_FIFO_AF_POS 5
<> 150:02e0a0aed4ec 173 #define MXC_F_UART_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 174 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS 6
<> 150:02e0a0aed4ec 175 #define MXC_F_UART_INTFL_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FIFO_OVERFLOW_POS))
<> 150:02e0a0aed4ec 176 #define MXC_F_UART_INTFL_RX_FRAMING_ERR_POS 7
<> 150:02e0a0aed4ec 177 #define MXC_F_UART_INTFL_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAMING_ERR_POS))
<> 150:02e0a0aed4ec 178 #define MXC_F_UART_INTFL_RX_PARITY_ERR_POS 8
<> 150:02e0a0aed4ec 179 #define MXC_F_UART_INTFL_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERR_POS))
<> 150:02e0a0aed4ec 180
<> 150:02e0a0aed4ec 181 #define MXC_F_UART_INTEN_TX_DONE_POS 0
<> 150:02e0a0aed4ec 182 #define MXC_F_UART_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_DONE_POS))
<> 150:02e0a0aed4ec 183 #define MXC_F_UART_INTEN_TX_UNSTALLED_POS 1
<> 150:02e0a0aed4ec 184 #define MXC_F_UART_INTEN_TX_UNSTALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_UNSTALLED_POS))
<> 150:02e0a0aed4ec 185 #define MXC_F_UART_INTEN_TX_FIFO_AE_POS 2
<> 150:02e0a0aed4ec 186 #define MXC_F_UART_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_FIFO_AE_POS))
<> 150:02e0a0aed4ec 187 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS 3
<> 150:02e0a0aed4ec 188 #define MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_NOT_EMPTY_POS))
<> 150:02e0a0aed4ec 189 #define MXC_F_UART_INTEN_RX_STALLED_POS 4
<> 150:02e0a0aed4ec 190 #define MXC_F_UART_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_STALLED_POS))
<> 150:02e0a0aed4ec 191 #define MXC_F_UART_INTEN_RX_FIFO_AF_POS 5
<> 150:02e0a0aed4ec 192 #define MXC_F_UART_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_AF_POS))
<> 150:02e0a0aed4ec 193 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS 6
<> 150:02e0a0aed4ec 194 #define MXC_F_UART_INTEN_RX_FIFO_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FIFO_OVERFLOW_POS))
<> 150:02e0a0aed4ec 195 #define MXC_F_UART_INTEN_RX_FRAMING_ERR_POS 7
<> 150:02e0a0aed4ec 196 #define MXC_F_UART_INTEN_RX_FRAMING_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAMING_ERR_POS))
<> 150:02e0a0aed4ec 197 #define MXC_F_UART_INTEN_RX_PARITY_ERR_POS 8
<> 150:02e0a0aed4ec 198 #define MXC_F_UART_INTEN_RX_PARITY_ERR ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERR_POS))
<> 150:02e0a0aed4ec 199
<> 150:02e0a0aed4ec 200 #if (MXC_UART_REV > 0)
<> 150:02e0a0aed4ec 201 #define MXC_F_UART_IDLE_TX_RX_IDLE_POS 0
<> 150:02e0a0aed4ec 202 #define MXC_F_UART_IDLE_TX_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_RX_IDLE_POS))
<> 150:02e0a0aed4ec 203 #define MXC_F_UART_IDLE_TX_IDLE_POS 1
<> 150:02e0a0aed4ec 204 #define MXC_F_UART_IDLE_TX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_TX_IDLE_POS))
<> 150:02e0a0aed4ec 205 #define MXC_F_UART_IDLE_RX_IDLE_POS 2
<> 150:02e0a0aed4ec 206 #define MXC_F_UART_IDLE_RX_IDLE ((uint32_t)(0x00000001UL << MXC_F_UART_IDLE_RX_IDLE_POS))
<> 150:02e0a0aed4ec 207 #endif
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209 /*
<> 150:02e0a0aed4ec 210 Field values and shifted values for module UART.
<> 150:02e0a0aed4ec 211 */
<> 150:02e0a0aed4ec 212
<> 150:02e0a0aed4ec 213 #define MXC_V_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 214 #define MXC_V_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 215 #define MXC_V_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 216 #define MXC_V_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 217
<> 150:02e0a0aed4ec 218 #define MXC_S_UART_CTRL_DATA_SIZE_5_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_5_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 150:02e0a0aed4ec 219 #define MXC_S_UART_CTRL_DATA_SIZE_6_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_6_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 150:02e0a0aed4ec 220 #define MXC_S_UART_CTRL_DATA_SIZE_7_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_7_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 150:02e0a0aed4ec 221 #define MXC_S_UART_CTRL_DATA_SIZE_8_BITS ((uint32_t)(MXC_V_UART_CTRL_DATA_SIZE_8_BITS << MXC_F_UART_CTRL_DATA_SIZE_POS))
<> 150:02e0a0aed4ec 222
<> 150:02e0a0aed4ec 223 #define MXC_V_UART_CTRL_PARITY_DISABLE ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 224 #define MXC_V_UART_CTRL_PARITY_ODD ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 225 #define MXC_V_UART_CTRL_PARITY_EVEN ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 226 #define MXC_V_UART_CTRL_PARITY_MARK ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228 #define MXC_S_UART_CTRL_PARITY_DISABLE ((uint32_t)(MXC_V_UART_CTRL_PARITY_DISABLE << MXC_F_UART_CTRL_PARITY_POS))
<> 150:02e0a0aed4ec 229 #define MXC_S_UART_CTRL_PARITY_ODD ((uint32_t)(MXC_V_UART_CTRL_PARITY_ODD << MXC_F_UART_CTRL_PARITY_POS))
<> 150:02e0a0aed4ec 230 #define MXC_S_UART_CTRL_PARITY_EVEN ((uint32_t)(MXC_V_UART_CTRL_PARITY_EVEN << MXC_F_UART_CTRL_PARITY_POS))
<> 150:02e0a0aed4ec 231 #define MXC_S_UART_CTRL_PARITY_MARK ((uint32_t)(MXC_V_UART_CTRL_PARITY_MARK << MXC_F_UART_CTRL_PARITY_POS))
<> 150:02e0a0aed4ec 232
<> 150:02e0a0aed4ec 233
<> 150:02e0a0aed4ec 234
<> 150:02e0a0aed4ec 235 #ifdef __cplusplus
<> 150:02e0a0aed4ec 236 }
<> 150:02e0a0aed4ec 237 #endif
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239 #endif /* _MXC_UART_REGS_H_ */
<> 150:02e0a0aed4ec 240