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targets/TARGET_Maxim/TARGET_MAX32625/device/pwrseq_regs.h@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_PWRSEQ_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_PWRSEQ_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
<> 150:02e0a0aed4ec 66 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
<> 150:02e0a0aed4ec 67 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
<> 150:02e0a0aed4ec 68 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
<> 150:02e0a0aed4ec 69 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
<> 150:02e0a0aed4ec 70 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
<> 150:02e0a0aed4ec 71 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
<> 150:02e0a0aed4ec 72 __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
<> 150:02e0a0aed4ec 73 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
<> 150:02e0a0aed4ec 74 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
<> 150:02e0a0aed4ec 75 __I uint32_t rsv028; /* 0x0028 */
<> 150:02e0a0aed4ec 76 __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
<> 150:02e0a0aed4ec 77 __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
<> 150:02e0a0aed4ec 78 __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
<> 150:02e0a0aed4ec 79 __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
<> 150:02e0a0aed4ec 80 __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
<> 150:02e0a0aed4ec 81 } mxc_pwrseq_regs_t;
<> 150:02e0a0aed4ec 82
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84 /*
<> 150:02e0a0aed4ec 85 Register offsets for module PWRSEQ.
<> 150:02e0a0aed4ec 86 */
<> 150:02e0a0aed4ec 87
<> 150:02e0a0aed4ec 88 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 89 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 90 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 91 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 92 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 93 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 94 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 95 #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 96 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
<> 150:02e0a0aed4ec 97 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
<> 150:02e0a0aed4ec 98 #define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
<> 150:02e0a0aed4ec 99 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
<> 150:02e0a0aed4ec 100 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
<> 150:02e0a0aed4ec 101 #define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
<> 150:02e0a0aed4ec 102 #define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
<> 150:02e0a0aed4ec 103
<> 150:02e0a0aed4ec 104
<> 150:02e0a0aed4ec 105 /*
<> 150:02e0a0aed4ec 106 Field positions and masks for module PWRSEQ.
<> 150:02e0a0aed4ec 107 */
<> 150:02e0a0aed4ec 108
<> 150:02e0a0aed4ec 109 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
<> 150:02e0a0aed4ec 110 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
<> 150:02e0a0aed4ec 111 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
<> 150:02e0a0aed4ec 112 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
<> 150:02e0a0aed4ec 113 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
<> 150:02e0a0aed4ec 114 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
<> 150:02e0a0aed4ec 115 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
<> 150:02e0a0aed4ec 116 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
<> 150:02e0a0aed4ec 117 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
<> 150:02e0a0aed4ec 118 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
<> 150:02e0a0aed4ec 119 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
<> 150:02e0a0aed4ec 120 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
<> 150:02e0a0aed4ec 121 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
<> 150:02e0a0aed4ec 122 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
<> 150:02e0a0aed4ec 123 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
<> 150:02e0a0aed4ec 124 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
<> 150:02e0a0aed4ec 125 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
<> 150:02e0a0aed4ec 126 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
<> 150:02e0a0aed4ec 127 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
<> 150:02e0a0aed4ec 128 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
<> 150:02e0a0aed4ec 129 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
<> 150:02e0a0aed4ec 130 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
<> 150:02e0a0aed4ec 131 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
<> 150:02e0a0aed4ec 132 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
<> 150:02e0a0aed4ec 133 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
<> 150:02e0a0aed4ec 134 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
<> 150:02e0a0aed4ec 135 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
<> 150:02e0a0aed4ec 136 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
<> 150:02e0a0aed4ec 137 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
<> 150:02e0a0aed4ec 138 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
<> 150:02e0a0aed4ec 139 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
<> 150:02e0a0aed4ec 140 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
<> 150:02e0a0aed4ec 141 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
<> 150:02e0a0aed4ec 142 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
<> 150:02e0a0aed4ec 143 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
<> 150:02e0a0aed4ec 144 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
<> 150:02e0a0aed4ec 145 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
<> 150:02e0a0aed4ec 146 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
<> 150:02e0a0aed4ec 147 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
<> 150:02e0a0aed4ec 148 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
<> 150:02e0a0aed4ec 149 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
<> 150:02e0a0aed4ec 150 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
<> 150:02e0a0aed4ec 151 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
<> 150:02e0a0aed4ec 152 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
<> 150:02e0a0aed4ec 153 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
<> 150:02e0a0aed4ec 154 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
<> 150:02e0a0aed4ec 155 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
<> 150:02e0a0aed4ec 156 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
<> 150:02e0a0aed4ec 157 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
<> 150:02e0a0aed4ec 158 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
<> 150:02e0a0aed4ec 159 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
<> 150:02e0a0aed4ec 160 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
<> 150:02e0a0aed4ec 161 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
<> 150:02e0a0aed4ec 162 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
<> 150:02e0a0aed4ec 165 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
<> 150:02e0a0aed4ec 166 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
<> 150:02e0a0aed4ec 167 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
<> 150:02e0a0aed4ec 168 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
<> 150:02e0a0aed4ec 169 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
<> 150:02e0a0aed4ec 170 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
<> 150:02e0a0aed4ec 171 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
<> 150:02e0a0aed4ec 173 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
<> 150:02e0a0aed4ec 174 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
<> 150:02e0a0aed4ec 175 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
<> 150:02e0a0aed4ec 176 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
<> 150:02e0a0aed4ec 177 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
<> 150:02e0a0aed4ec 178 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
<> 150:02e0a0aed4ec 179 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
<> 150:02e0a0aed4ec 180 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
<> 150:02e0a0aed4ec 181 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
<> 150:02e0a0aed4ec 182 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
<> 150:02e0a0aed4ec 183 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
<> 150:02e0a0aed4ec 184 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
<> 150:02e0a0aed4ec 185 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
<> 150:02e0a0aed4ec 186 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
<> 150:02e0a0aed4ec 187 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
<> 150:02e0a0aed4ec 188 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
<> 150:02e0a0aed4ec 189 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
<> 150:02e0a0aed4ec 190 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
<> 150:02e0a0aed4ec 191 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
<> 150:02e0a0aed4ec 192 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
<> 150:02e0a0aed4ec 193 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
<> 150:02e0a0aed4ec 194 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
<> 150:02e0a0aed4ec 195 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
<> 150:02e0a0aed4ec 198 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
<> 150:02e0a0aed4ec 199 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
<> 150:02e0a0aed4ec 200 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
<> 150:02e0a0aed4ec 201 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
<> 150:02e0a0aed4ec 202 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
<> 150:02e0a0aed4ec 203 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
<> 150:02e0a0aed4ec 204 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
<> 150:02e0a0aed4ec 205 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
<> 150:02e0a0aed4ec 206 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
<> 150:02e0a0aed4ec 207 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
<> 150:02e0a0aed4ec 208 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
<> 150:02e0a0aed4ec 209 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
<> 150:02e0a0aed4ec 210 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
<> 150:02e0a0aed4ec 211
<> 150:02e0a0aed4ec 212 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
<> 150:02e0a0aed4ec 213 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
<> 150:02e0a0aed4ec 214 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
<> 150:02e0a0aed4ec 215 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
<> 150:02e0a0aed4ec 216 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
<> 150:02e0a0aed4ec 217 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
<> 150:02e0a0aed4ec 218 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
<> 150:02e0a0aed4ec 219 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
<> 150:02e0a0aed4ec 220 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
<> 150:02e0a0aed4ec 221 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
<> 150:02e0a0aed4ec 222 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
<> 150:02e0a0aed4ec 223 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
<> 150:02e0a0aed4ec 224 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
<> 150:02e0a0aed4ec 225 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
<> 150:02e0a0aed4ec 226
<> 150:02e0a0aed4ec 227 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
<> 150:02e0a0aed4ec 228 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
<> 150:02e0a0aed4ec 229 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
<> 150:02e0a0aed4ec 230 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
<> 150:02e0a0aed4ec 231 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
<> 150:02e0a0aed4ec 232 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
<> 150:02e0a0aed4ec 233 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
<> 150:02e0a0aed4ec 234 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
<> 150:02e0a0aed4ec 235 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
<> 150:02e0a0aed4ec 236 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
<> 150:02e0a0aed4ec 237 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
<> 150:02e0a0aed4ec 238 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
<> 150:02e0a0aed4ec 239 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
<> 150:02e0a0aed4ec 240 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
<> 150:02e0a0aed4ec 241 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
<> 150:02e0a0aed4ec 242 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
<> 150:02e0a0aed4ec 243 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
<> 150:02e0a0aed4ec 244 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
<> 150:02e0a0aed4ec 245 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
<> 150:02e0a0aed4ec 246 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
<> 150:02e0a0aed4ec 247
<> 150:02e0a0aed4ec 248 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
<> 150:02e0a0aed4ec 249 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
<> 150:02e0a0aed4ec 250 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
<> 150:02e0a0aed4ec 251 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
<> 150:02e0a0aed4ec 252 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
<> 150:02e0a0aed4ec 253 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
<> 150:02e0a0aed4ec 254 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
<> 150:02e0a0aed4ec 255 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
<> 150:02e0a0aed4ec 256 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
<> 150:02e0a0aed4ec 257 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
<> 150:02e0a0aed4ec 258
<> 150:02e0a0aed4ec 259 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
<> 150:02e0a0aed4ec 260 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
<> 150:02e0a0aed4ec 261 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
<> 150:02e0a0aed4ec 262 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
<> 150:02e0a0aed4ec 263 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
<> 150:02e0a0aed4ec 264 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
<> 150:02e0a0aed4ec 265 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
<> 150:02e0a0aed4ec 266 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
<> 150:02e0a0aed4ec 267 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
<> 150:02e0a0aed4ec 268 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
<> 150:02e0a0aed4ec 269
<> 150:02e0a0aed4ec 270 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
<> 150:02e0a0aed4ec 271 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
<> 150:02e0a0aed4ec 272 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
<> 150:02e0a0aed4ec 273 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
<> 150:02e0a0aed4ec 274
<> 150:02e0a0aed4ec 275 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
<> 150:02e0a0aed4ec 276 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
<> 150:02e0a0aed4ec 277 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
<> 150:02e0a0aed4ec 278 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
<> 150:02e0a0aed4ec 279 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
<> 150:02e0a0aed4ec 280 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
<> 150:02e0a0aed4ec 281 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
<> 150:02e0a0aed4ec 282 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
<> 150:02e0a0aed4ec 283 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
<> 150:02e0a0aed4ec 284 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
<> 150:02e0a0aed4ec 285 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
<> 150:02e0a0aed4ec 286 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
<> 150:02e0a0aed4ec 287 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
<> 150:02e0a0aed4ec 288 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
<> 150:02e0a0aed4ec 289 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
<> 150:02e0a0aed4ec 290 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
<> 150:02e0a0aed4ec 291 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
<> 150:02e0a0aed4ec 292 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
<> 150:02e0a0aed4ec 293 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
<> 150:02e0a0aed4ec 294 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
<> 150:02e0a0aed4ec 295 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
<> 150:02e0a0aed4ec 296 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
<> 150:02e0a0aed4ec 297 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
<> 150:02e0a0aed4ec 298 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
<> 150:02e0a0aed4ec 299 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
<> 150:02e0a0aed4ec 300 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
<> 150:02e0a0aed4ec 301 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
<> 150:02e0a0aed4ec 302 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
<> 150:02e0a0aed4ec 303 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
<> 150:02e0a0aed4ec 304 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
<> 150:02e0a0aed4ec 305 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
<> 150:02e0a0aed4ec 306 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
<> 150:02e0a0aed4ec 307 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
<> 150:02e0a0aed4ec 308 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 150:02e0a0aed4ec 309 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
<> 150:02e0a0aed4ec 310 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 150:02e0a0aed4ec 311 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
<> 150:02e0a0aed4ec 312 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
<> 150:02e0a0aed4ec 313 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
<> 150:02e0a0aed4ec 314 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
<> 150:02e0a0aed4ec 315 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
<> 150:02e0a0aed4ec 316 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
<> 150:02e0a0aed4ec 317 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
<> 150:02e0a0aed4ec 318 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
<> 150:02e0a0aed4ec 319 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
<> 150:02e0a0aed4ec 320 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
<> 150:02e0a0aed4ec 321 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
<> 150:02e0a0aed4ec 322 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
<> 150:02e0a0aed4ec 323 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
<> 150:02e0a0aed4ec 324 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
<> 150:02e0a0aed4ec 325
<> 150:02e0a0aed4ec 326 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
<> 150:02e0a0aed4ec 327 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
<> 150:02e0a0aed4ec 328 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
<> 150:02e0a0aed4ec 329 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
<> 150:02e0a0aed4ec 330 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
<> 150:02e0a0aed4ec 331 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
<> 150:02e0a0aed4ec 332 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
<> 150:02e0a0aed4ec 333 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
<> 150:02e0a0aed4ec 334 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
<> 150:02e0a0aed4ec 335 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
<> 150:02e0a0aed4ec 336 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
<> 150:02e0a0aed4ec 337 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
<> 150:02e0a0aed4ec 338 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
<> 150:02e0a0aed4ec 339 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
<> 150:02e0a0aed4ec 340 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
<> 150:02e0a0aed4ec 341 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
<> 150:02e0a0aed4ec 342 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
<> 150:02e0a0aed4ec 343 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
<> 150:02e0a0aed4ec 344 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
<> 150:02e0a0aed4ec 345 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
<> 150:02e0a0aed4ec 346 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
<> 150:02e0a0aed4ec 347 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
<> 150:02e0a0aed4ec 348 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
<> 150:02e0a0aed4ec 349 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
<> 150:02e0a0aed4ec 350 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
<> 150:02e0a0aed4ec 351 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
<> 150:02e0a0aed4ec 352 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
<> 150:02e0a0aed4ec 353 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
<> 150:02e0a0aed4ec 354 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
<> 150:02e0a0aed4ec 355 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
<> 150:02e0a0aed4ec 356 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
<> 150:02e0a0aed4ec 357 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 150:02e0a0aed4ec 358 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
<> 150:02e0a0aed4ec 359 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 150:02e0a0aed4ec 360 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
<> 150:02e0a0aed4ec 361 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
<> 150:02e0a0aed4ec 362 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
<> 150:02e0a0aed4ec 363 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
<> 150:02e0a0aed4ec 364 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
<> 150:02e0a0aed4ec 365 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
<> 150:02e0a0aed4ec 366 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
<> 150:02e0a0aed4ec 367 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
<> 150:02e0a0aed4ec 368 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
<> 150:02e0a0aed4ec 369 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
<> 150:02e0a0aed4ec 370 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
<> 150:02e0a0aed4ec 371 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
<> 150:02e0a0aed4ec 372 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
<> 150:02e0a0aed4ec 373 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
<> 150:02e0a0aed4ec 376 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
<> 150:02e0a0aed4ec 377 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
<> 150:02e0a0aed4ec 378 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
<> 150:02e0a0aed4ec 379 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
<> 150:02e0a0aed4ec 380 #define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
<> 150:02e0a0aed4ec 381 #define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
<> 150:02e0a0aed4ec 382 #define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
<> 150:02e0a0aed4ec 383 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
<> 150:02e0a0aed4ec 384 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
<> 150:02e0a0aed4ec 385 #define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
<> 150:02e0a0aed4ec 386 #define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
<> 150:02e0a0aed4ec 387
<> 150:02e0a0aed4ec 388 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
<> 150:02e0a0aed4ec 389 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
<> 150:02e0a0aed4ec 390 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
<> 150:02e0a0aed4ec 391 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
<> 150:02e0a0aed4ec 392 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
<> 150:02e0a0aed4ec 393 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
<> 150:02e0a0aed4ec 394 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
<> 150:02e0a0aed4ec 395 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
<> 150:02e0a0aed4ec 396 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
<> 150:02e0a0aed4ec 397 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
<> 150:02e0a0aed4ec 398
<> 150:02e0a0aed4ec 399 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
<> 150:02e0a0aed4ec 400 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
<> 150:02e0a0aed4ec 401 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
<> 150:02e0a0aed4ec 402 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
<> 150:02e0a0aed4ec 403
<> 150:02e0a0aed4ec 404 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
<> 150:02e0a0aed4ec 405 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
<> 150:02e0a0aed4ec 406
<> 150:02e0a0aed4ec 407 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
<> 150:02e0a0aed4ec 408 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
<> 150:02e0a0aed4ec 409 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
<> 150:02e0a0aed4ec 410 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
<> 150:02e0a0aed4ec 411 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
<> 150:02e0a0aed4ec 412 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
<> 150:02e0a0aed4ec 413 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
<> 150:02e0a0aed4ec 414 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
<> 150:02e0a0aed4ec 415 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
<> 150:02e0a0aed4ec 416 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
<> 150:02e0a0aed4ec 417
<> 150:02e0a0aed4ec 418
<> 150:02e0a0aed4ec 419
<> 150:02e0a0aed4ec 420 #ifdef __cplusplus
<> 150:02e0a0aed4ec 421 }
<> 150:02e0a0aed4ec 422 #endif
<> 150:02e0a0aed4ec 423
<> 150:02e0a0aed4ec 424 #endif /* _MXC_PWRSEQ_REGS_H_ */
<> 150:02e0a0aed4ec 425