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targets/TARGET_Maxim/TARGET_MAX32625/device/flc_regs.h@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_FLC_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_FLC_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
<> 150:02e0a0aed4ec 58 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
<> 150:02e0a0aed4ec 59 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 /*
<> 150:02e0a0aed4ec 62 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 63 access to each register in module.
<> 150:02e0a0aed4ec 64 */
<> 150:02e0a0aed4ec 65
<> 150:02e0a0aed4ec 66 /* Offset Register Description
<> 150:02e0a0aed4ec 67 ============= ============================================================================ */
<> 150:02e0a0aed4ec 68 typedef struct {
<> 150:02e0a0aed4ec 69 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
<> 150:02e0a0aed4ec 70 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Pulse Divisor */
<> 150:02e0a0aed4ec 71 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
<> 150:02e0a0aed4ec 72 __I uint32_t rsv00C[6]; /* 0x000C-0x0020 */
<> 150:02e0a0aed4ec 73 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
<> 150:02e0a0aed4ec 74 __I uint32_t rsv028[2]; /* 0x0028-0x002C */
<> 150:02e0a0aed4ec 75 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
<> 150:02e0a0aed4ec 76 __I uint32_t rsv034[7]; /* 0x0034-0x004C */
<> 150:02e0a0aed4ec 77 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
<> 150:02e0a0aed4ec 78 __IO uint32_t tacc; /* 0x0054 Flash Read Cycle Config */
<> 150:02e0a0aed4ec 79 __IO uint32_t tprog; /* 0x0058 Flash Write Cycle Config */
<> 150:02e0a0aed4ec 80 __I uint32_t rsv05C[9]; /* 0x005C-0x007C */
<> 150:02e0a0aed4ec 81 __IO uint32_t status; /* 0x0080 Security Status Flags */
<> 150:02e0a0aed4ec 82 __I uint32_t rsv084; /* 0x0084 */
<> 150:02e0a0aed4ec 83 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
<> 150:02e0a0aed4ec 84 __I uint32_t rsv08C[4]; /* 0x008C-0x0098 */
<> 150:02e0a0aed4ec 85 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
<> 150:02e0a0aed4ec 86 __I uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */
<> 150:02e0a0aed4ec 87 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
<> 150:02e0a0aed4ec 88 __I uint32_t rsv104[15]; /* 0x0104-0x013C */
<> 150:02e0a0aed4ec 89 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
<> 150:02e0a0aed4ec 90 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
<> 150:02e0a0aed4ec 91 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
<> 150:02e0a0aed4ec 92 __I uint32_t rsv14C[9]; /* 0x014C-0x016C */
<> 150:02e0a0aed4ec 93 __IO uint32_t bl_ctrl; /* 0x0170 Bootloader Control Register */
<> 150:02e0a0aed4ec 94 __IO uint32_t twk; /* 0x0174 PDM33 Register */
<> 150:02e0a0aed4ec 95 __I uint32_t rsv178; /* 0x0178 */
<> 150:02e0a0aed4ec 96 __IO uint32_t slm; /* 0x017C Sleep Mode Register */
<> 150:02e0a0aed4ec 97 __I uint32_t rsv180[32]; /* 0x0180-0x01FC */
<> 150:02e0a0aed4ec 98 __IO uint32_t disable_xr0; /* 0x0200 Disable Flash Page Exec/Read Register 0 */
<> 150:02e0a0aed4ec 99 __IO uint32_t disable_xr1; /* 0x0204 Disable Flash Page Exec/Read Register 1 */
<> 150:02e0a0aed4ec 100 __IO uint32_t disable_xr2; /* 0x0208 Disable Flash Page Exec/Read Register 2 */
<> 150:02e0a0aed4ec 101 __IO uint32_t disable_xr3; /* 0x020C Disable Flash Page Exec/Read Register 3 */
<> 150:02e0a0aed4ec 102 __IO uint32_t disable_xr4; /* 0x0210 Disable Flash Page Exec/Read Register 4 */
<> 150:02e0a0aed4ec 103 __IO uint32_t disable_xr5; /* 0x0214 Disable Flash Page Exec/Read Register 5 */
<> 150:02e0a0aed4ec 104 __IO uint32_t disable_xr6; /* 0x0218 Disable Flash Page Exec/Read Register 6 */
<> 150:02e0a0aed4ec 105 __IO uint32_t disable_xr7; /* 0x021C Disable Flash Page Exec/Read Register 7 */
<> 150:02e0a0aed4ec 106 __I uint32_t rsv220[56]; /* 0x0220-0x02FC */
<> 150:02e0a0aed4ec 107 __IO uint32_t disable_we0; /* 0x0300 Disable Flash Page Write/Erase Register 0 */
<> 150:02e0a0aed4ec 108 __IO uint32_t disable_we1; /* 0x0304 Disable Flash Page Write/Erase Register 1 */
<> 150:02e0a0aed4ec 109 __IO uint32_t disable_we2; /* 0x0308 Disable Flash Page Write/Erase Register 2 */
<> 150:02e0a0aed4ec 110 __IO uint32_t disable_we3; /* 0x030C Disable Flash Page Write/Erase Register 3 */
<> 150:02e0a0aed4ec 111 __IO uint32_t disable_we4; /* 0x0310 Disable Flash Page Write/Erase Register 4 */
<> 150:02e0a0aed4ec 112 __IO uint32_t disable_we5; /* 0x0314 Disable Flash Page Write/Erase Register 5 */
<> 150:02e0a0aed4ec 113 __IO uint32_t disable_we6; /* 0x0318 Disable Flash Page Write/Erase Register 6 */
<> 150:02e0a0aed4ec 114 __IO uint32_t disable_we7; /* 0x031C Disable Flash Page Write/Erase Register 7 */
<> 150:02e0a0aed4ec 115 } mxc_flc_regs_t;
<> 150:02e0a0aed4ec 116
<> 150:02e0a0aed4ec 117
<> 150:02e0a0aed4ec 118 /*
<> 150:02e0a0aed4ec 119 Register offsets for module FLC.
<> 150:02e0a0aed4ec 120 */
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 123 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 124 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 125 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
<> 150:02e0a0aed4ec 126 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
<> 150:02e0a0aed4ec 127 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
<> 150:02e0a0aed4ec 128 #define MXC_R_FLC_OFFS_TACC ((uint32_t)0x00000054UL)
<> 150:02e0a0aed4ec 129 #define MXC_R_FLC_OFFS_TPROG ((uint32_t)0x00000058UL)
<> 150:02e0a0aed4ec 130 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
<> 150:02e0a0aed4ec 131 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
<> 150:02e0a0aed4ec 132 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
<> 150:02e0a0aed4ec 133 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
<> 150:02e0a0aed4ec 134 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
<> 150:02e0a0aed4ec 135 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
<> 150:02e0a0aed4ec 136 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
<> 150:02e0a0aed4ec 137 #define MXC_R_FLC_OFFS_BL_CTRL ((uint32_t)0x00000170UL)
<> 150:02e0a0aed4ec 138 #define MXC_R_FLC_OFFS_TWK ((uint32_t)0x00000174UL)
<> 150:02e0a0aed4ec 139 #define MXC_R_FLC_OFFS_SLM ((uint32_t)0x0000017CUL)
<> 150:02e0a0aed4ec 140 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000200UL)
<> 150:02e0a0aed4ec 141 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000204UL)
<> 150:02e0a0aed4ec 142 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000208UL)
<> 150:02e0a0aed4ec 143 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000020CUL)
<> 150:02e0a0aed4ec 144 #define MXC_R_FLC_OFFS_DISABLE_XR4 ((uint32_t)0x00000210UL)
<> 150:02e0a0aed4ec 145 #define MXC_R_FLC_OFFS_DISABLE_XR5 ((uint32_t)0x00000214UL)
<> 150:02e0a0aed4ec 146 #define MXC_R_FLC_OFFS_DISABLE_XR6 ((uint32_t)0x00000218UL)
<> 150:02e0a0aed4ec 147 #define MXC_R_FLC_OFFS_DISABLE_XR7 ((uint32_t)0x0000021CUL)
<> 150:02e0a0aed4ec 148 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000300UL)
<> 150:02e0a0aed4ec 149 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000304UL)
<> 150:02e0a0aed4ec 150 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000308UL)
<> 150:02e0a0aed4ec 151 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000030CUL)
<> 150:02e0a0aed4ec 152 #define MXC_R_FLC_OFFS_DISABLE_WE4 ((uint32_t)0x00000310UL)
<> 150:02e0a0aed4ec 153 #define MXC_R_FLC_OFFS_DISABLE_WE5 ((uint32_t)0x00000314UL)
<> 150:02e0a0aed4ec 154 #define MXC_R_FLC_OFFS_DISABLE_WE6 ((uint32_t)0x00000318UL)
<> 150:02e0a0aed4ec 155 #define MXC_R_FLC_OFFS_DISABLE_WE7 ((uint32_t)0x0000031CUL)
<> 150:02e0a0aed4ec 156
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158 /*
<> 150:02e0a0aed4ec 159 Field positions and masks for module FLC.
<> 150:02e0a0aed4ec 160 */
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 #define MXC_F_FLC_FADDR_FADDR_POS 0
<> 150:02e0a0aed4ec 163 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x003FFFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
<> 150:02e0a0aed4ec 164
<> 150:02e0a0aed4ec 165 #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
<> 150:02e0a0aed4ec 166 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000007FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
<> 150:02e0a0aed4ec 167 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS 16
<> 150:02e0a0aed4ec 168 #define MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_FCKDIV_AUTO_FCKDIV_RESULT_POS))
<> 150:02e0a0aed4ec 169
<> 150:02e0a0aed4ec 170 #define MXC_F_FLC_CTRL_WRITE_POS 0
<> 150:02e0a0aed4ec 171 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
<> 150:02e0a0aed4ec 173 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
<> 150:02e0a0aed4ec 174 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
<> 150:02e0a0aed4ec 175 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
<> 150:02e0a0aed4ec 176 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
<> 150:02e0a0aed4ec 177 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
<> 150:02e0a0aed4ec 178 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
<> 150:02e0a0aed4ec 179 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
<> 150:02e0a0aed4ec 180 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
<> 150:02e0a0aed4ec 181 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
<> 150:02e0a0aed4ec 182 #define MXC_F_FLC_CTRL_PENDING_POS 24
<> 150:02e0a0aed4ec 183 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
<> 150:02e0a0aed4ec 184 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
<> 150:02e0a0aed4ec 185 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
<> 150:02e0a0aed4ec 186 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
<> 150:02e0a0aed4ec 187 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
<> 150:02e0a0aed4ec 188 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
<> 150:02e0a0aed4ec 189 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 #define MXC_F_FLC_INTR_FINISHED_IF_POS 0
<> 150:02e0a0aed4ec 192 #define MXC_F_FLC_INTR_FINISHED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IF_POS))
<> 150:02e0a0aed4ec 193 #define MXC_F_FLC_INTR_FAILED_IF_POS 1
<> 150:02e0a0aed4ec 194 #define MXC_F_FLC_INTR_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IF_POS))
<> 150:02e0a0aed4ec 195 #define MXC_F_FLC_INTR_FINISHED_IE_POS 8
<> 150:02e0a0aed4ec 196 #define MXC_F_FLC_INTR_FINISHED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FINISHED_IE_POS))
<> 150:02e0a0aed4ec 197 #define MXC_F_FLC_INTR_FAILED_IE_POS 9
<> 150:02e0a0aed4ec 198 #define MXC_F_FLC_INTR_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FAILED_IE_POS))
<> 150:02e0a0aed4ec 199 #define MXC_F_FLC_INTR_FAIL_FLAGS_POS 16
<> 150:02e0a0aed4ec 200 #define MXC_F_FLC_INTR_FAIL_FLAGS ((uint32_t)(0x0000FFFFUL << MXC_F_FLC_INTR_FAIL_FLAGS_POS))
<> 150:02e0a0aed4ec 201
<> 150:02e0a0aed4ec 202 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
<> 150:02e0a0aed4ec 203 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
<> 150:02e0a0aed4ec 204 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
<> 150:02e0a0aed4ec 205 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
<> 150:02e0a0aed4ec 206 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS 12
<> 150:02e0a0aed4ec 207 #define MXC_F_FLC_PERFORM_EN_PREVENT_FAIL ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_PREVENT_FAIL_POS))
<> 150:02e0a0aed4ec 208 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS 16
<> 150:02e0a0aed4ec 209 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS_POS))
<> 150:02e0a0aed4ec 210 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS 20
<> 150:02e0a0aed4ec 211 #define MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_BACK2BACK_WRS_POS))
<> 150:02e0a0aed4ec 212 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS 24
<> 150:02e0a0aed4ec 213 #define MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT_POS))
<> 150:02e0a0aed4ec 214 #define MXC_F_FLC_PERFORM_AUTO_TACC_POS 28
<> 150:02e0a0aed4ec 215 #define MXC_F_FLC_PERFORM_AUTO_TACC ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_TACC_POS))
<> 150:02e0a0aed4ec 216 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS 29
<> 150:02e0a0aed4ec 217 #define MXC_F_FLC_PERFORM_AUTO_CLKDIV ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_AUTO_CLKDIV_POS))
<> 150:02e0a0aed4ec 218
<> 150:02e0a0aed4ec 219 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS 0
<> 150:02e0a0aed4ec 220 #define MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_WINDOW_POS))
<> 150:02e0a0aed4ec 221 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS 1
<> 150:02e0a0aed4ec 222 #define MXC_F_FLC_STATUS_JTAG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_JTAG_LOCK_STATIC_POS))
<> 150:02e0a0aed4ec 223 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
<> 150:02e0a0aed4ec 224 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
<> 150:02e0a0aed4ec 225 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS 29
<> 150:02e0a0aed4ec 226 #define MXC_F_FLC_STATUS_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_TRIM_UPDATE_DONE_POS))
<> 150:02e0a0aed4ec 227 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS 30
<> 150:02e0a0aed4ec 228 #define MXC_F_FLC_STATUS_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_INFO_BLOCK_VALID_POS))
<> 150:02e0a0aed4ec 229
<> 150:02e0a0aed4ec 230 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
<> 150:02e0a0aed4ec 231 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
<> 150:02e0a0aed4ec 232 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
<> 150:02e0a0aed4ec 233 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
<> 150:02e0a0aed4ec 234 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS 16
<> 150:02e0a0aed4ec 235 #define MXC_F_FLC_SECURITY_DISABLE_AHB_WR ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_DISABLE_AHB_WR_POS))
<> 150:02e0a0aed4ec 236 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS 24
<> 150:02e0a0aed4ec 237 #define MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_FLC_SETTINGS_LOCK_POS))
<> 150:02e0a0aed4ec 238 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 28
<> 150:02e0a0aed4ec 239 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
<> 150:02e0a0aed4ec 240
<> 150:02e0a0aed4ec 241 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
<> 150:02e0a0aed4ec 242 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
<> 150:02e0a0aed4ec 243 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
<> 150:02e0a0aed4ec 244 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
<> 150:02e0a0aed4ec 245 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
<> 150:02e0a0aed4ec 246 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
<> 150:02e0a0aed4ec 247 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
<> 150:02e0a0aed4ec 248 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
<> 150:02e0a0aed4ec 249
<> 150:02e0a0aed4ec 250 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
<> 150:02e0a0aed4ec 251 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
<> 150:02e0a0aed4ec 252 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS 1
<> 150:02e0a0aed4ec 253 #define MXC_F_FLC_CTRL2_FRC_FCLK1_ON ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_FRC_FCLK1_ON_POS))
<> 150:02e0a0aed4ec 254 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS 3
<> 150:02e0a0aed4ec 255 #define MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_WRITE_ALL_ZEROES_POS))
<> 150:02e0a0aed4ec 256 #define MXC_F_FLC_CTRL2_EN_CHANGE_POS 4
<> 150:02e0a0aed4ec 257 #define MXC_F_FLC_CTRL2_EN_CHANGE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_EN_CHANGE_POS))
<> 150:02e0a0aed4ec 258 #define MXC_F_FLC_CTRL2_SLOW_CLK_POS 5
<> 150:02e0a0aed4ec 259 #define MXC_F_FLC_CTRL2_SLOW_CLK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_SLOW_CLK_POS))
<> 150:02e0a0aed4ec 260 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS 6
<> 150:02e0a0aed4ec 261 #define MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL2_ENABLE_RAM_HRESP_POS))
<> 150:02e0a0aed4ec 262 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
<> 150:02e0a0aed4ec 263 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
<> 150:02e0a0aed4ec 264
<> 150:02e0a0aed4ec 265 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
<> 150:02e0a0aed4ec 266 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
<> 150:02e0a0aed4ec 267 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
<> 150:02e0a0aed4ec 268 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
<> 150:02e0a0aed4ec 269 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
<> 150:02e0a0aed4ec 270 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
<> 150:02e0a0aed4ec 271 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
<> 150:02e0a0aed4ec 272 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
<> 150:02e0a0aed4ec 273 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS 4
<> 150:02e0a0aed4ec 274 #define MXC_F_FLC_INTFL1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_STATE_DONE_POS))
<> 150:02e0a0aed4ec 275 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS 5
<> 150:02e0a0aed4ec 276 #define MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLC_PROG_COMPLETE_POS))
<> 150:02e0a0aed4ec 277
<> 150:02e0a0aed4ec 278 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
<> 150:02e0a0aed4ec 279 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
<> 150:02e0a0aed4ec 280 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
<> 150:02e0a0aed4ec 281 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
<> 150:02e0a0aed4ec 282 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
<> 150:02e0a0aed4ec 283 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
<> 150:02e0a0aed4ec 284 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
<> 150:02e0a0aed4ec 285 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
<> 150:02e0a0aed4ec 286 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS 4
<> 150:02e0a0aed4ec 287 #define MXC_F_FLC_INTEN1_FLC_STATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_STATE_DONE_POS))
<> 150:02e0a0aed4ec 288 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS 5
<> 150:02e0a0aed4ec 289 #define MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLC_PROG_COMPLETE_POS))
<> 150:02e0a0aed4ec 290
<> 150:02e0a0aed4ec 291
<> 150:02e0a0aed4ec 292
<> 150:02e0a0aed4ec 293 #ifdef __cplusplus
<> 150:02e0a0aed4ec 294 }
<> 150:02e0a0aed4ec 295 #endif
<> 150:02e0a0aed4ec 296
<> 150:02e0a0aed4ec 297 #endif /* _MXC_FLC_REGS_H_ */
<> 150:02e0a0aed4ec 298