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targets/TARGET_Maxim/TARGET_MAX32625/device/aes_regs.h@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
150:02e0a0aed4ec 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_AES_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_AES_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t ctrl; /* 0x0000 AES Control and Status */
<> 150:02e0a0aed4ec 66 __I uint32_t rsv004; /* 0x0004 */
<> 150:02e0a0aed4ec 67 __IO uint32_t erase_all; /* 0x0008 Write to Trigger AES Memory Erase */
<> 150:02e0a0aed4ec 68 } mxc_aes_regs_t;
<> 150:02e0a0aed4ec 69
<> 150:02e0a0aed4ec 70
<> 150:02e0a0aed4ec 71 /* Offset Register Description
<> 150:02e0a0aed4ec 72 ============= ============================================================================ */
<> 150:02e0a0aed4ec 73 typedef struct {
<> 150:02e0a0aed4ec 74 __IO uint32_t inp[4]; /* 0x0000-0x000C AES Input (128 bits) */
<> 150:02e0a0aed4ec 75 __IO uint32_t key[8]; /* 0x0010-0x002C AES Symmetric Key (up to 256 bits) */
<> 150:02e0a0aed4ec 76 __IO uint32_t out[4]; /* 0x0030-0x003C AES Output Data (128 bits) */
<> 150:02e0a0aed4ec 77 __IO uint32_t expkey[8]; /* 0x0040-0x005C AES Expanded Key Data (256 bits) */
<> 150:02e0a0aed4ec 78 } mxc_aes_mem_regs_t;
<> 150:02e0a0aed4ec 79
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 /*
<> 150:02e0a0aed4ec 82 Register offsets for module AES.
<> 150:02e0a0aed4ec 83 */
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 #define MXC_R_AES_OFFS_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 86 #define MXC_R_AES_OFFS_ERASE_ALL ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 87 #define MXC_R_AES_MEM_OFFS_INP0 ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 88 #define MXC_R_AES_MEM_OFFS_INP1 ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 89 #define MXC_R_AES_MEM_OFFS_INP2 ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 90 #define MXC_R_AES_MEM_OFFS_INP3 ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 91 #define MXC_R_AES_MEM_OFFS_KEY0 ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 92 #define MXC_R_AES_MEM_OFFS_KEY1 ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 93 #define MXC_R_AES_MEM_OFFS_KEY2 ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 94 #define MXC_R_AES_MEM_OFFS_KEY3 ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 95 #define MXC_R_AES_MEM_OFFS_KEY4 ((uint32_t)0x00000020UL)
<> 150:02e0a0aed4ec 96 #define MXC_R_AES_MEM_OFFS_KEY5 ((uint32_t)0x00000024UL)
<> 150:02e0a0aed4ec 97 #define MXC_R_AES_MEM_OFFS_KEY6 ((uint32_t)0x00000028UL)
<> 150:02e0a0aed4ec 98 #define MXC_R_AES_MEM_OFFS_KEY7 ((uint32_t)0x0000002CUL)
<> 150:02e0a0aed4ec 99 #define MXC_R_AES_MEM_OFFS_OUT0 ((uint32_t)0x00000030UL)
<> 150:02e0a0aed4ec 100 #define MXC_R_AES_MEM_OFFS_OUT1 ((uint32_t)0x00000034UL)
<> 150:02e0a0aed4ec 101 #define MXC_R_AES_MEM_OFFS_OUT2 ((uint32_t)0x00000038UL)
<> 150:02e0a0aed4ec 102 #define MXC_R_AES_MEM_OFFS_OUT3 ((uint32_t)0x0000003CUL)
<> 150:02e0a0aed4ec 103 #define MXC_R_AES_MEM_OFFS_EXPKEY0 ((uint32_t)0x00000040UL)
<> 150:02e0a0aed4ec 104 #define MXC_R_AES_MEM_OFFS_EXPKEY1 ((uint32_t)0x00000044UL)
<> 150:02e0a0aed4ec 105 #define MXC_R_AES_MEM_OFFS_EXPKEY2 ((uint32_t)0x00000048UL)
<> 150:02e0a0aed4ec 106 #define MXC_R_AES_MEM_OFFS_EXPKEY3 ((uint32_t)0x0000004CUL)
<> 150:02e0a0aed4ec 107 #define MXC_R_AES_MEM_OFFS_EXPKEY4 ((uint32_t)0x00000050UL)
<> 150:02e0a0aed4ec 108 #define MXC_R_AES_MEM_OFFS_EXPKEY5 ((uint32_t)0x00000054UL)
<> 150:02e0a0aed4ec 109 #define MXC_R_AES_MEM_OFFS_EXPKEY6 ((uint32_t)0x00000058UL)
<> 150:02e0a0aed4ec 110 #define MXC_R_AES_MEM_OFFS_EXPKEY7 ((uint32_t)0x0000005CUL)
<> 150:02e0a0aed4ec 111
<> 150:02e0a0aed4ec 112
<> 150:02e0a0aed4ec 113 /*
<> 150:02e0a0aed4ec 114 Field positions and masks for module AES.
<> 150:02e0a0aed4ec 115 */
<> 150:02e0a0aed4ec 116
<> 150:02e0a0aed4ec 117 #define MXC_F_AES_CTRL_START_POS 0
<> 150:02e0a0aed4ec 118 #define MXC_F_AES_CTRL_START ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
<> 150:02e0a0aed4ec 119 #define MXC_F_AES_CTRL_CRYPT_MODE_POS 1
<> 150:02e0a0aed4ec 120 #define MXC_F_AES_CTRL_CRYPT_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 150:02e0a0aed4ec 121 #define MXC_F_AES_CTRL_EXP_KEY_MODE_POS 2
<> 150:02e0a0aed4ec 122 #define MXC_F_AES_CTRL_EXP_KEY_MODE ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 150:02e0a0aed4ec 123 #define MXC_F_AES_CTRL_KEY_SIZE_POS 3
<> 150:02e0a0aed4ec 124 #define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 150:02e0a0aed4ec 125 #define MXC_F_AES_CTRL_INTEN_POS 5
<> 150:02e0a0aed4ec 126 #define MXC_F_AES_CTRL_INTEN ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
<> 150:02e0a0aed4ec 127 #define MXC_F_AES_CTRL_INTFL_POS 6
<> 150:02e0a0aed4ec 128 #define MXC_F_AES_CTRL_INTFL ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
<> 150:02e0a0aed4ec 129 #define MXC_F_AES_CTRL_LOAD_HW_KEY_POS 7
<> 150:02e0a0aed4ec 130 #define MXC_F_AES_CTRL_LOAD_HW_KEY ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_LOAD_HW_KEY_POS))
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 /*
<> 150:02e0a0aed4ec 135 Field values and shifted values for module AES.
<> 150:02e0a0aed4ec 136 */
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 #define MXC_V_AES_CTRL_ENCRYPT_MODE ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 139 #define MXC_V_AES_CTRL_DECRYPT_MODE ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 #define MXC_S_AES_CTRL_ENCRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 150:02e0a0aed4ec 142 #define MXC_S_AES_CTRL_DECRYPT_MODE ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 #define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 145 #define MXC_V_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 146
<> 150:02e0a0aed4ec 147 #define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 150:02e0a0aed4ec 148 #define MXC_S_AES_CTRL_USE_LAST_EXP_KEY ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
<> 150:02e0a0aed4ec 149
<> 150:02e0a0aed4ec 150 #define MXC_V_AES_CTRL_KEY_SIZE_128 ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 151 #define MXC_V_AES_CTRL_KEY_SIZE_192 ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 152 #define MXC_V_AES_CTRL_KEY_SIZE_256 ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 153
<> 150:02e0a0aed4ec 154 #define MXC_S_AES_CTRL_KEY_SIZE_128 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 150:02e0a0aed4ec 155 #define MXC_S_AES_CTRL_KEY_SIZE_192 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 150:02e0a0aed4ec 156 #define MXC_S_AES_CTRL_KEY_SIZE_256 ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160 #ifdef __cplusplus
<> 150:02e0a0aed4ec 161 }
<> 150:02e0a0aed4ec 162 #endif
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 #endif /* _MXC_AES_REGS_H_ */
<> 150:02e0a0aed4ec 165