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targets/TARGET_Maxim/TARGET_MAX32620/i2c_api.c@178:c26431f84b0d, 2017-11-09 (annotated)

Committer:
amithy
Date:
Thu Nov 09 22:14:37 2017 +0000
Revision:
178:c26431f84b0d
Parent:
149:156823d33999 
test export

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /*******************************************************************************
<> 149:156823d33999 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 149:156823d33999 5 * copy of this software and associated documentation files (the "Software"),
<> 149:156823d33999 6 * to deal in the Software without restriction, including without limitation
<> 149:156823d33999 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 149:156823d33999 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 149:156823d33999 9 * Software is furnished to do so, subject to the following conditions:
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * The above copyright notice and this permission notice shall be included
<> 149:156823d33999 12 * in all copies or substantial portions of the Software.
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 149:156823d33999 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 149:156823d33999 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 149:156823d33999 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 149:156823d33999 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 149:156823d33999 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 149:156823d33999 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 149:156823d33999 21 *
<> 149:156823d33999 22 * Except as contained in this notice, the name of Maxim Integrated
<> 149:156823d33999 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 149:156823d33999 24 * Products, Inc. Branding Policy.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * The mere transfer of this software does not imply any licenses
<> 149:156823d33999 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 149:156823d33999 28 * trademarks, maskwork rights, or any other form of intellectual
<> 149:156823d33999 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 149:156823d33999 30 * ownership rights.
<> 149:156823d33999 31 *******************************************************************************
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 #include "mbed_assert.h"
<> 149:156823d33999 35 #include "i2c_api.h"
<> 149:156823d33999 36 #include "cmsis.h"
<> 149:156823d33999 37 #include "i2cm_regs.h"
<> 149:156823d33999 38 #include "clkman_regs.h"
<> 149:156823d33999 39 #include "ioman_regs.h"
<> 149:156823d33999 40 #include "PeripheralPins.h"
<> 149:156823d33999 41
<> 149:156823d33999 42 #define I2C_SLAVE_ADDR_READ_BIT 0x0001
<> 149:156823d33999 43
<> 149:156823d33999 44 #ifndef MXC_I2CM_TX_TIMEOUT
<> 149:156823d33999 45 #define MXC_I2CM_TX_TIMEOUT 0x5000
<> 149:156823d33999 46 #endif
<> 149:156823d33999 47
<> 149:156823d33999 48 #ifndef MXC_I2CM_RX_TIMEOUT
<> 149:156823d33999 49 #define MXC_I2CM_RX_TIMEOUT 0x5000
<> 149:156823d33999 50 #endif
<> 149:156823d33999 51
<> 149:156823d33999 52 typedef enum {
<> 149:156823d33999 53 /** 100KHz */
<> 149:156823d33999 54 MXC_E_I2CM_SPEED_100KHZ = 0,
<> 149:156823d33999 55 /** 400KHz */
<> 149:156823d33999 56 MXC_E_I2CM_SPEED_400KHZ
<> 149:156823d33999 57 } i2cm_speed_t;
<> 149:156823d33999 58
<> 149:156823d33999 59 /* Clock divider lookup table */
<> 149:156823d33999 60 static const uint32_t clk_div_table[2][8] = {
<> 149:156823d33999 61 /* MXC_E_I2CM_SPEED_100KHZ */
<> 149:156823d33999 62 {
<> 149:156823d33999 63 /* 0: 12MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 64 (17 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 65 (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 66 /* 1: 24MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 67 (38 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 68 (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 69 /* 2: */ 0, /* not supported */
<> 149:156823d33999 70 /* 3: 48MHz */ ((24 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 71 (80 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 72 (288 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 73 /* 4: */ 0, /* not supported */
<> 149:156823d33999 74 /* 5: */ 0, /* not supported */
<> 149:156823d33999 75 /* 6: */ 0, /* not supported */
<> 149:156823d33999 76 /* 7: 96MHz */ ((48 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 77 (164 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 78 (576 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 79 },
<> 149:156823d33999 80 /* MXC_E_I2CM_SPEED_400KHZ */
<> 149:156823d33999 81 {
<> 149:156823d33999 82 /* 0: 12MHz */ ((2 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 83 (1 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 84 (18 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 85 /* 1: 24MHz */ ((3 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 86 (5 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 87 (36 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 88 /* 2: */ 0, /* not supported */
<> 149:156823d33999 89 /* 3: 48MHz */ ((6 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 90 (15 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 91 (72 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 92 /* 4: */ 0, /* not supported */
<> 149:156823d33999 93 /* 5: */ 0, /* not supported */
<> 149:156823d33999 94 /* 6: */ 0, /* not supported */
<> 149:156823d33999 95 /* 7: 96MHz */ ((12 << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS) |
<> 149:156823d33999 96 (33 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS) |
<> 149:156823d33999 97 (144 << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)),
<> 149:156823d33999 98 },
<> 149:156823d33999 99 };
<> 149:156823d33999 100
<> 149:156823d33999 101 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
<> 149:156823d33999 102 {
<> 149:156823d33999 103 // determine the I2C to use
<> 149:156823d33999 104 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
<> 149:156823d33999 105 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
<> 149:156823d33999 106 mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
<> 149:156823d33999 107 MBED_ASSERT((int)i2c != NC);
<> 149:156823d33999 108
<> 149:156823d33999 109 obj->i2c = i2c;
<> 149:156823d33999 110 obj->fifos = (mxc_i2cm_fifo_regs_t*)MXC_I2CM_GET_BASE_FIFO(MXC_I2CM_GET_IDX(i2c));
<> 149:156823d33999 111 obj->start_pending = 0;
<> 149:156823d33999 112 obj->stop_pending = 0;
<> 149:156823d33999 113
<> 149:156823d33999 114 // configure the pins
<> 149:156823d33999 115 pinmap_pinout(sda, PinMap_I2C_SDA);
<> 149:156823d33999 116 pinmap_pinout(scl, PinMap_I2C_SCL);
<> 149:156823d33999 117
<> 149:156823d33999 118 // enable the clock
<> 149:156823d33999 119 MXC_CLKMAN->sys_clk_ctrl_9_i2cm = MXC_S_CLKMAN_CLK_SCALE_DIV_1;
<> 149:156823d33999 120
<> 149:156823d33999 121 // reset module
<> 149:156823d33999 122 i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
<> 149:156823d33999 123 i2c->ctrl = 0;
<> 149:156823d33999 124
<> 149:156823d33999 125 // set default frequency at 100k
<> 149:156823d33999 126 i2c_frequency(obj, 100000);
<> 149:156823d33999 127
<> 149:156823d33999 128 // set timeout to 255 ms and turn on the auto-stop option
<> 149:156823d33999 129 i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
<> 149:156823d33999 130
<> 149:156823d33999 131 // enable tx_fifo and rx_fifo
<> 149:156823d33999 132 i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
<> 149:156823d33999 133 }
<> 149:156823d33999 134
<> 149:156823d33999 135 void i2c_frequency(i2c_t *obj, int hz)
<> 149:156823d33999 136 {
<> 149:156823d33999 137 // compute clock array index
<> 149:156823d33999 138 // (96Mhz/12M) -1 = 7
<> 149:156823d33999 139 // (48Mhz/12M) -1 = 3
<> 149:156823d33999 140 // (24Mhz/12M) -1 = 1
<> 149:156823d33999 141 // (12Mhz/12M) -1 = 0
<> 149:156823d33999 142 int clki = (SystemCoreClock / 12000000) - 1;
<> 149:156823d33999 143
<> 149:156823d33999 144 // get clock divider settings from lookup table
<> 149:156823d33999 145 if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
<> 149:156823d33999 146 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
<> 149:156823d33999 147 } else if ((hz >= 400000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
<> 149:156823d33999 148 obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
<> 149:156823d33999 149 }
<> 149:156823d33999 150 }
<> 149:156823d33999 151
<> 149:156823d33999 152 static int write_tx_fifo(i2c_t *obj, const uint16_t data)
<> 149:156823d33999 153 {
<> 149:156823d33999 154 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 149:156823d33999 155
<> 149:156823d33999 156 while (*obj->fifos->trans) {
<> 149:156823d33999 157 uint32_t intfl = obj->i2c->intfl;
<> 149:156823d33999 158 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 149:156823d33999 159 return I2C_ERROR_NO_SLAVE;
<> 149:156823d33999 160 }
<> 149:156823d33999 161 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
<> 149:156823d33999 162 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 163 }
<> 149:156823d33999 164 timeout--;
<> 149:156823d33999 165 }
<> 149:156823d33999 166 *obj->fifos->trans = data;
<> 149:156823d33999 167
<> 149:156823d33999 168 return 0;
<> 149:156823d33999 169 }
<> 149:156823d33999 170
<> 149:156823d33999 171 static int wait_tx_in_progress(i2c_t *obj)
<> 149:156823d33999 172 {
<> 149:156823d33999 173 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 149:156823d33999 174
<> 149:156823d33999 175 while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
<> 149:156823d33999 176
<> 149:156823d33999 177 uint32_t intfl = obj->i2c->intfl;
<> 149:156823d33999 178
<> 149:156823d33999 179 if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 149:156823d33999 180 i2c_reset(obj);
<> 149:156823d33999 181 return I2C_ERROR_NO_SLAVE;
<> 149:156823d33999 182 }
<> 149:156823d33999 183
<> 149:156823d33999 184 if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
<> 149:156823d33999 185 i2c_reset(obj);
<> 149:156823d33999 186 return I2C_ERROR_BUS_BUSY;
<> 149:156823d33999 187 }
<> 149:156823d33999 188
<> 149:156823d33999 189 return 0;
<> 149:156823d33999 190 }
<> 149:156823d33999 191
<> 149:156823d33999 192 int i2c_start(i2c_t *obj)
<> 149:156823d33999 193 {
<> 149:156823d33999 194 obj->start_pending = 1;
<> 149:156823d33999 195 return 0;
<> 149:156823d33999 196 }
<> 149:156823d33999 197
<> 149:156823d33999 198 int i2c_stop(i2c_t *obj)
<> 149:156823d33999 199 {
<> 149:156823d33999 200 obj->start_pending = 0;
<> 149:156823d33999 201 write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
<> 149:156823d33999 202
<> 149:156823d33999 203 return wait_tx_in_progress(obj);
<> 149:156823d33999 204 }
<> 149:156823d33999 205
<> 149:156823d33999 206 void i2c_reset(i2c_t *obj)
<> 149:156823d33999 207 {
<> 149:156823d33999 208 obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
<> 149:156823d33999 209 obj->i2c->intfl = 0x3FF; // clear all interrupts
<> 149:156823d33999 210 obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
<> 149:156823d33999 211 obj->start_pending = 0;
<> 149:156823d33999 212 }
<> 149:156823d33999 213
<> 149:156823d33999 214 int i2c_byte_write(i2c_t *obj, int data)
<> 149:156823d33999 215 {
<> 149:156823d33999 216 int err;
<> 149:156823d33999 217
<> 149:156823d33999 218 // clear all interrupts
<> 149:156823d33999 219 obj->i2c->intfl = 0x3FF;
<> 149:156823d33999 220
<> 149:156823d33999 221 if (obj->start_pending) {
<> 149:156823d33999 222 obj->start_pending = 0;
<> 149:156823d33999 223 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
<> 149:156823d33999 224 } else {
<> 149:156823d33999 225 data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
<> 149:156823d33999 226 }
<> 149:156823d33999 227
<> 149:156823d33999 228 if ((err = write_tx_fifo(obj, data)) != 0) {
<> 149:156823d33999 229 return err;
<> 149:156823d33999 230 }
<> 149:156823d33999 231
<> 149:156823d33999 232 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 149:156823d33999 233
<> 149:156823d33999 234 // Wait for the FIFO to be empty
<> 149:156823d33999 235 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY));
<> 149:156823d33999 236
<> 149:156823d33999 237 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
<> 149:156823d33999 238 i2c_reset(obj);
<> 149:156823d33999 239 return 0;
<> 149:156823d33999 240 }
<> 149:156823d33999 241
<> 149:156823d33999 242 if (obj->i2c->intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR)) {
<> 149:156823d33999 243 i2c_reset(obj);
<> 149:156823d33999 244 return 2;
<> 149:156823d33999 245 }
<> 149:156823d33999 246
<> 149:156823d33999 247 return 1;
<> 149:156823d33999 248 }
<> 149:156823d33999 249
<> 149:156823d33999 250 int i2c_byte_read(i2c_t *obj, int last)
<> 149:156823d33999 251 {
<> 149:156823d33999 252 uint16_t fifo_value;
<> 149:156823d33999 253 int err;
<> 149:156823d33999 254
<> 149:156823d33999 255 // clear all interrupts
<> 149:156823d33999 256 obj->i2c->intfl = 0x3FF;
<> 149:156823d33999 257
<> 149:156823d33999 258 if (last) {
<> 149:156823d33999 259 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
<> 149:156823d33999 260 } else {
<> 149:156823d33999 261 fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
<> 149:156823d33999 262 }
<> 149:156823d33999 263
<> 149:156823d33999 264 if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
<> 149:156823d33999 265 i2c_reset(obj);
<> 149:156823d33999 266 return err;
<> 149:156823d33999 267 }
<> 149:156823d33999 268
<> 149:156823d33999 269 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 149:156823d33999 270
<> 149:156823d33999 271 int timeout = MXC_I2CM_RX_TIMEOUT;
<> 149:156823d33999 272 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
<> 149:156823d33999 273 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
<> 149:156823d33999 274 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
<> 149:156823d33999 275 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
<> 149:156823d33999 276 break;
<> 149:156823d33999 277 }
<> 149:156823d33999 278 }
<> 149:156823d33999 279
<> 149:156823d33999 280 if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
<> 149:156823d33999 281 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
<> 149:156823d33999 282 return *obj->fifos->rslts;
<> 149:156823d33999 283 }
<> 149:156823d33999 284
<> 149:156823d33999 285 i2c_reset(obj);
<> 149:156823d33999 286
<> 149:156823d33999 287 return -1;
<> 149:156823d33999 288 }
<> 149:156823d33999 289
<> 149:156823d33999 290 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
<> 149:156823d33999 291 {
<> 149:156823d33999 292 int err, retval = 0;
<> 149:156823d33999 293 int i;
<> 149:156823d33999 294
<> 149:156823d33999 295 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
<> 149:156823d33999 296 return 0;
<> 149:156823d33999 297 }
<> 149:156823d33999 298
<> 149:156823d33999 299 // clear all interrupts
<> 149:156823d33999 300 obj->i2c->intfl = 0x3FF;
<> 149:156823d33999 301
<> 149:156823d33999 302 // write the address to the fifo
<> 149:156823d33999 303 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
<> 149:156823d33999 304 i2c_reset(obj);
<> 149:156823d33999 305 return err;
<> 149:156823d33999 306 }
<> 149:156823d33999 307 obj->start_pending = 0;
<> 149:156823d33999 308
<> 149:156823d33999 309 // start the transaction
<> 149:156823d33999 310 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 149:156823d33999 311
<> 149:156823d33999 312 // load as much of the cmd into the FIFO as possible
<> 149:156823d33999 313 for (i = 0; i < length; i++) {
<> 149:156823d33999 314 if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
<> 149:156823d33999 315 retval = (retval ? retval : err);
<> 149:156823d33999 316 break;
<> 149:156823d33999 317 }
<> 149:156823d33999 318 }
<> 149:156823d33999 319
<> 149:156823d33999 320 if (stop) {
<> 149:156823d33999 321 obj->stop_pending = 0;
<> 149:156823d33999 322 if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
<> 149:156823d33999 323 retval = (retval ? retval : err);
<> 149:156823d33999 324 }
<> 149:156823d33999 325
<> 149:156823d33999 326 if ((err = wait_tx_in_progress(obj)) != 0) {
<> 149:156823d33999 327 retval = (retval ? retval : err);
<> 149:156823d33999 328 }
<> 149:156823d33999 329 } else {
<> 149:156823d33999 330 obj->stop_pending = 1;
<> 149:156823d33999 331 int timeout = MXC_I2CM_TX_TIMEOUT;
<> 149:156823d33999 332 // Wait for TX fifo to be empty
<> 149:156823d33999 333 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--);
<> 149:156823d33999 334 }
<> 149:156823d33999 335
<> 149:156823d33999 336 if (retval == 0) {
<> 149:156823d33999 337 return length;
<> 149:156823d33999 338 }
<> 149:156823d33999 339
<> 149:156823d33999 340 i2c_reset(obj);
<> 149:156823d33999 341
<> 149:156823d33999 342 return retval;
<> 149:156823d33999 343 }
<> 149:156823d33999 344
<> 149:156823d33999 345 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
<> 149:156823d33999 346 {
<> 149:156823d33999 347 int err, retval = 0;
<> 149:156823d33999 348 int i = length;
<> 149:156823d33999 349 int timeout;
<> 149:156823d33999 350
<> 149:156823d33999 351 if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
<> 149:156823d33999 352 return 0;
<> 149:156823d33999 353 }
<> 149:156823d33999 354
<> 149:156823d33999 355 // clear all interrupts
<> 149:156823d33999 356 obj->i2c->intfl = 0x3FF;
<> 149:156823d33999 357
<> 149:156823d33999 358 // start + addr (read)
<> 149:156823d33999 359 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
<> 149:156823d33999 360 goto read_done;
<> 149:156823d33999 361 }
<> 149:156823d33999 362 obj->start_pending = 0;
<> 149:156823d33999 363
<> 149:156823d33999 364 while (i > 256) {
<> 149:156823d33999 365 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
<> 149:156823d33999 366 goto read_done;
<> 149:156823d33999 367 }
<> 149:156823d33999 368 i -= 256;
<> 149:156823d33999 369 }
<> 149:156823d33999 370
<> 149:156823d33999 371 if (i > 1) {
<> 149:156823d33999 372 if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
<> 149:156823d33999 373 goto read_done;
<> 149:156823d33999 374 }
<> 149:156823d33999 375 }
<> 149:156823d33999 376
<> 149:156823d33999 377 // start the transaction
<> 149:156823d33999 378 obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
<> 149:156823d33999 379
<> 149:156823d33999 380 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
<> 149:156823d33999 381 goto read_done;
<> 149:156823d33999 382 }
<> 149:156823d33999 383
<> 149:156823d33999 384 if (stop) {
<> 149:156823d33999 385 if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
<> 149:156823d33999 386 goto read_done;
<> 149:156823d33999 387 }
<> 149:156823d33999 388 }
<> 149:156823d33999 389
<> 149:156823d33999 390 timeout = MXC_I2CM_RX_TIMEOUT;
<> 149:156823d33999 391 i = 0;
<> 149:156823d33999 392 while (i < length) {
<> 149:156823d33999 393 while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
<> 149:156823d33999 394 (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
<> 149:156823d33999 395 if ((--timeout < 0) || (obj->i2c->trans & (MXC_F_I2CM_TRANS_TX_TIMEOUT |
<> 149:156823d33999 396 MXC_F_I2CM_TRANS_TX_LOST_ARBITR | MXC_F_I2CM_TRANS_TX_NACKED))) {
<> 149:156823d33999 397 retval = -3;
<> 149:156823d33999 398 goto read_done;
<> 149:156823d33999 399 }
<> 149:156823d33999 400 }
<> 149:156823d33999 401
<> 149:156823d33999 402 timeout = MXC_I2CM_RX_TIMEOUT;
<> 149:156823d33999 403
<> 149:156823d33999 404 obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
<> 149:156823d33999 405
<> 149:156823d33999 406 uint16_t temp = *obj->fifos->rslts;
<> 149:156823d33999 407
<> 149:156823d33999 408 if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
<> 149:156823d33999 409 continue;
<> 149:156823d33999 410 }
<> 149:156823d33999 411 data[i++] = (uint8_t) temp;
<> 149:156823d33999 412 }
<> 149:156823d33999 413
<> 149:156823d33999 414 read_done:
<> 149:156823d33999 415
<> 149:156823d33999 416 if (stop) {
<> 149:156823d33999 417 obj->stop_pending = 0;
<> 149:156823d33999 418 if ((err = wait_tx_in_progress(obj)) != 0) {
<> 149:156823d33999 419 retval = (retval ? retval : err);
<> 149:156823d33999 420 }
<> 149:156823d33999 421 } else {
<> 149:156823d33999 422 obj->stop_pending = 1;
<> 149:156823d33999 423 }
<> 149:156823d33999 424
<> 149:156823d33999 425 if (retval == 0) {
<> 149:156823d33999 426 return length;
<> 149:156823d33999 427 }
<> 149:156823d33999 428
<> 149:156823d33999 429 i2c_reset(obj);
<> 149:156823d33999 430
<> 149:156823d33999 431 return retval;
<> 149:156823d33999 432 }