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targets/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved. |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
<> | 144:ef7eb2e8f9f7 | 5 | * copy of this software and associated documentation files (the "Software"), |
<> | 144:ef7eb2e8f9f7 | 6 | * to deal in the Software without restriction, including without limitation |
<> | 144:ef7eb2e8f9f7 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
<> | 144:ef7eb2e8f9f7 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
<> | 144:ef7eb2e8f9f7 | 9 | * Software is furnished to do so, subject to the following conditions: |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * The above copyright notice and this permission notice shall be included |
<> | 144:ef7eb2e8f9f7 | 12 | * in all copies or substantial portions of the Software. |
<> | 144:ef7eb2e8f9f7 | 13 | * |
<> | 144:ef7eb2e8f9f7 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
<> | 144:ef7eb2e8f9f7 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
<> | 144:ef7eb2e8f9f7 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
<> | 144:ef7eb2e8f9f7 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
<> | 144:ef7eb2e8f9f7 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
<> | 144:ef7eb2e8f9f7 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
<> | 144:ef7eb2e8f9f7 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
<> | 144:ef7eb2e8f9f7 | 21 | * |
<> | 144:ef7eb2e8f9f7 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
<> | 144:ef7eb2e8f9f7 | 24 | * Products, Inc. Branding Policy. |
<> | 144:ef7eb2e8f9f7 | 25 | * |
<> | 144:ef7eb2e8f9f7 | 26 | * The mere transfer of this software does not imply any licenses |
<> | 144:ef7eb2e8f9f7 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
<> | 144:ef7eb2e8f9f7 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
<> | 144:ef7eb2e8f9f7 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
<> | 144:ef7eb2e8f9f7 | 30 | * ownership rights. |
<> | 144:ef7eb2e8f9f7 | 31 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 32 | */ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 35 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 36 | #include "gpio_irq_api.h" |
<> | 144:ef7eb2e8f9f7 | 37 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | #define NUM_PORTS 3 |
<> | 144:ef7eb2e8f9f7 | 40 | #define NUM_PINS_PER_PORT 8 |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 144:ef7eb2e8f9f7 | 42 | static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}}; |
<> | 144:ef7eb2e8f9f7 | 43 | static gpio_irq_handler irq_handler; |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | static void handle_irq(unsigned int port) |
<> | 144:ef7eb2e8f9f7 | 46 | { |
<> | 144:ef7eb2e8f9f7 | 47 | uint32_t intfl, in_val; |
<> | 144:ef7eb2e8f9f7 | 48 | uint32_t mask; |
<> | 144:ef7eb2e8f9f7 | 49 | unsigned int pin; |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /* Read pin state */ |
<> | 144:ef7eb2e8f9f7 | 52 | in_val = MXC_GPIO->in_val[port]; |
<> | 144:ef7eb2e8f9f7 | 53 | |
<> | 144:ef7eb2e8f9f7 | 54 | /* Read interrupts */ |
<> | 144:ef7eb2e8f9f7 | 55 | intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port]; |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | mask = 1; |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) { |
<> | 144:ef7eb2e8f9f7 | 60 | if (intfl & mask) { |
<> | 144:ef7eb2e8f9f7 | 61 | if (ids[port][pin]) { |
<> | 144:ef7eb2e8f9f7 | 62 | if (in_val & mask) { |
<> | 144:ef7eb2e8f9f7 | 63 | irq_handler(ids[port][pin], IRQ_RISE); |
<> | 144:ef7eb2e8f9f7 | 64 | } else { |
<> | 144:ef7eb2e8f9f7 | 65 | irq_handler(ids[port][pin], IRQ_FALL); |
<> | 144:ef7eb2e8f9f7 | 66 | } |
<> | 144:ef7eb2e8f9f7 | 67 | } |
<> | 144:ef7eb2e8f9f7 | 68 | MXC_GPIO->intfl[port] = mask; /* clear interrupt */ |
<> | 144:ef7eb2e8f9f7 | 69 | } |
<> | 144:ef7eb2e8f9f7 | 70 | mask <<= 1; |
<> | 144:ef7eb2e8f9f7 | 71 | } |
<> | 144:ef7eb2e8f9f7 | 72 | } |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | void gpio_irq_0(void) |
<> | 144:ef7eb2e8f9f7 | 75 | { |
<> | 144:ef7eb2e8f9f7 | 76 | handle_irq(0); |
<> | 144:ef7eb2e8f9f7 | 77 | } |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 144:ef7eb2e8f9f7 | 79 | void gpio_irq_1(void) |
<> | 144:ef7eb2e8f9f7 | 80 | { |
<> | 144:ef7eb2e8f9f7 | 81 | handle_irq(1); |
<> | 144:ef7eb2e8f9f7 | 82 | } |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | void gpio_irq_2(void) |
<> | 144:ef7eb2e8f9f7 | 85 | { |
<> | 144:ef7eb2e8f9f7 | 86 | handle_irq(2); |
<> | 144:ef7eb2e8f9f7 | 87 | } |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id) |
<> | 144:ef7eb2e8f9f7 | 90 | { |
<> | 144:ef7eb2e8f9f7 | 91 | if (name == NC) |
<> | 144:ef7eb2e8f9f7 | 92 | return -1; |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 144:ef7eb2e8f9f7 | 94 | uint8_t port = PINNAME_TO_PORT(name); |
<> | 144:ef7eb2e8f9f7 | 95 | uint8_t pin = PINNAME_TO_PIN(name); |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) { |
<> | 144:ef7eb2e8f9f7 | 98 | return 1; |
<> | 144:ef7eb2e8f9f7 | 99 | } |
<> | 144:ef7eb2e8f9f7 | 100 | |
<> | 144:ef7eb2e8f9f7 | 101 | obj->port = port; |
<> | 144:ef7eb2e8f9f7 | 102 | obj->pin = pin; |
<> | 144:ef7eb2e8f9f7 | 103 | |
<> | 144:ef7eb2e8f9f7 | 104 | irq_handler = handler; |
<> | 144:ef7eb2e8f9f7 | 105 | |
<> | 144:ef7eb2e8f9f7 | 106 | ids[port][pin] = id; |
<> | 144:ef7eb2e8f9f7 | 107 | |
<> | 144:ef7eb2e8f9f7 | 108 | /* register handlers */ |
<> | 144:ef7eb2e8f9f7 | 109 | NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0); |
<> | 144:ef7eb2e8f9f7 | 110 | NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1); |
<> | 144:ef7eb2e8f9f7 | 111 | NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2); |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /* disable the interrupt locally */ |
<> | 144:ef7eb2e8f9f7 | 114 | MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4)); |
<> | 144:ef7eb2e8f9f7 | 115 | |
<> | 144:ef7eb2e8f9f7 | 116 | /* clear a pending request */ |
<> | 144:ef7eb2e8f9f7 | 117 | MXC_GPIO->intfl[port] = 1 << pin; |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /* enable the requested interrupt */ |
<> | 144:ef7eb2e8f9f7 | 120 | MXC_GPIO->inten[port] |= (1 << pin); |
<> | 144:ef7eb2e8f9f7 | 121 | NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port)); |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | return 0; |
<> | 144:ef7eb2e8f9f7 | 124 | } |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | void gpio_irq_free(gpio_irq_t *obj) |
<> | 144:ef7eb2e8f9f7 | 127 | { |
<> | 144:ef7eb2e8f9f7 | 128 | /* disable interrupt */ |
<> | 144:ef7eb2e8f9f7 | 129 | MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 130 | MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4)); |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | ids[obj->port][obj->pin] = 0; |
<> | 144:ef7eb2e8f9f7 | 133 | } |
<> | 144:ef7eb2e8f9f7 | 134 | |
<> | 144:ef7eb2e8f9f7 | 135 | void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) |
<> | 144:ef7eb2e8f9f7 | 136 | { |
<> | 144:ef7eb2e8f9f7 | 137 | uint32_t int_mode = MXC_GPIO->int_mode[obj->port]; |
<> | 144:ef7eb2e8f9f7 | 138 | uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3; /* only supporting edge interrupts */ |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | uint32_t new_mode = curr_mode; |
<> | 144:ef7eb2e8f9f7 | 141 | if (event == IRQ_FALL) { |
<> | 144:ef7eb2e8f9f7 | 142 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 143 | new_mode |= 0x1; |
<> | 144:ef7eb2e8f9f7 | 144 | } else { |
<> | 144:ef7eb2e8f9f7 | 145 | new_mode &= ~0x1; |
<> | 144:ef7eb2e8f9f7 | 146 | } |
<> | 144:ef7eb2e8f9f7 | 147 | } else if (event == IRQ_RISE) { |
<> | 144:ef7eb2e8f9f7 | 148 | if (enable) { |
<> | 144:ef7eb2e8f9f7 | 149 | new_mode |= 0x2; |
<> | 144:ef7eb2e8f9f7 | 150 | } else { |
<> | 144:ef7eb2e8f9f7 | 151 | new_mode &= ~0x2; |
<> | 144:ef7eb2e8f9f7 | 152 | } |
<> | 144:ef7eb2e8f9f7 | 153 | } |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | int_mode &= ~(0xF << (obj->pin*4)); |
<> | 144:ef7eb2e8f9f7 | 156 | int_mode |= (new_mode << (obj->pin*4)); |
<> | 144:ef7eb2e8f9f7 | 157 | MXC_GPIO->int_mode[obj->port] = int_mode; |
<> | 144:ef7eb2e8f9f7 | 158 | } |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | void gpio_irq_enable(gpio_irq_t *obj) |
<> | 144:ef7eb2e8f9f7 | 161 | { |
<> | 144:ef7eb2e8f9f7 | 162 | MXC_GPIO->inten[obj->port] |= (1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 163 | } |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | void gpio_irq_disable(gpio_irq_t *obj) |
<> | 144:ef7eb2e8f9f7 | 166 | { |
<> | 144:ef7eb2e8f9f7 | 167 | MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin); |
<> | 144:ef7eb2e8f9f7 | 168 | } |