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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.h@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 149:156823d33999
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 15:a81a8d6c1dfe | 1 | /** |
mbed_official | 15:a81a8d6c1dfe | 2 | * \file |
mbed_official | 15:a81a8d6c1dfe | 3 | * |
mbed_official | 15:a81a8d6c1dfe | 4 | * \brief SAM Direct Memory Access Controller Driver |
mbed_official | 15:a81a8d6c1dfe | 5 | * |
mbed_official | 15:a81a8d6c1dfe | 6 | * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. |
mbed_official | 15:a81a8d6c1dfe | 7 | * |
mbed_official | 15:a81a8d6c1dfe | 8 | * \asf_license_start |
mbed_official | 15:a81a8d6c1dfe | 9 | * |
mbed_official | 15:a81a8d6c1dfe | 10 | * \page License |
mbed_official | 15:a81a8d6c1dfe | 11 | * |
mbed_official | 15:a81a8d6c1dfe | 12 | * Redistribution and use in source and binary forms, with or without |
mbed_official | 15:a81a8d6c1dfe | 13 | * modification, are permitted provided that the following conditions are met: |
mbed_official | 15:a81a8d6c1dfe | 14 | * |
mbed_official | 15:a81a8d6c1dfe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 15:a81a8d6c1dfe | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 15:a81a8d6c1dfe | 17 | * |
mbed_official | 15:a81a8d6c1dfe | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 15:a81a8d6c1dfe | 19 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 15:a81a8d6c1dfe | 20 | * and/or other materials provided with the distribution. |
mbed_official | 15:a81a8d6c1dfe | 21 | * |
mbed_official | 15:a81a8d6c1dfe | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
mbed_official | 15:a81a8d6c1dfe | 23 | * from this software without specific prior written permission. |
mbed_official | 15:a81a8d6c1dfe | 24 | * |
mbed_official | 15:a81a8d6c1dfe | 25 | * 4. This software may only be redistributed and used in connection with an |
mbed_official | 15:a81a8d6c1dfe | 26 | * Atmel microcontroller product. |
mbed_official | 15:a81a8d6c1dfe | 27 | * |
mbed_official | 15:a81a8d6c1dfe | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
mbed_official | 15:a81a8d6c1dfe | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
mbed_official | 15:a81a8d6c1dfe | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
mbed_official | 15:a81a8d6c1dfe | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
mbed_official | 15:a81a8d6c1dfe | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 15:a81a8d6c1dfe | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
mbed_official | 15:a81a8d6c1dfe | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
mbed_official | 15:a81a8d6c1dfe | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
mbed_official | 15:a81a8d6c1dfe | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
mbed_official | 15:a81a8d6c1dfe | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
mbed_official | 15:a81a8d6c1dfe | 38 | * POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 15:a81a8d6c1dfe | 39 | * |
mbed_official | 15:a81a8d6c1dfe | 40 | * \asf_license_stop |
mbed_official | 15:a81a8d6c1dfe | 41 | * |
mbed_official | 15:a81a8d6c1dfe | 42 | */ |
mbed_official | 15:a81a8d6c1dfe | 43 | /* |
mbed_official | 15:a81a8d6c1dfe | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
mbed_official | 15:a81a8d6c1dfe | 45 | */ |
mbed_official | 15:a81a8d6c1dfe | 46 | #ifndef DMA_H_INCLUDED |
mbed_official | 15:a81a8d6c1dfe | 47 | #define DMA_H_INCLUDED |
mbed_official | 15:a81a8d6c1dfe | 48 | |
mbed_official | 15:a81a8d6c1dfe | 49 | #ifdef __cplusplus |
mbed_official | 15:a81a8d6c1dfe | 50 | extern "C" { |
mbed_official | 15:a81a8d6c1dfe | 51 | #endif |
mbed_official | 15:a81a8d6c1dfe | 52 | |
mbed_official | 15:a81a8d6c1dfe | 53 | /** |
mbed_official | 15:a81a8d6c1dfe | 54 | * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller Driver (DMAC) |
mbed_official | 15:a81a8d6c1dfe | 55 | * |
mbed_official | 15:a81a8d6c1dfe | 56 | * This driver for Atmel® | SMART SAM devices provides an interface for the configuration |
mbed_official | 15:a81a8d6c1dfe | 57 | * and management of the Direct Memory Access Controller(DMAC) module within |
mbed_official | 15:a81a8d6c1dfe | 58 | * the device. The DMAC can transfer data between memories and peripherals, and |
mbed_official | 15:a81a8d6c1dfe | 59 | * thus off-load these tasks from the CPU. The module supports peripheral to |
mbed_official | 15:a81a8d6c1dfe | 60 | * peripheral, peripheral to memory, memory to peripheral, and memory to memory |
mbed_official | 15:a81a8d6c1dfe | 61 | * transfers. |
mbed_official | 15:a81a8d6c1dfe | 62 | * |
mbed_official | 15:a81a8d6c1dfe | 63 | * The following peripherals are used by the DMAC Driver: |
mbed_official | 15:a81a8d6c1dfe | 64 | * - DMAC (Direct Memory Access Controller) |
mbed_official | 15:a81a8d6c1dfe | 65 | * |
mbed_official | 15:a81a8d6c1dfe | 66 | * The following devices can use this module: |
mbed_official | 15:a81a8d6c1dfe | 67 | * - Atmel | SMART SAM D21 |
mbed_official | 15:a81a8d6c1dfe | 68 | * - Atmel | SMART SAM R21 |
mbed_official | 15:a81a8d6c1dfe | 69 | * - Atmel | SMART SAM D10/D11 |
mbed_official | 15:a81a8d6c1dfe | 70 | * - Atmel | SMART SAM L21 |
mbed_official | 15:a81a8d6c1dfe | 71 | * - Atmel | SMART SAM DAx |
mbed_official | 15:a81a8d6c1dfe | 72 | * - Atmel | SMART SAM C20/C21 |
mbed_official | 15:a81a8d6c1dfe | 73 | * |
mbed_official | 15:a81a8d6c1dfe | 74 | * The outline of this documentation is as follows: |
mbed_official | 15:a81a8d6c1dfe | 75 | * - \ref asfdoc_sam0_dma_prerequisites |
mbed_official | 15:a81a8d6c1dfe | 76 | * - \ref asfdoc_sam0_dma_module_overview |
mbed_official | 15:a81a8d6c1dfe | 77 | * - \ref asfdoc_sam0_dma_special_considerations |
mbed_official | 15:a81a8d6c1dfe | 78 | * - \ref asfdoc_sam0_dma_extra_info |
mbed_official | 15:a81a8d6c1dfe | 79 | * - \ref asfdoc_sam0_dma_examples |
mbed_official | 15:a81a8d6c1dfe | 80 | * - \ref asfdoc_sam0_dma_api_overview |
mbed_official | 15:a81a8d6c1dfe | 81 | * |
mbed_official | 15:a81a8d6c1dfe | 82 | * |
mbed_official | 15:a81a8d6c1dfe | 83 | * \section asfdoc_sam0_dma_prerequisites Prerequisites |
mbed_official | 15:a81a8d6c1dfe | 84 | * |
mbed_official | 15:a81a8d6c1dfe | 85 | * There are no prerequisites for this module. |
mbed_official | 15:a81a8d6c1dfe | 86 | * |
mbed_official | 15:a81a8d6c1dfe | 87 | * |
mbed_official | 15:a81a8d6c1dfe | 88 | * \section asfdoc_sam0_dma_module_overview Module Overview |
mbed_official | 15:a81a8d6c1dfe | 89 | * |
mbed_official | 15:a81a8d6c1dfe | 90 | * SAM devices with DMAC enables high data transfer rates with minimum |
mbed_official | 15:a81a8d6c1dfe | 91 | * CPU intervention and frees up CPU time. With access to all peripherals, |
mbed_official | 15:a81a8d6c1dfe | 92 | * the DMAC can handle automatic transfer of data to/from modules. |
mbed_official | 15:a81a8d6c1dfe | 93 | * It supports static and incremental addressing for both source and |
mbed_official | 15:a81a8d6c1dfe | 94 | * destination. |
mbed_official | 15:a81a8d6c1dfe | 95 | * |
mbed_official | 15:a81a8d6c1dfe | 96 | * The DMAC when used with Event System or peripheral triggers, provides a |
mbed_official | 15:a81a8d6c1dfe | 97 | * considerable advantage by reducing the power consumption and performing |
mbed_official | 15:a81a8d6c1dfe | 98 | * data transfer in the background. |
mbed_official | 15:a81a8d6c1dfe | 99 | * For example if the ADC is configured to generate an event, it can trigger |
mbed_official | 15:a81a8d6c1dfe | 100 | * the DMAC to transfer the data into another peripheral or into SRAM. |
mbed_official | 15:a81a8d6c1dfe | 101 | * The CPU can remain in sleep during this time to reduce power consumption. |
mbed_official | 15:a81a8d6c1dfe | 102 | * |
mbed_official | 15:a81a8d6c1dfe | 103 | * <table> |
mbed_official | 15:a81a8d6c1dfe | 104 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 105 | * <th>Device</th> |
mbed_official | 15:a81a8d6c1dfe | 106 | * <th>Dma channel number</th> |
mbed_official | 15:a81a8d6c1dfe | 107 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 108 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 109 | * <td>SAMD21/R21/C20/C21</td> |
mbed_official | 15:a81a8d6c1dfe | 110 | * <td>12</td> |
mbed_official | 15:a81a8d6c1dfe | 111 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 112 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 113 | * <td>SAMD10/D11</td> |
mbed_official | 15:a81a8d6c1dfe | 114 | * <td>6</td> |
mbed_official | 15:a81a8d6c1dfe | 115 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 116 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 117 | * <td>SAML21</td> |
mbed_official | 15:a81a8d6c1dfe | 118 | * <td>16</td> |
mbed_official | 15:a81a8d6c1dfe | 119 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 120 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 121 | * The DMA channel operation can be suspended at any time by software, by events |
mbed_official | 15:a81a8d6c1dfe | 122 | * from event system, or after selectable descriptor execution. The operation |
mbed_official | 15:a81a8d6c1dfe | 123 | * can be resumed by software or by events from event system. |
mbed_official | 15:a81a8d6c1dfe | 124 | * The DMAC driver for SAM supports four types of transfers such as |
mbed_official | 15:a81a8d6c1dfe | 125 | * peripheral to peripheral, peripheral to memory, memory to peripheral, and |
mbed_official | 15:a81a8d6c1dfe | 126 | * memory to memory. |
mbed_official | 15:a81a8d6c1dfe | 127 | * |
mbed_official | 15:a81a8d6c1dfe | 128 | * The basic transfer unit is a beat which is defined as a single bus access. |
mbed_official | 15:a81a8d6c1dfe | 129 | * There can be multiple beats in a single block transfer and multiple block |
mbed_official | 15:a81a8d6c1dfe | 130 | * transfers in a DMA transaction. |
mbed_official | 15:a81a8d6c1dfe | 131 | * DMA transfer is based on descriptors, which holds transfer properties |
mbed_official | 15:a81a8d6c1dfe | 132 | * such as the source and destination addresses, transfer counter, and other |
mbed_official | 15:a81a8d6c1dfe | 133 | * additional transfer control information. |
mbed_official | 15:a81a8d6c1dfe | 134 | * The descriptors can be static or linked. When static, a single block transfer |
mbed_official | 15:a81a8d6c1dfe | 135 | * is performed. When linked, a number of transfer descriptors can be used to |
mbed_official | 15:a81a8d6c1dfe | 136 | * enable multiple block transfers within a single DMA transaction. |
mbed_official | 15:a81a8d6c1dfe | 137 | * |
mbed_official | 15:a81a8d6c1dfe | 138 | * The implementation of the DMA driver is based on the idea that DMA channel |
mbed_official | 15:a81a8d6c1dfe | 139 | * is a finite resource of entities with the same abilities. A DMA channel resource |
mbed_official | 15:a81a8d6c1dfe | 140 | * is able to move a defined set of data from a source address to destination |
mbed_official | 15:a81a8d6c1dfe | 141 | * address triggered by a transfer trigger. On the SAM devices there are 12 |
mbed_official | 15:a81a8d6c1dfe | 142 | * DMA resources available for allocation. Each of these DMA resources can trigger |
mbed_official | 15:a81a8d6c1dfe | 143 | * interrupt callback routines and peripheral events. |
mbed_official | 15:a81a8d6c1dfe | 144 | * The other main features are |
mbed_official | 15:a81a8d6c1dfe | 145 | * |
mbed_official | 15:a81a8d6c1dfe | 146 | * - Selectable transfer trigger source |
mbed_official | 15:a81a8d6c1dfe | 147 | * - Software |
mbed_official | 15:a81a8d6c1dfe | 148 | * - Event System |
mbed_official | 15:a81a8d6c1dfe | 149 | * - Peripheral |
mbed_official | 15:a81a8d6c1dfe | 150 | * - Event input and output is supported for the four lower channels |
mbed_official | 15:a81a8d6c1dfe | 151 | * - Four level channel priority |
mbed_official | 15:a81a8d6c1dfe | 152 | * - Optional interrupt generation on transfer complete, channel error or channel suspend |
mbed_official | 15:a81a8d6c1dfe | 153 | * - Supports multi-buffer or circular buffer mode by linking multiple descriptors |
mbed_official | 15:a81a8d6c1dfe | 154 | * - Beat size configurable as 8-bit, 16-bit, or 32-bit |
mbed_official | 15:a81a8d6c1dfe | 155 | * |
mbed_official | 15:a81a8d6c1dfe | 156 | * A simplified block diagram of the DMA Resource can be seen in |
mbed_official | 15:a81a8d6c1dfe | 157 | * \ref asfdoc_sam0_dma_module_block_diagram "the figure below". |
mbed_official | 15:a81a8d6c1dfe | 158 | * |
mbed_official | 15:a81a8d6c1dfe | 159 | * \anchor asfdoc_sam0_dma_module_block_diagram |
mbed_official | 15:a81a8d6c1dfe | 160 | * \dot |
mbed_official | 15:a81a8d6c1dfe | 161 | * digraph overview { |
mbed_official | 15:a81a8d6c1dfe | 162 | * splines = false; |
mbed_official | 15:a81a8d6c1dfe | 163 | * rankdir=LR; |
mbed_official | 15:a81a8d6c1dfe | 164 | * |
mbed_official | 15:a81a8d6c1dfe | 165 | * mux1 [label="Transfer Trigger", shape=box]; |
mbed_official | 15:a81a8d6c1dfe | 166 | * |
mbed_official | 15:a81a8d6c1dfe | 167 | * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; |
mbed_official | 15:a81a8d6c1dfe | 168 | * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue]; |
mbed_official | 15:a81a8d6c1dfe | 169 | * |
mbed_official | 15:a81a8d6c1dfe | 170 | * mux1 -> dma; |
mbed_official | 15:a81a8d6c1dfe | 171 | * descriptor -> dma; |
mbed_official | 15:a81a8d6c1dfe | 172 | * |
mbed_official | 15:a81a8d6c1dfe | 173 | * interrupt [label="Interrupt", shape=box]; |
mbed_official | 15:a81a8d6c1dfe | 174 | * events [label="Events", shape=box]; |
mbed_official | 15:a81a8d6c1dfe | 175 | * |
mbed_official | 15:a81a8d6c1dfe | 176 | * dma:e -> interrupt:w; |
mbed_official | 15:a81a8d6c1dfe | 177 | * dma:e -> events:w; |
mbed_official | 15:a81a8d6c1dfe | 178 | * |
mbed_official | 15:a81a8d6c1dfe | 179 | * {rank=same; descriptor dma} |
mbed_official | 15:a81a8d6c1dfe | 180 | * |
mbed_official | 15:a81a8d6c1dfe | 181 | * } |
mbed_official | 15:a81a8d6c1dfe | 182 | * \enddot |
mbed_official | 15:a81a8d6c1dfe | 183 | * |
mbed_official | 15:a81a8d6c1dfe | 184 | * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition |
mbed_official | 15:a81a8d6c1dfe | 185 | * <table> |
mbed_official | 15:a81a8d6c1dfe | 186 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 187 | * <th>Driver Feature Macro</th> |
mbed_official | 15:a81a8d6c1dfe | 188 | * <th>Supported devices</th> |
mbed_official | 15:a81a8d6c1dfe | 189 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 190 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 191 | * <td>FEATURE_DMA_CHANNEL_STANDBY</td> |
mbed_official | 15:a81a8d6c1dfe | 192 | * <td>SAML21/C20/C21</td> |
mbed_official | 15:a81a8d6c1dfe | 193 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 194 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 195 | * \note The specific features are only available in the driver when the |
mbed_official | 15:a81a8d6c1dfe | 196 | * selected device supports those features. |
mbed_official | 15:a81a8d6c1dfe | 197 | * |
mbed_official | 15:a81a8d6c1dfe | 198 | * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers |
mbed_official | 15:a81a8d6c1dfe | 199 | * |
mbed_official | 15:a81a8d6c1dfe | 200 | * <table border="0" cellborder="1" cellspacing="0" > |
mbed_official | 15:a81a8d6c1dfe | 201 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 202 | * <th> Name </th> <th> Description </th> |
mbed_official | 15:a81a8d6c1dfe | 203 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 204 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 205 | * <td > Beat </td> |
mbed_official | 15:a81a8d6c1dfe | 206 | * <td > It is a single bus access by the DMAC. |
mbed_official | 15:a81a8d6c1dfe | 207 | * Configurable as 8-bit, 16-bit, or 32-bit |
mbed_official | 15:a81a8d6c1dfe | 208 | * </td> |
mbed_official | 15:a81a8d6c1dfe | 209 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 210 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 211 | * <td > Burst </td> |
mbed_official | 15:a81a8d6c1dfe | 212 | * <td> It is a transfer of n-beats (n=1,4,8,16). |
mbed_official | 15:a81a8d6c1dfe | 213 | * For the DMAC module in SAM, the burst size is one beat. |
mbed_official | 15:a81a8d6c1dfe | 214 | * Arbitration takes place each time a burst transfer is completed |
mbed_official | 15:a81a8d6c1dfe | 215 | * </td> |
mbed_official | 15:a81a8d6c1dfe | 216 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 217 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 218 | * <td > Block transfer </td> |
mbed_official | 15:a81a8d6c1dfe | 219 | * <td> A single block transfer is a configurable number of (1 to 64k) |
mbed_official | 15:a81a8d6c1dfe | 220 | * beat transfers |
mbed_official | 15:a81a8d6c1dfe | 221 | * </td> |
mbed_official | 15:a81a8d6c1dfe | 222 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 223 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 224 | * |
mbed_official | 15:a81a8d6c1dfe | 225 | * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels |
mbed_official | 15:a81a8d6c1dfe | 226 | * The DMAC in each device consists of several DMA channels, which |
mbed_official | 15:a81a8d6c1dfe | 227 | * along with the transfer descriptors defines the data transfer properties. |
mbed_official | 15:a81a8d6c1dfe | 228 | * - The transfer control descriptor defines the source and destination |
mbed_official | 15:a81a8d6c1dfe | 229 | * addresses, source and destination address increment settings, the |
mbed_official | 15:a81a8d6c1dfe | 230 | * block transfer count and event output condition selection |
mbed_official | 15:a81a8d6c1dfe | 231 | * - Dedicated channel registers control the peripheral trigger source, |
mbed_official | 15:a81a8d6c1dfe | 232 | * trigger mode settings, event input actions, and channel priority level |
mbed_official | 15:a81a8d6c1dfe | 233 | * settings |
mbed_official | 15:a81a8d6c1dfe | 234 | * |
mbed_official | 15:a81a8d6c1dfe | 235 | * With a successful DMA resource allocation, a dedicated |
mbed_official | 15:a81a8d6c1dfe | 236 | * DMA channel will be assigned. The channel will be occupied until the |
mbed_official | 15:a81a8d6c1dfe | 237 | * DMA resource is freed. A DMA resource handle is used to identify the specific |
mbed_official | 15:a81a8d6c1dfe | 238 | * DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 239 | * When there are multiple channels with active requests, the arbiter prioritizes |
mbed_official | 15:a81a8d6c1dfe | 240 | * the channels requesting access to the bus. |
mbed_official | 15:a81a8d6c1dfe | 241 | * |
mbed_official | 15:a81a8d6c1dfe | 242 | * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers |
mbed_official | 15:a81a8d6c1dfe | 243 | * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A |
mbed_official | 15:a81a8d6c1dfe | 244 | * transfer request can be triggered from software, peripheral, or an event. There |
mbed_official | 15:a81a8d6c1dfe | 245 | * are dedicated source trigger selections for each DMA channel usage. |
mbed_official | 15:a81a8d6c1dfe | 246 | |
mbed_official | 15:a81a8d6c1dfe | 247 | * |
mbed_official | 15:a81a8d6c1dfe | 248 | * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor |
mbed_official | 15:a81a8d6c1dfe | 249 | * The transfer descriptor resides in the SRAM and |
mbed_official | 15:a81a8d6c1dfe | 250 | * defines these channel properties. |
mbed_official | 15:a81a8d6c1dfe | 251 | * <table border="0" cellborder="1" cellspacing="0" > |
mbed_official | 15:a81a8d6c1dfe | 252 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 253 | * <th> Field name </th> <th> Field width </th> |
mbed_official | 15:a81a8d6c1dfe | 254 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 255 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 256 | * <td > Descriptor Next Address </td> <td > 32 bits </td> |
mbed_official | 15:a81a8d6c1dfe | 257 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 258 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 259 | * <td > Destination Address </td> <td> 32 bits </td> |
mbed_official | 15:a81a8d6c1dfe | 260 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 261 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 262 | * <td > Source Address </td> <td> 32 bits </td> |
mbed_official | 15:a81a8d6c1dfe | 263 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 264 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 265 | * <td > Block Transfer Counter </td> <td> 16 bits </td> |
mbed_official | 15:a81a8d6c1dfe | 266 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 267 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 268 | * <td > Block Transfer Control </td> <td> 16 bits </td> |
mbed_official | 15:a81a8d6c1dfe | 269 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 270 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 271 | * |
mbed_official | 15:a81a8d6c1dfe | 272 | * Before starting a transfer, at least one descriptor should be configured. |
mbed_official | 15:a81a8d6c1dfe | 273 | * After a successful allocation of a DMA channel, the transfer descriptor can |
mbed_official | 15:a81a8d6c1dfe | 274 | * be added with a call to \ref dma_add_descriptor(). If there is a transfer |
mbed_official | 15:a81a8d6c1dfe | 275 | * descriptor already allocated to the DMA resource, the descriptor will |
mbed_official | 15:a81a8d6c1dfe | 276 | * be linked to the next descriptor address. |
mbed_official | 15:a81a8d6c1dfe | 277 | * |
mbed_official | 15:a81a8d6c1dfe | 278 | * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events |
mbed_official | 15:a81a8d6c1dfe | 279 | * Both an interrupt callback and an peripheral event can be triggered by the |
mbed_official | 15:a81a8d6c1dfe | 280 | * DMA transfer. Three types of callbacks are supported by the DMA driver: |
mbed_official | 15:a81a8d6c1dfe | 281 | * transfer complete, channel suspend, and transfer error. Each of these callback |
mbed_official | 15:a81a8d6c1dfe | 282 | * types can be registered and enabled for each channel independently through |
mbed_official | 15:a81a8d6c1dfe | 283 | * the DMA driver API. |
mbed_official | 15:a81a8d6c1dfe | 284 | * |
mbed_official | 15:a81a8d6c1dfe | 285 | * The DMAC module can also generate events on transfer complete. Event |
mbed_official | 15:a81a8d6c1dfe | 286 | * generation is enabled through the DMA channel, event channel configuration, |
mbed_official | 15:a81a8d6c1dfe | 287 | * and event user multiplexing is done through the events driver. |
mbed_official | 15:a81a8d6c1dfe | 288 | * |
mbed_official | 15:a81a8d6c1dfe | 289 | * The DMAC can generate events in the below cases: |
mbed_official | 15:a81a8d6c1dfe | 290 | * |
mbed_official | 15:a81a8d6c1dfe | 291 | * - When a block transfer is complete |
mbed_official | 15:a81a8d6c1dfe | 292 | * |
mbed_official | 15:a81a8d6c1dfe | 293 | * - When each beat transfer within a block transfer is complete |
mbed_official | 15:a81a8d6c1dfe | 294 | * |
mbed_official | 15:a81a8d6c1dfe | 295 | * \section asfdoc_sam0_dma_special_considerations Special Considerations |
mbed_official | 15:a81a8d6c1dfe | 296 | * |
mbed_official | 15:a81a8d6c1dfe | 297 | * There are no special considerations for this module. |
mbed_official | 15:a81a8d6c1dfe | 298 | * |
mbed_official | 15:a81a8d6c1dfe | 299 | * |
mbed_official | 15:a81a8d6c1dfe | 300 | * \section asfdoc_sam0_dma_extra_info Extra Information |
mbed_official | 15:a81a8d6c1dfe | 301 | * |
mbed_official | 15:a81a8d6c1dfe | 302 | * For extra information, see \ref asfdoc_sam0_dma_extra. This includes: |
mbed_official | 15:a81a8d6c1dfe | 303 | * - \ref asfdoc_sam0_dma_extra_acronyms |
mbed_official | 15:a81a8d6c1dfe | 304 | * - \ref asfdoc_sam0_dma_extra_dependencies |
mbed_official | 15:a81a8d6c1dfe | 305 | * - \ref asfdoc_sam0_dma_extra_errata |
mbed_official | 15:a81a8d6c1dfe | 306 | * - \ref asfdoc_sam0_dma_extra_history |
mbed_official | 15:a81a8d6c1dfe | 307 | * |
mbed_official | 15:a81a8d6c1dfe | 308 | * |
mbed_official | 15:a81a8d6c1dfe | 309 | * \section asfdoc_sam0_dma_examples Examples |
mbed_official | 15:a81a8d6c1dfe | 310 | * |
mbed_official | 15:a81a8d6c1dfe | 311 | * For a list of examples related to this driver, see |
mbed_official | 15:a81a8d6c1dfe | 312 | * \ref asfdoc_sam0_dma_exqsg. |
mbed_official | 15:a81a8d6c1dfe | 313 | * |
mbed_official | 15:a81a8d6c1dfe | 314 | * |
mbed_official | 15:a81a8d6c1dfe | 315 | * \section asfdoc_sam0_dma_api_overview API Overview |
mbed_official | 15:a81a8d6c1dfe | 316 | * @{ |
mbed_official | 15:a81a8d6c1dfe | 317 | */ |
mbed_official | 15:a81a8d6c1dfe | 318 | |
mbed_official | 15:a81a8d6c1dfe | 319 | #include <compiler.h> |
mbed_official | 15:a81a8d6c1dfe | 320 | #include "conf_dma.h" |
mbed_official | 15:a81a8d6c1dfe | 321 | |
mbed_official | 15:a81a8d6c1dfe | 322 | #if (SAML21) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) |
mbed_official | 15:a81a8d6c1dfe | 323 | #define FEATURE_DMA_CHANNEL_STANDBY |
mbed_official | 15:a81a8d6c1dfe | 324 | #endif |
mbed_official | 15:a81a8d6c1dfe | 325 | |
mbed_official | 15:a81a8d6c1dfe | 326 | /** DMA invalid channel number. */ |
mbed_official | 15:a81a8d6c1dfe | 327 | #define DMA_INVALID_CHANNEL 0xff |
mbed_official | 15:a81a8d6c1dfe | 328 | |
mbed_official | 15:a81a8d6c1dfe | 329 | /** ExInitial description section. */ |
mbed_official | 15:a81a8d6c1dfe | 330 | extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM]; |
mbed_official | 15:a81a8d6c1dfe | 331 | |
mbed_official | 15:a81a8d6c1dfe | 332 | /* DMA channel interrup flag. */ |
mbed_official | 15:a81a8d6c1dfe | 333 | extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]; |
mbed_official | 15:a81a8d6c1dfe | 334 | |
mbed_official | 15:a81a8d6c1dfe | 335 | /** DMA priority level. */ |
mbed_official | 15:a81a8d6c1dfe | 336 | enum dma_priority_level { |
mbed_official | 15:a81a8d6c1dfe | 337 | /** Priority level 0. */ |
mbed_official | 15:a81a8d6c1dfe | 338 | DMA_PRIORITY_LEVEL_0, |
mbed_official | 15:a81a8d6c1dfe | 339 | /** Priority level 1. */ |
mbed_official | 15:a81a8d6c1dfe | 340 | DMA_PRIORITY_LEVEL_1, |
mbed_official | 15:a81a8d6c1dfe | 341 | /** Priority level 2. */ |
mbed_official | 15:a81a8d6c1dfe | 342 | DMA_PRIORITY_LEVEL_2, |
mbed_official | 15:a81a8d6c1dfe | 343 | /** Priority level 3. */ |
mbed_official | 15:a81a8d6c1dfe | 344 | DMA_PRIORITY_LEVEL_3, |
mbed_official | 15:a81a8d6c1dfe | 345 | }; |
mbed_official | 15:a81a8d6c1dfe | 346 | |
mbed_official | 15:a81a8d6c1dfe | 347 | /** DMA input actions. */ |
mbed_official | 15:a81a8d6c1dfe | 348 | enum dma_event_input_action { |
mbed_official | 15:a81a8d6c1dfe | 349 | /** No action. */ |
mbed_official | 15:a81a8d6c1dfe | 350 | DMA_EVENT_INPUT_NOACT, |
mbed_official | 15:a81a8d6c1dfe | 351 | /** Normal transfer and periodic transfer trigger. */ |
mbed_official | 15:a81a8d6c1dfe | 352 | DMA_EVENT_INPUT_TRIG, |
mbed_official | 15:a81a8d6c1dfe | 353 | /** Conditional transfer trigger. */ |
mbed_official | 15:a81a8d6c1dfe | 354 | DMA_EVENT_INPUT_CTRIG, |
mbed_official | 15:a81a8d6c1dfe | 355 | /** Conditional block transfer. */ |
mbed_official | 15:a81a8d6c1dfe | 356 | DMA_EVENT_INPUT_CBLOCK, |
mbed_official | 15:a81a8d6c1dfe | 357 | /** Channel suspend operation. */ |
mbed_official | 15:a81a8d6c1dfe | 358 | DMA_EVENT_INPUT_SUSPEND, |
mbed_official | 15:a81a8d6c1dfe | 359 | /** Channel resume operation. */ |
mbed_official | 15:a81a8d6c1dfe | 360 | DMA_EVENT_INPUT_RESUME, |
mbed_official | 15:a81a8d6c1dfe | 361 | /** Skip next block suspend action. */ |
mbed_official | 15:a81a8d6c1dfe | 362 | DMA_EVENT_INPUT_SSKIP, |
mbed_official | 15:a81a8d6c1dfe | 363 | }; |
mbed_official | 15:a81a8d6c1dfe | 364 | |
mbed_official | 15:a81a8d6c1dfe | 365 | /** |
mbed_official | 15:a81a8d6c1dfe | 366 | * Address increment step size. These bits select the address increment step |
mbed_official | 15:a81a8d6c1dfe | 367 | * size. The setting apply to source or destination address, depending on |
mbed_official | 15:a81a8d6c1dfe | 368 | * STEPSEL setting. |
mbed_official | 15:a81a8d6c1dfe | 369 | */ |
mbed_official | 15:a81a8d6c1dfe | 370 | enum dma_address_increment_stepsize { |
mbed_official | 15:a81a8d6c1dfe | 371 | /** The address is incremented by (beat size * 1). */ |
mbed_official | 15:a81a8d6c1dfe | 372 | DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, |
mbed_official | 15:a81a8d6c1dfe | 373 | /** The address is incremented by (beat size * 2). */ |
mbed_official | 15:a81a8d6c1dfe | 374 | DMA_ADDRESS_INCREMENT_STEP_SIZE_2, |
mbed_official | 15:a81a8d6c1dfe | 375 | /** The address is incremented by (beat size * 4). */ |
mbed_official | 15:a81a8d6c1dfe | 376 | DMA_ADDRESS_INCREMENT_STEP_SIZE_4, |
mbed_official | 15:a81a8d6c1dfe | 377 | /** The address is incremented by (beat size * 8). */ |
mbed_official | 15:a81a8d6c1dfe | 378 | DMA_ADDRESS_INCREMENT_STEP_SIZE_8, |
mbed_official | 15:a81a8d6c1dfe | 379 | /** The address is incremented by (beat size * 16). */ |
mbed_official | 15:a81a8d6c1dfe | 380 | DMA_ADDRESS_INCREMENT_STEP_SIZE_16, |
mbed_official | 15:a81a8d6c1dfe | 381 | /** The address is incremented by (beat size * 32). */ |
mbed_official | 15:a81a8d6c1dfe | 382 | DMA_ADDRESS_INCREMENT_STEP_SIZE_32, |
mbed_official | 15:a81a8d6c1dfe | 383 | /** The address is incremented by (beat size * 64). */ |
mbed_official | 15:a81a8d6c1dfe | 384 | DMA_ADDRESS_INCREMENT_STEP_SIZE_64, |
mbed_official | 15:a81a8d6c1dfe | 385 | /** The address is incremented by (beat size * 128). */ |
mbed_official | 15:a81a8d6c1dfe | 386 | DMA_ADDRESS_INCREMENT_STEP_SIZE_128, |
mbed_official | 15:a81a8d6c1dfe | 387 | }; |
mbed_official | 15:a81a8d6c1dfe | 388 | |
mbed_official | 15:a81a8d6c1dfe | 389 | /** |
mbed_official | 15:a81a8d6c1dfe | 390 | * DMA step selection. This bit determines whether the step size setting |
mbed_official | 15:a81a8d6c1dfe | 391 | * is applied to source or destination address. |
mbed_official | 15:a81a8d6c1dfe | 392 | */ |
mbed_official | 15:a81a8d6c1dfe | 393 | enum dma_step_selection { |
mbed_official | 15:a81a8d6c1dfe | 394 | /** Step size settings apply to the destination address. */ |
mbed_official | 15:a81a8d6c1dfe | 395 | DMA_STEPSEL_DST = 0, |
mbed_official | 15:a81a8d6c1dfe | 396 | /** Step size settings apply to the source address. */ |
mbed_official | 15:a81a8d6c1dfe | 397 | DMA_STEPSEL_SRC, |
mbed_official | 15:a81a8d6c1dfe | 398 | }; |
mbed_official | 15:a81a8d6c1dfe | 399 | |
mbed_official | 15:a81a8d6c1dfe | 400 | /** The basic transfer unit in DMAC is a beat, which is defined as a |
mbed_official | 15:a81a8d6c1dfe | 401 | * single bus access. Its size is configurable and applies to both read |
mbed_official | 15:a81a8d6c1dfe | 402 | * and write. */ |
mbed_official | 15:a81a8d6c1dfe | 403 | enum dma_beat_size { |
mbed_official | 15:a81a8d6c1dfe | 404 | /** 8-bit access. */ |
mbed_official | 15:a81a8d6c1dfe | 405 | DMA_BEAT_SIZE_BYTE = 0, |
mbed_official | 15:a81a8d6c1dfe | 406 | /** 16-bit access. */ |
mbed_official | 15:a81a8d6c1dfe | 407 | DMA_BEAT_SIZE_HWORD, |
mbed_official | 15:a81a8d6c1dfe | 408 | /** 32-bit access. */ |
mbed_official | 15:a81a8d6c1dfe | 409 | DMA_BEAT_SIZE_WORD, |
mbed_official | 15:a81a8d6c1dfe | 410 | }; |
mbed_official | 15:a81a8d6c1dfe | 411 | |
mbed_official | 15:a81a8d6c1dfe | 412 | /** |
mbed_official | 15:a81a8d6c1dfe | 413 | * Block action definitions. |
mbed_official | 15:a81a8d6c1dfe | 414 | */ |
mbed_official | 15:a81a8d6c1dfe | 415 | enum dma_block_action { |
mbed_official | 15:a81a8d6c1dfe | 416 | /** No action. */ |
mbed_official | 15:a81a8d6c1dfe | 417 | DMA_BLOCK_ACTION_NOACT = 0, |
mbed_official | 15:a81a8d6c1dfe | 418 | /** Channel in normal operation and sets transfer complete interrupt flag |
mbed_official | 15:a81a8d6c1dfe | 419 | * after block transfer. */ |
mbed_official | 15:a81a8d6c1dfe | 420 | DMA_BLOCK_ACTION_INT, |
mbed_official | 15:a81a8d6c1dfe | 421 | /** Trigger channel suspend after block transfer and sets channel |
mbed_official | 15:a81a8d6c1dfe | 422 | * suspend interrupt flag once the channel is suspended. */ |
mbed_official | 15:a81a8d6c1dfe | 423 | DMA_BLOCK_ACTION_SUSPEND, |
mbed_official | 15:a81a8d6c1dfe | 424 | /** Sets transfer complete interrupt flag after a block transfer and |
mbed_official | 15:a81a8d6c1dfe | 425 | * trigger channel suspend. The channel suspend interrupt flag will be set |
mbed_official | 15:a81a8d6c1dfe | 426 | * once the channel is suspended. */ |
mbed_official | 15:a81a8d6c1dfe | 427 | DMA_BLOCK_ACTION_BOTH, |
mbed_official | 15:a81a8d6c1dfe | 428 | }; |
mbed_official | 15:a81a8d6c1dfe | 429 | |
mbed_official | 15:a81a8d6c1dfe | 430 | /** Event output selection. */ |
mbed_official | 15:a81a8d6c1dfe | 431 | enum dma_event_output_selection { |
mbed_official | 15:a81a8d6c1dfe | 432 | /** Event generation disable. */ |
mbed_official | 15:a81a8d6c1dfe | 433 | DMA_EVENT_OUTPUT_DISABLE = 0, |
mbed_official | 15:a81a8d6c1dfe | 434 | /** Event strobe when block transfer complete. */ |
mbed_official | 15:a81a8d6c1dfe | 435 | DMA_EVENT_OUTPUT_BLOCK, |
mbed_official | 15:a81a8d6c1dfe | 436 | /** Event output reserved. */ |
mbed_official | 15:a81a8d6c1dfe | 437 | DMA_EVENT_OUTPUT_RESERVED, |
mbed_official | 15:a81a8d6c1dfe | 438 | /** Event strobe when beat transfer complete. */ |
mbed_official | 15:a81a8d6c1dfe | 439 | DMA_EVENT_OUTPUT_BEAT, |
mbed_official | 15:a81a8d6c1dfe | 440 | }; |
mbed_official | 15:a81a8d6c1dfe | 441 | |
mbed_official | 15:a81a8d6c1dfe | 442 | /** DMA trigger action type. */ |
mbed_official | 15:a81a8d6c1dfe | 443 | enum dma_transfer_trigger_action { |
mbed_official | 15:a81a8d6c1dfe | 444 | /** Perform a block transfer when triggered. */ |
mbed_official | 15:a81a8d6c1dfe | 445 | DMA_TRIGGER_ACTON_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val, |
mbed_official | 15:a81a8d6c1dfe | 446 | /** Perform a beat transfer when triggered. */ |
mbed_official | 15:a81a8d6c1dfe | 447 | DMA_TRIGGER_ACTON_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val, |
mbed_official | 15:a81a8d6c1dfe | 448 | /** Perform a transaction when triggered. */ |
mbed_official | 15:a81a8d6c1dfe | 449 | DMA_TRIGGER_ACTON_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val, |
mbed_official | 15:a81a8d6c1dfe | 450 | }; |
mbed_official | 15:a81a8d6c1dfe | 451 | |
mbed_official | 15:a81a8d6c1dfe | 452 | /** |
mbed_official | 15:a81a8d6c1dfe | 453 | * Callback types for DMA callback driver. |
mbed_official | 15:a81a8d6c1dfe | 454 | */ |
mbed_official | 15:a81a8d6c1dfe | 455 | enum dma_callback_type { |
mbed_official | 15:a81a8d6c1dfe | 456 | /** Callback for any of transfer errors. A transfer error is flagged |
mbed_official | 15:a81a8d6c1dfe | 457 | * if a bus error is detected during an AHB access or when the DMAC |
mbed_official | 15:a81a8d6c1dfe | 458 | * fetches an invalid descriptor. */ |
mbed_official | 15:a81a8d6c1dfe | 459 | DMA_CALLBACK_TRANSFER_ERROR, |
mbed_official | 15:a81a8d6c1dfe | 460 | /** Callback for transfer complete. */ |
mbed_official | 15:a81a8d6c1dfe | 461 | DMA_CALLBACK_TRANSFER_DONE, |
mbed_official | 15:a81a8d6c1dfe | 462 | /** Callback for channel suspend. */ |
mbed_official | 15:a81a8d6c1dfe | 463 | DMA_CALLBACK_CHANNEL_SUSPEND, |
mbed_official | 15:a81a8d6c1dfe | 464 | /** Number of available callbacks. */ |
mbed_official | 15:a81a8d6c1dfe | 465 | DMA_CALLBACK_N, |
mbed_official | 15:a81a8d6c1dfe | 466 | }; |
mbed_official | 15:a81a8d6c1dfe | 467 | |
mbed_official | 15:a81a8d6c1dfe | 468 | /** |
mbed_official | 15:a81a8d6c1dfe | 469 | * DMA transfer descriptor configuration. When the source or destination address |
mbed_official | 15:a81a8d6c1dfe | 470 | * increment is enabled, the addresses stored into the configuration structure |
mbed_official | 15:a81a8d6c1dfe | 471 | * must correspond to the end of the transfer. |
mbed_official | 15:a81a8d6c1dfe | 472 | * |
mbed_official | 15:a81a8d6c1dfe | 473 | */ |
mbed_official | 15:a81a8d6c1dfe | 474 | struct dma_descriptor_config { |
mbed_official | 15:a81a8d6c1dfe | 475 | /** Descriptor valid flag used to identify whether a descriptor is |
mbed_official | 15:a81a8d6c1dfe | 476 | valid or not. */ |
mbed_official | 15:a81a8d6c1dfe | 477 | bool descriptor_valid; |
mbed_official | 15:a81a8d6c1dfe | 478 | /** This is used to generate an event on specific transfer action in |
mbed_official | 15:a81a8d6c1dfe | 479 | a channel. Supported only in four lower channels. */ |
mbed_official | 15:a81a8d6c1dfe | 480 | enum dma_event_output_selection event_output_selection; |
mbed_official | 15:a81a8d6c1dfe | 481 | /** Action taken when a block transfer is completed. */ |
mbed_official | 15:a81a8d6c1dfe | 482 | enum dma_block_action block_action; |
mbed_official | 15:a81a8d6c1dfe | 483 | /** Beat size is configurable as 8-bit, 16-bit, or 32-bit. */ |
mbed_official | 15:a81a8d6c1dfe | 484 | enum dma_beat_size beat_size; |
mbed_official | 15:a81a8d6c1dfe | 485 | /** Used for enabling the source address increment. */ |
mbed_official | 15:a81a8d6c1dfe | 486 | bool src_increment_enable; |
mbed_official | 15:a81a8d6c1dfe | 487 | /** Used for enabling the destination address increment. */ |
mbed_official | 15:a81a8d6c1dfe | 488 | bool dst_increment_enable; |
mbed_official | 15:a81a8d6c1dfe | 489 | /** This bit selects whether the source or destination address is |
mbed_official | 15:a81a8d6c1dfe | 490 | using the step size settings. */ |
mbed_official | 15:a81a8d6c1dfe | 491 | enum dma_step_selection step_selection; |
mbed_official | 15:a81a8d6c1dfe | 492 | /** The step size for source/destination address increment. |
mbed_official | 15:a81a8d6c1dfe | 493 | The next address is calculated |
mbed_official | 15:a81a8d6c1dfe | 494 | as next_addr = addr + (2^step_size * beat size). */ |
mbed_official | 15:a81a8d6c1dfe | 495 | enum dma_address_increment_stepsize step_size; |
mbed_official | 15:a81a8d6c1dfe | 496 | /** It is the number of beats in a block. This count value is |
mbed_official | 15:a81a8d6c1dfe | 497 | * decremented by one after each beat data transfer. */ |
mbed_official | 15:a81a8d6c1dfe | 498 | uint16_t block_transfer_count; |
mbed_official | 15:a81a8d6c1dfe | 499 | /** Transfer source address. */ |
mbed_official | 15:a81a8d6c1dfe | 500 | uint32_t source_address; |
mbed_official | 15:a81a8d6c1dfe | 501 | /** Transfer destination address. */ |
mbed_official | 15:a81a8d6c1dfe | 502 | uint32_t destination_address; |
mbed_official | 15:a81a8d6c1dfe | 503 | /** Set to zero for static descriptors. This must have a valid memory |
mbed_official | 15:a81a8d6c1dfe | 504 | address for linked descriptors. */ |
mbed_official | 15:a81a8d6c1dfe | 505 | uint32_t next_descriptor_address; |
mbed_official | 15:a81a8d6c1dfe | 506 | }; |
mbed_official | 15:a81a8d6c1dfe | 507 | |
mbed_official | 15:a81a8d6c1dfe | 508 | /** Configurations for DMA events. */ |
mbed_official | 15:a81a8d6c1dfe | 509 | struct dma_events_config { |
mbed_official | 15:a81a8d6c1dfe | 510 | /** Event input actions. */ |
mbed_official | 15:a81a8d6c1dfe | 511 | enum dma_event_input_action input_action; |
mbed_official | 15:a81a8d6c1dfe | 512 | /** Enable DMA event output. */ |
mbed_official | 15:a81a8d6c1dfe | 513 | bool event_output_enable; |
mbed_official | 15:a81a8d6c1dfe | 514 | }; |
mbed_official | 15:a81a8d6c1dfe | 515 | |
mbed_official | 15:a81a8d6c1dfe | 516 | /** DMA configurations for transfer. */ |
mbed_official | 15:a81a8d6c1dfe | 517 | struct dma_resource_config { |
mbed_official | 15:a81a8d6c1dfe | 518 | /** DMA transfer priority. */ |
mbed_official | 15:a81a8d6c1dfe | 519 | enum dma_priority_level priority; |
mbed_official | 15:a81a8d6c1dfe | 520 | /**DMA peripheral trigger index. */ |
mbed_official | 15:a81a8d6c1dfe | 521 | uint8_t peripheral_trigger; |
mbed_official | 15:a81a8d6c1dfe | 522 | /** DMA trigger action. */ |
mbed_official | 15:a81a8d6c1dfe | 523 | enum dma_transfer_trigger_action trigger_action; |
mbed_official | 15:a81a8d6c1dfe | 524 | #ifdef FEATURE_DMA_CHANNEL_STANDBY |
mbed_official | 15:a81a8d6c1dfe | 525 | /** Keep DMA channel enabled in standby sleep mode if true. */ |
mbed_official | 15:a81a8d6c1dfe | 526 | bool run_in_standby; |
mbed_official | 15:a81a8d6c1dfe | 527 | #endif |
mbed_official | 15:a81a8d6c1dfe | 528 | /** DMA events configurations. */ |
mbed_official | 15:a81a8d6c1dfe | 529 | struct dma_events_config event_config; |
mbed_official | 15:a81a8d6c1dfe | 530 | }; |
mbed_official | 15:a81a8d6c1dfe | 531 | |
mbed_official | 15:a81a8d6c1dfe | 532 | /** Forward definition of the DMA resource. */ |
mbed_official | 15:a81a8d6c1dfe | 533 | struct dma_resource; |
mbed_official | 15:a81a8d6c1dfe | 534 | /** Type definition for a DMA resource callback function. */ |
mbed_official | 15:a81a8d6c1dfe | 535 | typedef void (*dma_callback_t)(struct dma_resource *const resource); |
mbed_official | 15:a81a8d6c1dfe | 536 | |
mbed_official | 15:a81a8d6c1dfe | 537 | /** Structure for DMA transfer resource. */ |
mbed_official | 15:a81a8d6c1dfe | 538 | struct dma_resource { |
mbed_official | 15:a81a8d6c1dfe | 539 | /** Allocated DMA channel ID. */ |
mbed_official | 15:a81a8d6c1dfe | 540 | uint8_t channel_id; |
mbed_official | 15:a81a8d6c1dfe | 541 | /** Array of callback functions for DMA transfer job. */ |
mbed_official | 15:a81a8d6c1dfe | 542 | dma_callback_t callback[DMA_CALLBACK_N]; |
mbed_official | 15:a81a8d6c1dfe | 543 | /** Bit mask for enabled callbacks. */ |
mbed_official | 15:a81a8d6c1dfe | 544 | uint8_t callback_enable; |
mbed_official | 15:a81a8d6c1dfe | 545 | /** Status of the last job. */ |
mbed_official | 15:a81a8d6c1dfe | 546 | volatile enum status_code job_status; |
mbed_official | 15:a81a8d6c1dfe | 547 | /** Transferred data size. */ |
mbed_official | 15:a81a8d6c1dfe | 548 | uint32_t transfered_size; |
mbed_official | 15:a81a8d6c1dfe | 549 | /** DMA transfer descriptor. */ |
mbed_official | 15:a81a8d6c1dfe | 550 | DmacDescriptor* descriptor; |
mbed_official | 15:a81a8d6c1dfe | 551 | }; |
mbed_official | 15:a81a8d6c1dfe | 552 | |
mbed_official | 15:a81a8d6c1dfe | 553 | /** |
mbed_official | 15:a81a8d6c1dfe | 554 | * \brief Get DMA resource status. |
mbed_official | 15:a81a8d6c1dfe | 555 | * |
mbed_official | 15:a81a8d6c1dfe | 556 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 557 | * |
mbed_official | 15:a81a8d6c1dfe | 558 | * \return Status of the DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 559 | */ |
mbed_official | 15:a81a8d6c1dfe | 560 | static inline enum status_code dma_get_job_status(struct dma_resource *resource) |
mbed_official | 15:a81a8d6c1dfe | 561 | { |
mbed_official | 15:a81a8d6c1dfe | 562 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 563 | |
mbed_official | 15:a81a8d6c1dfe | 564 | return resource->job_status; |
mbed_official | 15:a81a8d6c1dfe | 565 | } |
mbed_official | 15:a81a8d6c1dfe | 566 | |
mbed_official | 15:a81a8d6c1dfe | 567 | /** |
mbed_official | 15:a81a8d6c1dfe | 568 | * \brief Check if the given DMA resource is busy. |
mbed_official | 15:a81a8d6c1dfe | 569 | * |
mbed_official | 15:a81a8d6c1dfe | 570 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 571 | * |
mbed_official | 15:a81a8d6c1dfe | 572 | * \return Status which indicates whether the DMA resource is busy. |
mbed_official | 15:a81a8d6c1dfe | 573 | * |
mbed_official | 15:a81a8d6c1dfe | 574 | * \retval true The DMA resource has an on-going transfer |
mbed_official | 15:a81a8d6c1dfe | 575 | * \retval false The DMA resource is not busy |
mbed_official | 15:a81a8d6c1dfe | 576 | */ |
mbed_official | 15:a81a8d6c1dfe | 577 | static inline bool dma_is_busy(struct dma_resource *resource) |
mbed_official | 15:a81a8d6c1dfe | 578 | { |
mbed_official | 15:a81a8d6c1dfe | 579 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 580 | |
mbed_official | 15:a81a8d6c1dfe | 581 | return (resource->job_status == STATUS_BUSY); |
mbed_official | 15:a81a8d6c1dfe | 582 | } |
mbed_official | 15:a81a8d6c1dfe | 583 | |
mbed_official | 15:a81a8d6c1dfe | 584 | /** |
mbed_official | 15:a81a8d6c1dfe | 585 | * \brief Enable a callback function for a dedicated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 586 | * |
mbed_official | 15:a81a8d6c1dfe | 587 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 588 | * \param[in] type Callback function type |
mbed_official | 15:a81a8d6c1dfe | 589 | * |
mbed_official | 15:a81a8d6c1dfe | 590 | */ |
mbed_official | 15:a81a8d6c1dfe | 591 | static inline void dma_enable_callback(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 592 | enum dma_callback_type type) |
mbed_official | 15:a81a8d6c1dfe | 593 | { |
mbed_official | 15:a81a8d6c1dfe | 594 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 595 | |
mbed_official | 15:a81a8d6c1dfe | 596 | resource->callback_enable |= 1 << type; |
mbed_official | 15:a81a8d6c1dfe | 597 | g_chan_interrupt_flag[resource->channel_id] |= (1UL << type); |
mbed_official | 15:a81a8d6c1dfe | 598 | } |
mbed_official | 15:a81a8d6c1dfe | 599 | |
mbed_official | 15:a81a8d6c1dfe | 600 | /** |
mbed_official | 15:a81a8d6c1dfe | 601 | * \brief Disable a callback function for a dedicated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 602 | * |
mbed_official | 15:a81a8d6c1dfe | 603 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 604 | * \param[in] type Callback function type |
mbed_official | 15:a81a8d6c1dfe | 605 | * |
mbed_official | 15:a81a8d6c1dfe | 606 | */ |
mbed_official | 15:a81a8d6c1dfe | 607 | static inline void dma_disable_callback(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 608 | enum dma_callback_type type) |
mbed_official | 15:a81a8d6c1dfe | 609 | { |
mbed_official | 15:a81a8d6c1dfe | 610 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 611 | |
mbed_official | 15:a81a8d6c1dfe | 612 | resource->callback_enable &= ~(1 << type); |
mbed_official | 15:a81a8d6c1dfe | 613 | g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK); |
mbed_official | 15:a81a8d6c1dfe | 614 | DMAC->CHINTENCLR.reg = (1UL << type); |
mbed_official | 15:a81a8d6c1dfe | 615 | } |
mbed_official | 15:a81a8d6c1dfe | 616 | |
mbed_official | 15:a81a8d6c1dfe | 617 | /** |
mbed_official | 15:a81a8d6c1dfe | 618 | * \brief Register a callback function for a dedicated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 619 | * |
mbed_official | 15:a81a8d6c1dfe | 620 | * There are three types of callback functions, which can be registered: |
mbed_official | 15:a81a8d6c1dfe | 621 | * - Callback for transfer complete |
mbed_official | 15:a81a8d6c1dfe | 622 | * - Callback for transfer error |
mbed_official | 15:a81a8d6c1dfe | 623 | * - Callback for channel suspend |
mbed_official | 15:a81a8d6c1dfe | 624 | * |
mbed_official | 15:a81a8d6c1dfe | 625 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 626 | * \param[in] callback Pointer to the callback function |
mbed_official | 15:a81a8d6c1dfe | 627 | * \param[in] type Callback function type |
mbed_official | 15:a81a8d6c1dfe | 628 | * |
mbed_official | 15:a81a8d6c1dfe | 629 | */ |
mbed_official | 15:a81a8d6c1dfe | 630 | static inline void dma_register_callback(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 631 | dma_callback_t callback, enum dma_callback_type type) |
mbed_official | 15:a81a8d6c1dfe | 632 | { |
mbed_official | 15:a81a8d6c1dfe | 633 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 634 | |
mbed_official | 15:a81a8d6c1dfe | 635 | resource->callback[type] = callback; |
mbed_official | 15:a81a8d6c1dfe | 636 | } |
mbed_official | 15:a81a8d6c1dfe | 637 | |
mbed_official | 15:a81a8d6c1dfe | 638 | /** |
mbed_official | 15:a81a8d6c1dfe | 639 | * \brief Unregister a callback function for a dedicated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 640 | * |
mbed_official | 15:a81a8d6c1dfe | 641 | * There are three types of callback functions: |
mbed_official | 15:a81a8d6c1dfe | 642 | * - Callback for transfer complete |
mbed_official | 15:a81a8d6c1dfe | 643 | * - Callback for transfer error |
mbed_official | 15:a81a8d6c1dfe | 644 | * - Callback for channel suspend |
mbed_official | 15:a81a8d6c1dfe | 645 | * |
mbed_official | 15:a81a8d6c1dfe | 646 | * The application can unregister any of the callback functions which |
mbed_official | 15:a81a8d6c1dfe | 647 | * are already registered and are no longer needed. |
mbed_official | 15:a81a8d6c1dfe | 648 | * |
mbed_official | 15:a81a8d6c1dfe | 649 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 650 | * \param[in] type Callback function type |
mbed_official | 15:a81a8d6c1dfe | 651 | * |
mbed_official | 15:a81a8d6c1dfe | 652 | */ |
mbed_official | 15:a81a8d6c1dfe | 653 | static inline void dma_unregister_callback(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 654 | enum dma_callback_type type) |
mbed_official | 15:a81a8d6c1dfe | 655 | { |
mbed_official | 15:a81a8d6c1dfe | 656 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 657 | |
mbed_official | 15:a81a8d6c1dfe | 658 | resource->callback[type] = NULL; |
mbed_official | 15:a81a8d6c1dfe | 659 | } |
mbed_official | 15:a81a8d6c1dfe | 660 | |
mbed_official | 15:a81a8d6c1dfe | 661 | /** |
mbed_official | 15:a81a8d6c1dfe | 662 | * \brief Will set a software trigger for resource. |
mbed_official | 15:a81a8d6c1dfe | 663 | * |
mbed_official | 15:a81a8d6c1dfe | 664 | * This function is used to set a software trigger on the DMA channel |
mbed_official | 15:a81a8d6c1dfe | 665 | * associated with resource. If a trigger is already pending no new trigger |
mbed_official | 15:a81a8d6c1dfe | 666 | * will be generated for the channel. |
mbed_official | 15:a81a8d6c1dfe | 667 | * |
mbed_official | 15:a81a8d6c1dfe | 668 | * \param[in] resource Pointer to the DMA resource |
mbed_official | 15:a81a8d6c1dfe | 669 | */ |
mbed_official | 15:a81a8d6c1dfe | 670 | static inline void dma_trigger_transfer(struct dma_resource *resource) |
mbed_official | 15:a81a8d6c1dfe | 671 | { |
mbed_official | 15:a81a8d6c1dfe | 672 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 673 | |
mbed_official | 15:a81a8d6c1dfe | 674 | DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id); |
mbed_official | 15:a81a8d6c1dfe | 675 | } |
mbed_official | 15:a81a8d6c1dfe | 676 | |
mbed_official | 15:a81a8d6c1dfe | 677 | /** |
mbed_official | 15:a81a8d6c1dfe | 678 | * \brief Initializes DMA transfer configuration with predefined default values. |
mbed_official | 15:a81a8d6c1dfe | 679 | * |
mbed_official | 15:a81a8d6c1dfe | 680 | * This function will initialize a given DMA descriptor configuration structure to |
mbed_official | 15:a81a8d6c1dfe | 681 | * a set of known default values. This function should be called on |
mbed_official | 15:a81a8d6c1dfe | 682 | * any new instance of the configuration structure before being |
mbed_official | 15:a81a8d6c1dfe | 683 | * modified by the user application. |
mbed_official | 15:a81a8d6c1dfe | 684 | * |
mbed_official | 15:a81a8d6c1dfe | 685 | * The default configuration is as follows: |
mbed_official | 15:a81a8d6c1dfe | 686 | * \li Set the descriptor as valid |
mbed_official | 15:a81a8d6c1dfe | 687 | * \li Disable event output |
mbed_official | 15:a81a8d6c1dfe | 688 | * \li No block action |
mbed_official | 15:a81a8d6c1dfe | 689 | * \li Set beat size as byte |
mbed_official | 15:a81a8d6c1dfe | 690 | * \li Enable source increment |
mbed_official | 15:a81a8d6c1dfe | 691 | * \li Enable destination increment |
mbed_official | 15:a81a8d6c1dfe | 692 | * \li Step size is applied to the destination address |
mbed_official | 15:a81a8d6c1dfe | 693 | * \li Address increment is beat size multiplied by 1 |
mbed_official | 15:a81a8d6c1dfe | 694 | * \li Default transfer size is set to 0 |
mbed_official | 15:a81a8d6c1dfe | 695 | * \li Default source address is set to NULL |
mbed_official | 15:a81a8d6c1dfe | 696 | * \li Default destination address is set to NULL |
mbed_official | 15:a81a8d6c1dfe | 697 | * \li Default next descriptor not available |
mbed_official | 15:a81a8d6c1dfe | 698 | * \param[out] config Pointer to the configuration |
mbed_official | 15:a81a8d6c1dfe | 699 | * |
mbed_official | 15:a81a8d6c1dfe | 700 | */ |
mbed_official | 15:a81a8d6c1dfe | 701 | static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config) |
mbed_official | 15:a81a8d6c1dfe | 702 | { |
mbed_official | 15:a81a8d6c1dfe | 703 | Assert(config); |
mbed_official | 15:a81a8d6c1dfe | 704 | |
mbed_official | 15:a81a8d6c1dfe | 705 | /* Set descriptor as valid */ |
mbed_official | 15:a81a8d6c1dfe | 706 | config->descriptor_valid = true; |
mbed_official | 15:a81a8d6c1dfe | 707 | /* Disable event output */ |
mbed_official | 15:a81a8d6c1dfe | 708 | config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE; |
mbed_official | 15:a81a8d6c1dfe | 709 | /* No block action */ |
mbed_official | 15:a81a8d6c1dfe | 710 | config->block_action = DMA_BLOCK_ACTION_NOACT; |
mbed_official | 15:a81a8d6c1dfe | 711 | /* Set beat size to one byte */ |
mbed_official | 15:a81a8d6c1dfe | 712 | config->beat_size = DMA_BEAT_SIZE_BYTE; |
mbed_official | 15:a81a8d6c1dfe | 713 | /* Enable source increment */ |
mbed_official | 15:a81a8d6c1dfe | 714 | config->src_increment_enable = true; |
mbed_official | 15:a81a8d6c1dfe | 715 | /* Enable destination increment */ |
mbed_official | 15:a81a8d6c1dfe | 716 | config->dst_increment_enable = true; |
mbed_official | 15:a81a8d6c1dfe | 717 | /* Step size is applied to the destination address */ |
mbed_official | 15:a81a8d6c1dfe | 718 | config->step_selection = DMA_STEPSEL_DST; |
mbed_official | 15:a81a8d6c1dfe | 719 | /* Address increment is beat size multiplied by 1*/ |
mbed_official | 15:a81a8d6c1dfe | 720 | config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1; |
mbed_official | 15:a81a8d6c1dfe | 721 | /* Default transfer size is set to 0 */ |
mbed_official | 15:a81a8d6c1dfe | 722 | config->block_transfer_count = 0; |
mbed_official | 15:a81a8d6c1dfe | 723 | /* Default source address is set to NULL */ |
mbed_official | 15:a81a8d6c1dfe | 724 | config->source_address = (uint32_t)NULL; |
mbed_official | 15:a81a8d6c1dfe | 725 | /* Default destination address is set to NULL */ |
mbed_official | 15:a81a8d6c1dfe | 726 | config->destination_address = (uint32_t)NULL; |
mbed_official | 15:a81a8d6c1dfe | 727 | /** Next descriptor address set to 0 */ |
mbed_official | 15:a81a8d6c1dfe | 728 | config->next_descriptor_address = 0; |
mbed_official | 15:a81a8d6c1dfe | 729 | } |
mbed_official | 15:a81a8d6c1dfe | 730 | |
mbed_official | 15:a81a8d6c1dfe | 731 | /** |
mbed_official | 15:a81a8d6c1dfe | 732 | * \brief Update DMA descriptor. |
mbed_official | 15:a81a8d6c1dfe | 733 | * |
mbed_official | 15:a81a8d6c1dfe | 734 | * This function can update the descriptor of an allocated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 735 | * |
mbed_official | 15:a81a8d6c1dfe | 736 | */ |
mbed_official | 15:a81a8d6c1dfe | 737 | static inline void dma_update_descriptor(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 738 | DmacDescriptor* descriptor) |
mbed_official | 15:a81a8d6c1dfe | 739 | { |
mbed_official | 15:a81a8d6c1dfe | 740 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 741 | |
mbed_official | 15:a81a8d6c1dfe | 742 | resource->descriptor = descriptor; |
mbed_official | 15:a81a8d6c1dfe | 743 | } |
mbed_official | 15:a81a8d6c1dfe | 744 | |
mbed_official | 15:a81a8d6c1dfe | 745 | /** |
mbed_official | 15:a81a8d6c1dfe | 746 | * \brief Reset DMA descriptor. |
mbed_official | 15:a81a8d6c1dfe | 747 | * |
mbed_official | 15:a81a8d6c1dfe | 748 | * This function will clear the DESCADDR register of an allocated DMA resource. |
mbed_official | 15:a81a8d6c1dfe | 749 | * |
mbed_official | 15:a81a8d6c1dfe | 750 | */ |
mbed_official | 15:a81a8d6c1dfe | 751 | static inline void dma_reset_descriptor(struct dma_resource *resource) |
mbed_official | 15:a81a8d6c1dfe | 752 | { |
mbed_official | 15:a81a8d6c1dfe | 753 | Assert(resource); |
mbed_official | 15:a81a8d6c1dfe | 754 | |
mbed_official | 15:a81a8d6c1dfe | 755 | resource->descriptor = NULL; |
mbed_official | 15:a81a8d6c1dfe | 756 | } |
mbed_official | 15:a81a8d6c1dfe | 757 | |
mbed_official | 15:a81a8d6c1dfe | 758 | void dma_get_config_defaults(struct dma_resource_config *config); |
mbed_official | 15:a81a8d6c1dfe | 759 | enum status_code dma_allocate(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 760 | struct dma_resource_config *config); |
mbed_official | 15:a81a8d6c1dfe | 761 | enum status_code dma_free(struct dma_resource *resource); |
mbed_official | 15:a81a8d6c1dfe | 762 | enum status_code dma_start_transfer_job(struct dma_resource *resource); |
mbed_official | 15:a81a8d6c1dfe | 763 | void dma_abort_job(struct dma_resource *resource); |
mbed_official | 15:a81a8d6c1dfe | 764 | void dma_suspend_job(struct dma_resource *resource); |
mbed_official | 15:a81a8d6c1dfe | 765 | void dma_resume_job(struct dma_resource *resource); |
mbed_official | 15:a81a8d6c1dfe | 766 | void dma_descriptor_create(DmacDescriptor* descriptor, |
mbed_official | 15:a81a8d6c1dfe | 767 | struct dma_descriptor_config *config); |
mbed_official | 15:a81a8d6c1dfe | 768 | enum status_code dma_add_descriptor(struct dma_resource *resource, |
mbed_official | 15:a81a8d6c1dfe | 769 | DmacDescriptor* descriptor); |
mbed_official | 15:a81a8d6c1dfe | 770 | |
mbed_official | 15:a81a8d6c1dfe | 771 | /** @} */ |
mbed_official | 15:a81a8d6c1dfe | 772 | |
mbed_official | 15:a81a8d6c1dfe | 773 | /** |
mbed_official | 15:a81a8d6c1dfe | 774 | * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver |
mbed_official | 15:a81a8d6c1dfe | 775 | * |
mbed_official | 15:a81a8d6c1dfe | 776 | * \section asfdoc_sam0_dma_extra_acronyms Acronyms |
mbed_official | 15:a81a8d6c1dfe | 777 | * Below is a table listing the acronyms used in this module, along with their |
mbed_official | 15:a81a8d6c1dfe | 778 | * intended meanings. |
mbed_official | 15:a81a8d6c1dfe | 779 | * |
mbed_official | 15:a81a8d6c1dfe | 780 | * <table> |
mbed_official | 15:a81a8d6c1dfe | 781 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 782 | * <th>Acronym</th> |
mbed_official | 15:a81a8d6c1dfe | 783 | * <th>Description</th> |
mbed_official | 15:a81a8d6c1dfe | 784 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 785 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 786 | * <td>DMA</td> |
mbed_official | 15:a81a8d6c1dfe | 787 | * <td>Direct Memory Access</td> |
mbed_official | 15:a81a8d6c1dfe | 788 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 789 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 790 | * <td>DMAC</td> |
mbed_official | 15:a81a8d6c1dfe | 791 | * <td>Direct Memory Access Controller </td> |
mbed_official | 15:a81a8d6c1dfe | 792 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 793 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 794 | * <td>CPU</td> |
mbed_official | 15:a81a8d6c1dfe | 795 | * <td>Central Processing Unit</td> |
mbed_official | 15:a81a8d6c1dfe | 796 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 797 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 798 | * |
mbed_official | 15:a81a8d6c1dfe | 799 | * |
mbed_official | 15:a81a8d6c1dfe | 800 | * \section asfdoc_sam0_dma_extra_dependencies Dependencies |
mbed_official | 15:a81a8d6c1dfe | 801 | * This driver has the following dependencies: |
mbed_official | 15:a81a8d6c1dfe | 802 | * |
mbed_official | 15:a81a8d6c1dfe | 803 | * - \ref asfdoc_sam0_system_clock_group "System Clock Driver" |
mbed_official | 15:a81a8d6c1dfe | 804 | * |
mbed_official | 15:a81a8d6c1dfe | 805 | * |
mbed_official | 15:a81a8d6c1dfe | 806 | * \section asfdoc_sam0_dma_extra_errata Errata |
mbed_official | 15:a81a8d6c1dfe | 807 | * There are no errata related to this driver. |
mbed_official | 15:a81a8d6c1dfe | 808 | * |
mbed_official | 15:a81a8d6c1dfe | 809 | * |
mbed_official | 15:a81a8d6c1dfe | 810 | * \section asfdoc_sam0_dma_extra_history Module History |
mbed_official | 15:a81a8d6c1dfe | 811 | * An overview of the module history is presented in the table below, with |
mbed_official | 15:a81a8d6c1dfe | 812 | * details on the enhancements and fixes made to the module since its first |
mbed_official | 15:a81a8d6c1dfe | 813 | * release. The current version of this corresponds to the newest version in |
mbed_official | 15:a81a8d6c1dfe | 814 | * the table. |
mbed_official | 15:a81a8d6c1dfe | 815 | * |
mbed_official | 15:a81a8d6c1dfe | 816 | * <table> |
mbed_official | 15:a81a8d6c1dfe | 817 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 818 | * <th>Changelog</th> |
mbed_official | 15:a81a8d6c1dfe | 819 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 820 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 821 | * <td>Add SAM C21 support</td> |
mbed_official | 15:a81a8d6c1dfe | 822 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 823 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 824 | * <td>Add SAM L21 support</td> |
mbed_official | 15:a81a8d6c1dfe | 825 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 826 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 827 | * <td>Initial Release</td> |
mbed_official | 15:a81a8d6c1dfe | 828 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 829 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 830 | */ |
mbed_official | 15:a81a8d6c1dfe | 831 | |
mbed_official | 15:a81a8d6c1dfe | 832 | /** |
mbed_official | 15:a81a8d6c1dfe | 833 | * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver |
mbed_official | 15:a81a8d6c1dfe | 834 | * |
mbed_official | 15:a81a8d6c1dfe | 835 | * This is a list of the available Quick Start Guides (QSGs) and example |
mbed_official | 15:a81a8d6c1dfe | 836 | * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with |
mbed_official | 15:a81a8d6c1dfe | 837 | * step-by-step instructions to configure and use this driver in a selection of |
mbed_official | 15:a81a8d6c1dfe | 838 | * use cases. Note that QSGs can be compiled as a standalone application or be |
mbed_official | 15:a81a8d6c1dfe | 839 | * added to the user application. |
mbed_official | 15:a81a8d6c1dfe | 840 | * |
mbed_official | 15:a81a8d6c1dfe | 841 | * - \subpage asfdoc_sam0_dma_basic_use_case |
mbed_official | 15:a81a8d6c1dfe | 842 | * |
mbed_official | 15:a81a8d6c1dfe | 843 | * \note More DMA usage examples are available in peripheral QSGs. |
mbed_official | 15:a81a8d6c1dfe | 844 | * A quick start guide for TC/TCC |
mbed_official | 15:a81a8d6c1dfe | 845 | * shows the usage of DMA event trigger; SERCOM SPI/USART/I<SUP>2</SUP>C has example for |
mbed_official | 15:a81a8d6c1dfe | 846 | * DMA transfer from peripheral to memory or from memory to peripheral; |
mbed_official | 15:a81a8d6c1dfe | 847 | * ADC/DAC shows peripheral to peripheral transfer. |
mbed_official | 15:a81a8d6c1dfe | 848 | * |
mbed_official | 15:a81a8d6c1dfe | 849 | * \page asfdoc_sam0_dma_document_revision_history Document Revision History |
mbed_official | 15:a81a8d6c1dfe | 850 | * |
mbed_official | 15:a81a8d6c1dfe | 851 | * <table> |
mbed_official | 15:a81a8d6c1dfe | 852 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 853 | * <th>Doc. Rev.</td> |
mbed_official | 15:a81a8d6c1dfe | 854 | * <th>Date</td> |
mbed_official | 15:a81a8d6c1dfe | 855 | * <th>Comments</td> |
mbed_official | 15:a81a8d6c1dfe | 856 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 857 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 858 | * <td>C</td> |
mbed_official | 15:a81a8d6c1dfe | 859 | * <td>06/2015</td> |
mbed_official | 15:a81a8d6c1dfe | 860 | * <td>Added SAML21, SAMC21, and SAMDAx support</td> |
mbed_official | 15:a81a8d6c1dfe | 861 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 862 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 863 | * <td>B</td> |
mbed_official | 15:a81a8d6c1dfe | 864 | * <td>12/2014</td> |
mbed_official | 15:a81a8d6c1dfe | 865 | * <td>Added SAMR21 and SAMD10/D11 support</td> |
mbed_official | 15:a81a8d6c1dfe | 866 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 867 | * <tr> |
mbed_official | 15:a81a8d6c1dfe | 868 | * <td>A</td> |
mbed_official | 15:a81a8d6c1dfe | 869 | * <td>02/2014</td> |
mbed_official | 15:a81a8d6c1dfe | 870 | * <td>Initial release</td> |
mbed_official | 15:a81a8d6c1dfe | 871 | * </tr> |
mbed_official | 15:a81a8d6c1dfe | 872 | * </table> |
mbed_official | 15:a81a8d6c1dfe | 873 | */ |
mbed_official | 15:a81a8d6c1dfe | 874 | |
mbed_official | 15:a81a8d6c1dfe | 875 | #ifdef __cplusplus |
mbed_official | 15:a81a8d6c1dfe | 876 | } |
mbed_official | 15:a81a8d6c1dfe | 877 | #endif |
mbed_official | 15:a81a8d6c1dfe | 878 | |
mbed_official | 15:a81a8d6c1dfe | 879 | #endif /* DMA_H_INCLUDED */ |