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cmsis/core_cm4.h@178:c26431f84b0d, 2017-11-09 (annotated)
- Committer:
- amithy
- Date:
- Thu Nov 09 22:14:37 2017 +0000
- Revision:
- 178:c26431f84b0d
- Parent:
- 152:9a67f0b066fc
- Child:
- 167:e84263d55307
test export
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /**************************************************************************//** |
<> | 149:156823d33999 | 2 | * @file core_cm4.h |
<> | 149:156823d33999 | 3 | * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File |
<> | 149:156823d33999 | 4 | * @version V4.10 |
<> | 149:156823d33999 | 5 | * @date 18. March 2015 |
<> | 149:156823d33999 | 6 | * |
<> | 149:156823d33999 | 7 | * @note |
<> | 149:156823d33999 | 8 | * |
<> | 149:156823d33999 | 9 | ******************************************************************************/ |
<> | 149:156823d33999 | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
<> | 149:156823d33999 | 11 | |
<> | 149:156823d33999 | 12 | All rights reserved. |
<> | 149:156823d33999 | 13 | Redistribution and use in source and binary forms, with or without |
<> | 149:156823d33999 | 14 | modification, are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 15 | - Redistributions of source code must retain the above copyright |
<> | 149:156823d33999 | 16 | notice, this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 17 | - Redistributions in binary form must reproduce the above copyright |
<> | 149:156823d33999 | 18 | notice, this list of conditions and the following disclaimer in the |
<> | 149:156823d33999 | 19 | documentation and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 20 | - Neither the name of ARM nor the names of its contributors may be used |
<> | 149:156823d33999 | 21 | to endorse or promote products derived from this software without |
<> | 149:156823d33999 | 22 | specific prior written permission. |
<> | 149:156823d33999 | 23 | * |
<> | 149:156823d33999 | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
<> | 149:156823d33999 | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
<> | 149:156823d33999 | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
<> | 149:156823d33999 | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
<> | 149:156823d33999 | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
<> | 149:156823d33999 | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
<> | 149:156823d33999 | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
<> | 149:156823d33999 | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
<> | 149:156823d33999 | 34 | POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 35 | ---------------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 36 | |
<> | 149:156823d33999 | 37 | |
<> | 149:156823d33999 | 38 | #if defined ( __ICCARM__ ) |
<> | 149:156823d33999 | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
<> | 149:156823d33999 | 40 | #endif |
<> | 149:156823d33999 | 41 | |
<> | 149:156823d33999 | 42 | #ifndef __CORE_CM4_H_GENERIC |
<> | 149:156823d33999 | 43 | #define __CORE_CM4_H_GENERIC |
<> | 149:156823d33999 | 44 | |
<> | 149:156823d33999 | 45 | #ifdef __cplusplus |
<> | 149:156823d33999 | 46 | extern "C" { |
<> | 149:156823d33999 | 47 | #endif |
<> | 149:156823d33999 | 48 | |
<> | 149:156823d33999 | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
<> | 149:156823d33999 | 50 | CMSIS violates the following MISRA-C:2004 rules: |
<> | 149:156823d33999 | 51 | |
<> | 149:156823d33999 | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
<> | 149:156823d33999 | 53 | Function definitions in header files are used to allow 'inlining'. |
<> | 149:156823d33999 | 54 | |
<> | 149:156823d33999 | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
<> | 149:156823d33999 | 56 | Unions are used for effective representation of core registers. |
<> | 149:156823d33999 | 57 | |
<> | 149:156823d33999 | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
<> | 149:156823d33999 | 59 | Function-like macros are used to allow more efficient code. |
<> | 149:156823d33999 | 60 | */ |
<> | 149:156823d33999 | 61 | |
<> | 149:156823d33999 | 62 | |
<> | 149:156823d33999 | 63 | /******************************************************************************* |
<> | 149:156823d33999 | 64 | * CMSIS definitions |
<> | 149:156823d33999 | 65 | ******************************************************************************/ |
<> | 149:156823d33999 | 66 | /** \ingroup Cortex_M4 |
<> | 149:156823d33999 | 67 | @{ |
<> | 149:156823d33999 | 68 | */ |
<> | 149:156823d33999 | 69 | |
<> | 149:156823d33999 | 70 | /* CMSIS CM4 definitions */ |
<> | 149:156823d33999 | 71 | #define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
<> | 149:156823d33999 | 72 | #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
<> | 149:156823d33999 | 73 | #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ |
<> | 149:156823d33999 | 74 | __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
<> | 149:156823d33999 | 75 | |
<> | 149:156823d33999 | 76 | #define __CORTEX_M (0x04) /*!< Cortex-M Core */ |
<> | 149:156823d33999 | 77 | |
<> | 149:156823d33999 | 78 | |
<> | 149:156823d33999 | 79 | #if defined ( __CC_ARM ) |
<> | 149:156823d33999 | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
<> | 149:156823d33999 | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
<> | 149:156823d33999 | 82 | #define __STATIC_INLINE static __inline |
<> | 149:156823d33999 | 83 | |
<> | 149:156823d33999 | 84 | #elif defined ( __GNUC__ ) |
<> | 149:156823d33999 | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
<> | 149:156823d33999 | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
<> | 149:156823d33999 | 87 | #define __STATIC_INLINE static inline |
<> | 149:156823d33999 | 88 | |
<> | 149:156823d33999 | 89 | #elif defined ( __ICCARM__ ) |
<> | 149:156823d33999 | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
<> | 149:156823d33999 | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
<> | 149:156823d33999 | 92 | #define __STATIC_INLINE static inline |
<> | 149:156823d33999 | 93 | |
<> | 149:156823d33999 | 94 | #elif defined ( __TMS470__ ) |
<> | 149:156823d33999 | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
<> | 149:156823d33999 | 96 | #define __STATIC_INLINE static inline |
<> | 149:156823d33999 | 97 | |
<> | 149:156823d33999 | 98 | #elif defined ( __TASKING__ ) |
<> | 149:156823d33999 | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
<> | 149:156823d33999 | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
<> | 149:156823d33999 | 101 | #define __STATIC_INLINE static inline |
<> | 149:156823d33999 | 102 | |
<> | 149:156823d33999 | 103 | #elif defined ( __CSMC__ ) |
<> | 149:156823d33999 | 104 | #define __packed |
<> | 149:156823d33999 | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
<> | 149:156823d33999 | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
<> | 149:156823d33999 | 107 | #define __STATIC_INLINE static inline |
<> | 149:156823d33999 | 108 | |
<> | 149:156823d33999 | 109 | #endif |
<> | 149:156823d33999 | 110 | |
<> | 149:156823d33999 | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
<> | 149:156823d33999 | 112 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. |
<> | 149:156823d33999 | 113 | */ |
<> | 149:156823d33999 | 114 | #if defined ( __CC_ARM ) |
<> | 149:156823d33999 | 115 | #if defined __TARGET_FPU_VFP |
<> | 149:156823d33999 | 116 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 117 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 118 | #else |
<> | 149:156823d33999 | 119 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 120 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 121 | #endif |
<> | 149:156823d33999 | 122 | #else |
<> | 149:156823d33999 | 123 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 124 | #endif |
<> | 149:156823d33999 | 125 | |
<> | 149:156823d33999 | 126 | #elif defined ( __GNUC__ ) |
<> | 149:156823d33999 | 127 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
<> | 149:156823d33999 | 128 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 129 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 130 | #else |
<> | 149:156823d33999 | 131 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 132 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 133 | #endif |
<> | 149:156823d33999 | 134 | #else |
<> | 149:156823d33999 | 135 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 136 | #endif |
<> | 149:156823d33999 | 137 | |
<> | 149:156823d33999 | 138 | #elif defined ( __ICCARM__ ) |
<> | 149:156823d33999 | 139 | #if defined __ARMVFP__ |
<> | 149:156823d33999 | 140 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 141 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 142 | #else |
<> | 149:156823d33999 | 143 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 144 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 145 | #endif |
<> | 149:156823d33999 | 146 | #else |
<> | 149:156823d33999 | 147 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 148 | #endif |
<> | 149:156823d33999 | 149 | |
<> | 149:156823d33999 | 150 | #elif defined ( __TMS470__ ) |
<> | 149:156823d33999 | 151 | #if defined __TI_VFP_SUPPORT__ |
<> | 149:156823d33999 | 152 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 153 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 154 | #else |
<> | 149:156823d33999 | 155 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 156 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 157 | #endif |
<> | 149:156823d33999 | 158 | #else |
<> | 149:156823d33999 | 159 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 160 | #endif |
<> | 149:156823d33999 | 161 | |
<> | 149:156823d33999 | 162 | #elif defined ( __TASKING__ ) |
<> | 149:156823d33999 | 163 | #if defined __FPU_VFP__ |
<> | 149:156823d33999 | 164 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 165 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 166 | #else |
<> | 149:156823d33999 | 167 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 168 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 169 | #endif |
<> | 149:156823d33999 | 170 | #else |
<> | 149:156823d33999 | 171 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 172 | #endif |
<> | 149:156823d33999 | 173 | |
<> | 149:156823d33999 | 174 | #elif defined ( __CSMC__ ) /* Cosmic */ |
<> | 149:156823d33999 | 175 | #if ( __CSMC__ & 0x400) // FPU present for parser |
<> | 149:156823d33999 | 176 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 177 | #define __FPU_USED 1 |
<> | 149:156823d33999 | 178 | #else |
<> | 149:156823d33999 | 179 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
<> | 149:156823d33999 | 180 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 181 | #endif |
<> | 149:156823d33999 | 182 | #else |
<> | 149:156823d33999 | 183 | #define __FPU_USED 0 |
<> | 149:156823d33999 | 184 | #endif |
<> | 149:156823d33999 | 185 | #endif |
<> | 149:156823d33999 | 186 | |
<> | 149:156823d33999 | 187 | #include <stdint.h> /* standard types definitions */ |
<> | 149:156823d33999 | 188 | #include <core_cmInstr.h> /* Core Instruction Access */ |
<> | 149:156823d33999 | 189 | #include <core_cmFunc.h> /* Core Function Access */ |
<> | 149:156823d33999 | 190 | #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */ |
<> | 149:156823d33999 | 191 | |
<> | 149:156823d33999 | 192 | #ifdef __cplusplus |
<> | 149:156823d33999 | 193 | } |
<> | 149:156823d33999 | 194 | #endif |
<> | 149:156823d33999 | 195 | |
<> | 149:156823d33999 | 196 | #endif /* __CORE_CM4_H_GENERIC */ |
<> | 149:156823d33999 | 197 | |
<> | 149:156823d33999 | 198 | #ifndef __CMSIS_GENERIC |
<> | 149:156823d33999 | 199 | |
<> | 149:156823d33999 | 200 | #ifndef __CORE_CM4_H_DEPENDANT |
<> | 149:156823d33999 | 201 | #define __CORE_CM4_H_DEPENDANT |
<> | 149:156823d33999 | 202 | |
<> | 149:156823d33999 | 203 | #ifdef __cplusplus |
<> | 149:156823d33999 | 204 | extern "C" { |
<> | 149:156823d33999 | 205 | #endif |
<> | 149:156823d33999 | 206 | |
<> | 149:156823d33999 | 207 | /* check device defines and use defaults */ |
<> | 149:156823d33999 | 208 | #if defined __CHECK_DEVICE_DEFINES |
<> | 149:156823d33999 | 209 | #ifndef __CM4_REV |
<> | 149:156823d33999 | 210 | #define __CM4_REV 0x0000 |
<> | 149:156823d33999 | 211 | #warning "__CM4_REV not defined in device header file; using default!" |
<> | 149:156823d33999 | 212 | #endif |
<> | 149:156823d33999 | 213 | |
<> | 149:156823d33999 | 214 | #ifndef __FPU_PRESENT |
<> | 149:156823d33999 | 215 | #define __FPU_PRESENT 0 |
<> | 149:156823d33999 | 216 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
<> | 149:156823d33999 | 217 | #endif |
<> | 149:156823d33999 | 218 | |
<> | 149:156823d33999 | 219 | #ifndef __MPU_PRESENT |
<> | 149:156823d33999 | 220 | #define __MPU_PRESENT 0 |
<> | 149:156823d33999 | 221 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
<> | 149:156823d33999 | 222 | #endif |
<> | 149:156823d33999 | 223 | |
<> | 149:156823d33999 | 224 | #ifndef __NVIC_PRIO_BITS |
<> | 149:156823d33999 | 225 | #define __NVIC_PRIO_BITS 4 |
<> | 149:156823d33999 | 226 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
<> | 149:156823d33999 | 227 | #endif |
<> | 149:156823d33999 | 228 | |
<> | 149:156823d33999 | 229 | #ifndef __Vendor_SysTickConfig |
<> | 149:156823d33999 | 230 | #define __Vendor_SysTickConfig 0 |
<> | 149:156823d33999 | 231 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
<> | 149:156823d33999 | 232 | #endif |
<> | 149:156823d33999 | 233 | #endif |
<> | 149:156823d33999 | 234 | |
<> | 149:156823d33999 | 235 | /* IO definitions (access restrictions to peripheral registers) */ |
<> | 149:156823d33999 | 236 | /** |
<> | 149:156823d33999 | 237 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
<> | 149:156823d33999 | 238 | |
<> | 149:156823d33999 | 239 | <strong>IO Type Qualifiers</strong> are used |
<> | 149:156823d33999 | 240 | \li to specify the access to peripheral variables. |
<> | 149:156823d33999 | 241 | \li for automatic generation of peripheral register debug information. |
<> | 149:156823d33999 | 242 | */ |
<> | 149:156823d33999 | 243 | #ifdef __cplusplus |
<> | 149:156823d33999 | 244 | #define __I volatile /*!< Defines 'read only' permissions */ |
<> | 149:156823d33999 | 245 | #else |
<> | 149:156823d33999 | 246 | #define __I volatile const /*!< Defines 'read only' permissions */ |
<> | 149:156823d33999 | 247 | #endif |
<> | 149:156823d33999 | 248 | #define __O volatile /*!< Defines 'write only' permissions */ |
<> | 149:156823d33999 | 249 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
<> | 149:156823d33999 | 250 | |
<> | 150:02e0a0aed4ec | 251 | #ifdef __cplusplus |
<> | 150:02e0a0aed4ec | 252 | #define __IM volatile /*!< Defines 'read only' permissions */ |
<> | 150:02e0a0aed4ec | 253 | #else |
<> | 150:02e0a0aed4ec | 254 | #define __IM volatile const /*!< Defines 'read only' permissions */ |
<> | 150:02e0a0aed4ec | 255 | #endif |
<> | 150:02e0a0aed4ec | 256 | #define __OM volatile /*!< Defines 'write only' permissions */ |
<> | 150:02e0a0aed4ec | 257 | #define __IOM volatile /*!< Defines 'read / write' permissions */ |
<> | 150:02e0a0aed4ec | 258 | |
<> | 149:156823d33999 | 259 | /*@} end of group Cortex_M4 */ |
<> | 149:156823d33999 | 260 | |
<> | 149:156823d33999 | 261 | |
<> | 149:156823d33999 | 262 | |
<> | 149:156823d33999 | 263 | /******************************************************************************* |
<> | 149:156823d33999 | 264 | * Register Abstraction |
<> | 149:156823d33999 | 265 | Core Register contain: |
<> | 149:156823d33999 | 266 | - Core Register |
<> | 149:156823d33999 | 267 | - Core NVIC Register |
<> | 149:156823d33999 | 268 | - Core SCB Register |
<> | 149:156823d33999 | 269 | - Core SysTick Register |
<> | 149:156823d33999 | 270 | - Core Debug Register |
<> | 149:156823d33999 | 271 | - Core MPU Register |
<> | 149:156823d33999 | 272 | - Core FPU Register |
<> | 149:156823d33999 | 273 | ******************************************************************************/ |
<> | 149:156823d33999 | 274 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
<> | 149:156823d33999 | 275 | \brief Type definitions and defines for Cortex-M processor based devices. |
<> | 149:156823d33999 | 276 | */ |
<> | 149:156823d33999 | 277 | |
<> | 149:156823d33999 | 278 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 279 | \defgroup CMSIS_CORE Status and Control Registers |
<> | 149:156823d33999 | 280 | \brief Core Register type definitions. |
<> | 149:156823d33999 | 281 | @{ |
<> | 149:156823d33999 | 282 | */ |
<> | 149:156823d33999 | 283 | |
<> | 149:156823d33999 | 284 | /** \brief Union type to access the Application Program Status Register (APSR). |
<> | 149:156823d33999 | 285 | */ |
<> | 149:156823d33999 | 286 | typedef union |
<> | 149:156823d33999 | 287 | { |
<> | 149:156823d33999 | 288 | struct |
<> | 149:156823d33999 | 289 | { |
<> | 149:156823d33999 | 290 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
<> | 149:156823d33999 | 291 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
<> | 149:156823d33999 | 292 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
<> | 149:156823d33999 | 293 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
<> | 149:156823d33999 | 294 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
<> | 149:156823d33999 | 295 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
<> | 149:156823d33999 | 296 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
<> | 149:156823d33999 | 297 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
<> | 149:156823d33999 | 298 | } b; /*!< Structure used for bit access */ |
<> | 149:156823d33999 | 299 | uint32_t w; /*!< Type used for word access */ |
<> | 149:156823d33999 | 300 | } APSR_Type; |
<> | 149:156823d33999 | 301 | |
<> | 149:156823d33999 | 302 | /* APSR Register Definitions */ |
<> | 149:156823d33999 | 303 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
<> | 149:156823d33999 | 304 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
<> | 149:156823d33999 | 305 | |
<> | 149:156823d33999 | 306 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
<> | 149:156823d33999 | 307 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
<> | 149:156823d33999 | 308 | |
<> | 149:156823d33999 | 309 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
<> | 149:156823d33999 | 310 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
<> | 149:156823d33999 | 311 | |
<> | 149:156823d33999 | 312 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
<> | 149:156823d33999 | 313 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
<> | 149:156823d33999 | 314 | |
<> | 149:156823d33999 | 315 | #define APSR_Q_Pos 27 /*!< APSR: Q Position */ |
<> | 149:156823d33999 | 316 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
<> | 149:156823d33999 | 317 | |
<> | 149:156823d33999 | 318 | #define APSR_GE_Pos 16 /*!< APSR: GE Position */ |
<> | 149:156823d33999 | 319 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ |
<> | 149:156823d33999 | 320 | |
<> | 149:156823d33999 | 321 | |
<> | 149:156823d33999 | 322 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
<> | 149:156823d33999 | 323 | */ |
<> | 149:156823d33999 | 324 | typedef union |
<> | 149:156823d33999 | 325 | { |
<> | 149:156823d33999 | 326 | struct |
<> | 149:156823d33999 | 327 | { |
<> | 149:156823d33999 | 328 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
<> | 149:156823d33999 | 329 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
<> | 149:156823d33999 | 330 | } b; /*!< Structure used for bit access */ |
<> | 149:156823d33999 | 331 | uint32_t w; /*!< Type used for word access */ |
<> | 149:156823d33999 | 332 | } IPSR_Type; |
<> | 149:156823d33999 | 333 | |
<> | 149:156823d33999 | 334 | /* IPSR Register Definitions */ |
<> | 149:156823d33999 | 335 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
<> | 149:156823d33999 | 336 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
<> | 149:156823d33999 | 337 | |
<> | 149:156823d33999 | 338 | |
<> | 149:156823d33999 | 339 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
<> | 149:156823d33999 | 340 | */ |
<> | 149:156823d33999 | 341 | typedef union |
<> | 149:156823d33999 | 342 | { |
<> | 149:156823d33999 | 343 | struct |
<> | 149:156823d33999 | 344 | { |
<> | 149:156823d33999 | 345 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
<> | 149:156823d33999 | 346 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
<> | 149:156823d33999 | 347 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
<> | 149:156823d33999 | 348 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
<> | 149:156823d33999 | 349 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
<> | 149:156823d33999 | 350 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
<> | 149:156823d33999 | 351 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
<> | 149:156823d33999 | 352 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
<> | 149:156823d33999 | 353 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
<> | 149:156823d33999 | 354 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
<> | 149:156823d33999 | 355 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
<> | 149:156823d33999 | 356 | } b; /*!< Structure used for bit access */ |
<> | 149:156823d33999 | 357 | uint32_t w; /*!< Type used for word access */ |
<> | 149:156823d33999 | 358 | } xPSR_Type; |
<> | 149:156823d33999 | 359 | |
<> | 149:156823d33999 | 360 | /* xPSR Register Definitions */ |
<> | 149:156823d33999 | 361 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
<> | 149:156823d33999 | 362 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
<> | 149:156823d33999 | 363 | |
<> | 149:156823d33999 | 364 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
<> | 149:156823d33999 | 365 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
<> | 149:156823d33999 | 366 | |
<> | 149:156823d33999 | 367 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
<> | 149:156823d33999 | 368 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
<> | 149:156823d33999 | 369 | |
<> | 149:156823d33999 | 370 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
<> | 149:156823d33999 | 371 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
<> | 149:156823d33999 | 372 | |
<> | 149:156823d33999 | 373 | #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ |
<> | 149:156823d33999 | 374 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
<> | 149:156823d33999 | 375 | |
<> | 149:156823d33999 | 376 | #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ |
<> | 149:156823d33999 | 377 | #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ |
<> | 149:156823d33999 | 378 | |
<> | 149:156823d33999 | 379 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
<> | 149:156823d33999 | 380 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
<> | 149:156823d33999 | 381 | |
<> | 149:156823d33999 | 382 | #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ |
<> | 149:156823d33999 | 383 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ |
<> | 149:156823d33999 | 384 | |
<> | 149:156823d33999 | 385 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
<> | 149:156823d33999 | 386 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
<> | 149:156823d33999 | 387 | |
<> | 149:156823d33999 | 388 | |
<> | 149:156823d33999 | 389 | /** \brief Union type to access the Control Registers (CONTROL). |
<> | 149:156823d33999 | 390 | */ |
<> | 149:156823d33999 | 391 | typedef union |
<> | 149:156823d33999 | 392 | { |
<> | 149:156823d33999 | 393 | struct |
<> | 149:156823d33999 | 394 | { |
<> | 149:156823d33999 | 395 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
<> | 149:156823d33999 | 396 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
<> | 149:156823d33999 | 397 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
<> | 149:156823d33999 | 398 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
<> | 149:156823d33999 | 399 | } b; /*!< Structure used for bit access */ |
<> | 149:156823d33999 | 400 | uint32_t w; /*!< Type used for word access */ |
<> | 149:156823d33999 | 401 | } CONTROL_Type; |
<> | 149:156823d33999 | 402 | |
<> | 149:156823d33999 | 403 | /* CONTROL Register Definitions */ |
<> | 149:156823d33999 | 404 | #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ |
<> | 149:156823d33999 | 405 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ |
<> | 149:156823d33999 | 406 | |
<> | 149:156823d33999 | 407 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
<> | 149:156823d33999 | 408 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
<> | 149:156823d33999 | 409 | |
<> | 149:156823d33999 | 410 | #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ |
<> | 149:156823d33999 | 411 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
<> | 149:156823d33999 | 412 | |
<> | 149:156823d33999 | 413 | /*@} end of group CMSIS_CORE */ |
<> | 149:156823d33999 | 414 | |
<> | 149:156823d33999 | 415 | |
<> | 149:156823d33999 | 416 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 417 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
<> | 149:156823d33999 | 418 | \brief Type definitions for the NVIC Registers |
<> | 149:156823d33999 | 419 | @{ |
<> | 149:156823d33999 | 420 | */ |
<> | 149:156823d33999 | 421 | |
<> | 149:156823d33999 | 422 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
<> | 149:156823d33999 | 423 | */ |
<> | 149:156823d33999 | 424 | typedef struct |
<> | 149:156823d33999 | 425 | { |
<> | 149:156823d33999 | 426 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
<> | 149:156823d33999 | 427 | uint32_t RESERVED0[24]; |
<> | 149:156823d33999 | 428 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
<> | 149:156823d33999 | 429 | uint32_t RSERVED1[24]; |
<> | 149:156823d33999 | 430 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
<> | 149:156823d33999 | 431 | uint32_t RESERVED2[24]; |
<> | 149:156823d33999 | 432 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
<> | 149:156823d33999 | 433 | uint32_t RESERVED3[24]; |
<> | 149:156823d33999 | 434 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
<> | 149:156823d33999 | 435 | uint32_t RESERVED4[56]; |
<> | 149:156823d33999 | 436 | __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
<> | 149:156823d33999 | 437 | uint32_t RESERVED5[644]; |
<> | 149:156823d33999 | 438 | __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
<> | 149:156823d33999 | 439 | } NVIC_Type; |
<> | 149:156823d33999 | 440 | |
<> | 149:156823d33999 | 441 | /* Software Triggered Interrupt Register Definitions */ |
<> | 149:156823d33999 | 442 | #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ |
<> | 149:156823d33999 | 443 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
<> | 149:156823d33999 | 444 | |
<> | 149:156823d33999 | 445 | /*@} end of group CMSIS_NVIC */ |
<> | 149:156823d33999 | 446 | |
<> | 149:156823d33999 | 447 | |
<> | 149:156823d33999 | 448 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 449 | \defgroup CMSIS_SCB System Control Block (SCB) |
<> | 149:156823d33999 | 450 | \brief Type definitions for the System Control Block Registers |
<> | 149:156823d33999 | 451 | @{ |
<> | 149:156823d33999 | 452 | */ |
<> | 149:156823d33999 | 453 | |
<> | 149:156823d33999 | 454 | /** \brief Structure type to access the System Control Block (SCB). |
<> | 149:156823d33999 | 455 | */ |
<> | 149:156823d33999 | 456 | typedef struct |
<> | 149:156823d33999 | 457 | { |
<> | 149:156823d33999 | 458 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
<> | 149:156823d33999 | 459 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
<> | 149:156823d33999 | 460 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
<> | 149:156823d33999 | 461 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
<> | 149:156823d33999 | 462 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
<> | 149:156823d33999 | 463 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
<> | 149:156823d33999 | 464 | __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
<> | 149:156823d33999 | 465 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
<> | 149:156823d33999 | 466 | __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
<> | 149:156823d33999 | 467 | __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
<> | 149:156823d33999 | 468 | __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
<> | 149:156823d33999 | 469 | __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
<> | 149:156823d33999 | 470 | __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
<> | 149:156823d33999 | 471 | __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
<> | 149:156823d33999 | 472 | __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
<> | 149:156823d33999 | 473 | __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
<> | 149:156823d33999 | 474 | __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
<> | 149:156823d33999 | 475 | __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
<> | 149:156823d33999 | 476 | __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
<> | 149:156823d33999 | 477 | uint32_t RESERVED0[5]; |
<> | 149:156823d33999 | 478 | __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
<> | 149:156823d33999 | 479 | } SCB_Type; |
<> | 149:156823d33999 | 480 | |
<> | 149:156823d33999 | 481 | /* SCB CPUID Register Definitions */ |
<> | 149:156823d33999 | 482 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
<> | 149:156823d33999 | 483 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
<> | 149:156823d33999 | 484 | |
<> | 149:156823d33999 | 485 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
<> | 149:156823d33999 | 486 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
<> | 149:156823d33999 | 487 | |
<> | 149:156823d33999 | 488 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
<> | 149:156823d33999 | 489 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
<> | 149:156823d33999 | 490 | |
<> | 149:156823d33999 | 491 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
<> | 149:156823d33999 | 492 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
<> | 149:156823d33999 | 493 | |
<> | 149:156823d33999 | 494 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
<> | 149:156823d33999 | 495 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
<> | 149:156823d33999 | 496 | |
<> | 149:156823d33999 | 497 | /* SCB Interrupt Control State Register Definitions */ |
<> | 149:156823d33999 | 498 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
<> | 149:156823d33999 | 499 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
<> | 149:156823d33999 | 500 | |
<> | 149:156823d33999 | 501 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
<> | 149:156823d33999 | 502 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
<> | 149:156823d33999 | 503 | |
<> | 149:156823d33999 | 504 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
<> | 149:156823d33999 | 505 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
<> | 149:156823d33999 | 506 | |
<> | 149:156823d33999 | 507 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
<> | 149:156823d33999 | 508 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
<> | 149:156823d33999 | 509 | |
<> | 149:156823d33999 | 510 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
<> | 149:156823d33999 | 511 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
<> | 149:156823d33999 | 512 | |
<> | 149:156823d33999 | 513 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
<> | 149:156823d33999 | 514 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
<> | 149:156823d33999 | 515 | |
<> | 149:156823d33999 | 516 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
<> | 149:156823d33999 | 517 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
<> | 149:156823d33999 | 518 | |
<> | 149:156823d33999 | 519 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
<> | 149:156823d33999 | 520 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
<> | 149:156823d33999 | 521 | |
<> | 149:156823d33999 | 522 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
<> | 149:156823d33999 | 523 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
<> | 149:156823d33999 | 524 | |
<> | 149:156823d33999 | 525 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
<> | 149:156823d33999 | 526 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
<> | 149:156823d33999 | 527 | |
<> | 149:156823d33999 | 528 | /* SCB Vector Table Offset Register Definitions */ |
<> | 149:156823d33999 | 529 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
<> | 149:156823d33999 | 530 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
<> | 149:156823d33999 | 531 | |
<> | 149:156823d33999 | 532 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
<> | 149:156823d33999 | 533 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
<> | 149:156823d33999 | 534 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
<> | 149:156823d33999 | 535 | |
<> | 149:156823d33999 | 536 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
<> | 149:156823d33999 | 537 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
<> | 149:156823d33999 | 538 | |
<> | 149:156823d33999 | 539 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
<> | 149:156823d33999 | 540 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
<> | 149:156823d33999 | 541 | |
<> | 149:156823d33999 | 542 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
<> | 149:156823d33999 | 543 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
<> | 149:156823d33999 | 544 | |
<> | 149:156823d33999 | 545 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
<> | 149:156823d33999 | 546 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
<> | 149:156823d33999 | 547 | |
<> | 149:156823d33999 | 548 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
<> | 149:156823d33999 | 549 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
<> | 149:156823d33999 | 550 | |
<> | 149:156823d33999 | 551 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
<> | 149:156823d33999 | 552 | #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ |
<> | 149:156823d33999 | 553 | |
<> | 149:156823d33999 | 554 | /* SCB System Control Register Definitions */ |
<> | 149:156823d33999 | 555 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
<> | 149:156823d33999 | 556 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
<> | 149:156823d33999 | 557 | |
<> | 149:156823d33999 | 558 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
<> | 149:156823d33999 | 559 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
<> | 149:156823d33999 | 560 | |
<> | 149:156823d33999 | 561 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
<> | 149:156823d33999 | 562 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
<> | 149:156823d33999 | 563 | |
<> | 149:156823d33999 | 564 | /* SCB Configuration Control Register Definitions */ |
<> | 149:156823d33999 | 565 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
<> | 149:156823d33999 | 566 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
<> | 149:156823d33999 | 567 | |
<> | 149:156823d33999 | 568 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
<> | 149:156823d33999 | 569 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
<> | 149:156823d33999 | 570 | |
<> | 149:156823d33999 | 571 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
<> | 149:156823d33999 | 572 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
<> | 149:156823d33999 | 573 | |
<> | 149:156823d33999 | 574 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
<> | 149:156823d33999 | 575 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
<> | 149:156823d33999 | 576 | |
<> | 149:156823d33999 | 577 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
<> | 149:156823d33999 | 578 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
<> | 149:156823d33999 | 579 | |
<> | 149:156823d33999 | 580 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
<> | 149:156823d33999 | 581 | #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ |
<> | 149:156823d33999 | 582 | |
<> | 149:156823d33999 | 583 | /* SCB System Handler Control and State Register Definitions */ |
<> | 149:156823d33999 | 584 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
<> | 149:156823d33999 | 585 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
<> | 149:156823d33999 | 586 | |
<> | 149:156823d33999 | 587 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
<> | 149:156823d33999 | 588 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
<> | 149:156823d33999 | 589 | |
<> | 149:156823d33999 | 590 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
<> | 149:156823d33999 | 591 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
<> | 149:156823d33999 | 592 | |
<> | 149:156823d33999 | 593 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
<> | 149:156823d33999 | 594 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
<> | 149:156823d33999 | 595 | |
<> | 149:156823d33999 | 596 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
<> | 149:156823d33999 | 597 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
<> | 149:156823d33999 | 598 | |
<> | 149:156823d33999 | 599 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
<> | 149:156823d33999 | 600 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
<> | 149:156823d33999 | 601 | |
<> | 149:156823d33999 | 602 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
<> | 149:156823d33999 | 603 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
<> | 149:156823d33999 | 604 | |
<> | 149:156823d33999 | 605 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
<> | 149:156823d33999 | 606 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
<> | 149:156823d33999 | 607 | |
<> | 149:156823d33999 | 608 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
<> | 149:156823d33999 | 609 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
<> | 149:156823d33999 | 610 | |
<> | 149:156823d33999 | 611 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
<> | 149:156823d33999 | 612 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
<> | 149:156823d33999 | 613 | |
<> | 149:156823d33999 | 614 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
<> | 149:156823d33999 | 615 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
<> | 149:156823d33999 | 616 | |
<> | 149:156823d33999 | 617 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
<> | 149:156823d33999 | 618 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
<> | 149:156823d33999 | 619 | |
<> | 149:156823d33999 | 620 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
<> | 149:156823d33999 | 621 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
<> | 149:156823d33999 | 622 | |
<> | 149:156823d33999 | 623 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
<> | 149:156823d33999 | 624 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
<> | 149:156823d33999 | 625 | |
<> | 149:156823d33999 | 626 | /* SCB Configurable Fault Status Registers Definitions */ |
<> | 149:156823d33999 | 627 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
<> | 149:156823d33999 | 628 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
<> | 149:156823d33999 | 629 | |
<> | 149:156823d33999 | 630 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
<> | 149:156823d33999 | 631 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
<> | 149:156823d33999 | 632 | |
<> | 149:156823d33999 | 633 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
<> | 149:156823d33999 | 634 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
<> | 149:156823d33999 | 635 | |
<> | 149:156823d33999 | 636 | /* SCB Hard Fault Status Registers Definitions */ |
<> | 149:156823d33999 | 637 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
<> | 149:156823d33999 | 638 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
<> | 149:156823d33999 | 639 | |
<> | 149:156823d33999 | 640 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
<> | 149:156823d33999 | 641 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
<> | 149:156823d33999 | 642 | |
<> | 149:156823d33999 | 643 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
<> | 149:156823d33999 | 644 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
<> | 149:156823d33999 | 645 | |
<> | 149:156823d33999 | 646 | /* SCB Debug Fault Status Register Definitions */ |
<> | 149:156823d33999 | 647 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
<> | 149:156823d33999 | 648 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
<> | 149:156823d33999 | 649 | |
<> | 149:156823d33999 | 650 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
<> | 149:156823d33999 | 651 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
<> | 149:156823d33999 | 652 | |
<> | 149:156823d33999 | 653 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
<> | 149:156823d33999 | 654 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
<> | 149:156823d33999 | 655 | |
<> | 149:156823d33999 | 656 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
<> | 149:156823d33999 | 657 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
<> | 149:156823d33999 | 658 | |
<> | 149:156823d33999 | 659 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
<> | 149:156823d33999 | 660 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
<> | 149:156823d33999 | 661 | |
<> | 149:156823d33999 | 662 | /*@} end of group CMSIS_SCB */ |
<> | 149:156823d33999 | 663 | |
<> | 149:156823d33999 | 664 | |
<> | 149:156823d33999 | 665 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 666 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
<> | 149:156823d33999 | 667 | \brief Type definitions for the System Control and ID Register not in the SCB |
<> | 149:156823d33999 | 668 | @{ |
<> | 149:156823d33999 | 669 | */ |
<> | 149:156823d33999 | 670 | |
<> | 149:156823d33999 | 671 | /** \brief Structure type to access the System Control and ID Register not in the SCB. |
<> | 149:156823d33999 | 672 | */ |
<> | 149:156823d33999 | 673 | typedef struct |
<> | 149:156823d33999 | 674 | { |
<> | 149:156823d33999 | 675 | uint32_t RESERVED0[1]; |
<> | 149:156823d33999 | 676 | __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
<> | 149:156823d33999 | 677 | __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
<> | 149:156823d33999 | 678 | } SCnSCB_Type; |
<> | 149:156823d33999 | 679 | |
<> | 149:156823d33999 | 680 | /* Interrupt Controller Type Register Definitions */ |
<> | 149:156823d33999 | 681 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ |
<> | 149:156823d33999 | 682 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
<> | 149:156823d33999 | 683 | |
<> | 149:156823d33999 | 684 | /* Auxiliary Control Register Definitions */ |
<> | 149:156823d33999 | 685 | #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ |
<> | 149:156823d33999 | 686 | #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ |
<> | 149:156823d33999 | 687 | |
<> | 149:156823d33999 | 688 | #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ |
<> | 149:156823d33999 | 689 | #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ |
<> | 149:156823d33999 | 690 | |
<> | 149:156823d33999 | 691 | #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ |
<> | 149:156823d33999 | 692 | #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ |
<> | 149:156823d33999 | 693 | |
<> | 149:156823d33999 | 694 | #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ |
<> | 149:156823d33999 | 695 | #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ |
<> | 149:156823d33999 | 696 | |
<> | 149:156823d33999 | 697 | #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ |
<> | 149:156823d33999 | 698 | #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ |
<> | 149:156823d33999 | 699 | |
<> | 149:156823d33999 | 700 | /*@} end of group CMSIS_SCnotSCB */ |
<> | 149:156823d33999 | 701 | |
<> | 149:156823d33999 | 702 | |
<> | 149:156823d33999 | 703 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 704 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
<> | 149:156823d33999 | 705 | \brief Type definitions for the System Timer Registers. |
<> | 149:156823d33999 | 706 | @{ |
<> | 149:156823d33999 | 707 | */ |
<> | 149:156823d33999 | 708 | |
<> | 149:156823d33999 | 709 | /** \brief Structure type to access the System Timer (SysTick). |
<> | 149:156823d33999 | 710 | */ |
<> | 149:156823d33999 | 711 | typedef struct |
<> | 149:156823d33999 | 712 | { |
<> | 149:156823d33999 | 713 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
<> | 149:156823d33999 | 714 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
<> | 149:156823d33999 | 715 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
<> | 149:156823d33999 | 716 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
<> | 149:156823d33999 | 717 | } SysTick_Type; |
<> | 149:156823d33999 | 718 | |
<> | 149:156823d33999 | 719 | /* SysTick Control / Status Register Definitions */ |
<> | 149:156823d33999 | 720 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
<> | 149:156823d33999 | 721 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
<> | 149:156823d33999 | 722 | |
<> | 149:156823d33999 | 723 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
<> | 149:156823d33999 | 724 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
<> | 149:156823d33999 | 725 | |
<> | 149:156823d33999 | 726 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
<> | 149:156823d33999 | 727 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
<> | 149:156823d33999 | 728 | |
<> | 149:156823d33999 | 729 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
<> | 149:156823d33999 | 730 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
<> | 149:156823d33999 | 731 | |
<> | 149:156823d33999 | 732 | /* SysTick Reload Register Definitions */ |
<> | 149:156823d33999 | 733 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
<> | 149:156823d33999 | 734 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
<> | 149:156823d33999 | 735 | |
<> | 149:156823d33999 | 736 | /* SysTick Current Register Definitions */ |
<> | 149:156823d33999 | 737 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
<> | 149:156823d33999 | 738 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
<> | 149:156823d33999 | 739 | |
<> | 149:156823d33999 | 740 | /* SysTick Calibration Register Definitions */ |
<> | 149:156823d33999 | 741 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
<> | 149:156823d33999 | 742 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
<> | 149:156823d33999 | 743 | |
<> | 149:156823d33999 | 744 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
<> | 149:156823d33999 | 745 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
<> | 149:156823d33999 | 746 | |
<> | 149:156823d33999 | 747 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
<> | 149:156823d33999 | 748 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
<> | 149:156823d33999 | 749 | |
<> | 149:156823d33999 | 750 | /*@} end of group CMSIS_SysTick */ |
<> | 149:156823d33999 | 751 | |
<> | 149:156823d33999 | 752 | |
<> | 149:156823d33999 | 753 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 754 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
<> | 149:156823d33999 | 755 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
<> | 149:156823d33999 | 756 | @{ |
<> | 149:156823d33999 | 757 | */ |
<> | 149:156823d33999 | 758 | |
<> | 149:156823d33999 | 759 | /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
<> | 149:156823d33999 | 760 | */ |
<> | 149:156823d33999 | 761 | typedef struct |
<> | 149:156823d33999 | 762 | { |
<> | 149:156823d33999 | 763 | __O union |
<> | 149:156823d33999 | 764 | { |
<> | 149:156823d33999 | 765 | __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
<> | 149:156823d33999 | 766 | __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
<> | 149:156823d33999 | 767 | __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
<> | 149:156823d33999 | 768 | } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
<> | 149:156823d33999 | 769 | uint32_t RESERVED0[864]; |
<> | 149:156823d33999 | 770 | __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
<> | 149:156823d33999 | 771 | uint32_t RESERVED1[15]; |
<> | 149:156823d33999 | 772 | __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
<> | 149:156823d33999 | 773 | uint32_t RESERVED2[15]; |
<> | 149:156823d33999 | 774 | __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
<> | 149:156823d33999 | 775 | uint32_t RESERVED3[29]; |
<> | 149:156823d33999 | 776 | __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
<> | 149:156823d33999 | 777 | __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
<> | 149:156823d33999 | 778 | __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
<> | 149:156823d33999 | 779 | uint32_t RESERVED4[43]; |
<> | 149:156823d33999 | 780 | __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
<> | 149:156823d33999 | 781 | __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
<> | 149:156823d33999 | 782 | uint32_t RESERVED5[6]; |
<> | 149:156823d33999 | 783 | __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
<> | 149:156823d33999 | 784 | __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
<> | 149:156823d33999 | 785 | __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
<> | 149:156823d33999 | 786 | __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
<> | 149:156823d33999 | 787 | __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
<> | 149:156823d33999 | 788 | __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
<> | 149:156823d33999 | 789 | __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
<> | 149:156823d33999 | 790 | __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
<> | 149:156823d33999 | 791 | __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
<> | 149:156823d33999 | 792 | __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
<> | 149:156823d33999 | 793 | __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
<> | 149:156823d33999 | 794 | __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
<> | 149:156823d33999 | 795 | } ITM_Type; |
<> | 149:156823d33999 | 796 | |
<> | 149:156823d33999 | 797 | /* ITM Trace Privilege Register Definitions */ |
<> | 149:156823d33999 | 798 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
<> | 149:156823d33999 | 799 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
<> | 149:156823d33999 | 800 | |
<> | 149:156823d33999 | 801 | /* ITM Trace Control Register Definitions */ |
<> | 149:156823d33999 | 802 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
<> | 149:156823d33999 | 803 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
<> | 149:156823d33999 | 804 | |
<> | 149:156823d33999 | 805 | #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ |
<> | 149:156823d33999 | 806 | #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ |
<> | 149:156823d33999 | 807 | |
<> | 149:156823d33999 | 808 | #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ |
<> | 149:156823d33999 | 809 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
<> | 149:156823d33999 | 810 | |
<> | 149:156823d33999 | 811 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
<> | 149:156823d33999 | 812 | #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
<> | 149:156823d33999 | 813 | |
<> | 149:156823d33999 | 814 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
<> | 149:156823d33999 | 815 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
<> | 149:156823d33999 | 816 | |
<> | 149:156823d33999 | 817 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
<> | 149:156823d33999 | 818 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
<> | 149:156823d33999 | 819 | |
<> | 149:156823d33999 | 820 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
<> | 149:156823d33999 | 821 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
<> | 149:156823d33999 | 822 | |
<> | 149:156823d33999 | 823 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
<> | 149:156823d33999 | 824 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
<> | 149:156823d33999 | 825 | |
<> | 149:156823d33999 | 826 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
<> | 149:156823d33999 | 827 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
<> | 149:156823d33999 | 828 | |
<> | 149:156823d33999 | 829 | /* ITM Integration Write Register Definitions */ |
<> | 149:156823d33999 | 830 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
<> | 149:156823d33999 | 831 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
<> | 149:156823d33999 | 832 | |
<> | 149:156823d33999 | 833 | /* ITM Integration Read Register Definitions */ |
<> | 149:156823d33999 | 834 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
<> | 149:156823d33999 | 835 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
<> | 149:156823d33999 | 836 | |
<> | 149:156823d33999 | 837 | /* ITM Integration Mode Control Register Definitions */ |
<> | 149:156823d33999 | 838 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
<> | 149:156823d33999 | 839 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
<> | 149:156823d33999 | 840 | |
<> | 149:156823d33999 | 841 | /* ITM Lock Status Register Definitions */ |
<> | 149:156823d33999 | 842 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
<> | 149:156823d33999 | 843 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
<> | 149:156823d33999 | 844 | |
<> | 149:156823d33999 | 845 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
<> | 149:156823d33999 | 846 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
<> | 149:156823d33999 | 847 | |
<> | 149:156823d33999 | 848 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
<> | 149:156823d33999 | 849 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
<> | 149:156823d33999 | 850 | |
<> | 149:156823d33999 | 851 | /*@}*/ /* end of group CMSIS_ITM */ |
<> | 149:156823d33999 | 852 | |
<> | 149:156823d33999 | 853 | |
<> | 149:156823d33999 | 854 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 855 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
<> | 149:156823d33999 | 856 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
<> | 149:156823d33999 | 857 | @{ |
<> | 149:156823d33999 | 858 | */ |
<> | 149:156823d33999 | 859 | |
<> | 149:156823d33999 | 860 | /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
<> | 149:156823d33999 | 861 | */ |
<> | 149:156823d33999 | 862 | typedef struct |
<> | 149:156823d33999 | 863 | { |
<> | 149:156823d33999 | 864 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
<> | 149:156823d33999 | 865 | __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
<> | 149:156823d33999 | 866 | __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
<> | 149:156823d33999 | 867 | __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
<> | 149:156823d33999 | 868 | __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
<> | 149:156823d33999 | 869 | __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
<> | 149:156823d33999 | 870 | __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
<> | 149:156823d33999 | 871 | __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
<> | 149:156823d33999 | 872 | __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
<> | 149:156823d33999 | 873 | __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ |
<> | 149:156823d33999 | 874 | __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
<> | 149:156823d33999 | 875 | uint32_t RESERVED0[1]; |
<> | 149:156823d33999 | 876 | __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
<> | 149:156823d33999 | 877 | __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ |
<> | 149:156823d33999 | 878 | __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
<> | 149:156823d33999 | 879 | uint32_t RESERVED1[1]; |
<> | 149:156823d33999 | 880 | __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
<> | 149:156823d33999 | 881 | __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ |
<> | 149:156823d33999 | 882 | __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
<> | 149:156823d33999 | 883 | uint32_t RESERVED2[1]; |
<> | 149:156823d33999 | 884 | __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
<> | 149:156823d33999 | 885 | __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ |
<> | 149:156823d33999 | 886 | __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
<> | 149:156823d33999 | 887 | } DWT_Type; |
<> | 149:156823d33999 | 888 | |
<> | 149:156823d33999 | 889 | /* DWT Control Register Definitions */ |
<> | 149:156823d33999 | 890 | #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ |
<> | 149:156823d33999 | 891 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
<> | 149:156823d33999 | 892 | |
<> | 149:156823d33999 | 893 | #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ |
<> | 149:156823d33999 | 894 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
<> | 149:156823d33999 | 895 | |
<> | 149:156823d33999 | 896 | #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ |
<> | 149:156823d33999 | 897 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
<> | 149:156823d33999 | 898 | |
<> | 149:156823d33999 | 899 | #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ |
<> | 149:156823d33999 | 900 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
<> | 149:156823d33999 | 901 | |
<> | 149:156823d33999 | 902 | #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ |
<> | 149:156823d33999 | 903 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
<> | 149:156823d33999 | 904 | |
<> | 149:156823d33999 | 905 | #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ |
<> | 149:156823d33999 | 906 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
<> | 149:156823d33999 | 907 | |
<> | 149:156823d33999 | 908 | #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ |
<> | 149:156823d33999 | 909 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
<> | 149:156823d33999 | 910 | |
<> | 149:156823d33999 | 911 | #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ |
<> | 149:156823d33999 | 912 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
<> | 149:156823d33999 | 913 | |
<> | 149:156823d33999 | 914 | #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ |
<> | 149:156823d33999 | 915 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
<> | 149:156823d33999 | 916 | |
<> | 149:156823d33999 | 917 | #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ |
<> | 149:156823d33999 | 918 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
<> | 149:156823d33999 | 919 | |
<> | 149:156823d33999 | 920 | #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ |
<> | 149:156823d33999 | 921 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
<> | 149:156823d33999 | 922 | |
<> | 149:156823d33999 | 923 | #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ |
<> | 149:156823d33999 | 924 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
<> | 149:156823d33999 | 925 | |
<> | 149:156823d33999 | 926 | #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ |
<> | 149:156823d33999 | 927 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
<> | 149:156823d33999 | 928 | |
<> | 149:156823d33999 | 929 | #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ |
<> | 149:156823d33999 | 930 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
<> | 149:156823d33999 | 931 | |
<> | 149:156823d33999 | 932 | #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ |
<> | 149:156823d33999 | 933 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
<> | 149:156823d33999 | 934 | |
<> | 149:156823d33999 | 935 | #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ |
<> | 149:156823d33999 | 936 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
<> | 149:156823d33999 | 937 | |
<> | 149:156823d33999 | 938 | #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ |
<> | 149:156823d33999 | 939 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
<> | 149:156823d33999 | 940 | |
<> | 149:156823d33999 | 941 | #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ |
<> | 149:156823d33999 | 942 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
<> | 149:156823d33999 | 943 | |
<> | 149:156823d33999 | 944 | /* DWT CPI Count Register Definitions */ |
<> | 149:156823d33999 | 945 | #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ |
<> | 149:156823d33999 | 946 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
<> | 149:156823d33999 | 947 | |
<> | 149:156823d33999 | 948 | /* DWT Exception Overhead Count Register Definitions */ |
<> | 149:156823d33999 | 949 | #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ |
<> | 149:156823d33999 | 950 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
<> | 149:156823d33999 | 951 | |
<> | 149:156823d33999 | 952 | /* DWT Sleep Count Register Definitions */ |
<> | 149:156823d33999 | 953 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
<> | 149:156823d33999 | 954 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
<> | 149:156823d33999 | 955 | |
<> | 149:156823d33999 | 956 | /* DWT LSU Count Register Definitions */ |
<> | 149:156823d33999 | 957 | #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ |
<> | 149:156823d33999 | 958 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
<> | 149:156823d33999 | 959 | |
<> | 149:156823d33999 | 960 | /* DWT Folded-instruction Count Register Definitions */ |
<> | 149:156823d33999 | 961 | #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ |
<> | 149:156823d33999 | 962 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
<> | 149:156823d33999 | 963 | |
<> | 149:156823d33999 | 964 | /* DWT Comparator Mask Register Definitions */ |
<> | 149:156823d33999 | 965 | #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ |
<> | 149:156823d33999 | 966 | #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ |
<> | 149:156823d33999 | 967 | |
<> | 149:156823d33999 | 968 | /* DWT Comparator Function Register Definitions */ |
<> | 149:156823d33999 | 969 | #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ |
<> | 149:156823d33999 | 970 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
<> | 149:156823d33999 | 971 | |
<> | 149:156823d33999 | 972 | #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ |
<> | 149:156823d33999 | 973 | #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ |
<> | 149:156823d33999 | 974 | |
<> | 149:156823d33999 | 975 | #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ |
<> | 149:156823d33999 | 976 | #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ |
<> | 149:156823d33999 | 977 | |
<> | 149:156823d33999 | 978 | #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ |
<> | 149:156823d33999 | 979 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
<> | 149:156823d33999 | 980 | |
<> | 149:156823d33999 | 981 | #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ |
<> | 149:156823d33999 | 982 | #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ |
<> | 149:156823d33999 | 983 | |
<> | 149:156823d33999 | 984 | #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ |
<> | 149:156823d33999 | 985 | #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ |
<> | 149:156823d33999 | 986 | |
<> | 149:156823d33999 | 987 | #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ |
<> | 149:156823d33999 | 988 | #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ |
<> | 149:156823d33999 | 989 | |
<> | 149:156823d33999 | 990 | #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ |
<> | 149:156823d33999 | 991 | #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ |
<> | 149:156823d33999 | 992 | |
<> | 149:156823d33999 | 993 | #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ |
<> | 149:156823d33999 | 994 | #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ |
<> | 149:156823d33999 | 995 | |
<> | 149:156823d33999 | 996 | /*@}*/ /* end of group CMSIS_DWT */ |
<> | 149:156823d33999 | 997 | |
<> | 149:156823d33999 | 998 | |
<> | 149:156823d33999 | 999 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 1000 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
<> | 149:156823d33999 | 1001 | \brief Type definitions for the Trace Port Interface (TPI) |
<> | 149:156823d33999 | 1002 | @{ |
<> | 149:156823d33999 | 1003 | */ |
<> | 149:156823d33999 | 1004 | |
<> | 149:156823d33999 | 1005 | /** \brief Structure type to access the Trace Port Interface Register (TPI). |
<> | 149:156823d33999 | 1006 | */ |
<> | 149:156823d33999 | 1007 | typedef struct |
<> | 149:156823d33999 | 1008 | { |
<> | 149:156823d33999 | 1009 | __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
<> | 149:156823d33999 | 1010 | __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
<> | 149:156823d33999 | 1011 | uint32_t RESERVED0[2]; |
<> | 149:156823d33999 | 1012 | __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
<> | 149:156823d33999 | 1013 | uint32_t RESERVED1[55]; |
<> | 149:156823d33999 | 1014 | __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
<> | 149:156823d33999 | 1015 | uint32_t RESERVED2[131]; |
<> | 149:156823d33999 | 1016 | __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
<> | 149:156823d33999 | 1017 | __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
<> | 149:156823d33999 | 1018 | __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
<> | 149:156823d33999 | 1019 | uint32_t RESERVED3[759]; |
<> | 149:156823d33999 | 1020 | __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
<> | 149:156823d33999 | 1021 | __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
<> | 149:156823d33999 | 1022 | __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
<> | 149:156823d33999 | 1023 | uint32_t RESERVED4[1]; |
<> | 149:156823d33999 | 1024 | __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
<> | 149:156823d33999 | 1025 | __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
<> | 149:156823d33999 | 1026 | __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
<> | 149:156823d33999 | 1027 | uint32_t RESERVED5[39]; |
<> | 149:156823d33999 | 1028 | __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
<> | 149:156823d33999 | 1029 | __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
<> | 149:156823d33999 | 1030 | uint32_t RESERVED7[8]; |
<> | 149:156823d33999 | 1031 | __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
<> | 149:156823d33999 | 1032 | __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
<> | 149:156823d33999 | 1033 | } TPI_Type; |
<> | 149:156823d33999 | 1034 | |
<> | 149:156823d33999 | 1035 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
<> | 149:156823d33999 | 1036 | #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ |
<> | 149:156823d33999 | 1037 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
<> | 149:156823d33999 | 1038 | |
<> | 149:156823d33999 | 1039 | /* TPI Selected Pin Protocol Register Definitions */ |
<> | 149:156823d33999 | 1040 | #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ |
<> | 149:156823d33999 | 1041 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
<> | 149:156823d33999 | 1042 | |
<> | 149:156823d33999 | 1043 | /* TPI Formatter and Flush Status Register Definitions */ |
<> | 149:156823d33999 | 1044 | #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ |
<> | 149:156823d33999 | 1045 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
<> | 149:156823d33999 | 1046 | |
<> | 149:156823d33999 | 1047 | #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ |
<> | 149:156823d33999 | 1048 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
<> | 149:156823d33999 | 1049 | |
<> | 149:156823d33999 | 1050 | #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ |
<> | 149:156823d33999 | 1051 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
<> | 149:156823d33999 | 1052 | |
<> | 149:156823d33999 | 1053 | #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ |
<> | 149:156823d33999 | 1054 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
<> | 149:156823d33999 | 1055 | |
<> | 149:156823d33999 | 1056 | /* TPI Formatter and Flush Control Register Definitions */ |
<> | 149:156823d33999 | 1057 | #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ |
<> | 149:156823d33999 | 1058 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
<> | 149:156823d33999 | 1059 | |
<> | 149:156823d33999 | 1060 | #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ |
<> | 149:156823d33999 | 1061 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
<> | 149:156823d33999 | 1062 | |
<> | 149:156823d33999 | 1063 | /* TPI TRIGGER Register Definitions */ |
<> | 149:156823d33999 | 1064 | #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ |
<> | 149:156823d33999 | 1065 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
<> | 149:156823d33999 | 1066 | |
<> | 149:156823d33999 | 1067 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
<> | 149:156823d33999 | 1068 | #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ |
<> | 149:156823d33999 | 1069 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
<> | 149:156823d33999 | 1070 | |
<> | 149:156823d33999 | 1071 | #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ |
<> | 149:156823d33999 | 1072 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
<> | 149:156823d33999 | 1073 | |
<> | 149:156823d33999 | 1074 | #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ |
<> | 149:156823d33999 | 1075 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
<> | 149:156823d33999 | 1076 | |
<> | 149:156823d33999 | 1077 | #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ |
<> | 149:156823d33999 | 1078 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
<> | 149:156823d33999 | 1079 | |
<> | 149:156823d33999 | 1080 | #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ |
<> | 149:156823d33999 | 1081 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
<> | 149:156823d33999 | 1082 | |
<> | 149:156823d33999 | 1083 | #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ |
<> | 149:156823d33999 | 1084 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
<> | 149:156823d33999 | 1085 | |
<> | 149:156823d33999 | 1086 | #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ |
<> | 149:156823d33999 | 1087 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
<> | 149:156823d33999 | 1088 | |
<> | 149:156823d33999 | 1089 | /* TPI ITATBCTR2 Register Definitions */ |
<> | 149:156823d33999 | 1090 | #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ |
<> | 149:156823d33999 | 1091 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
<> | 149:156823d33999 | 1092 | |
<> | 149:156823d33999 | 1093 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
<> | 149:156823d33999 | 1094 | #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ |
<> | 149:156823d33999 | 1095 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
<> | 149:156823d33999 | 1096 | |
<> | 149:156823d33999 | 1097 | #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ |
<> | 149:156823d33999 | 1098 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
<> | 149:156823d33999 | 1099 | |
<> | 149:156823d33999 | 1100 | #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ |
<> | 149:156823d33999 | 1101 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
<> | 149:156823d33999 | 1102 | |
<> | 149:156823d33999 | 1103 | #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ |
<> | 149:156823d33999 | 1104 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
<> | 149:156823d33999 | 1105 | |
<> | 149:156823d33999 | 1106 | #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ |
<> | 149:156823d33999 | 1107 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
<> | 149:156823d33999 | 1108 | |
<> | 149:156823d33999 | 1109 | #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ |
<> | 149:156823d33999 | 1110 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
<> | 149:156823d33999 | 1111 | |
<> | 149:156823d33999 | 1112 | #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ |
<> | 149:156823d33999 | 1113 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
<> | 149:156823d33999 | 1114 | |
<> | 149:156823d33999 | 1115 | /* TPI ITATBCTR0 Register Definitions */ |
<> | 149:156823d33999 | 1116 | #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ |
<> | 149:156823d33999 | 1117 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
<> | 149:156823d33999 | 1118 | |
<> | 149:156823d33999 | 1119 | /* TPI Integration Mode Control Register Definitions */ |
<> | 149:156823d33999 | 1120 | #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ |
<> | 149:156823d33999 | 1121 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
<> | 149:156823d33999 | 1122 | |
<> | 149:156823d33999 | 1123 | /* TPI DEVID Register Definitions */ |
<> | 149:156823d33999 | 1124 | #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ |
<> | 149:156823d33999 | 1125 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
<> | 149:156823d33999 | 1126 | |
<> | 149:156823d33999 | 1127 | #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ |
<> | 149:156823d33999 | 1128 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
<> | 149:156823d33999 | 1129 | |
<> | 149:156823d33999 | 1130 | #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ |
<> | 149:156823d33999 | 1131 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
<> | 149:156823d33999 | 1132 | |
<> | 149:156823d33999 | 1133 | #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ |
<> | 149:156823d33999 | 1134 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
<> | 149:156823d33999 | 1135 | |
<> | 149:156823d33999 | 1136 | #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ |
<> | 149:156823d33999 | 1137 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
<> | 149:156823d33999 | 1138 | |
<> | 149:156823d33999 | 1139 | #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ |
<> | 149:156823d33999 | 1140 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
<> | 149:156823d33999 | 1141 | |
<> | 149:156823d33999 | 1142 | /* TPI DEVTYPE Register Definitions */ |
<> | 149:156823d33999 | 1143 | #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ |
<> | 149:156823d33999 | 1144 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
<> | 149:156823d33999 | 1145 | |
<> | 149:156823d33999 | 1146 | #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ |
<> | 149:156823d33999 | 1147 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
<> | 149:156823d33999 | 1148 | |
<> | 149:156823d33999 | 1149 | /*@}*/ /* end of group CMSIS_TPI */ |
<> | 149:156823d33999 | 1150 | |
<> | 149:156823d33999 | 1151 | |
<> | 149:156823d33999 | 1152 | #if (__MPU_PRESENT == 1) |
<> | 149:156823d33999 | 1153 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 1154 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
<> | 149:156823d33999 | 1155 | \brief Type definitions for the Memory Protection Unit (MPU) |
<> | 149:156823d33999 | 1156 | @{ |
<> | 149:156823d33999 | 1157 | */ |
<> | 149:156823d33999 | 1158 | |
<> | 149:156823d33999 | 1159 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
<> | 149:156823d33999 | 1160 | */ |
<> | 149:156823d33999 | 1161 | typedef struct |
<> | 149:156823d33999 | 1162 | { |
<> | 149:156823d33999 | 1163 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
<> | 149:156823d33999 | 1164 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
<> | 149:156823d33999 | 1165 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
<> | 149:156823d33999 | 1166 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
<> | 149:156823d33999 | 1167 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
<> | 149:156823d33999 | 1168 | __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ |
<> | 149:156823d33999 | 1169 | __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ |
<> | 149:156823d33999 | 1170 | __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ |
<> | 149:156823d33999 | 1171 | __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ |
<> | 149:156823d33999 | 1172 | __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ |
<> | 149:156823d33999 | 1173 | __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ |
<> | 149:156823d33999 | 1174 | } MPU_Type; |
<> | 149:156823d33999 | 1175 | |
<> | 149:156823d33999 | 1176 | /* MPU Type Register */ |
<> | 149:156823d33999 | 1177 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
<> | 149:156823d33999 | 1178 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
<> | 149:156823d33999 | 1179 | |
<> | 149:156823d33999 | 1180 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
<> | 149:156823d33999 | 1181 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
<> | 149:156823d33999 | 1182 | |
<> | 149:156823d33999 | 1183 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
<> | 149:156823d33999 | 1184 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
<> | 149:156823d33999 | 1185 | |
<> | 149:156823d33999 | 1186 | /* MPU Control Register */ |
<> | 149:156823d33999 | 1187 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
<> | 149:156823d33999 | 1188 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
<> | 149:156823d33999 | 1189 | |
<> | 149:156823d33999 | 1190 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
<> | 149:156823d33999 | 1191 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
<> | 149:156823d33999 | 1192 | |
<> | 149:156823d33999 | 1193 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
<> | 149:156823d33999 | 1194 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
<> | 149:156823d33999 | 1195 | |
<> | 149:156823d33999 | 1196 | /* MPU Region Number Register */ |
<> | 149:156823d33999 | 1197 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
<> | 149:156823d33999 | 1198 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
<> | 149:156823d33999 | 1199 | |
<> | 149:156823d33999 | 1200 | /* MPU Region Base Address Register */ |
<> | 149:156823d33999 | 1201 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
<> | 149:156823d33999 | 1202 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
<> | 149:156823d33999 | 1203 | |
<> | 149:156823d33999 | 1204 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
<> | 149:156823d33999 | 1205 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
<> | 149:156823d33999 | 1206 | |
<> | 149:156823d33999 | 1207 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
<> | 149:156823d33999 | 1208 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
<> | 149:156823d33999 | 1209 | |
<> | 149:156823d33999 | 1210 | /* MPU Region Attribute and Size Register */ |
<> | 149:156823d33999 | 1211 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
<> | 149:156823d33999 | 1212 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
<> | 149:156823d33999 | 1213 | |
<> | 149:156823d33999 | 1214 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
<> | 149:156823d33999 | 1215 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
<> | 149:156823d33999 | 1216 | |
<> | 149:156823d33999 | 1217 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
<> | 149:156823d33999 | 1218 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
<> | 149:156823d33999 | 1219 | |
<> | 149:156823d33999 | 1220 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
<> | 149:156823d33999 | 1221 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
<> | 149:156823d33999 | 1222 | |
<> | 149:156823d33999 | 1223 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
<> | 149:156823d33999 | 1224 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
<> | 149:156823d33999 | 1225 | |
<> | 149:156823d33999 | 1226 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
<> | 149:156823d33999 | 1227 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
<> | 149:156823d33999 | 1228 | |
<> | 149:156823d33999 | 1229 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
<> | 149:156823d33999 | 1230 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
<> | 149:156823d33999 | 1231 | |
<> | 149:156823d33999 | 1232 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
<> | 149:156823d33999 | 1233 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
<> | 149:156823d33999 | 1234 | |
<> | 149:156823d33999 | 1235 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
<> | 149:156823d33999 | 1236 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
<> | 149:156823d33999 | 1237 | |
<> | 149:156823d33999 | 1238 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
<> | 149:156823d33999 | 1239 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
<> | 149:156823d33999 | 1240 | |
<> | 149:156823d33999 | 1241 | /*@} end of group CMSIS_MPU */ |
<> | 149:156823d33999 | 1242 | #endif |
<> | 149:156823d33999 | 1243 | |
<> | 149:156823d33999 | 1244 | |
<> | 149:156823d33999 | 1245 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 1246 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 1247 | \defgroup CMSIS_FPU Floating Point Unit (FPU) |
<> | 149:156823d33999 | 1248 | \brief Type definitions for the Floating Point Unit (FPU) |
<> | 149:156823d33999 | 1249 | @{ |
<> | 149:156823d33999 | 1250 | */ |
<> | 149:156823d33999 | 1251 | |
<> | 149:156823d33999 | 1252 | /** \brief Structure type to access the Floating Point Unit (FPU). |
<> | 149:156823d33999 | 1253 | */ |
<> | 149:156823d33999 | 1254 | typedef struct |
<> | 149:156823d33999 | 1255 | { |
<> | 149:156823d33999 | 1256 | uint32_t RESERVED0[1]; |
<> | 149:156823d33999 | 1257 | __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ |
<> | 149:156823d33999 | 1258 | __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ |
<> | 149:156823d33999 | 1259 | __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ |
<> | 149:156823d33999 | 1260 | __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ |
<> | 149:156823d33999 | 1261 | __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ |
<> | 149:156823d33999 | 1262 | } FPU_Type; |
<> | 149:156823d33999 | 1263 | |
<> | 149:156823d33999 | 1264 | /* Floating-Point Context Control Register */ |
<> | 149:156823d33999 | 1265 | #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ |
<> | 149:156823d33999 | 1266 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ |
<> | 149:156823d33999 | 1267 | |
<> | 149:156823d33999 | 1268 | #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ |
<> | 149:156823d33999 | 1269 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ |
<> | 149:156823d33999 | 1270 | |
<> | 149:156823d33999 | 1271 | #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ |
<> | 149:156823d33999 | 1272 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ |
<> | 149:156823d33999 | 1273 | |
<> | 149:156823d33999 | 1274 | #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ |
<> | 149:156823d33999 | 1275 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ |
<> | 149:156823d33999 | 1276 | |
<> | 149:156823d33999 | 1277 | #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ |
<> | 149:156823d33999 | 1278 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ |
<> | 149:156823d33999 | 1279 | |
<> | 149:156823d33999 | 1280 | #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ |
<> | 149:156823d33999 | 1281 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ |
<> | 149:156823d33999 | 1282 | |
<> | 149:156823d33999 | 1283 | #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ |
<> | 149:156823d33999 | 1284 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ |
<> | 149:156823d33999 | 1285 | |
<> | 149:156823d33999 | 1286 | #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ |
<> | 149:156823d33999 | 1287 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ |
<> | 149:156823d33999 | 1288 | |
<> | 149:156823d33999 | 1289 | #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ |
<> | 149:156823d33999 | 1290 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ |
<> | 149:156823d33999 | 1291 | |
<> | 149:156823d33999 | 1292 | /* Floating-Point Context Address Register */ |
<> | 149:156823d33999 | 1293 | #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ |
<> | 149:156823d33999 | 1294 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ |
<> | 149:156823d33999 | 1295 | |
<> | 149:156823d33999 | 1296 | /* Floating-Point Default Status Control Register */ |
<> | 149:156823d33999 | 1297 | #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ |
<> | 149:156823d33999 | 1298 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ |
<> | 149:156823d33999 | 1299 | |
<> | 149:156823d33999 | 1300 | #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ |
<> | 149:156823d33999 | 1301 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ |
<> | 149:156823d33999 | 1302 | |
<> | 149:156823d33999 | 1303 | #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ |
<> | 149:156823d33999 | 1304 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ |
<> | 149:156823d33999 | 1305 | |
<> | 149:156823d33999 | 1306 | #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ |
<> | 149:156823d33999 | 1307 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ |
<> | 149:156823d33999 | 1308 | |
<> | 149:156823d33999 | 1309 | /* Media and FP Feature Register 0 */ |
<> | 149:156823d33999 | 1310 | #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ |
<> | 149:156823d33999 | 1311 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ |
<> | 149:156823d33999 | 1312 | |
<> | 149:156823d33999 | 1313 | #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ |
<> | 149:156823d33999 | 1314 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ |
<> | 149:156823d33999 | 1315 | |
<> | 149:156823d33999 | 1316 | #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ |
<> | 149:156823d33999 | 1317 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ |
<> | 149:156823d33999 | 1318 | |
<> | 149:156823d33999 | 1319 | #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ |
<> | 149:156823d33999 | 1320 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ |
<> | 149:156823d33999 | 1321 | |
<> | 149:156823d33999 | 1322 | #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ |
<> | 149:156823d33999 | 1323 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ |
<> | 149:156823d33999 | 1324 | |
<> | 149:156823d33999 | 1325 | #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ |
<> | 149:156823d33999 | 1326 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ |
<> | 149:156823d33999 | 1327 | |
<> | 149:156823d33999 | 1328 | #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ |
<> | 149:156823d33999 | 1329 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ |
<> | 149:156823d33999 | 1330 | |
<> | 149:156823d33999 | 1331 | #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ |
<> | 149:156823d33999 | 1332 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ |
<> | 149:156823d33999 | 1333 | |
<> | 149:156823d33999 | 1334 | /* Media and FP Feature Register 1 */ |
<> | 149:156823d33999 | 1335 | #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ |
<> | 149:156823d33999 | 1336 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ |
<> | 149:156823d33999 | 1337 | |
<> | 149:156823d33999 | 1338 | #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ |
<> | 149:156823d33999 | 1339 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ |
<> | 149:156823d33999 | 1340 | |
<> | 149:156823d33999 | 1341 | #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ |
<> | 149:156823d33999 | 1342 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ |
<> | 149:156823d33999 | 1343 | |
<> | 149:156823d33999 | 1344 | #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ |
<> | 149:156823d33999 | 1345 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ |
<> | 149:156823d33999 | 1346 | |
<> | 149:156823d33999 | 1347 | /*@} end of group CMSIS_FPU */ |
<> | 149:156823d33999 | 1348 | #endif |
<> | 149:156823d33999 | 1349 | |
<> | 149:156823d33999 | 1350 | |
<> | 149:156823d33999 | 1351 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 1352 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
<> | 149:156823d33999 | 1353 | \brief Type definitions for the Core Debug Registers |
<> | 149:156823d33999 | 1354 | @{ |
<> | 149:156823d33999 | 1355 | */ |
<> | 149:156823d33999 | 1356 | |
<> | 149:156823d33999 | 1357 | /** \brief Structure type to access the Core Debug Register (CoreDebug). |
<> | 149:156823d33999 | 1358 | */ |
<> | 149:156823d33999 | 1359 | typedef struct |
<> | 149:156823d33999 | 1360 | { |
<> | 149:156823d33999 | 1361 | __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
<> | 149:156823d33999 | 1362 | __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
<> | 149:156823d33999 | 1363 | __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
<> | 149:156823d33999 | 1364 | __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
<> | 149:156823d33999 | 1365 | } CoreDebug_Type; |
<> | 149:156823d33999 | 1366 | |
<> | 149:156823d33999 | 1367 | /* Debug Halting Control and Status Register */ |
<> | 149:156823d33999 | 1368 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
<> | 149:156823d33999 | 1369 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
<> | 149:156823d33999 | 1370 | |
<> | 149:156823d33999 | 1371 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
<> | 149:156823d33999 | 1372 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
<> | 149:156823d33999 | 1373 | |
<> | 149:156823d33999 | 1374 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
<> | 149:156823d33999 | 1375 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
<> | 149:156823d33999 | 1376 | |
<> | 149:156823d33999 | 1377 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
<> | 149:156823d33999 | 1378 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
<> | 149:156823d33999 | 1379 | |
<> | 149:156823d33999 | 1380 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
<> | 149:156823d33999 | 1381 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
<> | 149:156823d33999 | 1382 | |
<> | 149:156823d33999 | 1383 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
<> | 149:156823d33999 | 1384 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
<> | 149:156823d33999 | 1385 | |
<> | 149:156823d33999 | 1386 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
<> | 149:156823d33999 | 1387 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
<> | 149:156823d33999 | 1388 | |
<> | 149:156823d33999 | 1389 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
<> | 149:156823d33999 | 1390 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
<> | 149:156823d33999 | 1391 | |
<> | 149:156823d33999 | 1392 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
<> | 149:156823d33999 | 1393 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
<> | 149:156823d33999 | 1394 | |
<> | 149:156823d33999 | 1395 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
<> | 149:156823d33999 | 1396 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
<> | 149:156823d33999 | 1397 | |
<> | 149:156823d33999 | 1398 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
<> | 149:156823d33999 | 1399 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
<> | 149:156823d33999 | 1400 | |
<> | 149:156823d33999 | 1401 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
<> | 149:156823d33999 | 1402 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
<> | 149:156823d33999 | 1403 | |
<> | 149:156823d33999 | 1404 | /* Debug Core Register Selector Register */ |
<> | 149:156823d33999 | 1405 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
<> | 149:156823d33999 | 1406 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
<> | 149:156823d33999 | 1407 | |
<> | 149:156823d33999 | 1408 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
<> | 149:156823d33999 | 1409 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
<> | 149:156823d33999 | 1410 | |
<> | 149:156823d33999 | 1411 | /* Debug Exception and Monitor Control Register */ |
<> | 149:156823d33999 | 1412 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
<> | 149:156823d33999 | 1413 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
<> | 149:156823d33999 | 1414 | |
<> | 149:156823d33999 | 1415 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
<> | 149:156823d33999 | 1416 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
<> | 149:156823d33999 | 1417 | |
<> | 149:156823d33999 | 1418 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
<> | 149:156823d33999 | 1419 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
<> | 149:156823d33999 | 1420 | |
<> | 149:156823d33999 | 1421 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
<> | 149:156823d33999 | 1422 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
<> | 149:156823d33999 | 1423 | |
<> | 149:156823d33999 | 1424 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
<> | 149:156823d33999 | 1425 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
<> | 149:156823d33999 | 1426 | |
<> | 149:156823d33999 | 1427 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
<> | 149:156823d33999 | 1428 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
<> | 149:156823d33999 | 1429 | |
<> | 149:156823d33999 | 1430 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
<> | 149:156823d33999 | 1431 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
<> | 149:156823d33999 | 1432 | |
<> | 149:156823d33999 | 1433 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
<> | 149:156823d33999 | 1434 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
<> | 149:156823d33999 | 1435 | |
<> | 149:156823d33999 | 1436 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
<> | 149:156823d33999 | 1437 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
<> | 149:156823d33999 | 1438 | |
<> | 149:156823d33999 | 1439 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
<> | 149:156823d33999 | 1440 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
<> | 149:156823d33999 | 1441 | |
<> | 149:156823d33999 | 1442 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
<> | 149:156823d33999 | 1443 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
<> | 149:156823d33999 | 1444 | |
<> | 149:156823d33999 | 1445 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
<> | 149:156823d33999 | 1446 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
<> | 149:156823d33999 | 1447 | |
<> | 149:156823d33999 | 1448 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
<> | 149:156823d33999 | 1449 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
<> | 149:156823d33999 | 1450 | |
<> | 149:156823d33999 | 1451 | /*@} end of group CMSIS_CoreDebug */ |
<> | 149:156823d33999 | 1452 | |
<> | 149:156823d33999 | 1453 | |
<> | 149:156823d33999 | 1454 | /** \ingroup CMSIS_core_register |
<> | 149:156823d33999 | 1455 | \defgroup CMSIS_core_base Core Definitions |
<> | 149:156823d33999 | 1456 | \brief Definitions for base addresses, unions, and structures. |
<> | 149:156823d33999 | 1457 | @{ |
<> | 149:156823d33999 | 1458 | */ |
<> | 149:156823d33999 | 1459 | |
<> | 149:156823d33999 | 1460 | /* Memory mapping of Cortex-M4 Hardware */ |
<> | 149:156823d33999 | 1461 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
<> | 149:156823d33999 | 1462 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
<> | 149:156823d33999 | 1463 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
<> | 149:156823d33999 | 1464 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
<> | 149:156823d33999 | 1465 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
<> | 149:156823d33999 | 1466 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
<> | 149:156823d33999 | 1467 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
<> | 149:156823d33999 | 1468 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
<> | 149:156823d33999 | 1469 | |
<> | 149:156823d33999 | 1470 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
<> | 149:156823d33999 | 1471 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
<> | 149:156823d33999 | 1472 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
<> | 149:156823d33999 | 1473 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
<> | 149:156823d33999 | 1474 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
<> | 149:156823d33999 | 1475 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
<> | 149:156823d33999 | 1476 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
<> | 149:156823d33999 | 1477 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
<> | 149:156823d33999 | 1478 | |
<> | 149:156823d33999 | 1479 | #if (__MPU_PRESENT == 1) |
<> | 149:156823d33999 | 1480 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
<> | 149:156823d33999 | 1481 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
<> | 149:156823d33999 | 1482 | #endif |
<> | 149:156823d33999 | 1483 | |
<> | 149:156823d33999 | 1484 | #if (__FPU_PRESENT == 1) |
<> | 149:156823d33999 | 1485 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ |
<> | 149:156823d33999 | 1486 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ |
<> | 149:156823d33999 | 1487 | #endif |
<> | 149:156823d33999 | 1488 | |
<> | 149:156823d33999 | 1489 | /*@} */ |
<> | 149:156823d33999 | 1490 | |
<> | 149:156823d33999 | 1491 | |
<> | 149:156823d33999 | 1492 | |
<> | 149:156823d33999 | 1493 | /******************************************************************************* |
<> | 149:156823d33999 | 1494 | * Hardware Abstraction Layer |
<> | 149:156823d33999 | 1495 | Core Function Interface contains: |
<> | 149:156823d33999 | 1496 | - Core NVIC Functions |
<> | 149:156823d33999 | 1497 | - Core SysTick Functions |
<> | 149:156823d33999 | 1498 | - Core Debug Functions |
<> | 149:156823d33999 | 1499 | - Core Register Access Functions |
<> | 149:156823d33999 | 1500 | ******************************************************************************/ |
<> | 149:156823d33999 | 1501 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
<> | 149:156823d33999 | 1502 | */ |
<> | 149:156823d33999 | 1503 | |
<> | 149:156823d33999 | 1504 | |
<> | 149:156823d33999 | 1505 | |
<> | 149:156823d33999 | 1506 | /* ########################## NVIC functions #################################### */ |
<> | 149:156823d33999 | 1507 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 149:156823d33999 | 1508 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
<> | 149:156823d33999 | 1509 | \brief Functions that manage interrupts and exceptions via the NVIC. |
<> | 149:156823d33999 | 1510 | @{ |
<> | 149:156823d33999 | 1511 | */ |
<> | 149:156823d33999 | 1512 | |
<> | 149:156823d33999 | 1513 | #ifdef CMSIS_NVIC_VIRTUAL |
<> | 149:156823d33999 | 1514 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
<> | 149:156823d33999 | 1515 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
<> | 149:156823d33999 | 1516 | #endif |
<> | 149:156823d33999 | 1517 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
<> | 149:156823d33999 | 1518 | #else |
<> | 149:156823d33999 | 1519 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
<> | 149:156823d33999 | 1520 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
<> | 149:156823d33999 | 1521 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
<> | 149:156823d33999 | 1522 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
<> | 149:156823d33999 | 1523 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
<> | 149:156823d33999 | 1524 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
<> | 149:156823d33999 | 1525 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
<> | 149:156823d33999 | 1526 | #define NVIC_GetActive __NVIC_GetActive |
<> | 149:156823d33999 | 1527 | #define NVIC_SetPriority __NVIC_SetPriority |
<> | 149:156823d33999 | 1528 | #define NVIC_GetPriority __NVIC_GetPriority |
<> | 149:156823d33999 | 1529 | #define NVIC_SystemReset __NVIC_SystemReset |
<> | 149:156823d33999 | 1530 | #endif /* CMSIS_NVIC_VIRTUAL */ |
<> | 149:156823d33999 | 1531 | |
<> | 149:156823d33999 | 1532 | #ifdef CMSIS_VECTAB_VIRTUAL |
<> | 149:156823d33999 | 1533 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
<> | 149:156823d33999 | 1534 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
<> | 149:156823d33999 | 1535 | #endif |
<> | 149:156823d33999 | 1536 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
<> | 149:156823d33999 | 1537 | #else |
<> | 149:156823d33999 | 1538 | #define NVIC_SetVector __NVIC_SetVector |
<> | 149:156823d33999 | 1539 | #define NVIC_GetVector __NVIC_GetVector |
<> | 149:156823d33999 | 1540 | #endif /* CMSIS_VECTAB_VIRTUAL */ |
<> | 149:156823d33999 | 1541 | |
<> | 149:156823d33999 | 1542 | |
<> | 149:156823d33999 | 1543 | /** \brief Set Priority Grouping |
<> | 149:156823d33999 | 1544 | |
<> | 149:156823d33999 | 1545 | The function sets the priority grouping field using the required unlock sequence. |
<> | 149:156823d33999 | 1546 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
<> | 149:156823d33999 | 1547 | Only values from 0..7 are used. |
<> | 149:156823d33999 | 1548 | In case of a conflict between priority grouping and available |
<> | 149:156823d33999 | 1549 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
<> | 149:156823d33999 | 1550 | |
<> | 149:156823d33999 | 1551 | \param [in] PriorityGroup Priority grouping field. |
<> | 149:156823d33999 | 1552 | */ |
<> | 149:156823d33999 | 1553 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
<> | 149:156823d33999 | 1554 | { |
<> | 149:156823d33999 | 1555 | uint32_t reg_value; |
<> | 149:156823d33999 | 1556 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 149:156823d33999 | 1557 | |
<> | 149:156823d33999 | 1558 | reg_value = SCB->AIRCR; /* read old register configuration */ |
<> | 149:156823d33999 | 1559 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
<> | 149:156823d33999 | 1560 | reg_value = (reg_value | |
<> | 149:156823d33999 | 1561 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
<> | 149:156823d33999 | 1562 | (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ |
<> | 149:156823d33999 | 1563 | SCB->AIRCR = reg_value; |
<> | 149:156823d33999 | 1564 | } |
<> | 149:156823d33999 | 1565 | |
<> | 149:156823d33999 | 1566 | |
<> | 149:156823d33999 | 1567 | /** \brief Get Priority Grouping |
<> | 149:156823d33999 | 1568 | |
<> | 149:156823d33999 | 1569 | The function reads the priority grouping field from the NVIC Interrupt Controller. |
<> | 149:156823d33999 | 1570 | |
<> | 149:156823d33999 | 1571 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
<> | 149:156823d33999 | 1572 | */ |
<> | 149:156823d33999 | 1573 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) |
<> | 149:156823d33999 | 1574 | { |
<> | 149:156823d33999 | 1575 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
<> | 149:156823d33999 | 1576 | } |
<> | 149:156823d33999 | 1577 | |
<> | 149:156823d33999 | 1578 | |
<> | 149:156823d33999 | 1579 | /** \brief Enable External Interrupt |
<> | 149:156823d33999 | 1580 | |
<> | 149:156823d33999 | 1581 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
<> | 149:156823d33999 | 1582 | |
<> | 149:156823d33999 | 1583 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 149:156823d33999 | 1584 | */ |
<> | 149:156823d33999 | 1585 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1586 | { |
<> | 149:156823d33999 | 1587 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 149:156823d33999 | 1588 | } |
<> | 149:156823d33999 | 1589 | |
<> | 149:156823d33999 | 1590 | |
<> | 149:156823d33999 | 1591 | /** \brief Disable External Interrupt |
<> | 149:156823d33999 | 1592 | |
<> | 149:156823d33999 | 1593 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
<> | 149:156823d33999 | 1594 | |
<> | 149:156823d33999 | 1595 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 149:156823d33999 | 1596 | */ |
<> | 149:156823d33999 | 1597 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1598 | { |
<> | 149:156823d33999 | 1599 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 152:9a67f0b066fc | 1600 | __DSB(); |
<> | 152:9a67f0b066fc | 1601 | __ISB(); |
<> | 149:156823d33999 | 1602 | } |
<> | 149:156823d33999 | 1603 | |
<> | 149:156823d33999 | 1604 | |
<> | 149:156823d33999 | 1605 | /** \brief Get Pending Interrupt |
<> | 149:156823d33999 | 1606 | |
<> | 149:156823d33999 | 1607 | The function reads the pending register in the NVIC and returns the pending bit |
<> | 149:156823d33999 | 1608 | for the specified interrupt. |
<> | 149:156823d33999 | 1609 | |
<> | 149:156823d33999 | 1610 | \param [in] IRQn Interrupt number. |
<> | 149:156823d33999 | 1611 | |
<> | 149:156823d33999 | 1612 | \return 0 Interrupt status is not pending. |
<> | 149:156823d33999 | 1613 | \return 1 Interrupt status is pending. |
<> | 149:156823d33999 | 1614 | */ |
<> | 149:156823d33999 | 1615 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1616 | { |
<> | 149:156823d33999 | 1617 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
<> | 149:156823d33999 | 1618 | } |
<> | 149:156823d33999 | 1619 | |
<> | 149:156823d33999 | 1620 | |
<> | 149:156823d33999 | 1621 | /** \brief Set Pending Interrupt |
<> | 149:156823d33999 | 1622 | |
<> | 149:156823d33999 | 1623 | The function sets the pending bit of an external interrupt. |
<> | 149:156823d33999 | 1624 | |
<> | 149:156823d33999 | 1625 | \param [in] IRQn Interrupt number. Value cannot be negative. |
<> | 149:156823d33999 | 1626 | */ |
<> | 149:156823d33999 | 1627 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1628 | { |
<> | 149:156823d33999 | 1629 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 149:156823d33999 | 1630 | } |
<> | 149:156823d33999 | 1631 | |
<> | 149:156823d33999 | 1632 | |
<> | 149:156823d33999 | 1633 | /** \brief Clear Pending Interrupt |
<> | 149:156823d33999 | 1634 | |
<> | 149:156823d33999 | 1635 | The function clears the pending bit of an external interrupt. |
<> | 149:156823d33999 | 1636 | |
<> | 149:156823d33999 | 1637 | \param [in] IRQn External interrupt number. Value cannot be negative. |
<> | 149:156823d33999 | 1638 | */ |
<> | 149:156823d33999 | 1639 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1640 | { |
<> | 149:156823d33999 | 1641 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
<> | 149:156823d33999 | 1642 | } |
<> | 149:156823d33999 | 1643 | |
<> | 149:156823d33999 | 1644 | |
<> | 149:156823d33999 | 1645 | /** \brief Get Active Interrupt |
<> | 149:156823d33999 | 1646 | |
<> | 149:156823d33999 | 1647 | The function reads the active register in NVIC and returns the active bit. |
<> | 149:156823d33999 | 1648 | |
<> | 149:156823d33999 | 1649 | \param [in] IRQn Interrupt number. |
<> | 149:156823d33999 | 1650 | |
<> | 149:156823d33999 | 1651 | \return 0 Interrupt status is not active. |
<> | 149:156823d33999 | 1652 | \return 1 Interrupt status is active. |
<> | 149:156823d33999 | 1653 | */ |
<> | 149:156823d33999 | 1654 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1655 | { |
<> | 149:156823d33999 | 1656 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
<> | 149:156823d33999 | 1657 | } |
<> | 149:156823d33999 | 1658 | |
<> | 149:156823d33999 | 1659 | |
<> | 149:156823d33999 | 1660 | /** \brief Set Interrupt Priority |
<> | 149:156823d33999 | 1661 | |
<> | 149:156823d33999 | 1662 | The function sets the priority of an interrupt. |
<> | 149:156823d33999 | 1663 | |
<> | 149:156823d33999 | 1664 | \note The priority cannot be set for every core interrupt. |
<> | 149:156823d33999 | 1665 | |
<> | 149:156823d33999 | 1666 | \param [in] IRQn Interrupt number. |
<> | 149:156823d33999 | 1667 | \param [in] priority Priority to set. |
<> | 149:156823d33999 | 1668 | */ |
<> | 149:156823d33999 | 1669 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
<> | 149:156823d33999 | 1670 | { |
<> | 149:156823d33999 | 1671 | if((int32_t)IRQn < 0) { |
<> | 149:156823d33999 | 1672 | SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
<> | 149:156823d33999 | 1673 | } |
<> | 149:156823d33999 | 1674 | else { |
<> | 149:156823d33999 | 1675 | NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
<> | 149:156823d33999 | 1676 | } |
<> | 149:156823d33999 | 1677 | } |
<> | 149:156823d33999 | 1678 | |
<> | 149:156823d33999 | 1679 | |
<> | 149:156823d33999 | 1680 | /** \brief Get Interrupt Priority |
<> | 149:156823d33999 | 1681 | |
<> | 149:156823d33999 | 1682 | The function reads the priority of an interrupt. The interrupt |
<> | 149:156823d33999 | 1683 | number can be positive to specify an external (device specific) |
<> | 149:156823d33999 | 1684 | interrupt, or negative to specify an internal (core) interrupt. |
<> | 149:156823d33999 | 1685 | |
<> | 149:156823d33999 | 1686 | |
<> | 149:156823d33999 | 1687 | \param [in] IRQn Interrupt number. |
<> | 149:156823d33999 | 1688 | \return Interrupt Priority. Value is aligned automatically to the implemented |
<> | 149:156823d33999 | 1689 | priority bits of the microcontroller. |
<> | 149:156823d33999 | 1690 | */ |
<> | 149:156823d33999 | 1691 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
<> | 149:156823d33999 | 1692 | { |
<> | 149:156823d33999 | 1693 | |
<> | 149:156823d33999 | 1694 | if((int32_t)IRQn < 0) { |
<> | 149:156823d33999 | 1695 | return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); |
<> | 149:156823d33999 | 1696 | } |
<> | 149:156823d33999 | 1697 | else { |
<> | 149:156823d33999 | 1698 | return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); |
<> | 149:156823d33999 | 1699 | } |
<> | 149:156823d33999 | 1700 | } |
<> | 149:156823d33999 | 1701 | |
<> | 149:156823d33999 | 1702 | |
<> | 149:156823d33999 | 1703 | /** \brief Encode Priority |
<> | 149:156823d33999 | 1704 | |
<> | 149:156823d33999 | 1705 | The function encodes the priority for an interrupt with the given priority group, |
<> | 149:156823d33999 | 1706 | preemptive priority value, and subpriority value. |
<> | 149:156823d33999 | 1707 | In case of a conflict between priority grouping and available |
<> | 149:156823d33999 | 1708 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
<> | 149:156823d33999 | 1709 | |
<> | 149:156823d33999 | 1710 | \param [in] PriorityGroup Used priority group. |
<> | 149:156823d33999 | 1711 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
<> | 149:156823d33999 | 1712 | \param [in] SubPriority Subpriority value (starting from 0). |
<> | 149:156823d33999 | 1713 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
<> | 149:156823d33999 | 1714 | */ |
<> | 149:156823d33999 | 1715 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
<> | 149:156823d33999 | 1716 | { |
<> | 149:156823d33999 | 1717 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 149:156823d33999 | 1718 | uint32_t PreemptPriorityBits; |
<> | 149:156823d33999 | 1719 | uint32_t SubPriorityBits; |
<> | 149:156823d33999 | 1720 | |
<> | 149:156823d33999 | 1721 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
<> | 149:156823d33999 | 1722 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
<> | 149:156823d33999 | 1723 | |
<> | 149:156823d33999 | 1724 | return ( |
<> | 149:156823d33999 | 1725 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
<> | 149:156823d33999 | 1726 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
<> | 149:156823d33999 | 1727 | ); |
<> | 149:156823d33999 | 1728 | } |
<> | 149:156823d33999 | 1729 | |
<> | 149:156823d33999 | 1730 | |
<> | 149:156823d33999 | 1731 | /** \brief Decode Priority |
<> | 149:156823d33999 | 1732 | |
<> | 149:156823d33999 | 1733 | The function decodes an interrupt priority value with a given priority group to |
<> | 149:156823d33999 | 1734 | preemptive priority value and subpriority value. |
<> | 149:156823d33999 | 1735 | In case of a conflict between priority grouping and available |
<> | 149:156823d33999 | 1736 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
<> | 149:156823d33999 | 1737 | |
<> | 149:156823d33999 | 1738 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
<> | 149:156823d33999 | 1739 | \param [in] PriorityGroup Used priority group. |
<> | 149:156823d33999 | 1740 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
<> | 149:156823d33999 | 1741 | \param [out] pSubPriority Subpriority value (starting from 0). |
<> | 149:156823d33999 | 1742 | */ |
<> | 149:156823d33999 | 1743 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
<> | 149:156823d33999 | 1744 | { |
<> | 149:156823d33999 | 1745 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
<> | 149:156823d33999 | 1746 | uint32_t PreemptPriorityBits; |
<> | 149:156823d33999 | 1747 | uint32_t SubPriorityBits; |
<> | 149:156823d33999 | 1748 | |
<> | 149:156823d33999 | 1749 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
<> | 149:156823d33999 | 1750 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
<> | 149:156823d33999 | 1751 | |
<> | 149:156823d33999 | 1752 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
<> | 149:156823d33999 | 1753 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
<> | 149:156823d33999 | 1754 | } |
<> | 149:156823d33999 | 1755 | |
<> | 149:156823d33999 | 1756 | |
<> | 149:156823d33999 | 1757 | /** \brief System Reset |
<> | 149:156823d33999 | 1758 | |
<> | 149:156823d33999 | 1759 | The function initiates a system reset request to reset the MCU. |
<> | 149:156823d33999 | 1760 | */ |
<> | 149:156823d33999 | 1761 | __STATIC_INLINE void __NVIC_SystemReset(void) |
<> | 149:156823d33999 | 1762 | { |
<> | 149:156823d33999 | 1763 | __DSB(); /* Ensure all outstanding memory accesses included |
<> | 149:156823d33999 | 1764 | buffered write are completed before reset */ |
<> | 149:156823d33999 | 1765 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
<> | 149:156823d33999 | 1766 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
<> | 149:156823d33999 | 1767 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
<> | 149:156823d33999 | 1768 | __DSB(); /* Ensure completion of memory access */ |
<> | 149:156823d33999 | 1769 | while(1) { __NOP(); } /* wait until reset */ |
<> | 149:156823d33999 | 1770 | } |
<> | 149:156823d33999 | 1771 | |
<> | 149:156823d33999 | 1772 | /*@} end of CMSIS_Core_NVICFunctions */ |
<> | 149:156823d33999 | 1773 | |
<> | 149:156823d33999 | 1774 | |
<> | 149:156823d33999 | 1775 | |
<> | 149:156823d33999 | 1776 | /* ################################## SysTick function ############################################ */ |
<> | 149:156823d33999 | 1777 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 149:156823d33999 | 1778 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
<> | 149:156823d33999 | 1779 | \brief Functions that configure the System. |
<> | 149:156823d33999 | 1780 | @{ |
<> | 149:156823d33999 | 1781 | */ |
<> | 149:156823d33999 | 1782 | |
<> | 149:156823d33999 | 1783 | #if (__Vendor_SysTickConfig == 0) |
<> | 149:156823d33999 | 1784 | |
<> | 149:156823d33999 | 1785 | /** \brief System Tick Configuration |
<> | 149:156823d33999 | 1786 | |
<> | 149:156823d33999 | 1787 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
<> | 149:156823d33999 | 1788 | Counter is in free running mode to generate periodic interrupts. |
<> | 149:156823d33999 | 1789 | |
<> | 149:156823d33999 | 1790 | \param [in] ticks Number of ticks between two interrupts. |
<> | 149:156823d33999 | 1791 | |
<> | 149:156823d33999 | 1792 | \return 0 Function succeeded. |
<> | 149:156823d33999 | 1793 | \return 1 Function failed. |
<> | 149:156823d33999 | 1794 | |
<> | 149:156823d33999 | 1795 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
<> | 149:156823d33999 | 1796 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
<> | 149:156823d33999 | 1797 | must contain a vendor-specific implementation of this function. |
<> | 149:156823d33999 | 1798 | |
<> | 149:156823d33999 | 1799 | */ |
<> | 149:156823d33999 | 1800 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
<> | 149:156823d33999 | 1801 | { |
<> | 149:156823d33999 | 1802 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ |
<> | 149:156823d33999 | 1803 | |
<> | 149:156823d33999 | 1804 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
<> | 149:156823d33999 | 1805 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
<> | 149:156823d33999 | 1806 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
<> | 149:156823d33999 | 1807 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
<> | 149:156823d33999 | 1808 | SysTick_CTRL_TICKINT_Msk | |
<> | 149:156823d33999 | 1809 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
<> | 149:156823d33999 | 1810 | return (0UL); /* Function successful */ |
<> | 149:156823d33999 | 1811 | } |
<> | 149:156823d33999 | 1812 | |
<> | 149:156823d33999 | 1813 | #endif |
<> | 149:156823d33999 | 1814 | |
<> | 149:156823d33999 | 1815 | /*@} end of CMSIS_Core_SysTickFunctions */ |
<> | 149:156823d33999 | 1816 | |
<> | 149:156823d33999 | 1817 | |
<> | 149:156823d33999 | 1818 | |
<> | 149:156823d33999 | 1819 | /* ##################################### Debug In/Output function ########################################### */ |
<> | 149:156823d33999 | 1820 | /** \ingroup CMSIS_Core_FunctionInterface |
<> | 149:156823d33999 | 1821 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
<> | 149:156823d33999 | 1822 | \brief Functions that access the ITM debug interface. |
<> | 149:156823d33999 | 1823 | @{ |
<> | 149:156823d33999 | 1824 | */ |
<> | 149:156823d33999 | 1825 | |
<> | 149:156823d33999 | 1826 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
<> | 149:156823d33999 | 1827 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
<> | 149:156823d33999 | 1828 | |
<> | 149:156823d33999 | 1829 | |
<> | 149:156823d33999 | 1830 | /** \brief ITM Send Character |
<> | 149:156823d33999 | 1831 | |
<> | 149:156823d33999 | 1832 | The function transmits a character via the ITM channel 0, and |
<> | 149:156823d33999 | 1833 | \li Just returns when no debugger is connected that has booked the output. |
<> | 149:156823d33999 | 1834 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
<> | 149:156823d33999 | 1835 | |
<> | 149:156823d33999 | 1836 | \param [in] ch Character to transmit. |
<> | 149:156823d33999 | 1837 | |
<> | 149:156823d33999 | 1838 | \returns Character to transmit. |
<> | 149:156823d33999 | 1839 | */ |
<> | 149:156823d33999 | 1840 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
<> | 149:156823d33999 | 1841 | { |
<> | 149:156823d33999 | 1842 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
<> | 149:156823d33999 | 1843 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
<> | 149:156823d33999 | 1844 | { |
<> | 149:156823d33999 | 1845 | while (ITM->PORT[0].u32 == 0UL) { __NOP(); } |
<> | 149:156823d33999 | 1846 | ITM->PORT[0].u8 = (uint8_t)ch; |
<> | 149:156823d33999 | 1847 | } |
<> | 149:156823d33999 | 1848 | return (ch); |
<> | 149:156823d33999 | 1849 | } |
<> | 149:156823d33999 | 1850 | |
<> | 149:156823d33999 | 1851 | |
<> | 149:156823d33999 | 1852 | /** \brief ITM Receive Character |
<> | 149:156823d33999 | 1853 | |
<> | 149:156823d33999 | 1854 | The function inputs a character via the external variable \ref ITM_RxBuffer. |
<> | 149:156823d33999 | 1855 | |
<> | 149:156823d33999 | 1856 | \return Received character. |
<> | 149:156823d33999 | 1857 | \return -1 No character pending. |
<> | 149:156823d33999 | 1858 | */ |
<> | 149:156823d33999 | 1859 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) { |
<> | 149:156823d33999 | 1860 | int32_t ch = -1; /* no character available */ |
<> | 149:156823d33999 | 1861 | |
<> | 149:156823d33999 | 1862 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { |
<> | 149:156823d33999 | 1863 | ch = ITM_RxBuffer; |
<> | 149:156823d33999 | 1864 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
<> | 149:156823d33999 | 1865 | } |
<> | 149:156823d33999 | 1866 | |
<> | 149:156823d33999 | 1867 | return (ch); |
<> | 149:156823d33999 | 1868 | } |
<> | 149:156823d33999 | 1869 | |
<> | 149:156823d33999 | 1870 | |
<> | 149:156823d33999 | 1871 | /** \brief ITM Check Character |
<> | 149:156823d33999 | 1872 | |
<> | 149:156823d33999 | 1873 | The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
<> | 149:156823d33999 | 1874 | |
<> | 149:156823d33999 | 1875 | \return 0 No character available. |
<> | 149:156823d33999 | 1876 | \return 1 Character available. |
<> | 149:156823d33999 | 1877 | */ |
<> | 149:156823d33999 | 1878 | __STATIC_INLINE int32_t ITM_CheckChar (void) { |
<> | 149:156823d33999 | 1879 | |
<> | 149:156823d33999 | 1880 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { |
<> | 149:156823d33999 | 1881 | return (0); /* no character available */ |
<> | 149:156823d33999 | 1882 | } else { |
<> | 149:156823d33999 | 1883 | return (1); /* character available */ |
<> | 149:156823d33999 | 1884 | } |
<> | 149:156823d33999 | 1885 | } |
<> | 149:156823d33999 | 1886 | |
<> | 149:156823d33999 | 1887 | /*@} end of CMSIS_core_DebugFunctions */ |
<> | 149:156823d33999 | 1888 | |
<> | 149:156823d33999 | 1889 | |
<> | 149:156823d33999 | 1890 | |
<> | 149:156823d33999 | 1891 | |
<> | 149:156823d33999 | 1892 | #ifdef __cplusplus |
<> | 149:156823d33999 | 1893 | } |
<> | 149:156823d33999 | 1894 | #endif |
<> | 149:156823d33999 | 1895 | |
<> | 149:156823d33999 | 1896 | #endif /* __CORE_CM4_H_DEPENDANT */ |
<> | 149:156823d33999 | 1897 | |
<> | 149:156823d33999 | 1898 | #endif /* __CMSIS_GENERIC */ |