Amit Gandhi / sensen_copy_2

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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F429ZI/system_stm32f4xx.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
23:ee8ca7052b3c
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file system_stm32f4xx.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V2.1.0
bogdanm 0:9b334a45a8ff 6 * @date 19-June-2014
bogdanm 0:9b334a45a8ff 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides two functions and one global variable to be called from
bogdanm 0:9b334a45a8ff 10 * user application:
bogdanm 0:9b334a45a8ff 11 * - SystemInit(): This function is called at startup just after reset and
bogdanm 0:9b334a45a8ff 12 * before branch to main program. This call is made inside
bogdanm 0:9b334a45a8ff 13 * the "startup_stm32f4xx.s" file.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
bogdanm 0:9b334a45a8ff 16 * by the user application to setup the SysTick
bogdanm 0:9b334a45a8ff 17 * timer or configure other parameters.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
bogdanm 0:9b334a45a8ff 20 * be called whenever the core clock is changed
bogdanm 0:9b334a45a8ff 21 * during program execution.
bogdanm 0:9b334a45a8ff 22 *
bogdanm 0:9b334a45a8ff 23 * This file configures the system clock as follows:
bogdanm 0:9b334a45a8ff 24 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 25 * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL
bogdanm 0:9b334a45a8ff 26 * | (external 8 MHz clock) | (external 8 MHz clock)
bogdanm 0:9b334a45a8ff 27 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 28 * SYSCLK(MHz) | 168 | 180
bogdanm 0:9b334a45a8ff 29 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 30 * AHBCLK (MHz) | 168 | 180
bogdanm 0:9b334a45a8ff 31 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 32 * APB1CLK (MHz) | 42 | 45
bogdanm 0:9b334a45a8ff 33 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 34 * APB2CLK (MHz) | 84 | 90
bogdanm 0:9b334a45a8ff 35 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 36 * USB capable (48 MHz precise clock) | YES | NO
bogdanm 0:9b334a45a8ff 37 *--------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 38 ******************************************************************************
bogdanm 0:9b334a45a8ff 39 * @attention
bogdanm 0:9b334a45a8ff 40 *
bogdanm 0:9b334a45a8ff 41 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 42 *
bogdanm 0:9b334a45a8ff 43 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 44 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 45 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 46 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 47 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 48 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 49 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 50 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 51 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 52 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 53 *
bogdanm 0:9b334a45a8ff 54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 55 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 56 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 57 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 58 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 59 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 60 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 61 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 64 *
bogdanm 0:9b334a45a8ff 65 ******************************************************************************
bogdanm 0:9b334a45a8ff 66 */
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 /** @addtogroup CMSIS
bogdanm 0:9b334a45a8ff 69 * @{
bogdanm 0:9b334a45a8ff 70 */
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 /** @addtogroup stm32f4xx_system
bogdanm 0:9b334a45a8ff 73 * @{
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /** @addtogroup STM32F4xx_System_Private_Includes
bogdanm 0:9b334a45a8ff 77 * @{
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 #include "stm32f4xx.h"
bogdanm 0:9b334a45a8ff 82 #include "hal_tick.h"
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 #if !defined (HSE_VALUE)
bogdanm 0:9b334a45a8ff 85 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
bogdanm 0:9b334a45a8ff 86 #endif /* HSE_VALUE */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 #if !defined (HSI_VALUE)
bogdanm 0:9b334a45a8ff 89 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
bogdanm 0:9b334a45a8ff 90 #endif /* HSI_VALUE */
bogdanm 0:9b334a45a8ff 91
bogdanm 0:9b334a45a8ff 92 /**
bogdanm 0:9b334a45a8ff 93 * @}
bogdanm 0:9b334a45a8ff 94 */
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /**
bogdanm 0:9b334a45a8ff 101 * @}
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /** @addtogroup STM32F4xx_System_Private_Defines
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /************************* Miscellaneous Configuration ************************/
bogdanm 0:9b334a45a8ff 109 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
bogdanm 0:9b334a45a8ff 110 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
bogdanm 0:9b334a45a8ff 111 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 112 /* #define DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 113 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 114
bogdanm 0:9b334a45a8ff 115 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 116 /* #define DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 117 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 120 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
bogdanm 0:9b334a45a8ff 121 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 122
bogdanm 0:9b334a45a8ff 123 /*!< Uncomment the following line if you need to relocate your vector Table in
bogdanm 0:9b334a45a8ff 124 Internal SRAM. */
bogdanm 0:9b334a45a8ff 125 /* #define VECT_TAB_SRAM */
bogdanm 0:9b334a45a8ff 126 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
bogdanm 0:9b334a45a8ff 127 This value must be a multiple of 0x200. */
bogdanm 0:9b334a45a8ff 128 /******************************************************************************/
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 /**
bogdanm 0:9b334a45a8ff 131 * @}
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /** @addtogroup STM32F4xx_System_Private_Macros
bogdanm 0:9b334a45a8ff 135 * @{
bogdanm 0:9b334a45a8ff 136 */
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */
bogdanm 0:9b334a45a8ff 139 #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */
bogdanm 0:9b334a45a8ff 140 #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /**
bogdanm 0:9b334a45a8ff 143 * @}
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** @addtogroup STM32F4xx_System_Private_Variables
bogdanm 0:9b334a45a8ff 147 * @{
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149 /* This variable is updated in three ways:
bogdanm 0:9b334a45a8ff 150 1) by calling CMSIS function SystemCoreClockUpdate()
bogdanm 0:9b334a45a8ff 151 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
bogdanm 0:9b334a45a8ff 152 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
bogdanm 0:9b334a45a8ff 153 Note: If you use this function to configure the system clock; then there
bogdanm 0:9b334a45a8ff 154 is no need to call the 2 first functions listed above, since SystemCoreClock
bogdanm 0:9b334a45a8ff 155 variable is updated automatically.
bogdanm 0:9b334a45a8ff 156 */
bogdanm 0:9b334a45a8ff 157 uint32_t SystemCoreClock = 168000000;
bogdanm 0:9b334a45a8ff 158 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 /**
bogdanm 0:9b334a45a8ff 161 * @}
bogdanm 0:9b334a45a8ff 162 */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
bogdanm 0:9b334a45a8ff 165 * @{
bogdanm 0:9b334a45a8ff 166 */
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 169 static void SystemInit_ExtMemCtl(void);
bogdanm 0:9b334a45a8ff 170 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 void SystemClock_Config(void);
bogdanm 0:9b334a45a8ff 173 /**
bogdanm 0:9b334a45a8ff 174 * @}
bogdanm 0:9b334a45a8ff 175 */
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /** @addtogroup STM32F4xx_System_Private_Functions
bogdanm 0:9b334a45a8ff 178 * @{
bogdanm 0:9b334a45a8ff 179 */
bogdanm 0:9b334a45a8ff 180
bogdanm 0:9b334a45a8ff 181 /**
bogdanm 0:9b334a45a8ff 182 * @brief Setup the microcontroller system
bogdanm 0:9b334a45a8ff 183 * Initialize the FPU setting, vector table location and External memory
bogdanm 0:9b334a45a8ff 184 * configuration.
bogdanm 0:9b334a45a8ff 185 * @param None
bogdanm 0:9b334a45a8ff 186 * @retval None
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188 void SystemInit(void)
bogdanm 0:9b334a45a8ff 189 {
bogdanm 0:9b334a45a8ff 190 /* FPU settings ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 191 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
bogdanm 0:9b334a45a8ff 192 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
bogdanm 0:9b334a45a8ff 193 #endif
bogdanm 0:9b334a45a8ff 194 /* Reset the RCC clock configuration to the default reset state ------------*/
bogdanm 0:9b334a45a8ff 195 /* Set HSION bit */
bogdanm 0:9b334a45a8ff 196 RCC->CR |= (uint32_t)0x00000001;
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 199 RCC->CFGR = 0x00000000;
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 /* Reset HSEON, CSSON and PLLON bits */
bogdanm 0:9b334a45a8ff 202 RCC->CR &= (uint32_t)0xFEF6FFFF;
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /* Reset PLLCFGR register */
bogdanm 0:9b334a45a8ff 205 RCC->PLLCFGR = 0x24003010;
bogdanm 0:9b334a45a8ff 206
bogdanm 0:9b334a45a8ff 207 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 208 RCC->CR &= (uint32_t)0xFFFBFFFF;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 211 RCC->CIR = 0x00000000;
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 214 SystemInit_ExtMemCtl();
bogdanm 0:9b334a45a8ff 215 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 /* Configure the Vector Table location add offset address ------------------*/
bogdanm 0:9b334a45a8ff 218 #ifdef VECT_TAB_SRAM
bogdanm 0:9b334a45a8ff 219 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
bogdanm 0:9b334a45a8ff 220 #else
bogdanm 0:9b334a45a8ff 221 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
bogdanm 0:9b334a45a8ff 222 #endif
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /* Configure the Cube driver */
bogdanm 0:9b334a45a8ff 225 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
bogdanm 0:9b334a45a8ff 226 HAL_Init();
bogdanm 0:9b334a45a8ff 227
bogdanm 0:9b334a45a8ff 228 /* Configure the System clock source, PLL Multiplier and Divider factors,
bogdanm 0:9b334a45a8ff 229 AHB/APBx prescalers and Flash settings */
bogdanm 0:9b334a45a8ff 230 SystemClock_Config();
bogdanm 0:9b334a45a8ff 231 SystemCoreClockUpdate();
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Reset the timer to avoid issues after the RAM initialization */
bogdanm 0:9b334a45a8ff 234 TIM_MST_RESET_ON;
bogdanm 0:9b334a45a8ff 235 TIM_MST_RESET_OFF;
bogdanm 0:9b334a45a8ff 236 }
bogdanm 0:9b334a45a8ff 237
bogdanm 0:9b334a45a8ff 238 /**
bogdanm 0:9b334a45a8ff 239 * @brief Update SystemCoreClock variable according to Clock Register Values.
bogdanm 0:9b334a45a8ff 240 * The SystemCoreClock variable contains the core clock (HCLK), it can
bogdanm 0:9b334a45a8ff 241 * be used by the user application to setup the SysTick timer or configure
bogdanm 0:9b334a45a8ff 242 * other parameters.
bogdanm 0:9b334a45a8ff 243 *
bogdanm 0:9b334a45a8ff 244 * @note Each time the core clock (HCLK) changes, this function must be called
bogdanm 0:9b334a45a8ff 245 * to update SystemCoreClock variable value. Otherwise, any configuration
bogdanm 0:9b334a45a8ff 246 * based on this variable will be incorrect.
bogdanm 0:9b334a45a8ff 247 *
bogdanm 0:9b334a45a8ff 248 * @note - The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 249 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 250 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 251 *
bogdanm 0:9b334a45a8ff 252 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 253 *
bogdanm 0:9b334a45a8ff 254 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 255 *
bogdanm 0:9b334a45a8ff 256 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
bogdanm 0:9b334a45a8ff 257 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
bogdanm 0:9b334a45a8ff 258 *
bogdanm 0:9b334a45a8ff 259 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 260 * 16 MHz) but the real value may vary depending on the variations
bogdanm 0:9b334a45a8ff 261 * in voltage and temperature.
bogdanm 0:9b334a45a8ff 262 *
bogdanm 0:9b334a45a8ff 263 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
bogdanm 0:9b334a45a8ff 264 * depends on the application requirements), user has to ensure that HSE_VALUE
bogdanm 0:9b334a45a8ff 265 * is same as the real frequency of the crystal used. Otherwise, this function
bogdanm 0:9b334a45a8ff 266 * may have wrong result.
bogdanm 0:9b334a45a8ff 267 *
bogdanm 0:9b334a45a8ff 268 * - The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 269 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 270 *
bogdanm 0:9b334a45a8ff 271 * @param None
bogdanm 0:9b334a45a8ff 272 * @retval None
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274 void SystemCoreClockUpdate(void)
bogdanm 0:9b334a45a8ff 275 {
bogdanm 0:9b334a45a8ff 276 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
bogdanm 0:9b334a45a8ff 277
bogdanm 0:9b334a45a8ff 278 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 279 tmp = RCC->CFGR & RCC_CFGR_SWS;
bogdanm 0:9b334a45a8ff 280
bogdanm 0:9b334a45a8ff 281 switch (tmp)
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 case 0x00: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 284 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 285 break;
bogdanm 0:9b334a45a8ff 286 case 0x04: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 287 SystemCoreClock = HSE_VALUE;
bogdanm 0:9b334a45a8ff 288 break;
bogdanm 0:9b334a45a8ff 289 case 0x08: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
bogdanm 0:9b334a45a8ff 292 SYSCLK = PLL_VCO / PLL_P
bogdanm 0:9b334a45a8ff 293 */
bogdanm 0:9b334a45a8ff 294 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
bogdanm 0:9b334a45a8ff 295 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 if (pllsource != 0)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 /* HSE used as PLL clock source */
bogdanm 0:9b334a45a8ff 300 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 else
bogdanm 0:9b334a45a8ff 303 {
bogdanm 0:9b334a45a8ff 304 /* HSI used as PLL clock source */
bogdanm 0:9b334a45a8ff 305 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
bogdanm 0:9b334a45a8ff 309 SystemCoreClock = pllvco/pllp;
bogdanm 0:9b334a45a8ff 310 break;
bogdanm 0:9b334a45a8ff 311 default:
bogdanm 0:9b334a45a8ff 312 SystemCoreClock = HSI_VALUE;
bogdanm 0:9b334a45a8ff 313 break;
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315 /* Compute HCLK frequency --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 316 /* Get HCLK prescaler */
bogdanm 0:9b334a45a8ff 317 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
bogdanm 0:9b334a45a8ff 318 /* HCLK frequency */
bogdanm 0:9b334a45a8ff 319 SystemCoreClock >>= tmp;
bogdanm 0:9b334a45a8ff 320 }
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 323 /**
bogdanm 0:9b334a45a8ff 324 * @brief Setup the external memory controller.
bogdanm 0:9b334a45a8ff 325 * Called in startup_stm32f4xx.s before jump to main.
bogdanm 0:9b334a45a8ff 326 * This function configures the external memories (SRAM/SDRAM)
bogdanm 0:9b334a45a8ff 327 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
bogdanm 0:9b334a45a8ff 328 * @param None
bogdanm 0:9b334a45a8ff 329 * @retval None
bogdanm 0:9b334a45a8ff 330 */
bogdanm 0:9b334a45a8ff 331 void SystemInit_ExtMemCtl(void)
bogdanm 0:9b334a45a8ff 332 {
bogdanm 0:9b334a45a8ff 333 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 334 #if defined (DATA_IN_ExtSDRAM)
bogdanm 0:9b334a45a8ff 335 register uint32_t tmpreg = 0, timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 336 register uint32_t index;
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
bogdanm 0:9b334a45a8ff 339 clock */
bogdanm 0:9b334a45a8ff 340 RCC->AHB1ENR |= 0x000001F8;
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 343 GPIOD->AFR[0] = 0x000000CC;
bogdanm 0:9b334a45a8ff 344 GPIOD->AFR[1] = 0xCC000CCC;
bogdanm 0:9b334a45a8ff 345 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 346 GPIOD->MODER = 0xA02A000A;
bogdanm 0:9b334a45a8ff 347 /* Configure PDx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 348 GPIOD->OSPEEDR = 0xA02A000A;
bogdanm 0:9b334a45a8ff 349 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 350 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 351 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 352 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 353
bogdanm 0:9b334a45a8ff 354 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 355 GPIOE->AFR[0] = 0xC00000CC;
bogdanm 0:9b334a45a8ff 356 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 357 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 358 GPIOE->MODER = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 359 /* Configure PEx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 360 GPIOE->OSPEEDR = 0xAAAA800A;
bogdanm 0:9b334a45a8ff 361 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 362 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 363 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 364 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 367 GPIOF->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 368 GPIOF->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 369 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 370 GPIOF->MODER = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 371 /* Configure PFx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 372 GPIOF->OSPEEDR = 0xAA800AAA;
bogdanm 0:9b334a45a8ff 373 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 374 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 375 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 376 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 377
bogdanm 0:9b334a45a8ff 378 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 379 GPIOG->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 380 GPIOG->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 381 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 382 GPIOG->MODER = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 383 /* Configure PGx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 384 GPIOG->OSPEEDR = 0xAAAAAAAA;
bogdanm 0:9b334a45a8ff 385 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 386 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 387 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 388 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* Connect PHx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 391 GPIOH->AFR[0] = 0x00C0CC00;
bogdanm 0:9b334a45a8ff 392 GPIOH->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 393 /* Configure PHx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 394 GPIOH->MODER = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 395 /* Configure PHx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 396 GPIOH->OSPEEDR = 0xAAAA08A0;
bogdanm 0:9b334a45a8ff 397 /* Configure PHx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 398 GPIOH->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 399 /* No pull-up, pull-down for PHx pins */
bogdanm 0:9b334a45a8ff 400 GPIOH->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 /* Connect PIx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 403 GPIOI->AFR[0] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 404 GPIOI->AFR[1] = 0x00000CC0;
bogdanm 0:9b334a45a8ff 405 /* Configure PIx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 406 GPIOI->MODER = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 407 /* Configure PIx pins speed to 50 MHz */
bogdanm 0:9b334a45a8ff 408 GPIOI->OSPEEDR = 0x0028AAAA;
bogdanm 0:9b334a45a8ff 409 /* Configure PIx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 410 GPIOI->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 411 /* No pull-up, pull-down for PIx pins */
bogdanm 0:9b334a45a8ff 412 GPIOI->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 413
bogdanm 0:9b334a45a8ff 414 /*-- FMC Configuration ------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 415 /* Enable the FMC interface clock */
bogdanm 0:9b334a45a8ff 416 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 /* Configure and enable SDRAM bank1 */
bogdanm 0:9b334a45a8ff 419 FMC_Bank5_6->SDCR[0] = 0x000019E0;
bogdanm 0:9b334a45a8ff 420 FMC_Bank5_6->SDTR[0] = 0x01115351;
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 /* SDRAM initialization sequence */
bogdanm 0:9b334a45a8ff 423 /* Clock enable command */
bogdanm 0:9b334a45a8ff 424 FMC_Bank5_6->SDCMR = 0x00000011;
bogdanm 0:9b334a45a8ff 425 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 426 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 427 {
bogdanm 0:9b334a45a8ff 428 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /* Delay */
bogdanm 0:9b334a45a8ff 432 for (index = 0; index<1000; index++);
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434 /* PALL command */
bogdanm 0:9b334a45a8ff 435 FMC_Bank5_6->SDCMR = 0x00000012;
bogdanm 0:9b334a45a8ff 436 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 437 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 438 {
bogdanm 0:9b334a45a8ff 439 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 440 }
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Auto refresh command */
bogdanm 0:9b334a45a8ff 443 FMC_Bank5_6->SDCMR = 0x00000073;
bogdanm 0:9b334a45a8ff 444 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 445 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* MRD register program */
bogdanm 0:9b334a45a8ff 451 FMC_Bank5_6->SDCMR = 0x00046014;
bogdanm 0:9b334a45a8ff 452 timeout = 0xFFFF;
bogdanm 0:9b334a45a8ff 453 while((tmpreg != 0) && (timeout-- > 0))
bogdanm 0:9b334a45a8ff 454 {
bogdanm 0:9b334a45a8ff 455 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
bogdanm 0:9b334a45a8ff 456 }
bogdanm 0:9b334a45a8ff 457
bogdanm 0:9b334a45a8ff 458 /* Set refresh count */
bogdanm 0:9b334a45a8ff 459 tmpreg = FMC_Bank5_6->SDRTR;
bogdanm 0:9b334a45a8ff 460 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
bogdanm 0:9b334a45a8ff 461
bogdanm 0:9b334a45a8ff 462 /* Disable write protection */
bogdanm 0:9b334a45a8ff 463 tmpreg = FMC_Bank5_6->SDCR[0];
bogdanm 0:9b334a45a8ff 464 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
bogdanm 0:9b334a45a8ff 465 #endif /* DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 466 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 469 #if defined(DATA_IN_ExtSRAM)
bogdanm 0:9b334a45a8ff 470 /*-- GPIOs Configuration -----------------------------------------------------*/
bogdanm 0:9b334a45a8ff 471 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
bogdanm 0:9b334a45a8ff 472 RCC->AHB1ENR |= 0x00000078;
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Connect PDx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 475 GPIOD->AFR[0] = 0x00CCC0CC;
bogdanm 0:9b334a45a8ff 476 GPIOD->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 477 /* Configure PDx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 478 GPIOD->MODER = 0xAAAA0A8A;
bogdanm 0:9b334a45a8ff 479 /* Configure PDx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 480 GPIOD->OSPEEDR = 0xFFFF0FCF;
bogdanm 0:9b334a45a8ff 481 /* Configure PDx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 482 GPIOD->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 483 /* No pull-up, pull-down for PDx pins */
bogdanm 0:9b334a45a8ff 484 GPIOD->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 485
bogdanm 0:9b334a45a8ff 486 /* Connect PEx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 487 GPIOE->AFR[0] = 0xC00CC0CC;
bogdanm 0:9b334a45a8ff 488 GPIOE->AFR[1] = 0xCCCCCCCC;
bogdanm 0:9b334a45a8ff 489 /* Configure PEx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 490 GPIOE->MODER = 0xAAAA828A;
bogdanm 0:9b334a45a8ff 491 /* Configure PEx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 492 GPIOE->OSPEEDR = 0xFFFFC3CF;
bogdanm 0:9b334a45a8ff 493 /* Configure PEx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 494 GPIOE->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 495 /* No pull-up, pull-down for PEx pins */
bogdanm 0:9b334a45a8ff 496 GPIOE->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Connect PFx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 499 GPIOF->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 500 GPIOF->AFR[1] = 0xCCCC0000;
bogdanm 0:9b334a45a8ff 501 /* Configure PFx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 502 GPIOF->MODER = 0xAA000AAA;
bogdanm 0:9b334a45a8ff 503 /* Configure PFx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 504 GPIOF->OSPEEDR = 0xFF000FFF;
bogdanm 0:9b334a45a8ff 505 /* Configure PFx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 506 GPIOF->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 507 /* No pull-up, pull-down for PFx pins */
bogdanm 0:9b334a45a8ff 508 GPIOF->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Connect PGx pins to FMC Alternate function */
bogdanm 0:9b334a45a8ff 511 GPIOG->AFR[0] = 0x00CCCCCC;
bogdanm 0:9b334a45a8ff 512 GPIOG->AFR[1] = 0x000000C0;
bogdanm 0:9b334a45a8ff 513 /* Configure PGx pins in Alternate function mode */
bogdanm 0:9b334a45a8ff 514 GPIOG->MODER = 0x00085AAA;
bogdanm 0:9b334a45a8ff 515 /* Configure PGx pins speed to 100 MHz */
bogdanm 0:9b334a45a8ff 516 GPIOG->OSPEEDR = 0x000CAFFF;
bogdanm 0:9b334a45a8ff 517 /* Configure PGx pins Output type to push-pull */
bogdanm 0:9b334a45a8ff 518 GPIOG->OTYPER = 0x00000000;
bogdanm 0:9b334a45a8ff 519 /* No pull-up, pull-down for PGx pins */
bogdanm 0:9b334a45a8ff 520 GPIOG->PUPDR = 0x00000000;
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /*-- FMC/FSMC Configuration --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 523 /* Enable the FMC/FSMC interface clock */
bogdanm 0:9b334a45a8ff 524 RCC->AHB3ENR |= 0x00000001;
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
bogdanm 0:9b334a45a8ff 527 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 528 FMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 529 FMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 530 FMC_Bank1E->BWTR[2] = 0x0fffffff;
bogdanm 0:9b334a45a8ff 531 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
bogdanm 0:9b334a45a8ff 534 /* Configure and enable Bank1_SRAM2 */
bogdanm 0:9b334a45a8ff 535 FSMC_Bank1->BTCR[2] = 0x00001011;
bogdanm 0:9b334a45a8ff 536 FSMC_Bank1->BTCR[3] = 0x00000201;
bogdanm 0:9b334a45a8ff 537 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
bogdanm 0:9b334a45a8ff 538 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 #endif /* DATA_IN_ExtSRAM */
bogdanm 0:9b334a45a8ff 541 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 0:9b334a45a8ff 542 }
bogdanm 0:9b334a45a8ff 543 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /** System Clock Configuration
bogdanm 0:9b334a45a8ff 546 */
bogdanm 0:9b334a45a8ff 547 #if USE_SYSCLOCK_168 != 0
bogdanm 0:9b334a45a8ff 548 /*
bogdanm 0:9b334a45a8ff 549 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
bogdanm 0:9b334a45a8ff 550 * and SYSCLK=168MHZ
bogdanm 0:9b334a45a8ff 551 */
bogdanm 0:9b334a45a8ff 552 void SystemClock_Config(void)
bogdanm 0:9b334a45a8ff 553 {
bogdanm 0:9b334a45a8ff 554
bogdanm 0:9b334a45a8ff 555 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 556 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 557
bogdanm 0:9b334a45a8ff 558 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 563 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 564 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 565 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 566 RCC_OscInitStruct.PLL.PLLM = 8;
bogdanm 0:9b334a45a8ff 567 RCC_OscInitStruct.PLL.PLLN = 336;
bogdanm 0:9b334a45a8ff 568 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
bogdanm 0:9b334a45a8ff 569 RCC_OscInitStruct.PLL.PLLQ = 7;
bogdanm 0:9b334a45a8ff 570 HAL_RCC_OscConfig(&RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
bogdanm 0:9b334a45a8ff 573 |RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 574 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
bogdanm 0:9b334a45a8ff 575 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
bogdanm 0:9b334a45a8ff 576 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
bogdanm 0:9b334a45a8ff 577 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
bogdanm 0:9b334a45a8ff 578 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
bogdanm 0:9b334a45a8ff 579
bogdanm 0:9b334a45a8ff 580 }
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 #elif USE_SYSCLOCK_180 != 0
bogdanm 0:9b334a45a8ff 583 /*
bogdanm 0:9b334a45a8ff 584 * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery
bogdanm 0:9b334a45a8ff 585 * and SYSCLK=180MHZ
bogdanm 0:9b334a45a8ff 586 */
bogdanm 0:9b334a45a8ff 587 void SystemClock_Config(void)
bogdanm 0:9b334a45a8ff 588 {
bogdanm 0:9b334a45a8ff 589
bogdanm 0:9b334a45a8ff 590 RCC_OscInitTypeDef RCC_OscInitStruct;
bogdanm 0:9b334a45a8ff 591 RCC_ClkInitTypeDef RCC_ClkInitStruct;
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
bogdanm 0:9b334a45a8ff 596
bogdanm 0:9b334a45a8ff 597 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
bogdanm 0:9b334a45a8ff 598 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 599 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 600 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
bogdanm 0:9b334a45a8ff 601 RCC_OscInitStruct.PLL.PLLM = 8;
bogdanm 0:9b334a45a8ff 602 RCC_OscInitStruct.PLL.PLLN = 360;
bogdanm 0:9b334a45a8ff 603 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
bogdanm 0:9b334a45a8ff 604 RCC_OscInitStruct.PLL.PLLQ = 7;
bogdanm 0:9b334a45a8ff 605 HAL_RCC_OscConfig(&RCC_OscInitStruct);
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 HAL_PWREx_ActivateOverDrive();
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1
bogdanm 0:9b334a45a8ff 610 |RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 611 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
bogdanm 0:9b334a45a8ff 612 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
bogdanm 0:9b334a45a8ff 613 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
bogdanm 0:9b334a45a8ff 614 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
bogdanm 0:9b334a45a8ff 615 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5);
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 }
bogdanm 0:9b334a45a8ff 618 #endif
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /**
bogdanm 0:9b334a45a8ff 621 * @}
bogdanm 0:9b334a45a8ff 622 */
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 /**
bogdanm 0:9b334a45a8ff 625 * @}
bogdanm 0:9b334a45a8ff 626 */
bogdanm 0:9b334a45a8ff 627
bogdanm 0:9b334a45a8ff 628 /**
bogdanm 0:9b334a45a8ff 629 * @}
bogdanm 0:9b334a45a8ff 630 */
bogdanm 0:9b334a45a8ff 631 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/