Amit Gandhi
/
sensen_copy_2
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
mbed-dev
by 
mbed official
targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/system_stm32f0xx.c@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/system_stm32f0xx.c@144:ef7eb2e8f9f7
- Child:
- 156:95d6b41a828b
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 5:ac9f6c2c45e8 | 1 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 2 | ****************************************************************************** |
| mbed_official | 5:ac9f6c2c45e8 | 3 | * @file system_stm32f0xx.c |
| mbed_official | 5:ac9f6c2c45e8 | 4 | * @author MCD Application Team |
| <> | 144:ef7eb2e8f9f7 | 5 | * @version V2.3.0 |
| <> | 144:ef7eb2e8f9f7 | 6 | * @date 27-May-2016 |
| mbed_official | 5:ac9f6c2c45e8 | 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. |
| mbed_official | 5:ac9f6c2c45e8 | 8 | * |
| mbed_official | 5:ac9f6c2c45e8 | 9 | * 1. This file provides two functions and one global variable to be called from |
| mbed_official | 5:ac9f6c2c45e8 | 10 | * user application: |
| mbed_official | 5:ac9f6c2c45e8 | 11 | * - SystemInit(): This function is called at startup just after reset and |
| mbed_official | 5:ac9f6c2c45e8 | 12 | * before branch to main program. This call is made inside |
| mbed_official | 5:ac9f6c2c45e8 | 13 | * the "startup_stm32f0xx.s" file. |
| mbed_official | 5:ac9f6c2c45e8 | 14 | * |
| mbed_official | 5:ac9f6c2c45e8 | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 5:ac9f6c2c45e8 | 16 | * by the user application to setup the SysTick |
| mbed_official | 5:ac9f6c2c45e8 | 17 | * timer or configure other parameters. |
| mbed_official | 5:ac9f6c2c45e8 | 18 | * |
| mbed_official | 5:ac9f6c2c45e8 | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 5:ac9f6c2c45e8 | 20 | * be called whenever the core clock is changed |
| mbed_official | 5:ac9f6c2c45e8 | 21 | * during program execution. |
| mbed_official | 5:ac9f6c2c45e8 | 22 | * |
| mbed_official | 5:ac9f6c2c45e8 | 23 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. |
| mbed_official | 5:ac9f6c2c45e8 | 24 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to |
| mbed_official | 5:ac9f6c2c45e8 | 25 | * configure the system clock before to branch to main program. |
| mbed_official | 5:ac9f6c2c45e8 | 26 | * |
| mbed_official | 5:ac9f6c2c45e8 | 27 | * 3. This file configures the system clock as follows: |
| mbed_official | 5:ac9f6c2c45e8 | 28 | *============================================================================= |
| mbed_official | 5:ac9f6c2c45e8 | 29 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 5:ac9f6c2c45e8 | 30 | * | (external 8 MHz clock) | (internal 48 MHz) |
| mbed_official | 5:ac9f6c2c45e8 | 31 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 5:ac9f6c2c45e8 | 32 | * | (external 8 MHz xtal) | |
| mbed_official | 5:ac9f6c2c45e8 | 33 | *----------------------------------------------------------------------------- |
| mbed_official | 5:ac9f6c2c45e8 | 34 | * SYSCLK(MHz) | 48 | 48 |
| mbed_official | 5:ac9f6c2c45e8 | 35 | *----------------------------------------------------------------------------- |
| mbed_official | 5:ac9f6c2c45e8 | 36 | * AHBCLK (MHz) | 48 | 48 |
| mbed_official | 5:ac9f6c2c45e8 | 37 | *----------------------------------------------------------------------------- |
| mbed_official | 5:ac9f6c2c45e8 | 38 | * APB1CLK (MHz) | 48 | 48 |
| mbed_official | 5:ac9f6c2c45e8 | 39 | *----------------------------------------------------------------------------- |
| mbed_official | 5:ac9f6c2c45e8 | 40 | * USB capable (48 MHz precise clock) | YES | YES |
| mbed_official | 5:ac9f6c2c45e8 | 41 | *============================================================================= |
| mbed_official | 5:ac9f6c2c45e8 | 42 | ****************************************************************************** |
| mbed_official | 5:ac9f6c2c45e8 | 43 | * @attention |
| mbed_official | 5:ac9f6c2c45e8 | 44 | * |
| <> | 144:ef7eb2e8f9f7 | 45 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| mbed_official | 5:ac9f6c2c45e8 | 46 | * |
| mbed_official | 5:ac9f6c2c45e8 | 47 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 5:ac9f6c2c45e8 | 48 | * are permitted provided that the following conditions are met: |
| mbed_official | 5:ac9f6c2c45e8 | 49 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 5:ac9f6c2c45e8 | 50 | * this list of conditions and the following disclaimer. |
| mbed_official | 5:ac9f6c2c45e8 | 51 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 5:ac9f6c2c45e8 | 52 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 5:ac9f6c2c45e8 | 53 | * and/or other materials provided with the distribution. |
| mbed_official | 5:ac9f6c2c45e8 | 54 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 5:ac9f6c2c45e8 | 55 | * may be used to endorse or promote products derived from this software |
| mbed_official | 5:ac9f6c2c45e8 | 56 | * without specific prior written permission. |
| mbed_official | 5:ac9f6c2c45e8 | 57 | * |
| mbed_official | 5:ac9f6c2c45e8 | 58 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 5:ac9f6c2c45e8 | 59 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 5:ac9f6c2c45e8 | 60 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 5:ac9f6c2c45e8 | 61 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 5:ac9f6c2c45e8 | 62 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 5:ac9f6c2c45e8 | 63 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 5:ac9f6c2c45e8 | 64 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 5:ac9f6c2c45e8 | 65 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 5:ac9f6c2c45e8 | 66 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 5:ac9f6c2c45e8 | 67 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 5:ac9f6c2c45e8 | 68 | * |
| mbed_official | 5:ac9f6c2c45e8 | 69 | ****************************************************************************** |
| mbed_official | 5:ac9f6c2c45e8 | 70 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 71 | |
| mbed_official | 5:ac9f6c2c45e8 | 72 | /** @addtogroup CMSIS |
| mbed_official | 5:ac9f6c2c45e8 | 73 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 74 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 75 | |
| mbed_official | 5:ac9f6c2c45e8 | 76 | /** @addtogroup stm32f0xx_system |
| mbed_official | 5:ac9f6c2c45e8 | 77 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 78 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 79 | |
| mbed_official | 5:ac9f6c2c45e8 | 80 | /** @addtogroup STM32F0xx_System_Private_Includes |
| mbed_official | 5:ac9f6c2c45e8 | 81 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 82 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 83 | |
| mbed_official | 5:ac9f6c2c45e8 | 84 | #include "stm32f0xx.h" |
| mbed_official | 43:e3d4af315dd8 | 85 | #include "hal_tick.h" |
| mbed_official | 5:ac9f6c2c45e8 | 86 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 87 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 88 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 89 | |
| mbed_official | 5:ac9f6c2c45e8 | 90 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions |
| mbed_official | 5:ac9f6c2c45e8 | 91 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 92 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 93 | |
| mbed_official | 5:ac9f6c2c45e8 | 94 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 95 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 96 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 97 | |
| mbed_official | 5:ac9f6c2c45e8 | 98 | /** @addtogroup STM32F0xx_System_Private_Defines |
| mbed_official | 5:ac9f6c2c45e8 | 99 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 100 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 101 | #if !defined (HSE_VALUE) |
| mbed_official | 5:ac9f6c2c45e8 | 102 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
| mbed_official | 5:ac9f6c2c45e8 | 103 | This value can be provided and adapted by the user application. */ |
| mbed_official | 5:ac9f6c2c45e8 | 104 | #endif /* HSE_VALUE */ |
| mbed_official | 5:ac9f6c2c45e8 | 105 | |
| mbed_official | 5:ac9f6c2c45e8 | 106 | #if !defined (HSI_VALUE) |
| mbed_official | 5:ac9f6c2c45e8 | 107 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. |
| mbed_official | 5:ac9f6c2c45e8 | 108 | This value can be provided and adapted by the user application. */ |
| mbed_official | 5:ac9f6c2c45e8 | 109 | #endif /* HSI_VALUE */ |
| mbed_official | 5:ac9f6c2c45e8 | 110 | |
| <> | 144:ef7eb2e8f9f7 | 111 | #if !defined (HSI48_VALUE) |
| <> | 144:ef7eb2e8f9f7 | 112 | #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. |
| <> | 144:ef7eb2e8f9f7 | 113 | This value can be provided and adapted by the user application. */ |
| <> | 144:ef7eb2e8f9f7 | 114 | #endif /* HSI48_VALUE */ |
| mbed_official | 5:ac9f6c2c45e8 | 115 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 116 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 117 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 118 | |
| mbed_official | 5:ac9f6c2c45e8 | 119 | /** @addtogroup STM32F0xx_System_Private_Macros |
| mbed_official | 5:ac9f6c2c45e8 | 120 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 121 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 122 | |
| mbed_official | 5:ac9f6c2c45e8 | 123 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 34:bb6061527455 | 124 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
| mbed_official | 9:673ec039aeb3 | 125 | #define USE_PLL_HSE_XTAL (0) /* Use external xtal */ |
| mbed_official | 5:ac9f6c2c45e8 | 126 | |
| mbed_official | 5:ac9f6c2c45e8 | 127 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 128 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 129 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 130 | |
| mbed_official | 5:ac9f6c2c45e8 | 131 | /** @addtogroup STM32F0xx_System_Private_Variables |
| mbed_official | 5:ac9f6c2c45e8 | 132 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 133 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 134 | /* This variable is updated in three ways: |
| mbed_official | 5:ac9f6c2c45e8 | 135 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| mbed_official | 5:ac9f6c2c45e8 | 136 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| mbed_official | 5:ac9f6c2c45e8 | 137 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| mbed_official | 5:ac9f6c2c45e8 | 138 | Note: If you use this function to configure the system clock there is no need to |
| mbed_official | 5:ac9f6c2c45e8 | 139 | call the 2 first functions listed above, since SystemCoreClock variable is |
| mbed_official | 5:ac9f6c2c45e8 | 140 | updated automatically. |
| mbed_official | 5:ac9f6c2c45e8 | 141 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 142 | uint32_t SystemCoreClock = 48000000; |
| mbed_official | 5:ac9f6c2c45e8 | 143 | |
| mbed_official | 5:ac9f6c2c45e8 | 144 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| <> | 144:ef7eb2e8f9f7 | 145 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
| mbed_official | 5:ac9f6c2c45e8 | 146 | |
| mbed_official | 5:ac9f6c2c45e8 | 147 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 148 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 149 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 150 | |
| mbed_official | 5:ac9f6c2c45e8 | 151 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes |
| mbed_official | 5:ac9f6c2c45e8 | 152 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 153 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 154 | |
| mbed_official | 5:ac9f6c2c45e8 | 155 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 5:ac9f6c2c45e8 | 156 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 5:ac9f6c2c45e8 | 157 | #endif |
| mbed_official | 5:ac9f6c2c45e8 | 158 | |
| mbed_official | 5:ac9f6c2c45e8 | 159 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 5:ac9f6c2c45e8 | 160 | |
| mbed_official | 5:ac9f6c2c45e8 | 161 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 162 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 163 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 164 | |
| mbed_official | 5:ac9f6c2c45e8 | 165 | /** @addtogroup STM32F0xx_System_Private_Functions |
| mbed_official | 5:ac9f6c2c45e8 | 166 | * @{ |
| mbed_official | 5:ac9f6c2c45e8 | 167 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 168 | |
| mbed_official | 43:e3d4af315dd8 | 169 | |
| mbed_official | 5:ac9f6c2c45e8 | 170 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 171 | * @brief Setup the microcontroller system. |
| mbed_official | 5:ac9f6c2c45e8 | 172 | * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. |
| mbed_official | 5:ac9f6c2c45e8 | 173 | * @param None |
| mbed_official | 5:ac9f6c2c45e8 | 174 | * @retval None |
| mbed_official | 5:ac9f6c2c45e8 | 175 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 176 | void SystemInit(void) |
| mbed_official | 5:ac9f6c2c45e8 | 177 | { |
| mbed_official | 5:ac9f6c2c45e8 | 178 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| mbed_official | 5:ac9f6c2c45e8 | 179 | /* Set HSION bit */ |
| <> | 144:ef7eb2e8f9f7 | 180 | RCC->CR |= (uint32_t)0x00000001U; |
| mbed_official | 5:ac9f6c2c45e8 | 181 | |
| mbed_official | 5:ac9f6c2c45e8 | 182 | #if defined (STM32F051x8) || defined (STM32F058x8) |
| mbed_official | 5:ac9f6c2c45e8 | 183 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ |
| <> | 144:ef7eb2e8f9f7 | 184 | RCC->CFGR &= (uint32_t)0xF8FFB80CU; |
| mbed_official | 5:ac9f6c2c45e8 | 185 | #else |
| mbed_official | 5:ac9f6c2c45e8 | 186 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ |
| <> | 144:ef7eb2e8f9f7 | 187 | RCC->CFGR &= (uint32_t)0x08FFB80CU; |
| mbed_official | 5:ac9f6c2c45e8 | 188 | #endif /* STM32F051x8 or STM32F058x8 */ |
| mbed_official | 5:ac9f6c2c45e8 | 189 | |
| mbed_official | 5:ac9f6c2c45e8 | 190 | /* Reset HSEON, CSSON and PLLON bits */ |
| <> | 144:ef7eb2e8f9f7 | 191 | RCC->CR &= (uint32_t)0xFEF6FFFFU; |
| mbed_official | 5:ac9f6c2c45e8 | 192 | |
| mbed_official | 5:ac9f6c2c45e8 | 193 | /* Reset HSEBYP bit */ |
| <> | 144:ef7eb2e8f9f7 | 194 | RCC->CR &= (uint32_t)0xFFFBFFFFU; |
| mbed_official | 5:ac9f6c2c45e8 | 195 | |
| mbed_official | 5:ac9f6c2c45e8 | 196 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ |
| <> | 144:ef7eb2e8f9f7 | 197 | RCC->CFGR &= (uint32_t)0xFFC0FFFFU; |
| mbed_official | 5:ac9f6c2c45e8 | 198 | |
| mbed_official | 5:ac9f6c2c45e8 | 199 | /* Reset PREDIV[3:0] bits */ |
| <> | 144:ef7eb2e8f9f7 | 200 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; |
| mbed_official | 5:ac9f6c2c45e8 | 201 | |
| mbed_official | 5:ac9f6c2c45e8 | 202 | #if defined (STM32F072xB) || defined (STM32F078xx) |
| mbed_official | 5:ac9f6c2c45e8 | 203 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 204 | RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; |
| mbed_official | 5:ac9f6c2c45e8 | 205 | #elif defined (STM32F071xB) |
| mbed_official | 5:ac9f6c2c45e8 | 206 | /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 207 | RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; |
| mbed_official | 5:ac9f6c2c45e8 | 208 | #elif defined (STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 5:ac9f6c2c45e8 | 209 | /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 210 | RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; |
| mbed_official | 5:ac9f6c2c45e8 | 211 | #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) |
| mbed_official | 5:ac9f6c2c45e8 | 212 | /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 213 | RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; |
| mbed_official | 5:ac9f6c2c45e8 | 214 | #elif defined (STM32F051x8) || defined (STM32F058xx) |
| mbed_official | 5:ac9f6c2c45e8 | 215 | /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 216 | RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; |
| mbed_official | 5:ac9f6c2c45e8 | 217 | #elif defined (STM32F042x6) || defined (STM32F048xx) |
| mbed_official | 5:ac9f6c2c45e8 | 218 | /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 219 | RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; |
| mbed_official | 5:ac9f6c2c45e8 | 220 | #elif defined (STM32F070x6) || defined (STM32F070xB) |
| mbed_official | 5:ac9f6c2c45e8 | 221 | /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ |
| <> | 144:ef7eb2e8f9f7 | 222 | RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; |
| mbed_official | 5:ac9f6c2c45e8 | 223 | /* Set default USB clock to PLLCLK, since there is no HSI48 */ |
| <> | 144:ef7eb2e8f9f7 | 224 | RCC->CFGR3 |= (uint32_t)0x00000080U; |
| mbed_official | 5:ac9f6c2c45e8 | 225 | #else |
| mbed_official | 5:ac9f6c2c45e8 | 226 | #warning "No target selected" |
| mbed_official | 5:ac9f6c2c45e8 | 227 | #endif |
| mbed_official | 5:ac9f6c2c45e8 | 228 | |
| mbed_official | 5:ac9f6c2c45e8 | 229 | /* Reset HSI14 bit */ |
| <> | 144:ef7eb2e8f9f7 | 230 | RCC->CR2 &= (uint32_t)0xFFFFFFFEU; |
| mbed_official | 5:ac9f6c2c45e8 | 231 | |
| mbed_official | 5:ac9f6c2c45e8 | 232 | /* Disable all interrupts */ |
| <> | 144:ef7eb2e8f9f7 | 233 | RCC->CIR = 0x00000000U; |
| mbed_official | 43:e3d4af315dd8 | 234 | |
| mbed_official | 46:cb4f85f96d35 | 235 | /* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */ |
| mbed_official | 46:cb4f85f96d35 | 236 | RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; |
| mbed_official | 46:cb4f85f96d35 | 237 | |
| mbed_official | 43:e3d4af315dd8 | 238 | /* Configure the Cube driver */ |
| mbed_official | 43:e3d4af315dd8 | 239 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
| mbed_official | 43:e3d4af315dd8 | 240 | HAL_Init(); |
| mbed_official | 43:e3d4af315dd8 | 241 | |
| mbed_official | 43:e3d4af315dd8 | 242 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 43:e3d4af315dd8 | 243 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 43:e3d4af315dd8 | 244 | SetSysClock(); |
| mbed_official | 43:e3d4af315dd8 | 245 | |
| mbed_official | 43:e3d4af315dd8 | 246 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 43:e3d4af315dd8 | 247 | TIM_MST_RESET_ON; |
| mbed_official | 43:e3d4af315dd8 | 248 | TIM_MST_RESET_OFF; |
| mbed_official | 5:ac9f6c2c45e8 | 249 | } |
| mbed_official | 5:ac9f6c2c45e8 | 250 | |
| mbed_official | 5:ac9f6c2c45e8 | 251 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 252 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 5:ac9f6c2c45e8 | 253 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 5:ac9f6c2c45e8 | 254 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 5:ac9f6c2c45e8 | 255 | * other parameters. |
| mbed_official | 5:ac9f6c2c45e8 | 256 | * |
| mbed_official | 5:ac9f6c2c45e8 | 257 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 5:ac9f6c2c45e8 | 258 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 5:ac9f6c2c45e8 | 259 | * based on this variable will be incorrect. |
| mbed_official | 5:ac9f6c2c45e8 | 260 | * |
| mbed_official | 5:ac9f6c2c45e8 | 261 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 5:ac9f6c2c45e8 | 262 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 5:ac9f6c2c45e8 | 263 | * constant and the selected clock source: |
| mbed_official | 5:ac9f6c2c45e8 | 264 | * |
| mbed_official | 5:ac9f6c2c45e8 | 265 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 5:ac9f6c2c45e8 | 266 | * |
| mbed_official | 5:ac9f6c2c45e8 | 267 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 5:ac9f6c2c45e8 | 268 | * |
| mbed_official | 5:ac9f6c2c45e8 | 269 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 5:ac9f6c2c45e8 | 270 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| mbed_official | 5:ac9f6c2c45e8 | 271 | * |
| mbed_official | 5:ac9f6c2c45e8 | 272 | * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
| mbed_official | 5:ac9f6c2c45e8 | 273 | * 8 MHz) but the real value may vary depending on the variations |
| mbed_official | 5:ac9f6c2c45e8 | 274 | * in voltage and temperature. |
| mbed_official | 5:ac9f6c2c45e8 | 275 | * |
| mbed_official | 5:ac9f6c2c45e8 | 276 | * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value |
| mbed_official | 5:ac9f6c2c45e8 | 277 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
| mbed_official | 5:ac9f6c2c45e8 | 278 | * frequency of the crystal used. Otherwise, this function may |
| mbed_official | 5:ac9f6c2c45e8 | 279 | * have wrong result. |
| mbed_official | 5:ac9f6c2c45e8 | 280 | * |
| mbed_official | 5:ac9f6c2c45e8 | 281 | * - The result of this function could be not correct when using fractional |
| mbed_official | 5:ac9f6c2c45e8 | 282 | * value for HSE crystal. |
| mbed_official | 5:ac9f6c2c45e8 | 283 | * |
| mbed_official | 5:ac9f6c2c45e8 | 284 | * @param None |
| mbed_official | 5:ac9f6c2c45e8 | 285 | * @retval None |
| mbed_official | 5:ac9f6c2c45e8 | 286 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 287 | void SystemCoreClockUpdate (void) |
| mbed_official | 5:ac9f6c2c45e8 | 288 | { |
| mbed_official | 5:ac9f6c2c45e8 | 289 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; |
| mbed_official | 5:ac9f6c2c45e8 | 290 | |
| mbed_official | 5:ac9f6c2c45e8 | 291 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 5:ac9f6c2c45e8 | 292 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 5:ac9f6c2c45e8 | 293 | |
| mbed_official | 5:ac9f6c2c45e8 | 294 | switch (tmp) |
| mbed_official | 5:ac9f6c2c45e8 | 295 | { |
| mbed_official | 5:ac9f6c2c45e8 | 296 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 297 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 5:ac9f6c2c45e8 | 298 | break; |
| mbed_official | 5:ac9f6c2c45e8 | 299 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 300 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 5:ac9f6c2c45e8 | 301 | break; |
| mbed_official | 5:ac9f6c2c45e8 | 302 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 303 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| mbed_official | 5:ac9f6c2c45e8 | 304 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; |
| mbed_official | 5:ac9f6c2c45e8 | 305 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| mbed_official | 5:ac9f6c2c45e8 | 306 | pllmull = ( pllmull >> 18) + 2; |
| mbed_official | 5:ac9f6c2c45e8 | 307 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; |
| mbed_official | 5:ac9f6c2c45e8 | 308 | |
| mbed_official | 5:ac9f6c2c45e8 | 309 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) |
| mbed_official | 5:ac9f6c2c45e8 | 310 | { |
| mbed_official | 5:ac9f6c2c45e8 | 311 | /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ |
| mbed_official | 5:ac9f6c2c45e8 | 312 | SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; |
| mbed_official | 5:ac9f6c2c45e8 | 313 | } |
| mbed_official | 5:ac9f6c2c45e8 | 314 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 5:ac9f6c2c45e8 | 315 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) |
| mbed_official | 5:ac9f6c2c45e8 | 316 | { |
| mbed_official | 5:ac9f6c2c45e8 | 317 | /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ |
| mbed_official | 5:ac9f6c2c45e8 | 318 | SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; |
| mbed_official | 5:ac9f6c2c45e8 | 319 | } |
| mbed_official | 5:ac9f6c2c45e8 | 320 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ |
| mbed_official | 5:ac9f6c2c45e8 | 321 | else |
| mbed_official | 5:ac9f6c2c45e8 | 322 | { |
| mbed_official | 5:ac9f6c2c45e8 | 323 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ |
| mbed_official | 5:ac9f6c2c45e8 | 324 | || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ |
| mbed_official | 5:ac9f6c2c45e8 | 325 | || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) |
| mbed_official | 5:ac9f6c2c45e8 | 326 | /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ |
| mbed_official | 5:ac9f6c2c45e8 | 327 | SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; |
| mbed_official | 5:ac9f6c2c45e8 | 328 | #else |
| mbed_official | 5:ac9f6c2c45e8 | 329 | /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ |
| mbed_official | 5:ac9f6c2c45e8 | 330 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; |
| mbed_official | 5:ac9f6c2c45e8 | 331 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || |
| mbed_official | 5:ac9f6c2c45e8 | 332 | STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || |
| mbed_official | 5:ac9f6c2c45e8 | 333 | STM32F091xC || STM32F098xx || STM32F030xC */ |
| mbed_official | 5:ac9f6c2c45e8 | 334 | } |
| mbed_official | 5:ac9f6c2c45e8 | 335 | break; |
| mbed_official | 5:ac9f6c2c45e8 | 336 | default: /* HSI used as system clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 337 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 5:ac9f6c2c45e8 | 338 | break; |
| mbed_official | 5:ac9f6c2c45e8 | 339 | } |
| mbed_official | 5:ac9f6c2c45e8 | 340 | /* Compute HCLK clock frequency ----------------*/ |
| mbed_official | 5:ac9f6c2c45e8 | 341 | /* Get HCLK prescaler */ |
| mbed_official | 5:ac9f6c2c45e8 | 342 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 5:ac9f6c2c45e8 | 343 | /* HCLK clock frequency */ |
| mbed_official | 5:ac9f6c2c45e8 | 344 | SystemCoreClock >>= tmp; |
| mbed_official | 5:ac9f6c2c45e8 | 345 | } |
| mbed_official | 5:ac9f6c2c45e8 | 346 | |
| mbed_official | 5:ac9f6c2c45e8 | 347 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 348 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 5:ac9f6c2c45e8 | 349 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 5:ac9f6c2c45e8 | 350 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 5:ac9f6c2c45e8 | 351 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 5:ac9f6c2c45e8 | 352 | * @param None |
| mbed_official | 5:ac9f6c2c45e8 | 353 | * @retval None |
| mbed_official | 5:ac9f6c2c45e8 | 354 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 355 | void SetSysClock(void) |
| mbed_official | 5:ac9f6c2c45e8 | 356 | { |
| mbed_official | 5:ac9f6c2c45e8 | 357 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 358 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 5:ac9f6c2c45e8 | 359 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 5:ac9f6c2c45e8 | 360 | #endif |
| mbed_official | 5:ac9f6c2c45e8 | 361 | { |
| mbed_official | 5:ac9f6c2c45e8 | 362 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 5:ac9f6c2c45e8 | 363 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 5:ac9f6c2c45e8 | 364 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 5:ac9f6c2c45e8 | 365 | #endif |
| mbed_official | 5:ac9f6c2c45e8 | 366 | { |
| mbed_official | 5:ac9f6c2c45e8 | 367 | /* 3- If fail start with HSI clock */ |
| mbed_official | 5:ac9f6c2c45e8 | 368 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 5:ac9f6c2c45e8 | 369 | { |
| mbed_official | 5:ac9f6c2c45e8 | 370 | while(1) |
| mbed_official | 5:ac9f6c2c45e8 | 371 | { |
| mbed_official | 5:ac9f6c2c45e8 | 372 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 5:ac9f6c2c45e8 | 373 | } |
| mbed_official | 5:ac9f6c2c45e8 | 374 | } |
| mbed_official | 5:ac9f6c2c45e8 | 375 | } |
| mbed_official | 5:ac9f6c2c45e8 | 376 | } |
| mbed_official | 5:ac9f6c2c45e8 | 377 | |
| mbed_official | 5:ac9f6c2c45e8 | 378 | // Output clock on MCO pin(PA8) for debugging purpose |
| mbed_official | 5:ac9f6c2c45e8 | 379 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 380 | } |
| mbed_official | 5:ac9f6c2c45e8 | 381 | |
| mbed_official | 5:ac9f6c2c45e8 | 382 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 5:ac9f6c2c45e8 | 383 | /******************************************************************************/ |
| mbed_official | 5:ac9f6c2c45e8 | 384 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 5:ac9f6c2c45e8 | 385 | /******************************************************************************/ |
| mbed_official | 5:ac9f6c2c45e8 | 386 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 5:ac9f6c2c45e8 | 387 | { |
| mbed_official | 5:ac9f6c2c45e8 | 388 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
| mbed_official | 5:ac9f6c2c45e8 | 389 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
| mbed_official | 5:ac9f6c2c45e8 | 390 | //Select HSI as system clock source to allow modification of the PLL configuration |
| mbed_official | 5:ac9f6c2c45e8 | 391 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
| mbed_official | 5:ac9f6c2c45e8 | 392 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; |
| mbed_official | 5:ac9f6c2c45e8 | 393 | if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
| mbed_official | 5:ac9f6c2c45e8 | 394 | { |
| mbed_official | 5:ac9f6c2c45e8 | 395 | return 0; // FAIL |
| mbed_official | 5:ac9f6c2c45e8 | 396 | } |
| mbed_official | 5:ac9f6c2c45e8 | 397 | |
| mbed_official | 5:ac9f6c2c45e8 | 398 | |
| mbed_official | 5:ac9f6c2c45e8 | 399 | // Select HSE oscillator as PLL source |
| mbed_official | 5:ac9f6c2c45e8 | 400 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 5:ac9f6c2c45e8 | 401 | if (bypass == 0) { |
| mbed_official | 5:ac9f6c2c45e8 | 402 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
| mbed_official | 5:ac9f6c2c45e8 | 403 | } else { |
| mbed_official | 5:ac9f6c2c45e8 | 404 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only |
| mbed_official | 5:ac9f6c2c45e8 | 405 | } |
| mbed_official | 5:ac9f6c2c45e8 | 406 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 5:ac9f6c2c45e8 | 407 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 5:ac9f6c2c45e8 | 408 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2; |
| mbed_official | 5:ac9f6c2c45e8 | 409 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; |
| mbed_official | 5:ac9f6c2c45e8 | 410 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| mbed_official | 5:ac9f6c2c45e8 | 411 | return 0; // FAIL |
| mbed_official | 5:ac9f6c2c45e8 | 412 | } |
| mbed_official | 5:ac9f6c2c45e8 | 413 | |
| mbed_official | 5:ac9f6c2c45e8 | 414 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
| mbed_official | 5:ac9f6c2c45e8 | 415 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
| mbed_official | 5:ac9f6c2c45e8 | 416 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 417 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 418 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 419 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
| mbed_official | 5:ac9f6c2c45e8 | 420 | return 0; // FAIL |
| mbed_official | 5:ac9f6c2c45e8 | 421 | } |
| mbed_official | 5:ac9f6c2c45e8 | 422 | |
| mbed_official | 5:ac9f6c2c45e8 | 423 | // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 424 | |
| mbed_official | 5:ac9f6c2c45e8 | 425 | return 1; // OK |
| mbed_official | 5:ac9f6c2c45e8 | 426 | } |
| mbed_official | 5:ac9f6c2c45e8 | 427 | #endif |
| mbed_official | 5:ac9f6c2c45e8 | 428 | |
| mbed_official | 5:ac9f6c2c45e8 | 429 | /******************************************************************************/ |
| mbed_official | 5:ac9f6c2c45e8 | 430 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 5:ac9f6c2c45e8 | 431 | /******************************************************************************/ |
| mbed_official | 5:ac9f6c2c45e8 | 432 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 5:ac9f6c2c45e8 | 433 | { |
| mbed_official | 5:ac9f6c2c45e8 | 434 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 5:ac9f6c2c45e8 | 435 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 5:ac9f6c2c45e8 | 436 | |
| mbed_official | 56:05912f50f004 | 437 | // Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12) |
| mbed_official | 56:05912f50f004 | 438 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; |
| mbed_official | 56:05912f50f004 | 439 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| mbed_official | 56:05912f50f004 | 440 | RCC_OscInitStruct.LSEState = RCC_LSE_OFF; |
| mbed_official | 56:05912f50f004 | 441 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 56:05912f50f004 | 442 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
| mbed_official | 56:05912f50f004 | 443 | RCC_OscInitStruct.HSI14State = RCC_HSI_OFF; |
| mbed_official | 56:05912f50f004 | 444 | RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT; |
| mbed_official | 56:05912f50f004 | 445 | RCC_OscInitStruct.HSI48State = RCC_HSI_ON; |
| mbed_official | 56:05912f50f004 | 446 | RCC_OscInitStruct.LSIState = RCC_LSI_OFF; |
| mbed_official | 56:05912f50f004 | 447 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 56:05912f50f004 | 448 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2 |
| mbed_official | 56:05912f50f004 | 449 | RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; |
| mbed_official | 56:05912f50f004 | 450 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; |
| mbed_official | 5:ac9f6c2c45e8 | 451 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| mbed_official | 5:ac9f6c2c45e8 | 452 | return 0; // FAIL |
| mbed_official | 5:ac9f6c2c45e8 | 453 | } |
| mbed_official | 5:ac9f6c2c45e8 | 454 | |
| mbed_official | 5:ac9f6c2c45e8 | 455 | // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers |
| mbed_official | 5:ac9f6c2c45e8 | 456 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1); |
| mbed_official | 5:ac9f6c2c45e8 | 457 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 458 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 459 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 460 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { |
| mbed_official | 5:ac9f6c2c45e8 | 461 | return 0; // FAIL |
| mbed_official | 5:ac9f6c2c45e8 | 462 | } |
| mbed_official | 5:ac9f6c2c45e8 | 463 | |
| mbed_official | 5:ac9f6c2c45e8 | 464 | //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz |
| mbed_official | 5:ac9f6c2c45e8 | 465 | |
| mbed_official | 5:ac9f6c2c45e8 | 466 | return 1; // OK |
| mbed_official | 5:ac9f6c2c45e8 | 467 | } |
| mbed_official | 5:ac9f6c2c45e8 | 468 | |
| mbed_official | 5:ac9f6c2c45e8 | 469 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 470 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 471 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 472 | |
| mbed_official | 5:ac9f6c2c45e8 | 473 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 474 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 475 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 476 | |
| mbed_official | 5:ac9f6c2c45e8 | 477 | /** |
| mbed_official | 5:ac9f6c2c45e8 | 478 | * @} |
| mbed_official | 5:ac9f6c2c45e8 | 479 | */ |
| mbed_official | 5:ac9f6c2c45e8 | 480 | |
| mbed_official | 5:ac9f6c2c45e8 | 481 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| mbed_official | 5:ac9f6c2c45e8 | 482 |