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targets/TARGET_Maxim/TARGET_MAX32625/device/spix_regs.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

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<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_SPIX_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_SPIX_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /*
<> 150:02e0a0aed4ec 58 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 59 access to each register in module.
<> 150:02e0a0aed4ec 60 */
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /* Offset Register Description
<> 150:02e0a0aed4ec 63 ============= ============================================================================ */
<> 150:02e0a0aed4ec 64 typedef struct {
<> 150:02e0a0aed4ec 65 __IO uint32_t master_cfg; /* 0x0000 SPIX Master Configuration */
<> 150:02e0a0aed4ec 66 __IO uint32_t fetch_ctrl; /* 0x0004 SPIX Fetch Control */
<> 150:02e0a0aed4ec 67 __IO uint32_t mode_ctrl; /* 0x0008 SPIX Mode Control */
<> 150:02e0a0aed4ec 68 __IO uint32_t mode_data; /* 0x000C SPIX Mode Data */
<> 150:02e0a0aed4ec 69 __IO uint32_t sck_fb_ctrl; /* 0x0010 SPIX SCK_FB Control Register */
<> 150:02e0a0aed4ec 70 } mxc_spix_regs_t;
<> 150:02e0a0aed4ec 71
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73 /*
<> 150:02e0a0aed4ec 74 Register offsets for module SPIX.
<> 150:02e0a0aed4ec 75 */
<> 150:02e0a0aed4ec 76
<> 150:02e0a0aed4ec 77 #define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 78 #define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 79 #define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 80 #define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 81 #define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 82
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84 /*
<> 150:02e0a0aed4ec 85 Field positions and masks for module SPIX.
<> 150:02e0a0aed4ec 86 */
<> 150:02e0a0aed4ec 87
<> 150:02e0a0aed4ec 88 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0
<> 150:02e0a0aed4ec 89 #define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 150:02e0a0aed4ec 90 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2
<> 150:02e0a0aed4ec 91 #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 150:02e0a0aed4ec 92 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3
<> 150:02e0a0aed4ec 93 #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 150:02e0a0aed4ec 94 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4
<> 150:02e0a0aed4ec 95 #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS))
<> 150:02e0a0aed4ec 96 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8
<> 150:02e0a0aed4ec 97 #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS))
<> 150:02e0a0aed4ec 98 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12
<> 150:02e0a0aed4ec 99 #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS))
<> 150:02e0a0aed4ec 100 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16
<> 150:02e0a0aed4ec 101 #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 102 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18
<> 150:02e0a0aed4ec 103 #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 104 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20
<> 150:02e0a0aed4ec 105 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS))
<> 150:02e0a0aed4ec 106 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24
<> 150:02e0a0aed4ec 107 #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS))
<> 150:02e0a0aed4ec 108 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28
<> 150:02e0a0aed4ec 109 #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS))
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0
<> 150:02e0a0aed4ec 112 #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS))
<> 150:02e0a0aed4ec 113 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8
<> 150:02e0a0aed4ec 114 #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 150:02e0a0aed4ec 115 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10
<> 150:02e0a0aed4ec 116 #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 150:02e0a0aed4ec 117 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12
<> 150:02e0a0aed4ec 118 #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 150:02e0a0aed4ec 119 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16
<> 150:02e0a0aed4ec 120 #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS))
<> 150:02e0a0aed4ec 121
<> 150:02e0a0aed4ec 122 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0
<> 150:02e0a0aed4ec 123 #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS))
<> 150:02e0a0aed4ec 124 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8
<> 150:02e0a0aed4ec 125 #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS))
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0
<> 150:02e0a0aed4ec 128 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS))
<> 150:02e0a0aed4ec 129 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16
<> 150:02e0a0aed4ec 130 #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS))
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0
<> 150:02e0a0aed4ec 133 #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS))
<> 150:02e0a0aed4ec 134 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1
<> 150:02e0a0aed4ec 135 #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS))
<> 150:02e0a0aed4ec 136
<> 150:02e0a0aed4ec 137 #if(MXC_SPIX_REV == 0)
<> 150:02e0a0aed4ec 138 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4
<> 150:02e0a0aed4ec 139 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS))
<> 150:02e0a0aed4ec 140 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12
<> 150:02e0a0aed4ec 141 #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS))
<> 150:02e0a0aed4ec 142 #endif
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144
<> 150:02e0a0aed4ec 145 /*
<> 150:02e0a0aed4ec 146 Field values and shifted values for module SPIX.
<> 150:02e0a0aed4ec 147 */
<> 150:02e0a0aed4ec 148
<> 150:02e0a0aed4ec 149 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 150 #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 151
<> 150:02e0a0aed4ec 152 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 150:02e0a0aed4ec 153 #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS))
<> 150:02e0a0aed4ec 154
<> 150:02e0a0aed4ec 155 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 156 #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 150:02e0a0aed4ec 159 #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS))
<> 150:02e0a0aed4ec 160
<> 150:02e0a0aed4ec 161 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 162 #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 150:02e0a0aed4ec 165 #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS))
<> 150:02e0a0aed4ec 166
<> 150:02e0a0aed4ec 167 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 168 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 169 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 170 #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 173 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 174 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 175 #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS))
<> 150:02e0a0aed4ec 176
<> 150:02e0a0aed4ec 177 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 178 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 179 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 180 #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL))
<> 150:02e0a0aed4ec 181
<> 150:02e0a0aed4ec 182 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 183 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 184 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 185 #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS))
<> 150:02e0a0aed4ec 186
<> 150:02e0a0aed4ec 187 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 188 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 189 #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 190
<> 150:02e0a0aed4ec 191 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 150:02e0a0aed4ec 192 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 150:02e0a0aed4ec 193 #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS))
<> 150:02e0a0aed4ec 194
<> 150:02e0a0aed4ec 195 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 196 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 197 #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 198
<> 150:02e0a0aed4ec 199 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 150:02e0a0aed4ec 200 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 150:02e0a0aed4ec 201 #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS))
<> 150:02e0a0aed4ec 202
<> 150:02e0a0aed4ec 203 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL))
<> 150:02e0a0aed4ec 204 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL))
<> 150:02e0a0aed4ec 205 #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL))
<> 150:02e0a0aed4ec 206
<> 150:02e0a0aed4ec 207 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 150:02e0a0aed4ec 208 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 150:02e0a0aed4ec 209 #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS))
<> 150:02e0a0aed4ec 210
<> 150:02e0a0aed4ec 211
<> 150:02e0a0aed4ec 212
<> 150:02e0a0aed4ec 213 #ifdef __cplusplus
<> 150:02e0a0aed4ec 214 }
<> 150:02e0a0aed4ec 215 #endif
<> 150:02e0a0aed4ec 216
<> 150:02e0a0aed4ec 217 #endif /* _MXC_SPIX_REGS_H_ */
<> 150:02e0a0aed4ec 218