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targets/TARGET_Maxim/TARGET_MAX32625/device/pwrman_regs.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

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<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MXC_PWRMAN_REGS_H_
<> 150:02e0a0aed4ec 34 #define _MXC_PWRMAN_REGS_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #ifdef __cplusplus
<> 150:02e0a0aed4ec 37 extern "C" {
<> 150:02e0a0aed4ec 38 #endif
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 #include <stdint.h>
<> 150:02e0a0aed4ec 41 #include "mxc_device.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 /*
<> 150:02e0a0aed4ec 44 If types are not defined elsewhere (CMSIS) define them here
<> 150:02e0a0aed4ec 45 */
<> 150:02e0a0aed4ec 46 #ifndef __IO
<> 150:02e0a0aed4ec 47 #define __IO volatile
<> 150:02e0a0aed4ec 48 #endif
<> 150:02e0a0aed4ec 49 #ifndef __I
<> 150:02e0a0aed4ec 50 #define __I volatile const
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52 #ifndef __O
<> 150:02e0a0aed4ec 53 #define __O volatile
<> 150:02e0a0aed4ec 54 #endif
<> 150:02e0a0aed4ec 55
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 /**
<> 150:02e0a0aed4ec 58 * @brief Defines PAD Modes for Wake Up Detection.
<> 150:02e0a0aed4ec 59 */
<> 150:02e0a0aed4ec 60 typedef enum {
<> 150:02e0a0aed4ec 61 /** WUD Mode for Selected PAD = Clear/Activate */
<> 150:02e0a0aed4ec 62 MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
<> 150:02e0a0aed4ec 63 /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
<> 150:02e0a0aed4ec 64 MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
<> 150:02e0a0aed4ec 65 /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
<> 150:02e0a0aed4ec 66 MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
<> 150:02e0a0aed4ec 67 /** WUD Mode for Selected PAD = No pad state change */
<> 150:02e0a0aed4ec 68 MXC_E_PWRMAN_PAD_MODE_NONE
<> 150:02e0a0aed4ec 69 } mxc_pwrman_pad_mode_t;
<> 150:02e0a0aed4ec 70
<> 150:02e0a0aed4ec 71 /*
<> 150:02e0a0aed4ec 72 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 150:02e0a0aed4ec 73 access to each register in module.
<> 150:02e0a0aed4ec 74 */
<> 150:02e0a0aed4ec 75
<> 150:02e0a0aed4ec 76 /* Offset Register Description
<> 150:02e0a0aed4ec 77 ============= ============================================================================ */
<> 150:02e0a0aed4ec 78 typedef struct {
<> 150:02e0a0aed4ec 79 __IO uint32_t pwr_rst_ctrl; /* 0x0000 Power Reset Control and Status */
<> 150:02e0a0aed4ec 80 __IO uint32_t intfl; /* 0x0004 Interrupt Flags */
<> 150:02e0a0aed4ec 81 __IO uint32_t inten; /* 0x0008 Interrupt Enable/Disable Controls */
<> 150:02e0a0aed4ec 82 __IO uint32_t svm_events; /* 0x000C SVM Event Status Flags (read-only) */
<> 150:02e0a0aed4ec 83 __IO uint32_t wud_ctrl; /* 0x0010 Wake-Up Detect Control */
<> 150:02e0a0aed4ec 84 __IO uint32_t wud_pulse0; /* 0x0014 WUD Pulse To Mode Bit 0 */
<> 150:02e0a0aed4ec 85 __IO uint32_t wud_pulse1; /* 0x0018 WUD Pulse To Mode Bit 1 */
<> 150:02e0a0aed4ec 86 __IO uint32_t wud_seen0; /* 0x001C Wake-up Detect Status for P0/P1/P2/P3 */
<> 150:02e0a0aed4ec 87 __IO uint32_t wud_seen1; /* 0x0020 Wake-up Detect Status for P4/P5/P6/P7 */
<> 150:02e0a0aed4ec 88 __I uint32_t rsv024[3]; /* 0x0024-0x002C */
<> 150:02e0a0aed4ec 89 __IO uint32_t pt_regmap_ctrl; /* 0x0030 PT Register Mapping Control */
<> 150:02e0a0aed4ec 90 __I uint32_t rsv034; /* 0x0034 */
<> 150:02e0a0aed4ec 91 __IO uint32_t die_type; /* 0x0038 Die Type ID Register */
<> 150:02e0a0aed4ec 92 __IO uint32_t base_part_num; /* 0x003C Base Part Number */
<> 150:02e0a0aed4ec 93 __IO uint32_t mask_id0; /* 0x0040 Mask ID Register 0 */
<> 150:02e0a0aed4ec 94 __IO uint32_t mask_id1; /* 0x0044 Mask ID Register 1 */
<> 150:02e0a0aed4ec 95 __IO uint32_t peripheral_reset; /* 0x0048 Peripheral Reset Control Register */
<> 150:02e0a0aed4ec 96 } mxc_pwrman_regs_t;
<> 150:02e0a0aed4ec 97
<> 150:02e0a0aed4ec 98
<> 150:02e0a0aed4ec 99 /*
<> 150:02e0a0aed4ec 100 Register offsets for module PWRMAN.
<> 150:02e0a0aed4ec 101 */
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL ((uint32_t)0x00000000UL)
<> 150:02e0a0aed4ec 104 #define MXC_R_PWRMAN_OFFS_INTFL ((uint32_t)0x00000004UL)
<> 150:02e0a0aed4ec 105 #define MXC_R_PWRMAN_OFFS_INTEN ((uint32_t)0x00000008UL)
<> 150:02e0a0aed4ec 106 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS ((uint32_t)0x0000000CUL)
<> 150:02e0a0aed4ec 107 #define MXC_R_PWRMAN_OFFS_WUD_CTRL ((uint32_t)0x00000010UL)
<> 150:02e0a0aed4ec 108 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0 ((uint32_t)0x00000014UL)
<> 150:02e0a0aed4ec 109 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1 ((uint32_t)0x00000018UL)
<> 150:02e0a0aed4ec 110 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0 ((uint32_t)0x0000001CUL)
<> 150:02e0a0aed4ec 111 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1 ((uint32_t)0x00000020UL)
<> 150:02e0a0aed4ec 112 #define MXC_R_PWRMAN_OFFS_PT_REGMAP_CTRL ((uint32_t)0x00000030UL)
<> 150:02e0a0aed4ec 113 #define MXC_R_PWRMAN_OFFS_DIE_TYPE ((uint32_t)0x00000038UL)
<> 150:02e0a0aed4ec 114 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM ((uint32_t)0x0000003CUL)
<> 150:02e0a0aed4ec 115 #define MXC_R_PWRMAN_OFFS_MASK_ID0 ((uint32_t)0x00000040UL)
<> 150:02e0a0aed4ec 116 #define MXC_R_PWRMAN_OFFS_MASK_ID1 ((uint32_t)0x00000044UL)
<> 150:02e0a0aed4ec 117 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET ((uint32_t)0x00000048UL)
<> 150:02e0a0aed4ec 118
<> 150:02e0a0aed4ec 119
<> 150:02e0a0aed4ec 120 /*
<> 150:02e0a0aed4ec 121 Field positions and masks for module PWRMAN.
<> 150:02e0a0aed4ec 122 */
<> 150:02e0a0aed4ec 123
<> 150:02e0a0aed4ec 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS 2
<> 150:02e0a0aed4ec 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
<> 150:02e0a0aed4ec 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS 3
<> 150:02e0a0aed4ec 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
<> 150:02e0a0aed4ec 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS 4
<> 150:02e0a0aed4ec 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
<> 150:02e0a0aed4ec 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS 5
<> 150:02e0a0aed4ec 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
<> 150:02e0a0aed4ec 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS 8
<> 150:02e0a0aed4ec 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
<> 150:02e0a0aed4ec 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS 9
<> 150:02e0a0aed4ec 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
<> 150:02e0a0aed4ec 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS 16
<> 150:02e0a0aed4ec 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
<> 150:02e0a0aed4ec 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS 17
<> 150:02e0a0aed4ec 139 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
<> 150:02e0a0aed4ec 140 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS 18
<> 150:02e0a0aed4ec 141 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
<> 150:02e0a0aed4ec 142 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS 19
<> 150:02e0a0aed4ec 143 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
<> 150:02e0a0aed4ec 144 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS 20
<> 150:02e0a0aed4ec 145 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
<> 150:02e0a0aed4ec 146 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS 21
<> 150:02e0a0aed4ec 147 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
<> 150:02e0a0aed4ec 148 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS 22
<> 150:02e0a0aed4ec 149 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
<> 150:02e0a0aed4ec 150 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS 31
<> 150:02e0a0aed4ec 151 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS 0
<> 150:02e0a0aed4ec 154 #define MXC_F_PWRMAN_INTFL_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_2_WARNING_POS))
<> 150:02e0a0aed4ec 155 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS 1
<> 150:02e0a0aed4ec 156 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
<> 150:02e0a0aed4ec 157 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS 2
<> 150:02e0a0aed4ec 158 #define MXC_F_PWRMAN_INTFL_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
<> 150:02e0a0aed4ec 159 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS 3
<> 150:02e0a0aed4ec 160 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
<> 150:02e0a0aed4ec 161 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS 4
<> 150:02e0a0aed4ec 162 #define MXC_F_PWRMAN_INTFL_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDB_WARNING_POS))
<> 150:02e0a0aed4ec 163 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS 5
<> 150:02e0a0aed4ec 164 #define MXC_F_PWRMAN_INTFL_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIO_WARNING_POS))
<> 150:02e0a0aed4ec 165 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS 6
<> 150:02e0a0aed4ec 166 #define MXC_F_PWRMAN_INTFL_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDIOH_WARNING_POS))
<> 150:02e0a0aed4ec 167
<> 150:02e0a0aed4ec 168 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS 0
<> 150:02e0a0aed4ec 169 #define MXC_F_PWRMAN_INTEN_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_2_WARNING_POS))
<> 150:02e0a0aed4ec 170 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS 1
<> 150:02e0a0aed4ec 171 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
<> 150:02e0a0aed4ec 172 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS 2
<> 150:02e0a0aed4ec 173 #define MXC_F_PWRMAN_INTEN_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
<> 150:02e0a0aed4ec 174 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS 3
<> 150:02e0a0aed4ec 175 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
<> 150:02e0a0aed4ec 176 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS 4
<> 150:02e0a0aed4ec 177 #define MXC_F_PWRMAN_INTEN_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDB_WARNING_POS))
<> 150:02e0a0aed4ec 178 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS 5
<> 150:02e0a0aed4ec 179 #define MXC_F_PWRMAN_INTEN_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIO_WARNING_POS))
<> 150:02e0a0aed4ec 180 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS 6
<> 150:02e0a0aed4ec 181 #define MXC_F_PWRMAN_INTEN_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDIOH_WARNING_POS))
<> 150:02e0a0aed4ec 182
<> 150:02e0a0aed4ec 183 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS 0
<> 150:02e0a0aed4ec 184 #define MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_2_WARNING_POS))
<> 150:02e0a0aed4ec 185 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS 1
<> 150:02e0a0aed4ec 186 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
<> 150:02e0a0aed4ec 187 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS 2
<> 150:02e0a0aed4ec 188 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
<> 150:02e0a0aed4ec 189 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS 3
<> 150:02e0a0aed4ec 190 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
<> 150:02e0a0aed4ec 191 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS 4
<> 150:02e0a0aed4ec 192 #define MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDB_WARNING_POS))
<> 150:02e0a0aed4ec 193 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS 5
<> 150:02e0a0aed4ec 194 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIO_WARNING_POS))
<> 150:02e0a0aed4ec 195 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS 6
<> 150:02e0a0aed4ec 196 #define MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDIOH_WARNING_POS))
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS 0
<> 150:02e0a0aed4ec 199 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
<> 150:02e0a0aed4ec 200 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS 8
<> 150:02e0a0aed4ec 201 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
<> 150:02e0a0aed4ec 202 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS 12
<> 150:02e0a0aed4ec 203 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
<> 150:02e0a0aed4ec 204 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS 16
<> 150:02e0a0aed4ec 205 #define MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CTRL_ENABLE_POS))
<> 150:02e0a0aed4ec 206
<> 150:02e0a0aed4ec 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS 0
<> 150:02e0a0aed4ec 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
<> 150:02e0a0aed4ec 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS 1
<> 150:02e0a0aed4ec 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
<> 150:02e0a0aed4ec 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS 2
<> 150:02e0a0aed4ec 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
<> 150:02e0a0aed4ec 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS 3
<> 150:02e0a0aed4ec 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
<> 150:02e0a0aed4ec 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS 4
<> 150:02e0a0aed4ec 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
<> 150:02e0a0aed4ec 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS 5
<> 150:02e0a0aed4ec 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
<> 150:02e0a0aed4ec 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS 6
<> 150:02e0a0aed4ec 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
<> 150:02e0a0aed4ec 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS 7
<> 150:02e0a0aed4ec 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
<> 150:02e0a0aed4ec 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS 8
<> 150:02e0a0aed4ec 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
<> 150:02e0a0aed4ec 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS 9
<> 150:02e0a0aed4ec 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
<> 150:02e0a0aed4ec 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS 10
<> 150:02e0a0aed4ec 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
<> 150:02e0a0aed4ec 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS 11
<> 150:02e0a0aed4ec 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
<> 150:02e0a0aed4ec 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS 12
<> 150:02e0a0aed4ec 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
<> 150:02e0a0aed4ec 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS 13
<> 150:02e0a0aed4ec 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
<> 150:02e0a0aed4ec 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS 14
<> 150:02e0a0aed4ec 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
<> 150:02e0a0aed4ec 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS 15
<> 150:02e0a0aed4ec 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
<> 150:02e0a0aed4ec 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS 16
<> 150:02e0a0aed4ec 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
<> 150:02e0a0aed4ec 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS 17
<> 150:02e0a0aed4ec 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
<> 150:02e0a0aed4ec 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS 18
<> 150:02e0a0aed4ec 244 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
<> 150:02e0a0aed4ec 245 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS 19
<> 150:02e0a0aed4ec 246 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
<> 150:02e0a0aed4ec 247 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS 20
<> 150:02e0a0aed4ec 248 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
<> 150:02e0a0aed4ec 249 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS 21
<> 150:02e0a0aed4ec 250 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
<> 150:02e0a0aed4ec 251 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS 22
<> 150:02e0a0aed4ec 252 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
<> 150:02e0a0aed4ec 253 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS 23
<> 150:02e0a0aed4ec 254 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
<> 150:02e0a0aed4ec 255 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS 24
<> 150:02e0a0aed4ec 256 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
<> 150:02e0a0aed4ec 257 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS 25
<> 150:02e0a0aed4ec 258 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
<> 150:02e0a0aed4ec 259 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS 26
<> 150:02e0a0aed4ec 260 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
<> 150:02e0a0aed4ec 261 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS 27
<> 150:02e0a0aed4ec 262 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
<> 150:02e0a0aed4ec 263 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS 28
<> 150:02e0a0aed4ec 264 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
<> 150:02e0a0aed4ec 265 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS 29
<> 150:02e0a0aed4ec 266 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
<> 150:02e0a0aed4ec 267 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS 30
<> 150:02e0a0aed4ec 268 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
<> 150:02e0a0aed4ec 269 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS 31
<> 150:02e0a0aed4ec 270 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
<> 150:02e0a0aed4ec 271
<> 150:02e0a0aed4ec 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS 0
<> 150:02e0a0aed4ec 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
<> 150:02e0a0aed4ec 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS 1
<> 150:02e0a0aed4ec 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
<> 150:02e0a0aed4ec 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS 2
<> 150:02e0a0aed4ec 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
<> 150:02e0a0aed4ec 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS 3
<> 150:02e0a0aed4ec 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
<> 150:02e0a0aed4ec 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS 4
<> 150:02e0a0aed4ec 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
<> 150:02e0a0aed4ec 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS 5
<> 150:02e0a0aed4ec 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
<> 150:02e0a0aed4ec 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS 6
<> 150:02e0a0aed4ec 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
<> 150:02e0a0aed4ec 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS 7
<> 150:02e0a0aed4ec 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
<> 150:02e0a0aed4ec 288
<> 150:02e0a0aed4ec 289 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS 0
<> 150:02e0a0aed4ec 290 #define MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE_POS))
<> 150:02e0a0aed4ec 291
<> 150:02e0a0aed4ec 292 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS 0
<> 150:02e0a0aed4ec 293 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
<> 150:02e0a0aed4ec 294
<> 150:02e0a0aed4ec 295 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS 0
<> 150:02e0a0aed4ec 296 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
<> 150:02e0a0aed4ec 297 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS 4
<> 150:02e0a0aed4ec 298 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
<> 150:02e0a0aed4ec 299
<> 150:02e0a0aed4ec 300 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS 0
<> 150:02e0a0aed4ec 301 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
<> 150:02e0a0aed4ec 302 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS 31
<> 150:02e0a0aed4ec 303 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
<> 150:02e0a0aed4ec 304
<> 150:02e0a0aed4ec 305 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS 0
<> 150:02e0a0aed4ec 306 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
<> 150:02e0a0aed4ec 307 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS 1
<> 150:02e0a0aed4ec 308 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIX_POS))
<> 150:02e0a0aed4ec 309 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS 2
<> 150:02e0a0aed4ec 310 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PMU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PMU_POS))
<> 150:02e0a0aed4ec 311 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS 3
<> 150:02e0a0aed4ec 312 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
<> 150:02e0a0aed4ec 313 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS 4
<> 150:02e0a0aed4ec 314 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
<> 150:02e0a0aed4ec 315 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS 5
<> 150:02e0a0aed4ec 316 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
<> 150:02e0a0aed4ec 317 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS 6
<> 150:02e0a0aed4ec 318 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
<> 150:02e0a0aed4ec 319 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS 7
<> 150:02e0a0aed4ec 320 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
<> 150:02e0a0aed4ec 321 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS 8
<> 150:02e0a0aed4ec 322 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
<> 150:02e0a0aed4ec 323 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS 9
<> 150:02e0a0aed4ec 324 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
<> 150:02e0a0aed4ec 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS 10
<> 150:02e0a0aed4ec 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
<> 150:02e0a0aed4ec 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS 11
<> 150:02e0a0aed4ec 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
<> 150:02e0a0aed4ec 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS 12
<> 150:02e0a0aed4ec 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER4_POS))
<> 150:02e0a0aed4ec 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS 13
<> 150:02e0a0aed4ec 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER5_POS))
<> 150:02e0a0aed4ec 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS 14
<> 150:02e0a0aed4ec 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
<> 150:02e0a0aed4ec 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS 15
<> 150:02e0a0aed4ec 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
<> 150:02e0a0aed4ec 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS 16
<> 150:02e0a0aed4ec 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
<> 150:02e0a0aed4ec 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS 17
<> 150:02e0a0aed4ec 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART2_POS))
<> 150:02e0a0aed4ec 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS 19
<> 150:02e0a0aed4ec 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
<> 150:02e0a0aed4ec 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS 20
<> 150:02e0a0aed4ec 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
<> 150:02e0a0aed4ec 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS 22
<> 150:02e0a0aed4ec 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
<> 150:02e0a0aed4ec 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS 23
<> 150:02e0a0aed4ec 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM0_POS))
<> 150:02e0a0aed4ec 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS 24
<> 150:02e0a0aed4ec 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM1_POS))
<> 150:02e0a0aed4ec 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS 25
<> 150:02e0a0aed4ec 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIM2_POS))
<> 150:02e0a0aed4ec 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS 27
<> 150:02e0a0aed4ec 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_OWM ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_OWM_POS))
<> 150:02e0a0aed4ec 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS 28
<> 150:02e0a0aed4ec 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
<> 150:02e0a0aed4ec 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS 29
<> 150:02e0a0aed4ec 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPIS_POS))
<> 150:02e0a0aed4ec 359
<> 150:02e0a0aed4ec 360
<> 150:02e0a0aed4ec 361
<> 150:02e0a0aed4ec 362 #ifdef __cplusplus
<> 150:02e0a0aed4ec 363 }
<> 150:02e0a0aed4ec 364 #endif
<> 150:02e0a0aed4ec 365
<> 150:02e0a0aed4ec 366 #endif /* _MXC_PWRMAN_REGS_H_ */
<> 150:02e0a0aed4ec 367