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targets/cmsis/TARGET_Freescale/TARGET_K64F/system_MK64F12.c@121:7f86b4238bec, 2016-05-03 (annotated)

Committer:
mbed_official
Date:
Tue May 03 00:15:16 2016 +0100
Revision:
121:7f86b4238bec
Synchronized with git revision 9cef243de23875778f461bbe9a8c1bc47e65212b



Full URL: https://github.com/mbedmicro/mbed/commit/9cef243de23875778f461bbe9a8c1bc47e65212b/



Switch to KSDK 2.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 121:7f86b4238bec 1 /*
mbed_official 121:7f86b4238bec 2 ** ###################################################################
mbed_official 121:7f86b4238bec 3 ** Processors: MK64FN1M0VDC12
mbed_official 121:7f86b4238bec 4 ** MK64FN1M0VLL12
mbed_official 121:7f86b4238bec 5 ** MK64FN1M0VLQ12
mbed_official 121:7f86b4238bec 6 ** MK64FN1M0VMD12
mbed_official 121:7f86b4238bec 7 ** MK64FX512VDC12
mbed_official 121:7f86b4238bec 8 ** MK64FX512VLL12
mbed_official 121:7f86b4238bec 9 ** MK64FX512VLQ12
mbed_official 121:7f86b4238bec 10 ** MK64FX512VMD12
mbed_official 121:7f86b4238bec 11 **
mbed_official 121:7f86b4238bec 12 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 121:7f86b4238bec 13 ** Freescale C/C++ for Embedded ARM
mbed_official 121:7f86b4238bec 14 ** GNU C Compiler
mbed_official 121:7f86b4238bec 15 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 121:7f86b4238bec 16 **
mbed_official 121:7f86b4238bec 17 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 121:7f86b4238bec 18 ** Version: rev. 2.8, 2015-02-19
mbed_official 121:7f86b4238bec 19 ** Build: b151216
mbed_official 121:7f86b4238bec 20 **
mbed_official 121:7f86b4238bec 21 ** Abstract:
mbed_official 121:7f86b4238bec 22 ** Provides a system configuration function and a global variable that
mbed_official 121:7f86b4238bec 23 ** contains the system frequency. It configures the device and initializes
mbed_official 121:7f86b4238bec 24 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 121:7f86b4238bec 25 **
mbed_official 121:7f86b4238bec 26 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
mbed_official 121:7f86b4238bec 27 ** All rights reserved.
mbed_official 121:7f86b4238bec 28 **
mbed_official 121:7f86b4238bec 29 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 121:7f86b4238bec 30 ** are permitted provided that the following conditions are met:
mbed_official 121:7f86b4238bec 31 **
mbed_official 121:7f86b4238bec 32 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 121:7f86b4238bec 33 ** of conditions and the following disclaimer.
mbed_official 121:7f86b4238bec 34 **
mbed_official 121:7f86b4238bec 35 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 121:7f86b4238bec 36 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 121:7f86b4238bec 37 ** other materials provided with the distribution.
mbed_official 121:7f86b4238bec 38 **
mbed_official 121:7f86b4238bec 39 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 121:7f86b4238bec 40 ** contributors may be used to endorse or promote products derived from this
mbed_official 121:7f86b4238bec 41 ** software without specific prior written permission.
mbed_official 121:7f86b4238bec 42 **
mbed_official 121:7f86b4238bec 43 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 121:7f86b4238bec 44 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 121:7f86b4238bec 45 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 121:7f86b4238bec 46 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 121:7f86b4238bec 47 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 121:7f86b4238bec 48 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 121:7f86b4238bec 49 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 121:7f86b4238bec 50 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 121:7f86b4238bec 51 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 121:7f86b4238bec 52 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 121:7f86b4238bec 53 **
mbed_official 121:7f86b4238bec 54 ** http: www.freescale.com
mbed_official 121:7f86b4238bec 55 ** mail: support@freescale.com
mbed_official 121:7f86b4238bec 56 **
mbed_official 121:7f86b4238bec 57 ** Revisions:
mbed_official 121:7f86b4238bec 58 ** - rev. 1.0 (2013-08-12)
mbed_official 121:7f86b4238bec 59 ** Initial version.
mbed_official 121:7f86b4238bec 60 ** - rev. 2.0 (2013-10-29)
mbed_official 121:7f86b4238bec 61 ** Register accessor macros added to the memory map.
mbed_official 121:7f86b4238bec 62 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 121:7f86b4238bec 63 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 121:7f86b4238bec 64 ** System initialization updated.
mbed_official 121:7f86b4238bec 65 ** MCG - registers updated.
mbed_official 121:7f86b4238bec 66 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 121:7f86b4238bec 67 ** - rev. 2.1 (2013-10-30)
mbed_official 121:7f86b4238bec 68 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 121:7f86b4238bec 69 ** - rev. 2.2 (2013-12-09)
mbed_official 121:7f86b4238bec 70 ** DMA - EARS register removed.
mbed_official 121:7f86b4238bec 71 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 121:7f86b4238bec 72 ** - rev. 2.3 (2014-01-24)
mbed_official 121:7f86b4238bec 73 ** Update according to reference manual rev. 2
mbed_official 121:7f86b4238bec 74 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 121:7f86b4238bec 75 ** - rev. 2.4 (2014-02-10)
mbed_official 121:7f86b4238bec 76 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 121:7f86b4238bec 77 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 121:7f86b4238bec 78 ** - rev. 2.5 (2014-02-10)
mbed_official 121:7f86b4238bec 79 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 121:7f86b4238bec 80 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 121:7f86b4238bec 81 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 121:7f86b4238bec 82 ** - rev. 2.6 (2014-08-28)
mbed_official 121:7f86b4238bec 83 ** Update of system files - default clock configuration changed.
mbed_official 121:7f86b4238bec 84 ** Update of startup files - possibility to override DefaultISR added.
mbed_official 121:7f86b4238bec 85 ** - rev. 2.7 (2014-10-14)
mbed_official 121:7f86b4238bec 86 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
mbed_official 121:7f86b4238bec 87 ** - rev. 2.8 (2015-02-19)
mbed_official 121:7f86b4238bec 88 ** Renamed interrupt vector LLW to LLWU.
mbed_official 121:7f86b4238bec 89 **
mbed_official 121:7f86b4238bec 90 ** ###################################################################
mbed_official 121:7f86b4238bec 91 */
mbed_official 121:7f86b4238bec 92
mbed_official 121:7f86b4238bec 93 /*!
mbed_official 121:7f86b4238bec 94 * @file MK64F12
mbed_official 121:7f86b4238bec 95 * @version 2.8
mbed_official 121:7f86b4238bec 96 * @date 2015-02-19
mbed_official 121:7f86b4238bec 97 * @brief Device specific configuration file for MK64F12 (implementation file)
mbed_official 121:7f86b4238bec 98 *
mbed_official 121:7f86b4238bec 99 * Provides a system configuration function and a global variable that contains
mbed_official 121:7f86b4238bec 100 * the system frequency. It configures the device and initializes the oscillator
mbed_official 121:7f86b4238bec 101 * (PLL) that is part of the microcontroller device.
mbed_official 121:7f86b4238bec 102 */
mbed_official 121:7f86b4238bec 103
mbed_official 121:7f86b4238bec 104 #include <stdint.h>
mbed_official 121:7f86b4238bec 105 #include "fsl_device_registers.h"
mbed_official 121:7f86b4238bec 106
mbed_official 121:7f86b4238bec 107
mbed_official 121:7f86b4238bec 108
mbed_official 121:7f86b4238bec 109 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 110 -- Core clock
mbed_official 121:7f86b4238bec 111 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 112
mbed_official 121:7f86b4238bec 113 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 121:7f86b4238bec 114
mbed_official 121:7f86b4238bec 115 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 116 -- SystemInit()
mbed_official 121:7f86b4238bec 117 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 118
mbed_official 121:7f86b4238bec 119 void SystemInit (void) {
mbed_official 121:7f86b4238bec 120 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
mbed_official 121:7f86b4238bec 121 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
mbed_official 121:7f86b4238bec 122 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
mbed_official 121:7f86b4238bec 123 #if (DISABLE_WDOG)
mbed_official 121:7f86b4238bec 124 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
mbed_official 121:7f86b4238bec 125 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
mbed_official 121:7f86b4238bec 126 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
mbed_official 121:7f86b4238bec 127 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
mbed_official 121:7f86b4238bec 128 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
mbed_official 121:7f86b4238bec 129 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
mbed_official 121:7f86b4238bec 130 WDOG_STCTRLH_WAITEN_MASK |
mbed_official 121:7f86b4238bec 131 WDOG_STCTRLH_STOPEN_MASK |
mbed_official 121:7f86b4238bec 132 WDOG_STCTRLH_ALLOWUPDATE_MASK |
mbed_official 121:7f86b4238bec 133 WDOG_STCTRLH_CLKSRC_MASK |
mbed_official 121:7f86b4238bec 134 0x0100U;
mbed_official 121:7f86b4238bec 135 #endif /* (DISABLE_WDOG) */
mbed_official 121:7f86b4238bec 136
mbed_official 121:7f86b4238bec 137 }
mbed_official 121:7f86b4238bec 138
mbed_official 121:7f86b4238bec 139 /* ----------------------------------------------------------------------------
mbed_official 121:7f86b4238bec 140 -- SystemCoreClockUpdate()
mbed_official 121:7f86b4238bec 141 ---------------------------------------------------------------------------- */
mbed_official 121:7f86b4238bec 142
mbed_official 121:7f86b4238bec 143 void SystemCoreClockUpdate (void) {
mbed_official 121:7f86b4238bec 144 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 121:7f86b4238bec 145 uint16_t Divider;
mbed_official 121:7f86b4238bec 146
mbed_official 121:7f86b4238bec 147 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
mbed_official 121:7f86b4238bec 148 /* Output of FLL or PLL is selected */
mbed_official 121:7f86b4238bec 149 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
mbed_official 121:7f86b4238bec 150 /* FLL is selected */
mbed_official 121:7f86b4238bec 151 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
mbed_official 121:7f86b4238bec 152 /* External reference clock is selected */
mbed_official 121:7f86b4238bec 153 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 121:7f86b4238bec 154 case 0x00U:
mbed_official 121:7f86b4238bec 155 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 156 break;
mbed_official 121:7f86b4238bec 157 case 0x01U:
mbed_official 121:7f86b4238bec 158 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 159 break;
mbed_official 121:7f86b4238bec 160 case 0x02U:
mbed_official 121:7f86b4238bec 161 default:
mbed_official 121:7f86b4238bec 162 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 163 break;
mbed_official 121:7f86b4238bec 164 }
mbed_official 121:7f86b4238bec 165 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
mbed_official 121:7f86b4238bec 166 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
mbed_official 121:7f86b4238bec 167 case 0x38U:
mbed_official 121:7f86b4238bec 168 Divider = 1536U;
mbed_official 121:7f86b4238bec 169 break;
mbed_official 121:7f86b4238bec 170 case 0x30U:
mbed_official 121:7f86b4238bec 171 Divider = 1280U;
mbed_official 121:7f86b4238bec 172 break;
mbed_official 121:7f86b4238bec 173 default:
mbed_official 121:7f86b4238bec 174 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 121:7f86b4238bec 175 break;
mbed_official 121:7f86b4238bec 176 }
mbed_official 121:7f86b4238bec 177 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
mbed_official 121:7f86b4238bec 178 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 121:7f86b4238bec 179 }
mbed_official 121:7f86b4238bec 180 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 121:7f86b4238bec 181 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 182 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 121:7f86b4238bec 183 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 184 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 121:7f86b4238bec 185 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 121:7f86b4238bec 186 case 0x00U:
mbed_official 121:7f86b4238bec 187 MCGOUTClock *= 640U;
mbed_official 121:7f86b4238bec 188 break;
mbed_official 121:7f86b4238bec 189 case 0x20U:
mbed_official 121:7f86b4238bec 190 MCGOUTClock *= 1280U;
mbed_official 121:7f86b4238bec 191 break;
mbed_official 121:7f86b4238bec 192 case 0x40U:
mbed_official 121:7f86b4238bec 193 MCGOUTClock *= 1920U;
mbed_official 121:7f86b4238bec 194 break;
mbed_official 121:7f86b4238bec 195 case 0x60U:
mbed_official 121:7f86b4238bec 196 MCGOUTClock *= 2560U;
mbed_official 121:7f86b4238bec 197 break;
mbed_official 121:7f86b4238bec 198 case 0x80U:
mbed_official 121:7f86b4238bec 199 MCGOUTClock *= 732U;
mbed_official 121:7f86b4238bec 200 break;
mbed_official 121:7f86b4238bec 201 case 0xA0U:
mbed_official 121:7f86b4238bec 202 MCGOUTClock *= 1464U;
mbed_official 121:7f86b4238bec 203 break;
mbed_official 121:7f86b4238bec 204 case 0xC0U:
mbed_official 121:7f86b4238bec 205 MCGOUTClock *= 2197U;
mbed_official 121:7f86b4238bec 206 break;
mbed_official 121:7f86b4238bec 207 case 0xE0U:
mbed_official 121:7f86b4238bec 208 MCGOUTClock *= 2929U;
mbed_official 121:7f86b4238bec 209 break;
mbed_official 121:7f86b4238bec 210 default:
mbed_official 121:7f86b4238bec 211 break;
mbed_official 121:7f86b4238bec 212 }
mbed_official 121:7f86b4238bec 213 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 214 /* PLL is selected */
mbed_official 121:7f86b4238bec 215 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
mbed_official 121:7f86b4238bec 216 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 121:7f86b4238bec 217 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
mbed_official 121:7f86b4238bec 218 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 121:7f86b4238bec 219 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 220 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
mbed_official 121:7f86b4238bec 221 /* Internal reference clock is selected */
mbed_official 121:7f86b4238bec 222 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
mbed_official 121:7f86b4238bec 223 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 121:7f86b4238bec 224 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 225 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
mbed_official 121:7f86b4238bec 226 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
mbed_official 121:7f86b4238bec 227 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 121:7f86b4238bec 228 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
mbed_official 121:7f86b4238bec 229 /* External reference clock is selected */
mbed_official 121:7f86b4238bec 230 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 121:7f86b4238bec 231 case 0x00U:
mbed_official 121:7f86b4238bec 232 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 233 break;
mbed_official 121:7f86b4238bec 234 case 0x01U:
mbed_official 121:7f86b4238bec 235 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 236 break;
mbed_official 121:7f86b4238bec 237 case 0x02U:
mbed_official 121:7f86b4238bec 238 default:
mbed_official 121:7f86b4238bec 239 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 121:7f86b4238bec 240 break;
mbed_official 121:7f86b4238bec 241 }
mbed_official 121:7f86b4238bec 242 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 121:7f86b4238bec 243 /* Reserved value */
mbed_official 121:7f86b4238bec 244 return;
mbed_official 121:7f86b4238bec 245 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 121:7f86b4238bec 246 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 121:7f86b4238bec 247 }