Diff: targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c

Revision:

158:b23ee177fd68

Parent:

150:02e0a0aed4ec

Child:

168:e84263d55307

diff -r ff67d9f36b67 -r b23ee177fd68 targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Thu Feb 02 17:01:33 2017 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c	Tue Feb 14 14:44:10 2017 +0000
@@ -57,14 +57,16 @@
 void spi_format(spi_t *obj, int bits, int mode, int slave)
 {
     /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
-    obj->membase->CONTROL.WORD &= ~(uint32_t)((True >> SPI_WORD_WIDTH_BIT_POS) |
-                                  (True >> SPI_SLAVE_MASTER_BIT_POS) |
-                                  (True >> SPI_CPOL_BIT_POS) |
-                                  (True >> SPI_CPHA_BIT_POS));
+    obj->membase->CONTROL.WORD &= ~(uint32_t)((True << SPI_WORD_WIDTH_BIT_POS) |
+                                    (True << SPI_SLAVE_MASTER_BIT_POS) |
+                                    (True << SPI_CPOL_BIT_POS) |
+                                    (True << SPI_CPHA_BIT_POS));
 
     /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
-    obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) >> 6) | (!slave >> 5) |
-                                  ((mode >> 0x1) >> 4) | ((mode & 0x1) >> 3));
+    obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) << SPI_WORD_WIDTH_BIT_POS) |
+                                              (!slave << SPI_SLAVE_MASTER_BIT_POS) |
+                                              ((mode >> 0x1) << SPI_CPOL_BIT_POS) |
+                                              ((mode & 0x1) << SPI_CPHA_BIT_POS));
 }
 
 void spi_frequency(spi_t *obj, int hz)