Amit Gandhi / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/device/adc_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-09-30 19:43:43 -0500 (Fri, 30 Sep 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24540 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_ADC_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_ADC_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 /// @cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 /// @endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /* **** Definitions **** */
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /**
<> 157:ff67d9f36b67 74 * @ingroup adc
<> 157:ff67d9f36b67 75 * @defgroup adc_registers Registers
<> 157:ff67d9f36b67 76 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module.
<> 157:ff67d9f36b67 77 */
<> 157:ff67d9f36b67 78
<> 157:ff67d9f36b67 79 /**
<> 157:ff67d9f36b67 80 * @ingroup adc_registers
<> 157:ff67d9f36b67 81 * Structure type to access the ADC Registers.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 typedef struct {
<> 157:ff67d9f36b67 84 __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> ADC CTRL Register */
<> 157:ff67d9f36b67 85 __IO uint32_t status; /**< <tt>\b 0x004:</tt> ADC STATUS Register */
<> 157:ff67d9f36b67 86 __IO uint32_t data; /**< <tt>\b 0x008:</tt> ADC DATA Register */
<> 157:ff67d9f36b67 87 __IO uint32_t intr; /**< <tt>\b 0x00C:</tt> ADC INTR Register */
<> 157:ff67d9f36b67 88 __IO uint32_t limit[4]; /**< <tt>\b 0x010:</tt> ADC LIMIT0, LIMIT1, LIMIT2, LIMIT3 Register */
<> 157:ff67d9f36b67 89 __IO uint32_t afe_ctrl; /**< <tt>\b 0x020:</tt> ADC AFE_CTRL Register */
<> 157:ff67d9f36b67 90 __IO uint32_t ro_cal0; /**< <tt>\b 0x024:</tt> ADC RO_CAL0 Register */
<> 157:ff67d9f36b67 91 __IO uint32_t ro_cal1; /**< <tt>\b 0x028:</tt> ADC RO_CAL1 Register */
<> 157:ff67d9f36b67 92 __IO uint32_t ro_cal2; /**< <tt>\b 0x02C:</tt> ADC RO_CAL2 Register */
<> 157:ff67d9f36b67 93 } mxc_adc_regs_t;
<> 157:ff67d9f36b67 94
<> 157:ff67d9f36b67 95
<> 157:ff67d9f36b67 96 /* Register offsets for module ADC. */
<> 157:ff67d9f36b67 97 /**
<> 157:ff67d9f36b67 98 * @ingroup adc_registers
<> 157:ff67d9f36b67 99 * @defgroup ADC_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 100 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address.
<> 157:ff67d9f36b67 101 * @{
<> 157:ff67d9f36b67 102 */
<> 157:ff67d9f36b67 103 #define MXC_R_ADC_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt>\b 0x000</tt> */
<> 157:ff67d9f36b67 104 #define MXC_R_ADC_OFFS_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt>\b 0x004</tt> */
<> 157:ff67d9f36b67 105 #define MXC_R_ADC_OFFS_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt>\b 0x008</tt> */
<> 157:ff67d9f36b67 106 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt>\b 0x00C</tt> */
<> 157:ff67d9f36b67 107 #define MXC_R_ADC_OFFS_LIMIT0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt>\b 0x010</tt> */
<> 157:ff67d9f36b67 108 #define MXC_R_ADC_OFFS_LIMIT1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt>\b 0x014</tt> */
<> 157:ff67d9f36b67 109 #define MXC_R_ADC_OFFS_LIMIT2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt>\b 0x018</tt> */
<> 157:ff67d9f36b67 110 #define MXC_R_ADC_OFFS_LIMIT3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt>\b 0x01C</tt> */
<> 157:ff67d9f36b67 111 #define MXC_R_ADC_OFFS_AFE_CTRL ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt>\b 0x020</tt> */
<> 157:ff67d9f36b67 112 #define MXC_R_ADC_OFFS_RO_CAL0 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt>\b 0x024</tt> */
<> 157:ff67d9f36b67 113 #define MXC_R_ADC_OFFS_RO_CAL1 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt>\b 0x028</tt> */
<> 157:ff67d9f36b67 114 #define MXC_R_ADC_OFFS_RO_CAL2 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt>\b 0x02C</tt> */
<> 157:ff67d9f36b67 115 /**@} end of group adc_registers */
<> 157:ff67d9f36b67 116
<> 157:ff67d9f36b67 117 /**
<> 157:ff67d9f36b67 118 * @ingroup adc_registers
<> 157:ff67d9f36b67 119 * @defgroup ADC_CTRL_Register ADC_CTRL
<> 157:ff67d9f36b67 120 * @brief Field Positions and Bit Masks for the ADC_CTRL register
<> 157:ff67d9f36b67 121 * @{
<> 157:ff67d9f36b67 122 */
<> 157:ff67d9f36b67 123 #define MXC_F_ADC_CTRL_CPU_ADC_START_POS 0 /**< CPU_ADC_START Position */
<> 157:ff67d9f36b67 124 #define MXC_F_ADC_CTRL_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_CPU_ADC_START_POS)) /**< CPU_ADC_START Mask */
<> 157:ff67d9f36b67 125 #define MXC_F_ADC_CTRL_ADC_PU_POS 1 /**< ADC_PU Position */
<> 157:ff67d9f36b67 126 #define MXC_F_ADC_CTRL_ADC_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_PU_POS)) /**< ADC_PU Mask */
<> 157:ff67d9f36b67 127 #define MXC_F_ADC_CTRL_BUF_PU_POS 2 /**< BUF_PU Position */
<> 157:ff67d9f36b67 128 #define MXC_F_ADC_CTRL_BUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PU_POS)) /**< BUF_PU Mask */
<> 157:ff67d9f36b67 129 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS 3 /**< REFBUF_PU Position */
<> 157:ff67d9f36b67 130 #define MXC_F_ADC_CTRL_ADC_REFBUF_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFBUF_PU_POS)) /**< REFBUF_PU Mask */
<> 157:ff67d9f36b67 131 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS 4 /**< CHGPUMP_PU Position */
<> 157:ff67d9f36b67 132 #define MXC_F_ADC_CTRL_ADC_CHGPUMP_PU ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CHGPUMP_PU_POS)) /**< CHGPUMP_PU Mask */
<> 157:ff67d9f36b67 133 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS 5 /**< BUF_CHOP_DIS Position */
<> 157:ff67d9f36b67 134 #define MXC_F_ADC_CTRL_BUF_CHOP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_CHOP_DIS_POS)) /**< BUF_CHOP_DIS Mask */
<> 157:ff67d9f36b67 135 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS 6 /**< BUF_PUMP_DIS Position */
<> 157:ff67d9f36b67 136 #define MXC_F_ADC_CTRL_BUF_PUMP_DIS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_PUMP_DIS_POS)) /**< BUF_PUMP_DIS Mask */
<> 157:ff67d9f36b67 137 #define MXC_F_ADC_CTRL_BUF_BYPASS_POS 7 /**< BUF_BYPASS Position */
<> 157:ff67d9f36b67 138 #define MXC_F_ADC_CTRL_BUF_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_BUF_BYPASS_POS)) /**< BUF_BYPASS Mask */
<> 157:ff67d9f36b67 139 #define MXC_F_ADC_CTRL_ADC_REFSCL_POS 8 /**< ADC_REFSCL Position */
<> 157:ff67d9f36b67 140 #define MXC_F_ADC_CTRL_ADC_REFSCL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSCL_POS)) /**< ADC_REFSCL Mask */
<> 157:ff67d9f36b67 141 #define MXC_F_ADC_CTRL_ADC_SCALE_POS 9 /**< ADC_SCALE Position */
<> 157:ff67d9f36b67 142 #define MXC_F_ADC_CTRL_ADC_SCALE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_SCALE_POS)) /**< ADC_SCALE Mask */
<> 157:ff67d9f36b67 143 #define MXC_F_ADC_CTRL_ADC_REFSEL_POS 10 /**< ADC_REFSEL Position */
<> 157:ff67d9f36b67 144 #define MXC_F_ADC_CTRL_ADC_REFSEL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_REFSEL_POS)) /**< ADC_REFSEL Mask */
<> 157:ff67d9f36b67 145 #define MXC_F_ADC_CTRL_ADC_CLK_EN_POS 11 /**< ADC_CLK_EN Position */
<> 157:ff67d9f36b67 146 #define MXC_F_ADC_CTRL_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_CLK_EN_POS)) /**< ADC_CLK_EN Mask */
<> 157:ff67d9f36b67 147 #define MXC_F_ADC_CTRL_ADC_CHSEL_POS 12 /**< ADC_CHSEL Position */
<> 157:ff67d9f36b67 148 #define MXC_F_ADC_CTRL_ADC_CHSEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL_ADC_CHSEL_POS)) /**< ADC_CHSEL Mask */
<> 157:ff67d9f36b67 149
<> 157:ff67d9f36b67 150 #if (MXC_ADC_REV == 0)
<> 157:ff67d9f36b67 151 #define MXC_F_ADC_CTRL_ADC_XREF_POS 16 /**< ADC_XREF Position */
<> 157:ff67d9f36b67 152 #define MXC_F_ADC_CTRL_ADC_XREF ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_XREF_POS)) /**< ADC_XREF Mask */
<> 157:ff67d9f36b67 153 #endif
<> 157:ff67d9f36b67 154 #define MXC_F_ADC_CTRL_ADC_DATAALIGN_POS 17 /**< ADC_DATAALIGN Position */
<> 157:ff67d9f36b67 155 #define MXC_F_ADC_CTRL_ADC_DATAALIGN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL_ADC_DATAALIGN_POS)) /**< ADC_DATAALIGN Mask */
<> 157:ff67d9f36b67 156 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS 24 /**< AFE_PWR_UP_DLY Position */
<> 157:ff67d9f36b67 157 #define MXC_F_ADC_CTRL_AFE_PWR_UP_DLY ((uint32_t)(0x000000FFUL << MXC_F_ADC_CTRL_AFE_PWR_UP_DLY_POS)) /**< AFE_PWR_UP_DLY Mask */
<> 157:ff67d9f36b67 158
<> 157:ff67d9f36b67 159 /**@} end of group adc_ctrl_register */
<> 157:ff67d9f36b67 160
<> 157:ff67d9f36b67 161 /**
<> 157:ff67d9f36b67 162 * @ingroup adc_registers
<> 157:ff67d9f36b67 163 * @defgroup ADC_STATUS_Register ADC_STATUS
<> 157:ff67d9f36b67 164 * @brief Field Positions and Bit Masks for the ADC_STATUS register
<> 157:ff67d9f36b67 165 * @{
<> 157:ff67d9f36b67 166 */
<> 157:ff67d9f36b67 167 #define MXC_F_ADC_STATUS_ADC_ACTIVE_POS 0 /**< ADC_ACTIVE Position */
<> 157:ff67d9f36b67 168 #define MXC_F_ADC_STATUS_ADC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_ACTIVE_POS)) /**< ADC_ACTIVE Mask */
<> 157:ff67d9f36b67 169 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS 1 /**< RO_CAL_ATOMIC_ACTIVE Position */
<> 157:ff67d9f36b67 170 #define MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_RO_CAL_ATOMIC_ACTIVE_POS)) /**< RO_CAL_ATOMIC_ACTIVE Mask */
<> 157:ff67d9f36b67 171 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< AFE_PWR_UP_ACTIVE Position */
<> 157:ff67d9f36b67 172 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< AFE_PWR_UP_ACTIVE Mask */
<> 157:ff67d9f36b67 173 #define MXC_F_ADC_STATUS_ADC_OVERFLOW_POS 3 /**< ADC_OVERFLOW Position */
<> 157:ff67d9f36b67 174 #define MXC_F_ADC_STATUS_ADC_OVERFLOW ((uint32_t)(0x00000001UL << MXC_F_ADC_STATUS_ADC_OVERFLOW_POS)) /**< ADC_OVERFLOW Mask */
<> 157:ff67d9f36b67 175 /**@} end of group ADC_STATUS_register */
<> 157:ff67d9f36b67 176
<> 157:ff67d9f36b67 177 /**
<> 157:ff67d9f36b67 178 * @ingroup adc_registers
<> 157:ff67d9f36b67 179 * @defgroup ADC_DATA_Register ADC_DATA
<> 157:ff67d9f36b67 180 * @brief Field Positions and Bit Masks for the ADC_DATA register
<> 157:ff67d9f36b67 181 * @{
<> 157:ff67d9f36b67 182 */
<> 157:ff67d9f36b67 183 #define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< ADC_DATA Position */
<> 157:ff67d9f36b67 184 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< ADC_DATA Mask */
<> 157:ff67d9f36b67 185 /**@} end of group ADC_DATA_register */
<> 157:ff67d9f36b67 186
<> 157:ff67d9f36b67 187 /**
<> 157:ff67d9f36b67 188 * @ingroup adc_registers
<> 157:ff67d9f36b67 189 * @defgroup ADC_INTR_Register ADC_INTR Register
<> 157:ff67d9f36b67 190 * @brief Interrupt Enable and Interrupt Flag Field Positions and Bit Masks
<> 157:ff67d9f36b67 191 */
<> 157:ff67d9f36b67 192 /**
<> 157:ff67d9f36b67 193 * @ingroup ADC_INTR_Register
<> 157:ff67d9f36b67 194 * @defgroup ADC_INTR_IE_Register Interrupt Enable Bits
<> 157:ff67d9f36b67 195 * @brief Interrupt Enable Bit Positions and Masks
<> 157:ff67d9f36b67 196 * @{
<> 157:ff67d9f36b67 197 */
<> 157:ff67d9f36b67 198 #define MXC_F_ADC_INTR_ADC_DONE_IE_POS 0 /**< ADC_DONE_IE Position */
<> 157:ff67d9f36b67 199 #define MXC_F_ADC_INTR_ADC_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IE_POS)) /**< ADC_DONE_IE Mask */
<> 157:ff67d9f36b67 200 #define MXC_F_ADC_INTR_ADC_REF_READY_IE_POS 1 /**< ADC_REF_READY_IE Position */
<> 157:ff67d9f36b67 201 #define MXC_F_ADC_INTR_ADC_REF_READY_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IE_POS)) /**< ADC_REF_READY_IE Mask */
<> 157:ff67d9f36b67 202 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS 2 /**< ADC_HI_LIMIT_IE Position */
<> 157:ff67d9f36b67 203 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IE_POS)) /**< ADC_HI_LIMIT_IE Mask */
<> 157:ff67d9f36b67 204 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS 3 /**< ADC_LO_LIMIT_IE Position */
<> 157:ff67d9f36b67 205 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IE_POS)) /**< ADC_LO_LIMIT_IE Mask */
<> 157:ff67d9f36b67 206 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS 4 /**< ADC_OVERFLOW_IE Position */
<> 157:ff67d9f36b67 207 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IE_POS)) /**< ADC_OVERFLOW_IE Mask */
<> 157:ff67d9f36b67 208 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS 5 /**< RO_CAL_DONE_IE Position */
<> 157:ff67d9f36b67 209 #define MXC_F_ADC_INTR_RO_CAL_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IE_POS)) /**< RO_CAL_DONE_IE Mask */
<> 157:ff67d9f36b67 210 /**@} end of group ADC_INTR_IE_Register */
<> 157:ff67d9f36b67 211
<> 157:ff67d9f36b67 212
<> 157:ff67d9f36b67 213 /**
<> 157:ff67d9f36b67 214 * @ingroup ADC_INTR_Register
<> 157:ff67d9f36b67 215 * @defgroup ADC_INTR_IF_Register Interrupt Flag Bits
<> 157:ff67d9f36b67 216 * @brief Interrupt Flag Bit Positions and Masks
<> 157:ff67d9f36b67 217 * @{
<> 157:ff67d9f36b67 218 */
<> 157:ff67d9f36b67 219 #define MXC_F_ADC_INTR_ADC_DONE_IF_POS 16 /**< ADC_DONE_IF Position */
<> 157:ff67d9f36b67 220 #define MXC_F_ADC_INTR_ADC_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_DONE_IF_POS)) /**< ADC_DONE_IF Mask */
<> 157:ff67d9f36b67 221 #define MXC_F_ADC_INTR_ADC_REF_READY_IF_POS 17 /**< ADC_REF_READY_IF Position */
<> 157:ff67d9f36b67 222 #define MXC_F_ADC_INTR_ADC_REF_READY_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_REF_READY_IF_POS)) /**< ADC_REF_READY_IF Mask */
<> 157:ff67d9f36b67 223 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS 18 /**< ADC_HI_LIMIT_IF Position */
<> 157:ff67d9f36b67 224 #define MXC_F_ADC_INTR_ADC_HI_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_HI_LIMIT_IF_POS)) /**< ADC_HI_LIMIT_IF Mask */
<> 157:ff67d9f36b67 225 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS 19 /**< ADC_LO_LIMIT_IF Position */
<> 157:ff67d9f36b67 226 #define MXC_F_ADC_INTR_ADC_LO_LIMIT_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_LO_LIMIT_IF_POS)) /**< ADC_LO_LIMIT_IF Mask */
<> 157:ff67d9f36b67 227 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS 20 /**< ADC_OVERFLOW_IF Position */
<> 157:ff67d9f36b67 228 #define MXC_F_ADC_INTR_ADC_OVERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_OVERFLOW_IF_POS)) /**< ADC_OVERFLOW_IF Mask */
<> 157:ff67d9f36b67 229 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS 21 /**< RO_CAL_DONE_IF Position */
<> 157:ff67d9f36b67 230 #define MXC_F_ADC_INTR_RO_CAL_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_RO_CAL_DONE_IF_POS)) /**< RO_CAL_DONE_IF Mask */
<> 157:ff67d9f36b67 231 #define MXC_F_ADC_INTR_ADC_INT_PENDING_POS 22 /**< ADC_INT_PENDING Position */
<> 157:ff67d9f36b67 232 #define MXC_F_ADC_INTR_ADC_INT_PENDING ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_ADC_INT_PENDING_POS)) /**< ADC_INT_PENDING Mask */
<> 157:ff67d9f36b67 233 /**@} end of group ADC_INTR_IF_Register */
<> 157:ff67d9f36b67 234
<> 157:ff67d9f36b67 235 /**
<> 157:ff67d9f36b67 236 * @ingroup adc_registers
<> 157:ff67d9f36b67 237 * @defgroup ADC_LIMIT0_Register ADC_LIMIT0
<> 157:ff67d9f36b67 238 * @brief Field Positions and Bit Masks for the ADC_LIMIT0 register
<> 157:ff67d9f36b67 239 * @{
<> 157:ff67d9f36b67 240 */
<> 157:ff67d9f36b67 241 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
<> 157:ff67d9f36b67 242 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
<> 157:ff67d9f36b67 243 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
<> 157:ff67d9f36b67 244 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
<> 157:ff67d9f36b67 245 #define MXC_F_ADC_LIMIT0_CH_SEL_POS 24 /**< CH_SEL Position */
<> 157:ff67d9f36b67 246 #define MXC_F_ADC_LIMIT0_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT0_CH_SEL_POS)) /**< CH_SEL Mask */
<> 157:ff67d9f36b67 247 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
<> 157:ff67d9f36b67 248 #define MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
<> 157:ff67d9f36b67 249 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
<> 157:ff67d9f36b67 250 #define MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT0_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
<> 157:ff67d9f36b67 251 /**@} end of group ADC_LIMIT0_register */
<> 157:ff67d9f36b67 252
<> 157:ff67d9f36b67 253 /**
<> 157:ff67d9f36b67 254 * @ingroup adc_registers
<> 157:ff67d9f36b67 255 * @defgroup ADC_LIMIT1_Register ADC_LIMIT1
<> 157:ff67d9f36b67 256 * @brief Field Positions and Bit Masks for the ADC_LIMIT1 register
<> 157:ff67d9f36b67 257 * @{
<> 157:ff67d9f36b67 258 */
<> 157:ff67d9f36b67 259 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
<> 157:ff67d9f36b67 260 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
<> 157:ff67d9f36b67 261 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
<> 157:ff67d9f36b67 262 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
<> 157:ff67d9f36b67 263 #define MXC_F_ADC_LIMIT1_CH_SEL_POS 24 /**< CH_SEL Position */
<> 157:ff67d9f36b67 264 #define MXC_F_ADC_LIMIT1_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT1_CH_SEL_POS)) /**< CH_SEL Mask */
<> 157:ff67d9f36b67 265 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
<> 157:ff67d9f36b67 266 #define MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
<> 157:ff67d9f36b67 267 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
<> 157:ff67d9f36b67 268 #define MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT1_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
<> 157:ff67d9f36b67 269 /**@} end of group ADC_LIMIT1_register */
<> 157:ff67d9f36b67 270
<> 157:ff67d9f36b67 271 /**
<> 157:ff67d9f36b67 272 * @ingroup adc_registers
<> 157:ff67d9f36b67 273 * @defgroup ADC_LIMIT2_Register ADC_LIMIT2
<> 157:ff67d9f36b67 274 * @brief Field Positions and Bit Masks for the ADC_LIMIT2 register
<> 157:ff67d9f36b67 275 * @{
<> 157:ff67d9f36b67 276 */
<> 157:ff67d9f36b67 277 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
<> 157:ff67d9f36b67 278 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
<> 157:ff67d9f36b67 279 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
<> 157:ff67d9f36b67 280 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
<> 157:ff67d9f36b67 281 #define MXC_F_ADC_LIMIT2_CH_SEL_POS 24 /**< CH_SEL Position */
<> 157:ff67d9f36b67 282 #define MXC_F_ADC_LIMIT2_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT2_CH_SEL_POS)) /**< CH_SEL Mask */
<> 157:ff67d9f36b67 283 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
<> 157:ff67d9f36b67 284 #define MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
<> 157:ff67d9f36b67 285 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
<> 157:ff67d9f36b67 286 #define MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT2_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
<> 157:ff67d9f36b67 287 /**@} end of group ADC_LIMIT2_register */
<> 157:ff67d9f36b67 288
<> 157:ff67d9f36b67 289 /**
<> 157:ff67d9f36b67 290 * @ingroup adc_registers
<> 157:ff67d9f36b67 291 * @defgroup ADC_LIMIT3_Register ADC_LIMIT3
<> 157:ff67d9f36b67 292 * @brief Field Positions and Bit Masks for the ADC_LIMIT3 register
<> 157:ff67d9f36b67 293 * @{
<> 157:ff67d9f36b67 294 */
<> 157:ff67d9f36b67 295 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS 0 /**< CH_LO_LIMIT Position */
<> 157:ff67d9f36b67 296 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_POS)) /**< CH_LO_LIMIT Mask */
<> 157:ff67d9f36b67 297 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS 12 /**< CH_HI_LIMIT Position */
<> 157:ff67d9f36b67 298 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT ((uint32_t)(0x000003FFUL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_POS)) /**< CH_HI_LIMIT Mask */
<> 157:ff67d9f36b67 299 #define MXC_F_ADC_LIMIT3_CH_SEL_POS 24 /**< CH_SEL Position */
<> 157:ff67d9f36b67 300 #define MXC_F_ADC_LIMIT3_CH_SEL ((uint32_t)(0x0000000FUL << MXC_F_ADC_LIMIT3_CH_SEL_POS)) /**< CH_SEL Mask */
<> 157:ff67d9f36b67 301 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS 28 /**< CH_LO_LIMIT_EN Position */
<> 157:ff67d9f36b67 302 #define MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_LO_LIMIT_EN_POS)) /**< CH_LO_LIMIT_EN Mask */
<> 157:ff67d9f36b67 303 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS 29 /**< CH_HI_LIMIT_EN Position */
<> 157:ff67d9f36b67 304 #define MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_LIMIT3_CH_HI_LIMIT_EN_POS)) /**< CH_HI_LIMIT_EN Mask */
<> 157:ff67d9f36b67 305 /**@} end of group ADC_LIMIT3_register */
<> 157:ff67d9f36b67 306
<> 157:ff67d9f36b67 307 /**
<> 157:ff67d9f36b67 308 * @ingroup adc_registers
<> 157:ff67d9f36b67 309 * @defgroup ADC_AFE_CTRL_Register ADC_AFE_CTRL
<> 157:ff67d9f36b67 310 * @brief Field Positions and Bit Masks for the ADC_AFE_CTRL register
<> 157:ff67d9f36b67 311 * @{
<> 157:ff67d9f36b67 312 */
<> 157:ff67d9f36b67 313 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS 8 /**< TMON_INTBIAS_EN Position */
<> 157:ff67d9f36b67 314 #define MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_INTBIAS_EN_POS)) /**< TMON_INTBIAS_EN Mask */
<> 157:ff67d9f36b67 315 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS 9 /**< TMON_EXTBIAS_EN Position */
<> 157:ff67d9f36b67 316 #define MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_AFE_CTRL_TMON_EXTBIAS_EN_POS)) /**< TMON_EXTBIAS_EN Mask */
<> 157:ff67d9f36b67 317 /**@} end of group ADC_AFE_CTRL_register */
<> 157:ff67d9f36b67 318
<> 157:ff67d9f36b67 319 /**
<> 157:ff67d9f36b67 320 * @ingroup adc_registers
<> 157:ff67d9f36b67 321 * @defgroup ADC_RO_CAL0_Register ADC_RO_CAL0
<> 157:ff67d9f36b67 322 * @brief Field Positions and Bit Masks for the ADC_RO_CAL0 register
<> 157:ff67d9f36b67 323 * @{
<> 157:ff67d9f36b67 324 */
<> 157:ff67d9f36b67 325 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0 /**< RO_CAL_EN Position */
<> 157:ff67d9f36b67 326 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS)) /**< RO_CAL_EN Mask */
<> 157:ff67d9f36b67 327 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1 /**< RO_CAL_RUN Position */
<> 157:ff67d9f36b67 328 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS)) /**< RO_CAL_RUN Mask */
<> 157:ff67d9f36b67 329 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2 /**< RO_CAL_LOAD Position */
<> 157:ff67d9f36b67 330 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS)) /**< RO_CAL_LOAD Mask */
<> 157:ff67d9f36b67 331 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS 4 /**< RO_CAL_ATOMIC Position */
<> 157:ff67d9f36b67 332 #define MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC_POS)) /**< RO_CAL_ATOMIC Mask */
<> 157:ff67d9f36b67 333 #define MXC_F_ADC_RO_CAL0_DUMMY_POS 5 /**< DUMMY Position */
<> 157:ff67d9f36b67 334 #define MXC_F_ADC_RO_CAL0_DUMMY ((uint32_t)(0x00000007UL << MXC_F_ADC_RO_CAL0_DUMMY_POS)) /**< DUMMY Mask */
<> 157:ff67d9f36b67 335 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8 /**< TRM_MU Position */
<> 157:ff67d9f36b67 336 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS)) /**< TRM_MU Mask */
<> 157:ff67d9f36b67 337 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23 /**< RO_TRM Position */
<> 157:ff67d9f36b67 338 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS)) /**< RO_TRM Mask */
<> 157:ff67d9f36b67 339 /**@} end of group ADC_RO_CAL0_register */
<> 157:ff67d9f36b67 340
<> 157:ff67d9f36b67 341 /**
<> 157:ff67d9f36b67 342 * @ingroup adc_registers
<> 157:ff67d9f36b67 343 * @defgroup ADC_RO_CAL1_Register ADC_RO_CAL1
<> 157:ff67d9f36b67 344 * @brief Field Positions and Bit Masks for the ADC_RO_CAL1 register
<> 157:ff67d9f36b67 345 * @{
<> 157:ff67d9f36b67 346 */
<> 157:ff67d9f36b67 347 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0 /**< TRM_INIT Position */
<> 157:ff67d9f36b67 348 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS)) /**< TRM_INIT Mask */
<> 157:ff67d9f36b67 349 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10 /**< TRM_MIN Position */
<> 157:ff67d9f36b67 350 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS)) /**< TRM_MIN Mask */
<> 157:ff67d9f36b67 351 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20 /**< TRM_MAX Position */
<> 157:ff67d9f36b67 352 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS)) /**< TRM_MAX Mask */
<> 157:ff67d9f36b67 353 /**@} end of group RO_CAL1_register */
<> 157:ff67d9f36b67 354
<> 157:ff67d9f36b67 355 /**
<> 157:ff67d9f36b67 356 * @ingroup adc_registers
<> 157:ff67d9f36b67 357 * @defgroup ADC_RO_CAL2_Register ADC_RO_CAL2
<> 157:ff67d9f36b67 358 * @brief Field Positions and Bit Masks for the ADC_RO_CAL2 register
<> 157:ff67d9f36b67 359 * @{
<> 157:ff67d9f36b67 360 */
<> 157:ff67d9f36b67 361 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS 0 /**< AUTO_CAL_DONE_CNT Position */
<> 157:ff67d9f36b67 362 #define MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT ((uint32_t)(0x000000FFUL << MXC_F_ADC_RO_CAL2_AUTO_CAL_DONE_CNT_POS)) /**< AUTO_CAL_DONE_CNT Mask */
<> 157:ff67d9f36b67 363 /**@} end of group RO_CAL2_register */
<> 157:ff67d9f36b67 364
<> 157:ff67d9f36b67 365 /**
<> 157:ff67d9f36b67 366 * @ingroup ADC_CTRL_Register
<> 157:ff67d9f36b67 367 * @defgroup ADC_CHSEL_values ADC Channel Select Values
<> 157:ff67d9f36b67 368 * @brief Channel Select Values
<> 157:ff67d9f36b67 369 * @{
<> 157:ff67d9f36b67 370 */
<> 157:ff67d9f36b67 371 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0 ((uint32_t)(0x00000000UL)) /**< Channel 0 Select */
<> 157:ff67d9f36b67 372 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1 ((uint32_t)(0x00000001UL)) /**< Channel 1 Select */
<> 157:ff67d9f36b67 373 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN2 ((uint32_t)(0x00000002UL)) /**< Channel 2 Select */
<> 157:ff67d9f36b67 374 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN3 ((uint32_t)(0x00000003UL)) /**< Channel 3 Select */
<> 157:ff67d9f36b67 375 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN0_DIV_5 ((uint32_t)(0x00000004UL)) /**< Channel 0 divided by 5 */
<> 157:ff67d9f36b67 376 #define MXC_V_ADC_CTRL_ADC_CHSEL_AIN1_DIV_5 ((uint32_t)(0x00000005UL)) /**< Channel 1 divided by 5 */
<> 157:ff67d9f36b67 377 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDB_DIV_4 ((uint32_t)(0x00000006UL)) /**< VDDB divided by 4 */
<> 157:ff67d9f36b67 378 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD18 ((uint32_t)(0x00000007UL)) /**< VDD18 input select */
<> 157:ff67d9f36b67 379 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDD12 ((uint32_t)(0x00000008UL)) /**< VDD12 input select */
<> 157:ff67d9f36b67 380 #define MXC_V_ADC_CTRL_ADC_CHSEL_VRTC_DIV_2 ((uint32_t)(0x00000009UL)) /**< VRTC divided by 2 */
<> 157:ff67d9f36b67 381 #define MXC_V_ADC_CTRL_ADC_CHSEL_TMON ((uint32_t)(0x0000000AUL)) /**< TMON input select */
<> 157:ff67d9f36b67 382
<> 157:ff67d9f36b67 383 #if(MXC_ADC_REV > 0)
<> 157:ff67d9f36b67 384 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIO_DIV_4 ((uint32_t)(0x0000000BUL)) /**< VDDIO divided by 4 select */
<> 157:ff67d9f36b67 385 #define MXC_V_ADC_CTRL_ADC_CHSEL_VDDIOH_DIV_4 ((uint32_t)(0x0000000CUL)) /**< VDDIOH divided by 4 select */
<> 157:ff67d9f36b67 386 #endif
<> 157:ff67d9f36b67 387 /**@} end of group ADC_CHSEL_values */
<> 157:ff67d9f36b67 388
<> 157:ff67d9f36b67 389 #ifdef __cplusplus
<> 157:ff67d9f36b67 390 }
<> 157:ff67d9f36b67 391 #endif
<> 157:ff67d9f36b67 392
<> 157:ff67d9f36b67 393 #endif /* _MXC_ADC_REGS_H_ */