Amit Gandhi / mbed-dev

test

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/objects.h@153:fa9ff456f731, 2016-12-20 (annotated)

Committer:
<>
Date:
Tue Dec 20 17:27:56 2016 +0000
Revision:
153:fa9ff456f731
Parent:
150:02e0a0aed4ec 
This updates the lib to the mbed lib v132

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file Objects.h
<> 149:156823d33999 4 * @brief Implements an assertion.
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 0.1 $
<> 149:156823d33999 8 * $Date: 2015-11-06 $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup debug
<> 149:156823d33999 28 */
<> 149:156823d33999 29 #ifndef OBJECTS_H_
<> 149:156823d33999 30 #define OBJECTS_H_
<> 149:156823d33999 31
<> 149:156823d33999 32
<> 149:156823d33999 33 #ifdef __cplusplus
<> 149:156823d33999 34 extern "C" {
<> 149:156823d33999 35 #endif
<> 149:156823d33999 36
<> 149:156823d33999 37 #include "gpio_map.h"
<> 149:156823d33999 38 #include "uart_16c550_map.h"
<> 149:156823d33999 39 #include "PinNames.h"
<> 149:156823d33999 40 #include "PortNames.h"
<> 149:156823d33999 41 #include "PeripheralNames.h"
<> 149:156823d33999 42 #include "target_config.h"
<> 149:156823d33999 43 #include "spi.h"
<> 149:156823d33999 44
<> 149:156823d33999 45 typedef enum {
<> 149:156823d33999 46 FlowControlNone_1,
<> 149:156823d33999 47 FlowControlRTS_1,
<> 149:156823d33999 48 FlowControlCTS_1,
<> 149:156823d33999 49 FlowControlRTSCTS_1
<> 149:156823d33999 50 } FlowControl_1;
<> 149:156823d33999 51
<> 149:156823d33999 52 struct serial_s {
<> 149:156823d33999 53 Uart16C550Reg_pt UARTREG;
<> 149:156823d33999 54 FlowControl_1 FlowCtrl;
<> 149:156823d33999 55 IRQn_Type IRQType;
<> 149:156823d33999 56 int index;
<> 149:156823d33999 57 };
<> 149:156823d33999 58
<> 149:156823d33999 59 typedef struct _gpio_t {
<> 149:156823d33999 60 GpioReg_pt GPIOMEMBASE;
<> 149:156823d33999 61 PinName gpioPin;
<> 149:156823d33999 62 uint32_t gpioMask;
<> 149:156823d33999 63
<> 149:156823d33999 64 } gpio_t;
<> 149:156823d33999 65
<> 149:156823d33999 66
<> 149:156823d33999 67 /* TODO: This is currently a dummy structure; implementation will be done along
<> 149:156823d33999 68 * with the sleep API implementation
<> 149:156823d33999 69 */
<> 149:156823d33999 70 typedef struct sleep_s {
<> 149:156823d33999 71 uint32_t timeToSleep; /* 0: Use sleep type variable to select low power mode; Noz-zero: Selects sleep type based on timeToSleep duration using table 1. sleep below */
<> 149:156823d33999 72 uint8_t SleepType; /* 0: Sleep; 1: DeepSleep; 2: Coma */
<> 149:156823d33999 73 } sleep_t;
<> 149:156823d33999 74
<> 149:156823d33999 75 /* Table 1. Sleep
<> 149:156823d33999 76 ___________________________________________________________________________________
<> 149:156823d33999 77 | Sleep duration | Sleep Type |
<> 149:156823d33999 78 |-------------------------------------------------------------------|---------------|
<> 149:156823d33999 79 | > Zero AND <= SLEEP_DURATION_SLEEP_MAX | sleep |
<> 149:156823d33999 80 | > SLEEP_DURATION_SLEEP_MAX AND <= SLEEP_DURATION_DEEPSLEEP_MAX | deepsleep |
<> 149:156823d33999 81 | > SLEEP_DURATION_DEEPSLEEP_MAX | coma |
<> 149:156823d33999 82 |___________________________________________________________________|_______________|
<> 149:156823d33999 83
<> 149:156823d33999 84 */
<> 149:156823d33999 85
<> 149:156823d33999 86 struct gpio_irq_s {
<> 149:156823d33999 87 uint32_t pin;
<> 149:156823d33999 88 uint32_t pinMask;
<> 149:156823d33999 89 GpioReg_pt GPIOMEMBASE;
<> 149:156823d33999 90 };
<> 149:156823d33999 91
<> 149:156823d33999 92 typedef struct {
<> 149:156823d33999 93
<> 149:156823d33999 94 /* options to configure the ADC */
<> 149:156823d33999 95 uint8_t interruptConfig; /**< 1= interrupt Enable 0=Interrupt Disable */
<> 149:156823d33999 96 uint8_t PrescaleVal; /**< Prescaler: Sets the converter clock frequency. Fclk = 32 MHz/(prescaler + 1) where prescaler is the value of this register segment. The minimum tested value is 07 (4 MHz clock) */
<> 149:156823d33999 97 uint8_t measurementType; /**< 1= Absolute 0= Differential */
<> 149:156823d33999 98 uint8_t mode; /**< 1= Continuous Conversion 0= Single Shot */
<> 149:156823d33999 99 uint8_t referenceCh; /**< Selects 1 to 8 channels for reference channel */
<> 149:156823d33999 100 uint8_t convCh; /**< Selects 1 or 8 channels to do a conversion on.*/
<> 149:156823d33999 101 uint8_t inputScale; /**< Sets the input scale, 000 ? 1.0, 001 ? 0.6923, 010 ? 0.5294, 011 ? 0.4286, 100 ? 0.3600, 101 ? 0.3103, 110 ? 0.2728, 111 ? 0.2432 */
<> 149:156823d33999 102 uint8_t samplingTime; /**< Sample Time. Sets the measure time in units of PCLKperiod * (Prescale + 1).*/
<> 149:156823d33999 103 uint8_t WarmUpTime; /**< The number of converter clock cycles that the state machine dwells in the warm or warm_meas state */
<> 149:156823d33999 104 uint16_t samplingRate; /**< Sets the sample rate in units of PCLKperiod * (Prescale + 1). */
<> 149:156823d33999 105
<> 149:156823d33999 106 } analog_config_s;
<> 149:156823d33999 107
<> 149:156823d33999 108 struct analogin_s {
<> 149:156823d33999 109
<> 149:156823d33999 110 analog_config_s *adcConf;
<> 149:156823d33999 111 AdcReg_pt adcReg;
<> 149:156823d33999 112 PinName pin;
<> 149:156823d33999 113 uint8_t pinFlag;
<> 153:fa9ff456f731 114 uint32_t ADC_Offset_Value;
<> 149:156823d33999 115 };
<> 149:156823d33999 116
<> 149:156823d33999 117 struct pwmout_s {
<> 149:156823d33999 118
<> 149:156823d33999 119 PwmReg_pt pwmReg;
<> 149:156823d33999 120 };
<> 149:156823d33999 121
<> 149:156823d33999 122 struct port_s {
<> 149:156823d33999 123 GpioReg_pt GPIOMEMBASE;
<> 149:156823d33999 124 PortName port;
<> 149:156823d33999 125 uint32_t mask;
<> 149:156823d33999 126 };
<> 149:156823d33999 127
<> 149:156823d33999 128 typedef enum {
<> 149:156823d33999 129 littleEndian = 0,
<> 149:156823d33999 130 bigEndian
<> 149:156823d33999 131 } spi_ipc7207_endian_t, *spi_ipc7207_endian_pt;
<> 149:156823d33999 132
<> 149:156823d33999 133 /** Type for the clock polarity. */
<> 149:156823d33999 134 typedef enum {
<> 149:156823d33999 135 activeLow = 0,
<> 149:156823d33999 136 activeHigh
<> 149:156823d33999 137 } spi_clockPolarity_t, *spi_clockPolarity_pt;
<> 149:156823d33999 138
<> 149:156823d33999 139 /** Type for the clock phase. */
<> 149:156823d33999 140 typedef enum {
<> 149:156823d33999 141 risingEdge = 0,
<> 149:156823d33999 142 fallingEdge
<> 149:156823d33999 143 } spi_clockPhase_t, *spi_clockPhase_pt;
<> 149:156823d33999 144
<> 149:156823d33999 145 struct spi_s {
<> 149:156823d33999 146 SpiIpc7207Reg_pt membase; /* Register address */
<> 149:156823d33999 147 IRQn_Type irq; /* IRQ number of the IRQ associated to the device. */
<> 149:156823d33999 148 uint8_t irqEnable; /* IRQ enables for 8 IRQ sources:
<> 149:156823d33999 149 * - bit 7 = Receive FIFO Full
<> 149:156823d33999 150 * - bit 6 = Receive FIFO 'Half' Full (watermark level)
<> 149:156823d33999 151 * - bit 5 = Receive FIFO Not Empty
<> 149:156823d33999 152 * - bit 4 = Transmit FIFO Not Full
<> 149:156823d33999 153 * - bit 3 = Transmit FIFO 'Half' Empty (watermark level)
<> 149:156823d33999 154 * - bit 2 = Transmit FIFO Empty
<> 149:156823d33999 155 * - bit 1 = Transfer Error
<> 149:156823d33999 156 * - bit 0 = ssIn (conditionally inverted and synchronized to PCLK)
<> 149:156823d33999 157 * (unused option in current implementation / irq 6 and 7 used) */
<> 149:156823d33999 158 uint8_t slaveSelectEnable; /* Slave Select enables (x4):
<> 149:156823d33999 159 * - 0 (x4) = Slave select enable
<> 149:156823d33999 160 * - 1 (x4) = Slave select disable */
<> 149:156823d33999 161 uint8_t slaveSelectBurst; /* Slave Select burst mode:
<> 149:156823d33999 162 * - NO_BURST_MODE = Burst mode disable
<> 149:156823d33999 163 * - BURST_MODE = Burst mode enable */
<> 149:156823d33999 164 uint8_t slaveSelectPolarity; /* Slave Select polarity (x4) for up to 4 slaves:
<> 149:156823d33999 165 * - 0 (x4) = Slave select is active low
<> 149:156823d33999 166 * - 1 (x4) = Slave select is active high */
<> 149:156823d33999 167 uint8_t txWatermark; /* Transmit FIFO Watermark: Defines level of RX Half Full Flag
<> 149:156823d33999 168 * - Value between 1 and 15
<> 149:156823d33999 169 * (unused option in current implementation / not txWatermark irq used) */
<> 149:156823d33999 170 uint8_t rxWatermark; /* Receive FIFO Watermark: Defines level of TX Half Full Flag:
<> 149:156823d33999 171 * - Value between 1 and 15
<> 149:156823d33999 172 * * (unused option in current implementation / rxWatermark fixed to 1) */
<> 150:02e0a0aed4ec 173 spi_ipc7207_endian_t endian; /* Bits endianness:
<> 149:156823d33999 174 * - LITTLE_ENDIAN = LSB first
<> 149:156823d33999 175 * - BIG_ENDIAN = MSB first */
<> 149:156823d33999 176 uint8_t samplingEdge; /* SDI sampling edge (relative to SDO sampling edge):
<> 149:156823d33999 177 * - 0 = opposite to SDO sampling edge
<> 149:156823d33999 178 * - 1 = same as SDO sampling edge */
<> 149:156823d33999 179 uint32_t baudrate; /* The expected baud rate. */
<> 149:156823d33999 180 spi_clockPolarity_t clockPolarity; /* The clock polarity (active high or low). */
<> 149:156823d33999 181 spi_clockPhase_t clockPhase; /* The clock phase (sample on rising or falling edge). */
<> 149:156823d33999 182 uint8_t wordSize; /* The size word size in number of bits. */
<> 149:156823d33999 183 uint8_t Mode;
<> 149:156823d33999 184 uint32_t event;
<> 149:156823d33999 185 };
<> 149:156823d33999 186
<> 149:156823d33999 187 struct i2c_s {
<> 149:156823d33999 188 uint32_t baudrate; /**< The expected baud rate. */
<> 149:156823d33999 189 uint32_t I2cStatusFromInt;
<> 149:156823d33999 190 uint8_t ClockSource; /**< I2C clock source, 0 – clkI2C pin, 1 – PCLK */
<> 149:156823d33999 191 uint8_t irqEnable; /**< IRQs to be enabled */
<> 149:156823d33999 192 I2cIpc7208Reg_pt membase; /**< The memory base for the device's registers. */
<> 149:156823d33999 193 IRQn_Type irq; /**< The IRQ number of the IRQ associated to the device. */
<> 149:156823d33999 194 //queue_pt rxQueue; /**< The receive queue for the device instance. */
<> 149:156823d33999 195 };
<> 149:156823d33999 196
<> 150:02e0a0aed4ec 197 struct trng_s {
<> 150:02e0a0aed4ec 198 RandReg_pt membase; /**< The memory base for the device's registers. */
<> 150:02e0a0aed4ec 199 };
<> 150:02e0a0aed4ec 200
<> 149:156823d33999 201 #ifdef __cplusplus
<> 149:156823d33999 202 }
<> 149:156823d33999 203 #endif
<> 149:156823d33999 204
<> 149:156823d33999 205 #endif //OBJECTS_H_