test
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targets/TARGET_NXP/TARGET_LPC81X/pinmap.c@178:d650f5d4c87a, 2017-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Nov 08 13:50:44 2017 +0000
- Revision:
- 178:d650f5d4c87a
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v 155
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include "mbed_assert.h" |
<> | 144:ef7eb2e8f9f7 | 17 | #include "pinmap.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "mbed_error.h" |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | __IO uint32_t* IOCON_REGISTERS[18] = { |
<> | 144:ef7eb2e8f9f7 | 21 | &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 , |
<> | 144:ef7eb2e8f9f7 | 22 | &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 , |
<> | 144:ef7eb2e8f9f7 | 23 | &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 , |
<> | 144:ef7eb2e8f9f7 | 24 | &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11, |
<> | 144:ef7eb2e8f9f7 | 25 | &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14, |
<> | 144:ef7eb2e8f9f7 | 26 | &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17, |
<> | 144:ef7eb2e8f9f7 | 27 | }; |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | void pin_function(PinName pin, int function) { |
<> | 144:ef7eb2e8f9f7 | 30 | if (function == 0) { |
<> | 144:ef7eb2e8f9f7 | 31 | // Disable initial fixed function for P0_2, P0_3 and P0_5 |
<> | 144:ef7eb2e8f9f7 | 32 | uint32_t enable = 0; |
<> | 144:ef7eb2e8f9f7 | 33 | if (pin == P0_2) |
<> | 144:ef7eb2e8f9f7 | 34 | enable = 1 << 3; |
<> | 144:ef7eb2e8f9f7 | 35 | else if (pin == P0_3) |
<> | 144:ef7eb2e8f9f7 | 36 | enable = 1 << 2; |
<> | 144:ef7eb2e8f9f7 | 37 | else if (pin == P0_5) |
<> | 144:ef7eb2e8f9f7 | 38 | enable = 1 << 6; |
<> | 144:ef7eb2e8f9f7 | 39 | LPC_SWM->PINENABLE0 |= enable; |
<> | 144:ef7eb2e8f9f7 | 40 | } |
<> | 144:ef7eb2e8f9f7 | 41 | } |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | void pin_mode(PinName pin, PinMode mode) { |
<> | 144:ef7eb2e8f9f7 | 44 | MBED_ASSERT(pin != (PinName)NC); |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | if ((pin == 10) || (pin == 11)) { |
<> | 144:ef7eb2e8f9f7 | 47 | // True open-drain pins can be configured for different I2C-bus speeds |
<> | 144:ef7eb2e8f9f7 | 48 | return; |
<> | 144:ef7eb2e8f9f7 | 49 | } |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | __IO uint32_t *reg = IOCON_REGISTERS[pin]; |
<> | 144:ef7eb2e8f9f7 | 52 | |
<> | 144:ef7eb2e8f9f7 | 53 | if (mode == OpenDrain) { |
<> | 144:ef7eb2e8f9f7 | 54 | *reg |= (1 << 10); |
<> | 144:ef7eb2e8f9f7 | 55 | } else { |
<> | 144:ef7eb2e8f9f7 | 56 | uint32_t tmp = *reg; |
<> | 144:ef7eb2e8f9f7 | 57 | tmp &= ~(0x3 << 3); |
<> | 144:ef7eb2e8f9f7 | 58 | tmp |= (mode & 0x3) << 3; |
<> | 144:ef7eb2e8f9f7 | 59 | *reg = tmp; |
<> | 144:ef7eb2e8f9f7 | 60 | } |
<> | 144:ef7eb2e8f9f7 | 61 | } |