Amit Gandhi / mbed-dev

test

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
150:02e0a0aed4ec 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (c) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *******************************************************************************
<> 150:02e0a0aed4ec 32 */
<> 150:02e0a0aed4ec 33
<> 150:02e0a0aed4ec 34 #include "device.h"
<> 150:02e0a0aed4ec 35 #include "PeripheralPins.h"
<> 150:02e0a0aed4ec 36 #include "ioman_regs.h"
<> 150:02e0a0aed4ec 37 #include "ioman.h"
<> 150:02e0a0aed4ec 38 #include "adc.h"
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 /*
<> 150:02e0a0aed4ec 41 * To select a peripheral function on Maxim microcontrollers, multiple
<> 150:02e0a0aed4ec 42 * configurations must be made. The mbed PinMap structure only includes one
<> 150:02e0a0aed4ec 43 * data member to hold this information. To extend the configuration storage,
<> 150:02e0a0aed4ec 44 * the "function" data member is used as a pointer to a pin_function_t
<> 150:02e0a0aed4ec 45 * structure. This structure is defined in objects.h. The definitions below
<> 150:02e0a0aed4ec 46 * include the creation of the pin_function_t structures and the assignment of
<> 150:02e0a0aed4ec 47 * the pointers to the "function" data members.
<> 150:02e0a0aed4ec 48 */
<> 150:02e0a0aed4ec 49
<> 150:02e0a0aed4ec 50 #ifdef TOOLCHAIN_ARM_STD
<> 150:02e0a0aed4ec 51 #pragma diag_suppress 1296
<> 150:02e0a0aed4ec 52 #endif
<> 150:02e0a0aed4ec 53
<> 150:02e0a0aed4ec 54 /************I2C***************/
<> 150:02e0a0aed4ec 55 const PinMap PinMap_I2C_SDA[] = {
<> 150:02e0a0aed4ec 56 { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
<> 150:02e0a0aed4ec 57 { P3_4, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK}) },
<> 150:02e0a0aed4ec 58 { NC, NC, 0 }
<> 150:02e0a0aed4ec 59 };
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 const PinMap PinMap_I2C_SCL[] = {
<> 150:02e0a0aed4ec 62 { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK}) },
<> 150:02e0a0aed4ec 63 { P3_5, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ, MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK}) },
<> 150:02e0a0aed4ec 64 { NC, NC, 0 }
<> 150:02e0a0aed4ec 65 };
<> 150:02e0a0aed4ec 66
<> 150:02e0a0aed4ec 67 /************UART***************/
<> 150:02e0a0aed4ec 68 const PinMap PinMap_UART_TX[] = {
<> 150:02e0a0aed4ec 69 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 70 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 71 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 72 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 73 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 74 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 75 { NC, NC, 0 }
<> 150:02e0a0aed4ec 76 };
<> 150:02e0a0aed4ec 77
<> 150:02e0a0aed4ec 78 const PinMap PinMap_UART_RX[] = {
<> 150:02e0a0aed4ec 79 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 80 { P2_0, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 81 { P3_0, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 82 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_IO_REQ), (MXC_F_IOMAN_UART0_ACK_IO_MAP | MXC_F_IOMAN_UART0_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 83 { P2_1, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_IO_REQ), (MXC_F_IOMAN_UART1_ACK_IO_MAP | MXC_F_IOMAN_UART1_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 84 { P3_1, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_IO_REQ), (MXC_F_IOMAN_UART2_ACK_IO_MAP | MXC_F_IOMAN_UART2_ACK_IO_ACK)}) },
<> 150:02e0a0aed4ec 85 { NC, NC, 0 }
<> 150:02e0a0aed4ec 86 };
<> 150:02e0a0aed4ec 87
<> 150:02e0a0aed4ec 88 const PinMap PinMap_UART_CTS[] = {
<> 150:02e0a0aed4ec 89 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 90 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 91 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 92 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_CTS_MAP | MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 93 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_CTS_MAP | MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 94 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_CTS_MAP | MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 95 { NC, NC, 0 }
<> 150:02e0a0aed4ec 96 };
<> 150:02e0a0aed4ec 97
<> 150:02e0a0aed4ec 98 const PinMap PinMap_UART_RTS[] = {
<> 150:02e0a0aed4ec 99 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 100 { P2_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 101 { P3_3, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_A | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 102 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART0_ACK_RTS_MAP | MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 103 { P2_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART1_ACK_RTS_MAP | MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 104 { P3_2, UART_2, (int)&((pin_function_t){&MXC_IOMAN->uart2_req, &MXC_IOMAN->uart2_ack, ((uint32_t)IOMAN_MAP_B | MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ), (MXC_F_IOMAN_UART2_ACK_RTS_MAP | MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK)}) },
<> 150:02e0a0aed4ec 105 { NC, NC, 0 }
<> 150:02e0a0aed4ec 106 };
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 /************SPI***************/
<> 150:02e0a0aed4ec 109 const PinMap PinMap_SPI_SCLK[] = {
<> 150:02e0a0aed4ec 110 { P0_4, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 111 { P1_0, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 112 { P2_4, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 113 { NC, NC, 0 }
<> 150:02e0a0aed4ec 114 };
<> 150:02e0a0aed4ec 115
<> 150:02e0a0aed4ec 116 const PinMap PinMap_SPI_MOSI[] = {
<> 150:02e0a0aed4ec 117 { P0_5, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 118 { P1_1, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 119 { P2_5, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 120 { NC, NC, 0 }
<> 150:02e0a0aed4ec 121 };
<> 150:02e0a0aed4ec 122
<> 150:02e0a0aed4ec 123 const PinMap PinMap_SPI_MISO[] = {
<> 150:02e0a0aed4ec 124 { P0_6, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 125 { P1_2, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 126 { P2_6, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK}) },
<> 150:02e0a0aed4ec 127 { NC, NC, 0 }
<> 150:02e0a0aed4ec 128 };
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 const PinMap PinMap_SPI_SSEL[] = {
<> 150:02e0a0aed4ec 131 { P0_7, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spim0_req, &MXC_IOMAN->spim0_ack, MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK}) },
<> 150:02e0a0aed4ec 132 { P1_3, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spim1_req, &MXC_IOMAN->spim1_ack, MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK}) },
<> 150:02e0a0aed4ec 133 { P2_7, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spim2_req, &MXC_IOMAN->spim2_ack, MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ, MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK}) },
<> 150:02e0a0aed4ec 134 { NC, NC, 0 }
<> 150:02e0a0aed4ec 135 };
<> 150:02e0a0aed4ec 136
<> 150:02e0a0aed4ec 137 /************PWM***************/
<> 150:02e0a0aed4ec 138 const PinMap PinMap_PWM[] = {
<> 150:02e0a0aed4ec 139 { P0_0, PWM_0, 1 }, { P2_0, PWM_0, 1 }, { P4_0, PWM_0, 1 },
<> 150:02e0a0aed4ec 140 { P0_1, PWM_1, 1 }, { P2_1, PWM_1, 1 }, { P4_1, PWM_1, 1 },
<> 150:02e0a0aed4ec 141 { P0_2, PWM_2, 1 }, { P2_2, PWM_2, 1 }, { P4_2, PWM_2, 1 },
<> 150:02e0a0aed4ec 142 { P0_3, PWM_3, 1 }, { P2_3, PWM_3, 1 }, { P4_3, PWM_3, 1 },
<> 150:02e0a0aed4ec 143 { P0_4, PWM_4, 1 }, { P2_4, PWM_4, 1 }, { P4_4, PWM_4, 1 },
<> 150:02e0a0aed4ec 144 { P0_5, PWM_5, 1 }, { P2_5, PWM_5, 1 }, { P4_5, PWM_5, 1 },
<> 150:02e0a0aed4ec 145 { P0_6, PWM_6, 1 }, { P2_6, PWM_6, 1 }, { P4_6, PWM_6, 1 },
<> 150:02e0a0aed4ec 146 { P0_7, PWM_7, 1 }, { P2_7, PWM_7, 1 }, { P4_7, PWM_7, 1 },
<> 150:02e0a0aed4ec 147 { P1_0, PWM_8, 1 }, { P3_0, PWM_8, 1 },
<> 150:02e0a0aed4ec 148 { P1_1, PWM_9, 1 }, { P3_1, PWM_9, 1 },
<> 150:02e0a0aed4ec 149 { P1_2, PWM_10, 1 }, { P3_2, PWM_10, 1 },
<> 150:02e0a0aed4ec 150 { P1_3, PWM_11, 1 }, { P3_3, PWM_11, 1 },
<> 150:02e0a0aed4ec 151 { P1_4, PWM_12, 1 }, { P3_4, PWM_12, 1 },
<> 150:02e0a0aed4ec 152 { P1_5, PWM_13, 1 }, { P3_5, PWM_13, 1 },
<> 150:02e0a0aed4ec 153 { P1_6, PWM_14, 1 }, { P3_6, PWM_14, 1 },
<> 150:02e0a0aed4ec 154 { P1_7, PWM_15, 1 }, { P3_7, PWM_15, 1 },
<> 150:02e0a0aed4ec 155 { NC, NC, 0 }
<> 150:02e0a0aed4ec 156 };
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158 /************ADC***************/
<> 150:02e0a0aed4ec 159 const PinMap PinMap_ADC[] = {
<> 150:02e0a0aed4ec 160 { AIN_0, ADC, ADC_CH_0 },
<> 150:02e0a0aed4ec 161 { AIN_1, ADC, ADC_CH_1 },
<> 150:02e0a0aed4ec 162 { AIN_2, ADC, ADC_CH_2 },
<> 150:02e0a0aed4ec 163 { AIN_3, ADC, ADC_CH_3 },
<> 150:02e0a0aed4ec 164 { AIN_4, ADC, ADC_CH_0_DIV_5 },
<> 150:02e0a0aed4ec 165 { AIN_5, ADC, ADC_CH_1_DIV_5 },
<> 150:02e0a0aed4ec 166 { NC, NC, 0 }
<> 150:02e0a0aed4ec 167 };
<> 150:02e0a0aed4ec 168