Amit Gandhi / mbed-dev

test

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_K20XX/rtc_api.c@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
176:af195413fb11 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2015 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 static void init(void) {
<> 144:ef7eb2e8f9f7 19 // enable PORTC clock
<> 144:ef7eb2e8f9f7 20 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
<> 144:ef7eb2e8f9f7 21
<> 144:ef7eb2e8f9f7 22 // enable RTC clock
<> 144:ef7eb2e8f9f7 23 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 // OSC32 as source
<> 144:ef7eb2e8f9f7 26 SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK;
<> 144:ef7eb2e8f9f7 27 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(0);
<> 144:ef7eb2e8f9f7 28 }
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 void rtc_init(void) {
<> 144:ef7eb2e8f9f7 31 init();
AnnaBridge 176:af195413fb11 32
<> 144:ef7eb2e8f9f7 33 // Enable the oscillator
<> 144:ef7eb2e8f9f7 34 #if defined (TARGET_K20D50M)
<> 144:ef7eb2e8f9f7 35 RTC->CR |= RTC_CR_OSCE_MASK;
<> 144:ef7eb2e8f9f7 36 #else
<> 144:ef7eb2e8f9f7 37 // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator
<> 144:ef7eb2e8f9f7 38 /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */
AnnaBridge 176:af195413fb11 39 RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK;
<> 144:ef7eb2e8f9f7 40 #endif
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 //Configure the TSR. default value: 1
<> 144:ef7eb2e8f9f7 43 RTC->TSR = 1;
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 // enable counter
<> 144:ef7eb2e8f9f7 46 RTC->SR |= RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 47 }
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 void rtc_free(void) {
<> 144:ef7eb2e8f9f7 50 // [TODO]
<> 144:ef7eb2e8f9f7 51 }
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /*
<> 144:ef7eb2e8f9f7 54 * Little check routine to see if the RTC has been enabled
<> 144:ef7eb2e8f9f7 55 * 0 = Disabled, 1 = Enabled
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57 int rtc_isenabled(void) {
<> 144:ef7eb2e8f9f7 58 // even if the RTC module is enabled,
<> 144:ef7eb2e8f9f7 59 // as we use RTC_CLKIN and an external clock,
<> 144:ef7eb2e8f9f7 60 // we need to reconfigure the pins. That is why we
<> 144:ef7eb2e8f9f7 61 // call init() if the rtc is enabled
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 // if RTC not enabled return 0
<> 144:ef7eb2e8f9f7 64 SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
<> 144:ef7eb2e8f9f7 65 SIM->SCGC6 |= SIM_SCGC6_RTC_MASK;
<> 144:ef7eb2e8f9f7 66 if ((RTC->SR & RTC_SR_TCE_MASK) == 0)
<> 144:ef7eb2e8f9f7 67 return 0;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 init();
<> 144:ef7eb2e8f9f7 70 return 1;
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 time_t rtc_read(void) {
<> 144:ef7eb2e8f9f7 74 return RTC->TSR;
<> 144:ef7eb2e8f9f7 75 }
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 void rtc_write(time_t t) {
<> 144:ef7eb2e8f9f7 78 // disable counter
<> 144:ef7eb2e8f9f7 79 RTC->SR &= ~RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // write seconds
<> 144:ef7eb2e8f9f7 82 RTC->TSR = t;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 // re-enable counter
<> 144:ef7eb2e8f9f7 85 RTC->SR |= RTC_SR_TCE_MASK;
<> 144:ef7eb2e8f9f7 86 }