Amit Gandhi / mbed-dev

test

Fork of mbed-dev by mbed official

targets/TARGET_STM/stm_spi_api.c@171:19eb464bc2be, 2017-08-03 (annotated)

Committer:
Kojto
Date:
Thu Aug 03 13:13:39 2017 +0100
Revision:
171:19eb464bc2be
Parent:
169:9672193075cf
Child:
174:e131a1973e81
This updates the lib to the mbed lib v 148

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * Copyright (c) 2015, STMicroelectronics
<> 149:156823d33999 4 * All rights reserved.
<> 149:156823d33999 5 *
<> 149:156823d33999 6 * Redistribution and use in source and binary forms, with or without
<> 149:156823d33999 7 * modification, are permitted provided that the following conditions are met:
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 10 * this list of conditions and the following disclaimer.
<> 149:156823d33999 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 12 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 13 * and/or other materials provided with the distribution.
<> 149:156823d33999 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 15 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 16 * without specific prior written permission.
<> 149:156823d33999 17 *
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 28 *******************************************************************************
<> 149:156823d33999 29 */
<> 149:156823d33999 30 #include "mbed_assert.h"
<> 149:156823d33999 31 #include "mbed_error.h"
<> 149:156823d33999 32 #include "spi_api.h"
<> 149:156823d33999 33
<> 149:156823d33999 34 #if DEVICE_SPI
<> 149:156823d33999 35 #include <stdbool.h>
<> 149:156823d33999 36 #include <math.h>
<> 149:156823d33999 37 #include <string.h>
<> 149:156823d33999 38 #include "cmsis.h"
<> 149:156823d33999 39 #include "pinmap.h"
<> 149:156823d33999 40 #include "PeripheralPins.h"
AnnaBridge 169:9672193075cf 41 #include "spi_device.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 44 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi))
<> 149:156823d33999 45 #else
<> 149:156823d33999 46 #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi))
<> 149:156823d33999 47 #endif
<> 149:156823d33999 48
<> 149:156823d33999 49 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 50 #define SPI_S(obj) (( struct spi_s *)(&(obj->spi)))
<> 149:156823d33999 51 #else
<> 149:156823d33999 52 #define SPI_S(obj) (( struct spi_s *)(obj))
<> 149:156823d33999 53 #endif
<> 149:156823d33999 54
<> 149:156823d33999 55 #ifndef DEBUG_STDIO
<> 149:156823d33999 56 # define DEBUG_STDIO 0
<> 149:156823d33999 57 #endif
<> 149:156823d33999 58
<> 149:156823d33999 59 #if DEBUG_STDIO
<> 149:156823d33999 60 # include <stdio.h>
<> 149:156823d33999 61 # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0)
<> 149:156823d33999 62 #else
<> 149:156823d33999 63 # define DEBUG_PRINTF(...) {}
<> 149:156823d33999 64 #endif
<> 149:156823d33999 65
<> 149:156823d33999 66 void init_spi(spi_t *obj)
<> 149:156823d33999 67 {
<> 149:156823d33999 68 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 69 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 70
<> 149:156823d33999 71 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 72
<> 149:156823d33999 73 DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance);
<> 149:156823d33999 74 if (HAL_SPI_Init(handle) != HAL_OK) {
<> 149:156823d33999 75 error("Cannot initialize SPI");
<> 149:156823d33999 76 }
<> 149:156823d33999 77
<> 149:156823d33999 78 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
<> 149:156823d33999 82 {
<> 149:156823d33999 83 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 84 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 85
<> 149:156823d33999 86 // Determine the SPI to use
<> 149:156823d33999 87 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 88 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 149:156823d33999 89 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 90 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 91
<> 149:156823d33999 92 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 149:156823d33999 93 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 149:156823d33999 94
<> 149:156823d33999 95 spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
<> 149:156823d33999 96 MBED_ASSERT(spiobj->spi != (SPIName)NC);
<> 149:156823d33999 97
<> 149:156823d33999 98 #if defined SPI1_BASE
<> 149:156823d33999 99 // Enable SPI clock
<> 149:156823d33999 100 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 101 __HAL_RCC_SPI1_CLK_ENABLE();
<> 149:156823d33999 102 spiobj->spiIRQ = SPI1_IRQn;
<> 149:156823d33999 103 }
<> 149:156823d33999 104 #endif
<> 149:156823d33999 105
<> 149:156823d33999 106 #if defined SPI2_BASE
<> 149:156823d33999 107 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 108 __HAL_RCC_SPI2_CLK_ENABLE();
<> 149:156823d33999 109 spiobj->spiIRQ = SPI2_IRQn;
<> 149:156823d33999 110 }
<> 149:156823d33999 111 #endif
<> 149:156823d33999 112
<> 149:156823d33999 113 #if defined SPI3_BASE
<> 149:156823d33999 114 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 115 __HAL_RCC_SPI3_CLK_ENABLE();
<> 149:156823d33999 116 spiobj->spiIRQ = SPI3_IRQn;
<> 149:156823d33999 117 }
<> 149:156823d33999 118 #endif
<> 149:156823d33999 119
<> 149:156823d33999 120 #if defined SPI4_BASE
<> 149:156823d33999 121 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 122 __HAL_RCC_SPI4_CLK_ENABLE();
<> 149:156823d33999 123 spiobj->spiIRQ = SPI4_IRQn;
<> 149:156823d33999 124 }
<> 149:156823d33999 125 #endif
<> 149:156823d33999 126
<> 149:156823d33999 127 #if defined SPI5_BASE
<> 149:156823d33999 128 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 129 __HAL_RCC_SPI5_CLK_ENABLE();
<> 149:156823d33999 130 spiobj->spiIRQ = SPI5_IRQn;
<> 149:156823d33999 131 }
<> 149:156823d33999 132 #endif
<> 149:156823d33999 133
<> 149:156823d33999 134 #if defined SPI6_BASE
<> 149:156823d33999 135 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 136 __HAL_RCC_SPI6_CLK_ENABLE();
<> 149:156823d33999 137 spiobj->spiIRQ = SPI6_IRQn;
<> 149:156823d33999 138 }
<> 149:156823d33999 139 #endif
<> 149:156823d33999 140
<> 149:156823d33999 141 // Configure the SPI pins
<> 149:156823d33999 142 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 149:156823d33999 143 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 149:156823d33999 144 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 149:156823d33999 145 spiobj->pin_miso = miso;
<> 149:156823d33999 146 spiobj->pin_mosi = mosi;
<> 149:156823d33999 147 spiobj->pin_sclk = sclk;
<> 149:156823d33999 148 spiobj->pin_ssel = ssel;
<> 149:156823d33999 149 if (ssel != NC) {
<> 149:156823d33999 150 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 149:156823d33999 151 } else {
<> 149:156823d33999 152 handle->Init.NSS = SPI_NSS_SOFT;
<> 149:156823d33999 153 }
<> 149:156823d33999 154
<> 149:156823d33999 155 /* Fill default value */
<> 149:156823d33999 156 handle->Instance = SPI_INST(obj);
<> 149:156823d33999 157 handle->Init.Mode = SPI_MODE_MASTER;
<> 149:156823d33999 158 handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
<> 149:156823d33999 159 handle->Init.Direction = SPI_DIRECTION_2LINES;
<> 149:156823d33999 160 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 161 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
AnnaBridge 166:e614a9f1c9e2 162 handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
<> 149:156823d33999 163 handle->Init.CRCPolynomial = 7;
<> 149:156823d33999 164 handle->Init.DataSize = SPI_DATASIZE_8BIT;
<> 149:156823d33999 165 handle->Init.FirstBit = SPI_FIRSTBIT_MSB;
AnnaBridge 166:e614a9f1c9e2 166 handle->Init.TIMode = SPI_TIMODE_DISABLE;
<> 149:156823d33999 167
<> 149:156823d33999 168 init_spi(obj);
<> 149:156823d33999 169 }
<> 149:156823d33999 170
<> 149:156823d33999 171 void spi_free(spi_t *obj)
<> 149:156823d33999 172 {
<> 149:156823d33999 173 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 174 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 175
<> 149:156823d33999 176 DEBUG_PRINTF("spi_free\r\n");
<> 149:156823d33999 177
<> 149:156823d33999 178 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 179 HAL_SPI_DeInit(handle);
<> 149:156823d33999 180
<> 149:156823d33999 181 #if defined SPI1_BASE
<> 149:156823d33999 182 // Reset SPI and disable clock
<> 149:156823d33999 183 if (spiobj->spi == SPI_1) {
<> 149:156823d33999 184 __HAL_RCC_SPI1_FORCE_RESET();
<> 149:156823d33999 185 __HAL_RCC_SPI1_RELEASE_RESET();
<> 149:156823d33999 186 __HAL_RCC_SPI1_CLK_DISABLE();
<> 149:156823d33999 187 }
<> 149:156823d33999 188 #endif
<> 149:156823d33999 189 #if defined SPI2_BASE
<> 149:156823d33999 190 if (spiobj->spi == SPI_2) {
<> 149:156823d33999 191 __HAL_RCC_SPI2_FORCE_RESET();
<> 149:156823d33999 192 __HAL_RCC_SPI2_RELEASE_RESET();
<> 149:156823d33999 193 __HAL_RCC_SPI2_CLK_DISABLE();
<> 149:156823d33999 194 }
<> 149:156823d33999 195 #endif
<> 149:156823d33999 196
<> 149:156823d33999 197 #if defined SPI3_BASE
<> 149:156823d33999 198 if (spiobj->spi == SPI_3) {
<> 149:156823d33999 199 __HAL_RCC_SPI3_FORCE_RESET();
<> 149:156823d33999 200 __HAL_RCC_SPI3_RELEASE_RESET();
<> 149:156823d33999 201 __HAL_RCC_SPI3_CLK_DISABLE();
<> 149:156823d33999 202 }
<> 149:156823d33999 203 #endif
<> 149:156823d33999 204
<> 149:156823d33999 205 #if defined SPI4_BASE
<> 149:156823d33999 206 if (spiobj->spi == SPI_4) {
<> 149:156823d33999 207 __HAL_RCC_SPI4_FORCE_RESET();
<> 149:156823d33999 208 __HAL_RCC_SPI4_RELEASE_RESET();
<> 149:156823d33999 209 __HAL_RCC_SPI4_CLK_DISABLE();
<> 149:156823d33999 210 }
<> 149:156823d33999 211 #endif
<> 149:156823d33999 212
<> 149:156823d33999 213 #if defined SPI5_BASE
<> 149:156823d33999 214 if (spiobj->spi == SPI_5) {
<> 149:156823d33999 215 __HAL_RCC_SPI5_FORCE_RESET();
<> 149:156823d33999 216 __HAL_RCC_SPI5_RELEASE_RESET();
<> 149:156823d33999 217 __HAL_RCC_SPI5_CLK_DISABLE();
<> 149:156823d33999 218 }
<> 149:156823d33999 219 #endif
<> 149:156823d33999 220
<> 149:156823d33999 221 #if defined SPI6_BASE
<> 149:156823d33999 222 if (spiobj->spi == SPI_6) {
<> 149:156823d33999 223 __HAL_RCC_SPI6_FORCE_RESET();
<> 149:156823d33999 224 __HAL_RCC_SPI6_RELEASE_RESET();
<> 149:156823d33999 225 __HAL_RCC_SPI6_CLK_DISABLE();
<> 149:156823d33999 226 }
<> 149:156823d33999 227 #endif
<> 149:156823d33999 228
<> 149:156823d33999 229 // Configure GPIOs
<> 149:156823d33999 230 pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 231 pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 232 pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 233 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 234 pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
<> 149:156823d33999 235 }
<> 149:156823d33999 236 }
<> 149:156823d33999 237
<> 149:156823d33999 238 void spi_format(spi_t *obj, int bits, int mode, int slave)
<> 149:156823d33999 239 {
<> 149:156823d33999 240 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 241 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 242
<> 149:156823d33999 243 DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave);
<> 149:156823d33999 244
<> 149:156823d33999 245 // Save new values
<> 149:156823d33999 246 handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT;
<> 149:156823d33999 247
<> 149:156823d33999 248 switch (mode) {
<> 149:156823d33999 249 case 0:
<> 149:156823d33999 250 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 251 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 252 break;
<> 149:156823d33999 253 case 1:
<> 149:156823d33999 254 handle->Init.CLKPolarity = SPI_POLARITY_LOW;
<> 149:156823d33999 255 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 256 break;
<> 149:156823d33999 257 case 2:
<> 149:156823d33999 258 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 259 handle->Init.CLKPhase = SPI_PHASE_1EDGE;
<> 149:156823d33999 260 break;
<> 149:156823d33999 261 default:
<> 149:156823d33999 262 handle->Init.CLKPolarity = SPI_POLARITY_HIGH;
<> 149:156823d33999 263 handle->Init.CLKPhase = SPI_PHASE_2EDGE;
<> 149:156823d33999 264 break;
<> 149:156823d33999 265 }
<> 149:156823d33999 266
<> 149:156823d33999 267 if (handle->Init.NSS != SPI_NSS_SOFT) {
<> 149:156823d33999 268 handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
<> 149:156823d33999 269 }
<> 149:156823d33999 270
<> 149:156823d33999 271 handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
<> 149:156823d33999 272
<> 149:156823d33999 273 init_spi(obj);
<> 149:156823d33999 274 }
<> 149:156823d33999 275
<> 149:156823d33999 276 /*
<> 149:156823d33999 277 * Only the IP clock input is family dependant so it computed
<> 149:156823d33999 278 * separately in spi_get_clock_freq
<> 149:156823d33999 279 */
<> 149:156823d33999 280 extern int spi_get_clock_freq(spi_t *obj);
<> 149:156823d33999 281
<> 149:156823d33999 282 static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2,
<> 149:156823d33999 283 SPI_BAUDRATEPRESCALER_4,
<> 149:156823d33999 284 SPI_BAUDRATEPRESCALER_8,
<> 149:156823d33999 285 SPI_BAUDRATEPRESCALER_16,
<> 149:156823d33999 286 SPI_BAUDRATEPRESCALER_32,
<> 149:156823d33999 287 SPI_BAUDRATEPRESCALER_64,
<> 149:156823d33999 288 SPI_BAUDRATEPRESCALER_128,
<> 149:156823d33999 289 SPI_BAUDRATEPRESCALER_256};
<> 149:156823d33999 290
<> 149:156823d33999 291 void spi_frequency(spi_t *obj, int hz) {
<> 149:156823d33999 292 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 293 int spi_hz = 0;
<> 149:156823d33999 294 uint8_t prescaler_rank = 0;
<> 159:612c381a210f 295 uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1;
<> 149:156823d33999 296 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 297
<> 159:612c381a210f 298 /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */
<> 159:612c381a210f 299 spi_hz = spi_get_clock_freq(obj) / 2;
<> 149:156823d33999 300
<> 149:156823d33999 301 /* Define pre-scaler in order to get highest available frequency below requested frequency */
<> 159:612c381a210f 302 while ((spi_hz > hz) && (prescaler_rank < last_index)) {
<> 149:156823d33999 303 spi_hz = spi_hz / 2;
<> 149:156823d33999 304 prescaler_rank++;
<> 149:156823d33999 305 }
<> 149:156823d33999 306
<> 159:612c381a210f 307 /* Use the best fit pre-scaler */
<> 159:612c381a210f 308 handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank];
<> 159:612c381a210f 309
<> 159:612c381a210f 310 /* In case maximum pre-scaler still gives too high freq, raise an error */
<> 159:612c381a210f 311 if (spi_hz > hz) {
<> 160:d5399cc887bb 312 DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz);
<> 149:156823d33999 313 }
<> 149:156823d33999 314
<> 159:612c381a210f 315 DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz);
<> 159:612c381a210f 316
<> 149:156823d33999 317 init_spi(obj);
<> 149:156823d33999 318 }
<> 149:156823d33999 319
<> 149:156823d33999 320 static inline int ssp_readable(spi_t *obj)
<> 149:156823d33999 321 {
<> 149:156823d33999 322 int status;
<> 149:156823d33999 323 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 324 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 325
<> 149:156823d33999 326 // Check if data is received
<> 149:156823d33999 327 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
<> 149:156823d33999 328 return status;
<> 149:156823d33999 329 }
<> 149:156823d33999 330
<> 149:156823d33999 331 static inline int ssp_writeable(spi_t *obj)
<> 149:156823d33999 332 {
<> 149:156823d33999 333 int status;
<> 149:156823d33999 334 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 335 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 336
<> 149:156823d33999 337 // Check if data is transmitted
<> 149:156823d33999 338 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
<> 149:156823d33999 339 return status;
<> 149:156823d33999 340 }
<> 149:156823d33999 341
<> 149:156823d33999 342 static inline int ssp_busy(spi_t *obj)
<> 149:156823d33999 343 {
<> 149:156823d33999 344 int status;
<> 149:156823d33999 345 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 346 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 347 status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
<> 149:156823d33999 348 return status;
<> 149:156823d33999 349 }
<> 149:156823d33999 350
<> 149:156823d33999 351 int spi_master_write(spi_t *obj, int value)
<> 149:156823d33999 352 {
<> 149:156823d33999 353 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 354 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 355
AnnaBridge 169:9672193075cf 356 #if defined(LL_SPI_RX_FIFO_TH_HALF)
AnnaBridge 169:9672193075cf 357 /* Configure the default data size */
AnnaBridge 169:9672193075cf 358 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 169:9672193075cf 359 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF);
AnnaBridge 169:9672193075cf 360 } else {
AnnaBridge 169:9672193075cf 361 LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER);
AnnaBridge 169:9672193075cf 362 }
AnnaBridge 169:9672193075cf 363 #endif
<> 149:156823d33999 364
AnnaBridge 169:9672193075cf 365 /* Here we're using LL which means direct registers access
AnnaBridge 169:9672193075cf 366 * There is no error management, so we may end up looping
AnnaBridge 169:9672193075cf 367 * infinitely here in case of faulty device for insatnce,
AnnaBridge 169:9672193075cf 368 * but this will increase performances significantly
AnnaBridge 169:9672193075cf 369 */
<> 149:156823d33999 370
AnnaBridge 169:9672193075cf 371 /* Wait TXE flag to transmit data */
AnnaBridge 169:9672193075cf 372 while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj)));
AnnaBridge 169:9672193075cf 373
AnnaBridge 169:9672193075cf 374 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 169:9672193075cf 375 LL_SPI_TransmitData16(SPI_INST(obj), value);
<> 149:156823d33999 376 } else {
AnnaBridge 169:9672193075cf 377 LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value);
AnnaBridge 169:9672193075cf 378 }
AnnaBridge 169:9672193075cf 379
AnnaBridge 169:9672193075cf 380 /* Then wait RXE flag before reading */
AnnaBridge 169:9672193075cf 381 while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj)));
AnnaBridge 169:9672193075cf 382
AnnaBridge 169:9672193075cf 383 if (handle->Init.DataSize == SPI_DATASIZE_16BIT) {
AnnaBridge 169:9672193075cf 384 return LL_SPI_ReceiveData16(SPI_INST(obj));
AnnaBridge 169:9672193075cf 385 } else {
AnnaBridge 169:9672193075cf 386 return LL_SPI_ReceiveData8(SPI_INST(obj));
<> 149:156823d33999 387 }
<> 149:156823d33999 388 }
<> 149:156823d33999 389
Kojto 171:19eb464bc2be 390 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
Kojto 171:19eb464bc2be 391 char *rx_buffer, int rx_length, char write_fill)
AnnaBridge 168:e84263d55307 392 {
AnnaBridge 168:e84263d55307 393 int total = (tx_length > rx_length) ? tx_length : rx_length;
AnnaBridge 168:e84263d55307 394
AnnaBridge 168:e84263d55307 395 for (int i = 0; i < total; i++) {
Kojto 171:19eb464bc2be 396 char out = (i < tx_length) ? tx_buffer[i] : write_fill;
AnnaBridge 168:e84263d55307 397 char in = spi_master_write(obj, out);
AnnaBridge 168:e84263d55307 398 if (i < rx_length) {
AnnaBridge 168:e84263d55307 399 rx_buffer[i] = in;
AnnaBridge 168:e84263d55307 400 }
AnnaBridge 168:e84263d55307 401 }
AnnaBridge 168:e84263d55307 402
AnnaBridge 168:e84263d55307 403 return total;
AnnaBridge 168:e84263d55307 404 }
AnnaBridge 168:e84263d55307 405
<> 149:156823d33999 406 int spi_slave_receive(spi_t *obj)
<> 149:156823d33999 407 {
<> 149:156823d33999 408 return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0);
<> 149:156823d33999 409 };
<> 149:156823d33999 410
<> 149:156823d33999 411 int spi_slave_read(spi_t *obj)
<> 149:156823d33999 412 {
<> 149:156823d33999 413 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 414 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 415 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 416 while (!ssp_readable(obj));
<> 149:156823d33999 417 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 418 // Force 8-bit access to the data register
<> 149:156823d33999 419 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 420 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 421 return (int)(*p_spi_dr);
<> 149:156823d33999 422 } else {
<> 149:156823d33999 423 return (int)spi->DR;
<> 149:156823d33999 424 }
<> 149:156823d33999 425 }
<> 149:156823d33999 426
<> 149:156823d33999 427 void spi_slave_write(spi_t *obj, int value)
<> 149:156823d33999 428 {
<> 149:156823d33999 429 SPI_TypeDef *spi = SPI_INST(obj);
<> 149:156823d33999 430 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 431 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 432 while (!ssp_writeable(obj));
<> 149:156823d33999 433 if (handle->Init.DataSize == SPI_DATASIZE_8BIT) {
<> 149:156823d33999 434 // Force 8-bit access to the data register
<> 149:156823d33999 435 uint8_t *p_spi_dr = 0;
<> 149:156823d33999 436 p_spi_dr = (uint8_t *) & (spi->DR);
<> 149:156823d33999 437 *p_spi_dr = (uint8_t)value;
<> 149:156823d33999 438 } else { // SPI_DATASIZE_16BIT
<> 149:156823d33999 439 spi->DR = (uint16_t)value;
<> 149:156823d33999 440 }
<> 149:156823d33999 441 }
<> 149:156823d33999 442
<> 149:156823d33999 443 int spi_busy(spi_t *obj)
<> 149:156823d33999 444 {
<> 149:156823d33999 445 return ssp_busy(obj);
<> 149:156823d33999 446 }
<> 149:156823d33999 447
<> 149:156823d33999 448 #ifdef DEVICE_SPI_ASYNCH
<> 149:156823d33999 449 typedef enum {
<> 149:156823d33999 450 SPI_TRANSFER_TYPE_NONE = 0,
<> 149:156823d33999 451 SPI_TRANSFER_TYPE_TX = 1,
<> 149:156823d33999 452 SPI_TRANSFER_TYPE_RX = 2,
<> 149:156823d33999 453 SPI_TRANSFER_TYPE_TXRX = 3,
<> 149:156823d33999 454 } transfer_type_t;
<> 149:156823d33999 455
<> 149:156823d33999 456
<> 149:156823d33999 457 /// @returns the number of bytes transferred, or `0` if nothing transferred
<> 149:156823d33999 458 static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length)
<> 149:156823d33999 459 {
<> 149:156823d33999 460 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 461 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 462 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 463 // the HAL expects number of transfers instead of number of bytes
<> 149:156823d33999 464 // so for 16 bit transfer width the count needs to be halved
<> 149:156823d33999 465 size_t words;
<> 149:156823d33999 466
<> 149:156823d33999 467 DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length);
<> 149:156823d33999 468
<> 149:156823d33999 469 obj->spi.transfer_type = transfer_type;
<> 149:156823d33999 470
<> 149:156823d33999 471 if (is16bit) {
<> 149:156823d33999 472 words = length / 2;
<> 149:156823d33999 473 } else {
<> 149:156823d33999 474 words = length;
<> 149:156823d33999 475 }
<> 149:156823d33999 476
<> 149:156823d33999 477 // enable the interrupt
<> 149:156823d33999 478 IRQn_Type irq_n = spiobj->spiIRQ;
<> 153:fa9ff456f731 479 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 480 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 481 NVIC_SetPriority(irq_n, 1);
<> 149:156823d33999 482 NVIC_EnableIRQ(irq_n);
<> 149:156823d33999 483
<> 149:156823d33999 484 // enable the right hal transfer
<> 149:156823d33999 485 int rc = 0;
<> 149:156823d33999 486 switch(transfer_type) {
<> 149:156823d33999 487 case SPI_TRANSFER_TYPE_TXRX:
<> 149:156823d33999 488 rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words);
<> 149:156823d33999 489 break;
<> 149:156823d33999 490 case SPI_TRANSFER_TYPE_TX:
<> 149:156823d33999 491 rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words);
<> 149:156823d33999 492 break;
<> 149:156823d33999 493 case SPI_TRANSFER_TYPE_RX:
<> 149:156823d33999 494 // the receive function also "transmits" the receive buffer so in order
<> 149:156823d33999 495 // to guarantee that 0xff is on the line, we explicitly memset it here
<> 149:156823d33999 496 memset(rx, SPI_FILL_WORD, length);
<> 149:156823d33999 497 rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words);
<> 149:156823d33999 498 break;
<> 149:156823d33999 499 default:
<> 149:156823d33999 500 length = 0;
<> 149:156823d33999 501 }
<> 149:156823d33999 502
<> 149:156823d33999 503 if (rc) {
<> 149:156823d33999 504 DEBUG_PRINTF("SPI: RC=%u\n", rc);
<> 149:156823d33999 505 length = 0;
<> 149:156823d33999 506 }
<> 149:156823d33999 507
<> 149:156823d33999 508 return length;
<> 149:156823d33999 509 }
<> 149:156823d33999 510
<> 149:156823d33999 511 // asynchronous API
<> 149:156823d33999 512 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 149:156823d33999 513 {
<> 149:156823d33999 514 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 515 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 516
<> 149:156823d33999 517 // TODO: DMA usage is currently ignored
<> 149:156823d33999 518 (void) hint;
<> 149:156823d33999 519
<> 149:156823d33999 520 // check which use-case we have
<> 149:156823d33999 521 bool use_tx = (tx != NULL && tx_length > 0);
<> 149:156823d33999 522 bool use_rx = (rx != NULL && rx_length > 0);
<> 149:156823d33999 523 bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT);
<> 149:156823d33999 524
<> 149:156823d33999 525 // don't do anything, if the buffers aren't valid
<> 149:156823d33999 526 if (!use_tx && !use_rx)
<> 149:156823d33999 527 return;
<> 149:156823d33999 528
<> 149:156823d33999 529 // copy the buffers to the SPI object
<> 149:156823d33999 530 obj->tx_buff.buffer = (void *) tx;
<> 149:156823d33999 531 obj->tx_buff.length = tx_length;
<> 149:156823d33999 532 obj->tx_buff.pos = 0;
<> 149:156823d33999 533 obj->tx_buff.width = is16bit ? 16 : 8;
<> 149:156823d33999 534
<> 149:156823d33999 535 obj->rx_buff.buffer = rx;
<> 149:156823d33999 536 obj->rx_buff.length = rx_length;
<> 149:156823d33999 537 obj->rx_buff.pos = 0;
<> 149:156823d33999 538 obj->rx_buff.width = obj->tx_buff.width;
<> 149:156823d33999 539
<> 149:156823d33999 540 obj->spi.event = event;
<> 149:156823d33999 541
<> 149:156823d33999 542 DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length);
<> 149:156823d33999 543
<> 149:156823d33999 544 // register the thunking handler
<> 149:156823d33999 545 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 546 NVIC_SetVector(irq_n, (uint32_t)handler);
<> 149:156823d33999 547
<> 149:156823d33999 548 // enable the right hal transfer
<> 149:156823d33999 549 if (use_tx && use_rx) {
<> 149:156823d33999 550 // we cannot manage different rx / tx sizes, let's use smaller one
<> 149:156823d33999 551 size_t size = (tx_length < rx_length)? tx_length : rx_length;
<> 149:156823d33999 552 if(tx_length != rx_length) {
<> 149:156823d33999 553 DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size);
<> 149:156823d33999 554 obj->tx_buff.length = size;
<> 149:156823d33999 555 obj->rx_buff.length = size;
<> 149:156823d33999 556 }
<> 149:156823d33999 557 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size);
<> 149:156823d33999 558 } else if (use_tx) {
<> 149:156823d33999 559 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length);
<> 149:156823d33999 560 } else if (use_rx) {
<> 149:156823d33999 561 spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length);
<> 149:156823d33999 562 }
<> 149:156823d33999 563 }
<> 149:156823d33999 564
<> 153:fa9ff456f731 565 inline uint32_t spi_irq_handler_asynch(spi_t *obj)
<> 149:156823d33999 566 {
<> 149:156823d33999 567 int event = 0;
<> 149:156823d33999 568
<> 149:156823d33999 569 // call the CubeF4 handler, this will update the handle
<> 153:fa9ff456f731 570 HAL_SPI_IRQHandler(&obj->spi.handle);
<> 149:156823d33999 571
<> 153:fa9ff456f731 572 if (obj->spi.handle.State == HAL_SPI_STATE_READY) {
<> 149:156823d33999 573 // When HAL SPI is back to READY state, check if there was an error
<> 153:fa9ff456f731 574 int error = obj->spi.handle.ErrorCode;
<> 149:156823d33999 575 if(error != HAL_SPI_ERROR_NONE) {
<> 149:156823d33999 576 // something went wrong and the transfer has definitely completed
<> 149:156823d33999 577 event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 578
<> 149:156823d33999 579 if (error & HAL_SPI_ERROR_OVR) {
<> 149:156823d33999 580 // buffer overrun
<> 149:156823d33999 581 event |= SPI_EVENT_RX_OVERFLOW;
<> 149:156823d33999 582 }
<> 149:156823d33999 583 } else {
<> 149:156823d33999 584 // else we're done
<> 149:156823d33999 585 event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE;
<> 149:156823d33999 586 }
<> 153:fa9ff456f731 587 // enable the interrupt
<> 153:fa9ff456f731 588 NVIC_DisableIRQ(obj->spi.spiIRQ);
<> 153:fa9ff456f731 589 NVIC_ClearPendingIRQ(obj->spi.spiIRQ);
<> 149:156823d33999 590 }
<> 149:156823d33999 591
<> 149:156823d33999 592
<> 149:156823d33999 593 return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE));
<> 149:156823d33999 594 }
<> 149:156823d33999 595
<> 149:156823d33999 596 uint8_t spi_active(spi_t *obj)
<> 149:156823d33999 597 {
<> 149:156823d33999 598 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 599 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 600 HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle);
<> 149:156823d33999 601
<> 149:156823d33999 602 switch(state) {
<> 149:156823d33999 603 case HAL_SPI_STATE_RESET:
<> 149:156823d33999 604 case HAL_SPI_STATE_READY:
<> 149:156823d33999 605 case HAL_SPI_STATE_ERROR:
<> 149:156823d33999 606 return 0;
<> 149:156823d33999 607 default:
<> 149:156823d33999 608 return 1;
<> 149:156823d33999 609 }
<> 149:156823d33999 610 }
<> 149:156823d33999 611
<> 149:156823d33999 612 void spi_abort_asynch(spi_t *obj)
<> 149:156823d33999 613 {
<> 149:156823d33999 614 struct spi_s *spiobj = SPI_S(obj);
<> 149:156823d33999 615 SPI_HandleTypeDef *handle = &(spiobj->handle);
<> 149:156823d33999 616
<> 149:156823d33999 617 // disable interrupt
<> 149:156823d33999 618 IRQn_Type irq_n = spiobj->spiIRQ;
<> 149:156823d33999 619 NVIC_ClearPendingIRQ(irq_n);
<> 149:156823d33999 620 NVIC_DisableIRQ(irq_n);
<> 149:156823d33999 621
<> 149:156823d33999 622 // clean-up
<> 149:156823d33999 623 __HAL_SPI_DISABLE(handle);
<> 149:156823d33999 624 HAL_SPI_DeInit(handle);
<> 149:156823d33999 625 HAL_SPI_Init(handle);
<> 149:156823d33999 626 __HAL_SPI_ENABLE(handle);
<> 149:156823d33999 627 }
<> 149:156823d33999 628
<> 149:156823d33999 629 #endif //DEVICE_SPI_ASYNCH
<> 149:156823d33999 630
<> 149:156823d33999 631 #endif