Amit Gandhi / mbed-dev

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targets/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/device/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L432KC/TOOLCHAIN_GCC_ARM/startup_stm32l432xx.S@144:ef7eb2e8f9f7
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file startup_stm32l432xx.s
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.1
<> 144:ef7eb2e8f9f7 6 * @date 29-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief STM32L432xx devices vector table for GCC toolchain.
<> 144:ef7eb2e8f9f7 8 * This module performs:
<> 144:ef7eb2e8f9f7 9 * - Set the initial SP
<> 144:ef7eb2e8f9f7 10 * - Set the initial PC == Reset_Handler,
<> 144:ef7eb2e8f9f7 11 * - Set the vector table entries with the exceptions ISR address,
<> 144:ef7eb2e8f9f7 12 * - Configure the clock system
<> 144:ef7eb2e8f9f7 13 * - Branches to main in the C library (which eventually
<> 144:ef7eb2e8f9f7 14 * calls main()).
<> 144:ef7eb2e8f9f7 15 * After Reset the Cortex-M4 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 16 * priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 17 ******************************************************************************
<> 144:ef7eb2e8f9f7 18 * @attention
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 23 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 24 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 25 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 26 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 27 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 28 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 29 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 30 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 31 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 36 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 40 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 41 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 42 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 43 *
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 .syntax unified
<> 144:ef7eb2e8f9f7 48 .cpu cortex-m4
<> 144:ef7eb2e8f9f7 49 .fpu softvfp
<> 144:ef7eb2e8f9f7 50 .thumb
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 .global g_pfnVectors
<> 144:ef7eb2e8f9f7 53 .global Default_Handler
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* start address for the initialization values of the .data section.
<> 144:ef7eb2e8f9f7 56 defined in linker script */
<> 144:ef7eb2e8f9f7 57 .word _sidata
<> 144:ef7eb2e8f9f7 58 /* start address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 59 .word _sdata
<> 144:ef7eb2e8f9f7 60 /* end address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 61 .word _edata
<> 144:ef7eb2e8f9f7 62 /* start address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 63 .word _sbss
<> 144:ef7eb2e8f9f7 64 /* end address for the .bss section. defined in linker script */
<> 144:ef7eb2e8f9f7 65 .word _ebss
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 .equ BootRAM, 0xF1E0F85F
<> 144:ef7eb2e8f9f7 68 /**
<> 144:ef7eb2e8f9f7 69 * @brief This is the code that gets called when the processor first
<> 144:ef7eb2e8f9f7 70 * starts execution following a reset event. Only the absolutely
<> 144:ef7eb2e8f9f7 71 * necessary set is performed, after which the application
<> 144:ef7eb2e8f9f7 72 * supplied main() routine is called.
<> 144:ef7eb2e8f9f7 73 * @param None
<> 144:ef7eb2e8f9f7 74 * @retval : None
<> 144:ef7eb2e8f9f7 75 */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 78 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 79 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 80 Reset_Handler:
<> 144:ef7eb2e8f9f7 81 ldr sp, =_estack /* Atollic update: set stack pointer */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /* Copy the data segment initializers from flash to SRAM */
<> 144:ef7eb2e8f9f7 84 movs r1, #0
<> 144:ef7eb2e8f9f7 85 b LoopCopyDataInit
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 CopyDataInit:
<> 144:ef7eb2e8f9f7 88 ldr r3, =_sidata
<> 144:ef7eb2e8f9f7 89 ldr r3, [r3, r1]
<> 144:ef7eb2e8f9f7 90 str r3, [r0, r1]
<> 144:ef7eb2e8f9f7 91 adds r1, r1, #4
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 LoopCopyDataInit:
<> 144:ef7eb2e8f9f7 94 ldr r0, =_sdata
<> 144:ef7eb2e8f9f7 95 ldr r3, =_edata
<> 144:ef7eb2e8f9f7 96 adds r2, r0, r1
<> 144:ef7eb2e8f9f7 97 cmp r2, r3
<> 144:ef7eb2e8f9f7 98 bcc CopyDataInit
<> 144:ef7eb2e8f9f7 99 ldr r2, =_sbss
<> 144:ef7eb2e8f9f7 100 b LoopFillZerobss
<> 144:ef7eb2e8f9f7 101 /* Zero fill the bss segment. */
<> 144:ef7eb2e8f9f7 102 FillZerobss:
<> 144:ef7eb2e8f9f7 103 movs r3, #0
<> 144:ef7eb2e8f9f7 104 str r3, [r2], #4
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 LoopFillZerobss:
<> 144:ef7eb2e8f9f7 107 ldr r3, = _ebss
<> 144:ef7eb2e8f9f7 108 cmp r2, r3
<> 144:ef7eb2e8f9f7 109 bcc FillZerobss
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Call the clock system intitialization function.*/
<> 144:ef7eb2e8f9f7 112 bl SystemInit
<> 144:ef7eb2e8f9f7 113 /* Call static constructors */
<> 144:ef7eb2e8f9f7 114 //bl __libc_init_array
<> 144:ef7eb2e8f9f7 115 /* Call the application's entry point.*/
<> 144:ef7eb2e8f9f7 116 //bl main
<> 144:ef7eb2e8f9f7 117 // Calling the crt0 'cold-start' entry point. There __libc_init_array is called
<> 144:ef7eb2e8f9f7 118 // and when existing hardware_init_hook() and software_init_hook() before
<> 144:ef7eb2e8f9f7 119 // starting main(). software_init_hook() is available and has to be called due
<> 144:ef7eb2e8f9f7 120 // to initializsation when using rtos.
<> 144:ef7eb2e8f9f7 121 bl _start
<> 144:ef7eb2e8f9f7 122 bx lr
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 LoopForever:
<> 144:ef7eb2e8f9f7 125 b LoopForever
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 .size Reset_Handler, .-Reset_Handler
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /**
<> 144:ef7eb2e8f9f7 130 * @brief This is the code that gets called when the processor receives an
<> 144:ef7eb2e8f9f7 131 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 144:ef7eb2e8f9f7 132 * the system state for examination by a debugger.
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * @param None
<> 144:ef7eb2e8f9f7 135 * @retval : None
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 .section .text.Default_Handler,"ax",%progbits
<> 144:ef7eb2e8f9f7 138 Default_Handler:
<> 144:ef7eb2e8f9f7 139 Infinite_Loop:
<> 144:ef7eb2e8f9f7 140 b Infinite_Loop
<> 144:ef7eb2e8f9f7 141 .size Default_Handler, .-Default_Handler
<> 144:ef7eb2e8f9f7 142 /******************************************************************************
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 * The minimal vector table for a Cortex-M4. Note that the proper constructs
<> 144:ef7eb2e8f9f7 145 * must be placed on this to ensure that it ends up at physical address
<> 144:ef7eb2e8f9f7 146 * 0x0000.0000.
<> 144:ef7eb2e8f9f7 147 *
<> 144:ef7eb2e8f9f7 148 ******************************************************************************/
<> 144:ef7eb2e8f9f7 149 .section .isr_vector,"a",%progbits
<> 144:ef7eb2e8f9f7 150 .type g_pfnVectors, %object
<> 144:ef7eb2e8f9f7 151 .size g_pfnVectors, .-g_pfnVectors
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 g_pfnVectors:
<> 144:ef7eb2e8f9f7 155 .word _estack
<> 144:ef7eb2e8f9f7 156 .word Reset_Handler
<> 144:ef7eb2e8f9f7 157 .word NMI_Handler
<> 144:ef7eb2e8f9f7 158 .word HardFault_Handler
<> 144:ef7eb2e8f9f7 159 .word MemManage_Handler
<> 144:ef7eb2e8f9f7 160 .word BusFault_Handler
<> 144:ef7eb2e8f9f7 161 .word UsageFault_Handler
<> 144:ef7eb2e8f9f7 162 .word 0
<> 144:ef7eb2e8f9f7 163 .word 0
<> 144:ef7eb2e8f9f7 164 .word 0
<> 144:ef7eb2e8f9f7 165 .word 0
<> 144:ef7eb2e8f9f7 166 .word SVC_Handler
<> 144:ef7eb2e8f9f7 167 .word DebugMon_Handler
<> 144:ef7eb2e8f9f7 168 .word 0
<> 144:ef7eb2e8f9f7 169 .word PendSV_Handler
<> 144:ef7eb2e8f9f7 170 .word SysTick_Handler
<> 144:ef7eb2e8f9f7 171 .word WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 172 .word PVD_PVM_IRQHandler
<> 144:ef7eb2e8f9f7 173 .word TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 174 .word RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 175 .word FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 176 .word RCC_IRQHandler
<> 144:ef7eb2e8f9f7 177 .word EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 178 .word EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 179 .word EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 180 .word EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 181 .word EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 182 .word DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 183 .word DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 184 .word DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 185 .word DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 186 .word DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 187 .word DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 188 .word DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 189 .word ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 190 .word CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 191 .word CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 192 .word CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 193 .word CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 194 .word EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 195 .word TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 196 .word TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 197 .word TIM1_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 198 .word TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 199 .word TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 200 .word 0
<> 144:ef7eb2e8f9f7 201 .word 0
<> 144:ef7eb2e8f9f7 202 .word I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 203 .word I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 204 .word 0
<> 144:ef7eb2e8f9f7 205 .word 0
<> 144:ef7eb2e8f9f7 206 .word SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 207 .word 0
<> 144:ef7eb2e8f9f7 208 .word USART1_IRQHandler
<> 144:ef7eb2e8f9f7 209 .word USART2_IRQHandler
<> 144:ef7eb2e8f9f7 210 .word 0
<> 144:ef7eb2e8f9f7 211 .word EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 212 .word RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 213 .word 0
<> 144:ef7eb2e8f9f7 214 .word 0
<> 144:ef7eb2e8f9f7 215 .word 0
<> 144:ef7eb2e8f9f7 216 .word 0
<> 144:ef7eb2e8f9f7 217 .word 0
<> 144:ef7eb2e8f9f7 218 .word 0
<> 144:ef7eb2e8f9f7 219 .word 0
<> 144:ef7eb2e8f9f7 220 .word 0
<> 144:ef7eb2e8f9f7 221 .word 0
<> 144:ef7eb2e8f9f7 222 .word SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 223 .word 0
<> 144:ef7eb2e8f9f7 224 .word 0
<> 144:ef7eb2e8f9f7 225 .word TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 226 .word TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 227 .word DMA2_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 228 .word DMA2_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 229 .word DMA2_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 230 .word DMA2_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 231 .word DMA2_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 232 .word 0
<> 144:ef7eb2e8f9f7 233 .word 0
<> 144:ef7eb2e8f9f7 234 .word 0
<> 144:ef7eb2e8f9f7 235 .word COMP_IRQHandler
<> 144:ef7eb2e8f9f7 236 .word LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 237 .word LPTIM2_IRQHandler
<> 144:ef7eb2e8f9f7 238 .word USB_IRQHandler
<> 144:ef7eb2e8f9f7 239 .word DMA2_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 240 .word DMA2_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 241 .word LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 242 .word QUADSPI_IRQHandler
<> 144:ef7eb2e8f9f7 243 .word I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 244 .word I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 245 .word SAI1_IRQHandler
<> 144:ef7eb2e8f9f7 246 .word 0
<> 144:ef7eb2e8f9f7 247 .word SWPMI1_IRQHandler
<> 144:ef7eb2e8f9f7 248 .word TSC_IRQHandler
<> 144:ef7eb2e8f9f7 249 .word 0
<> 144:ef7eb2e8f9f7 250 .word 0
<> 144:ef7eb2e8f9f7 251 .word RNG_IRQHandler
<> 144:ef7eb2e8f9f7 252 .word FPU_IRQHandler
<> 144:ef7eb2e8f9f7 253 .word CRS_IRQHandler
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /*******************************************************************************
<> 144:ef7eb2e8f9f7 257 *
<> 144:ef7eb2e8f9f7 258 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 144:ef7eb2e8f9f7 259 * As they are weak aliases, any function with the same name will override
<> 144:ef7eb2e8f9f7 260 * this definition.
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 *******************************************************************************/
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 265 .thumb_set NMI_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 268 .thumb_set HardFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 .weak MemManage_Handler
<> 144:ef7eb2e8f9f7 271 .thumb_set MemManage_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 .weak BusFault_Handler
<> 144:ef7eb2e8f9f7 274 .thumb_set BusFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 .weak UsageFault_Handler
<> 144:ef7eb2e8f9f7 277 .thumb_set UsageFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 280 .thumb_set SVC_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 .weak DebugMon_Handler
<> 144:ef7eb2e8f9f7 283 .thumb_set DebugMon_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 286 .thumb_set PendSV_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 289 .thumb_set SysTick_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 .weak WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 292 .thumb_set WWDG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 .weak PVD_PVM_IRQHandler
<> 144:ef7eb2e8f9f7 295 .thumb_set PVD_PVM_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 .weak TAMP_STAMP_IRQHandler
<> 144:ef7eb2e8f9f7 298 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 .weak RTC_WKUP_IRQHandler
<> 144:ef7eb2e8f9f7 301 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 .weak FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 304 .thumb_set FLASH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 .weak RCC_IRQHandler
<> 144:ef7eb2e8f9f7 307 .thumb_set RCC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 .weak EXTI0_IRQHandler
<> 144:ef7eb2e8f9f7 310 .thumb_set EXTI0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 .weak EXTI1_IRQHandler
<> 144:ef7eb2e8f9f7 313 .thumb_set EXTI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315 .weak EXTI2_IRQHandler
<> 144:ef7eb2e8f9f7 316 .thumb_set EXTI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 .weak EXTI3_IRQHandler
<> 144:ef7eb2e8f9f7 319 .thumb_set EXTI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 .weak EXTI4_IRQHandler
<> 144:ef7eb2e8f9f7 322 .thumb_set EXTI4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 .weak DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 325 .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 .weak DMA1_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 328 .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 .weak DMA1_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 331 .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 .weak DMA1_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 334 .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 .weak DMA1_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 337 .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 .weak DMA1_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 340 .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 .weak DMA1_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 343 .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 .weak ADC1_IRQHandler
<> 144:ef7eb2e8f9f7 346 .thumb_set ADC1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 .weak CAN1_TX_IRQHandler
<> 144:ef7eb2e8f9f7 349 .thumb_set CAN1_TX_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 .weak CAN1_RX0_IRQHandler
<> 144:ef7eb2e8f9f7 352 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 .weak CAN1_RX1_IRQHandler
<> 144:ef7eb2e8f9f7 355 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 .weak CAN1_SCE_IRQHandler
<> 144:ef7eb2e8f9f7 358 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 .weak EXTI9_5_IRQHandler
<> 144:ef7eb2e8f9f7 361 .thumb_set EXTI9_5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 .weak TIM1_BRK_TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 364 .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 .weak TIM1_UP_TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 367 .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 .weak TIM1_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 370 .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 .weak TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 373 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 .weak TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 376 .thumb_set TIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 .weak I2C1_EV_IRQHandler
<> 144:ef7eb2e8f9f7 379 .thumb_set I2C1_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 .weak I2C1_ER_IRQHandler
<> 144:ef7eb2e8f9f7 382 .thumb_set I2C1_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 385 .thumb_set SPI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 .weak USART1_IRQHandler
<> 144:ef7eb2e8f9f7 388 .thumb_set USART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 .weak USART2_IRQHandler
<> 144:ef7eb2e8f9f7 391 .thumb_set USART2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 .weak EXTI15_10_IRQHandler
<> 144:ef7eb2e8f9f7 394 .thumb_set EXTI15_10_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 .weak RTC_Alarm_IRQHandler
<> 144:ef7eb2e8f9f7 397 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 .weak SPI3_IRQHandler
<> 144:ef7eb2e8f9f7 400 .thumb_set SPI3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 .weak TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 403 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 .weak TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 406 .thumb_set TIM7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 .weak DMA2_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 409 .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 .weak DMA2_Channel2_IRQHandler
<> 144:ef7eb2e8f9f7 412 .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 .weak DMA2_Channel3_IRQHandler
<> 144:ef7eb2e8f9f7 415 .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 .weak DMA2_Channel4_IRQHandler
<> 144:ef7eb2e8f9f7 418 .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 .weak DMA2_Channel5_IRQHandler
<> 144:ef7eb2e8f9f7 421 .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 .weak COMP_IRQHandler
<> 144:ef7eb2e8f9f7 424 .thumb_set COMP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 .weak LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 427 .thumb_set LPTIM1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 .weak LPTIM2_IRQHandler
<> 144:ef7eb2e8f9f7 430 .thumb_set LPTIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 .weak USB_IRQHandler
<> 144:ef7eb2e8f9f7 433 .thumb_set USB_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 .weak DMA2_Channel6_IRQHandler
<> 144:ef7eb2e8f9f7 436 .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 .weak DMA2_Channel7_IRQHandler
<> 144:ef7eb2e8f9f7 439 .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 .weak LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 442 .thumb_set LPUART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 .weak QUADSPI_IRQHandler
<> 144:ef7eb2e8f9f7 445 .thumb_set QUADSPI_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 .weak I2C3_EV_IRQHandler
<> 144:ef7eb2e8f9f7 448 .thumb_set I2C3_EV_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 .weak I2C3_ER_IRQHandler
<> 144:ef7eb2e8f9f7 451 .thumb_set I2C3_ER_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 .weak SAI1_IRQHandler
<> 144:ef7eb2e8f9f7 454 .thumb_set SAI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 .weak SWPMI1_IRQHandler
<> 144:ef7eb2e8f9f7 457 .thumb_set SWPMI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 .weak TSC_IRQHandler
<> 144:ef7eb2e8f9f7 460 .thumb_set TSC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 .weak RNG_IRQHandler
<> 144:ef7eb2e8f9f7 463 .thumb_set RNG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 .weak FPU_IRQHandler
<> 144:ef7eb2e8f9f7 466 .thumb_set FPU_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 .weak CRS_IRQHandler
<> 144:ef7eb2e8f9f7 469 .thumb_set CRS_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 470 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/