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targets/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h@149:156823d33999, 2016-10-28 (annotated)
- Committer:
- <>
- Date:
- Fri Oct 28 11:17:30 2016 +0100
- Revision:
- 149:156823d33999
- Parent:
- targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h@144:ef7eb2e8f9f7
This updates the lib to the mbed lib v128
NOTE: This release includes a restructuring of the file and directory locations and thus some
include paths in your code may need updating accordingly.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #ifndef MBED_PERIPHERALNAMES_H |
<> | 144:ef7eb2e8f9f7 | 17 | #define MBED_PERIPHERALNAMES_H |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | #include "cmsis.h" |
<> | 144:ef7eb2e8f9f7 | 20 | #include "PinNames.h" |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 23 | extern "C" { |
<> | 144:ef7eb2e8f9f7 | 24 | #endif |
<> | 144:ef7eb2e8f9f7 | 25 | |
<> | 144:ef7eb2e8f9f7 | 26 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 27 | UART0, |
<> | 144:ef7eb2e8f9f7 | 28 | UART1, |
<> | 144:ef7eb2e8f9f7 | 29 | UART2, |
<> | 144:ef7eb2e8f9f7 | 30 | UART3, |
<> | 144:ef7eb2e8f9f7 | 31 | UART4, |
<> | 144:ef7eb2e8f9f7 | 32 | UART5, |
<> | 144:ef7eb2e8f9f7 | 33 | UART6, |
<> | 144:ef7eb2e8f9f7 | 34 | UART7, |
<> | 144:ef7eb2e8f9f7 | 35 | } UARTName; |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | // PWMType & 1 == 1 then have to use PWDTR[12] == 1 |
<> | 144:ef7eb2e8f9f7 | 38 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 39 | PWM1A = 0, |
<> | 144:ef7eb2e8f9f7 | 40 | PWM1B, |
<> | 144:ef7eb2e8f9f7 | 41 | PWM1C, |
<> | 144:ef7eb2e8f9f7 | 42 | PWM1D, |
<> | 144:ef7eb2e8f9f7 | 43 | PWM1E, |
<> | 144:ef7eb2e8f9f7 | 44 | PWM1F, |
<> | 144:ef7eb2e8f9f7 | 45 | PWM1G, |
<> | 144:ef7eb2e8f9f7 | 46 | PWM1H, |
<> | 144:ef7eb2e8f9f7 | 47 | PWM2A = 0x10, |
<> | 144:ef7eb2e8f9f7 | 48 | PWM2B, |
<> | 144:ef7eb2e8f9f7 | 49 | PWM2C, |
<> | 144:ef7eb2e8f9f7 | 50 | PWM2D, |
<> | 144:ef7eb2e8f9f7 | 51 | PWM2E, |
<> | 144:ef7eb2e8f9f7 | 52 | PWM2F, |
<> | 144:ef7eb2e8f9f7 | 53 | PWM2G, |
<> | 144:ef7eb2e8f9f7 | 54 | PWM2H, |
<> | 144:ef7eb2e8f9f7 | 55 | } PWMType; |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 58 | TIOC0A = 0, |
<> | 144:ef7eb2e8f9f7 | 59 | TIOC0B, |
<> | 144:ef7eb2e8f9f7 | 60 | TIOC0C, |
<> | 144:ef7eb2e8f9f7 | 61 | TIOC0D, |
<> | 144:ef7eb2e8f9f7 | 62 | TIOC1A = 0x10, |
<> | 144:ef7eb2e8f9f7 | 63 | TIOC1B, |
<> | 144:ef7eb2e8f9f7 | 64 | TIOC2A = 0x20, |
<> | 144:ef7eb2e8f9f7 | 65 | TIOC2B, |
<> | 144:ef7eb2e8f9f7 | 66 | TIOC3A = 0x30, |
<> | 144:ef7eb2e8f9f7 | 67 | TIOC3B, |
<> | 144:ef7eb2e8f9f7 | 68 | TIOC3C, |
<> | 144:ef7eb2e8f9f7 | 69 | TIOC3D, |
<> | 144:ef7eb2e8f9f7 | 70 | TIOC4A = 0x40, |
<> | 144:ef7eb2e8f9f7 | 71 | TIOC4B, |
<> | 144:ef7eb2e8f9f7 | 72 | TIOC4C, |
<> | 144:ef7eb2e8f9f7 | 73 | TIOC4D, |
<> | 144:ef7eb2e8f9f7 | 74 | } MTU2_PWMType; |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 77 | PWM0_PIN = 0, |
<> | 144:ef7eb2e8f9f7 | 78 | PWM1_PIN, |
<> | 144:ef7eb2e8f9f7 | 79 | PWM2_PIN, |
<> | 144:ef7eb2e8f9f7 | 80 | PWM3_PIN, |
<> | 144:ef7eb2e8f9f7 | 81 | PWM4_PIN, |
<> | 144:ef7eb2e8f9f7 | 82 | PWM5_PIN, |
<> | 144:ef7eb2e8f9f7 | 83 | PWM6_PIN, |
<> | 144:ef7eb2e8f9f7 | 84 | PWM7_PIN, |
<> | 144:ef7eb2e8f9f7 | 85 | PWM8_PIN, |
<> | 144:ef7eb2e8f9f7 | 86 | PWM9_PIN, |
<> | 144:ef7eb2e8f9f7 | 87 | PWM10_PIN, |
<> | 144:ef7eb2e8f9f7 | 88 | PWM11_PIN, |
<> | 144:ef7eb2e8f9f7 | 89 | PWM12_PIN, |
<> | 144:ef7eb2e8f9f7 | 90 | PWM13_PIN, |
<> | 144:ef7eb2e8f9f7 | 91 | MTU2_PWM0_PIN = 0x20, |
<> | 144:ef7eb2e8f9f7 | 92 | MTU2_PWM1_PIN, |
<> | 144:ef7eb2e8f9f7 | 93 | MTU2_PWM2_PIN, |
<> | 144:ef7eb2e8f9f7 | 94 | MTU2_PWM3_PIN, |
<> | 144:ef7eb2e8f9f7 | 95 | MTU2_PWM4_PIN, |
<> | 144:ef7eb2e8f9f7 | 96 | MTU2_PWM5_PIN, |
<> | 144:ef7eb2e8f9f7 | 97 | MTU2_PWM6_PIN, |
<> | 144:ef7eb2e8f9f7 | 98 | MTU2_PWM7_PIN, |
<> | 144:ef7eb2e8f9f7 | 99 | MTU2_PWM8_PIN, |
<> | 144:ef7eb2e8f9f7 | 100 | MTU2_PWM9_PIN, |
<> | 144:ef7eb2e8f9f7 | 101 | MTU2_PWM10_PIN, |
<> | 144:ef7eb2e8f9f7 | 102 | MTU2_PWM11_PIN, |
<> | 144:ef7eb2e8f9f7 | 103 | MTU2_PWM12_PIN, |
<> | 144:ef7eb2e8f9f7 | 104 | MTU2_PWM13_PIN, |
<> | 144:ef7eb2e8f9f7 | 105 | MTU2_PWM14_PIN, |
<> | 144:ef7eb2e8f9f7 | 106 | MTU2_PWM15_PIN, |
<> | 144:ef7eb2e8f9f7 | 107 | MTU2_PWM16_PIN, |
<> | 144:ef7eb2e8f9f7 | 108 | MTU2_PWM17_PIN, |
<> | 144:ef7eb2e8f9f7 | 109 | MTU2_PWM18_PIN, |
<> | 144:ef7eb2e8f9f7 | 110 | MTU2_PWM19_PIN, |
<> | 144:ef7eb2e8f9f7 | 111 | MTU2_PWM20_PIN, |
<> | 144:ef7eb2e8f9f7 | 112 | MTU2_PWM21_PIN, |
<> | 144:ef7eb2e8f9f7 | 113 | } PWMName; |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 116 | AN0= 0, |
<> | 144:ef7eb2e8f9f7 | 117 | AN1= 1, |
<> | 144:ef7eb2e8f9f7 | 118 | AN2= 2, |
<> | 144:ef7eb2e8f9f7 | 119 | AN3= 3, |
<> | 144:ef7eb2e8f9f7 | 120 | AN4= 4, |
<> | 144:ef7eb2e8f9f7 | 121 | AN5= 5, |
<> | 144:ef7eb2e8f9f7 | 122 | AN6= 6, |
<> | 144:ef7eb2e8f9f7 | 123 | AN7= 7, |
<> | 144:ef7eb2e8f9f7 | 124 | } ADCName; |
<> | 144:ef7eb2e8f9f7 | 125 | |
<> | 144:ef7eb2e8f9f7 | 126 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 127 | SPI_0 = 0, |
<> | 144:ef7eb2e8f9f7 | 128 | SPI_1, |
<> | 144:ef7eb2e8f9f7 | 129 | SPI_2, |
<> | 144:ef7eb2e8f9f7 | 130 | SPI_3, |
<> | 144:ef7eb2e8f9f7 | 131 | } SPIName; |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 134 | I2C_0 = 0, |
<> | 144:ef7eb2e8f9f7 | 135 | I2C_1, |
<> | 144:ef7eb2e8f9f7 | 136 | I2C_2, |
<> | 144:ef7eb2e8f9f7 | 137 | I2C_3 |
<> | 144:ef7eb2e8f9f7 | 138 | } I2CName; |
<> | 144:ef7eb2e8f9f7 | 139 | |
<> | 144:ef7eb2e8f9f7 | 140 | typedef enum { |
<> | 144:ef7eb2e8f9f7 | 141 | CAN_0 = 0, |
<> | 144:ef7eb2e8f9f7 | 142 | CAN_1, |
<> | 144:ef7eb2e8f9f7 | 143 | CAN_2, |
<> | 144:ef7eb2e8f9f7 | 144 | CAN_3, |
<> | 144:ef7eb2e8f9f7 | 145 | CAN_4 |
<> | 144:ef7eb2e8f9f7 | 146 | } CANName; |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | #define STDIO_UART_TX USBTX |
<> | 144:ef7eb2e8f9f7 | 150 | #define STDIO_UART_RX USBRX |
<> | 144:ef7eb2e8f9f7 | 151 | #define STDIO_UART UART2 |
<> | 144:ef7eb2e8f9f7 | 152 | |
<> | 144:ef7eb2e8f9f7 | 153 | |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 156 | } |
<> | 144:ef7eb2e8f9f7 | 157 | #endif |
<> | 144:ef7eb2e8f9f7 | 158 | |
<> | 144:ef7eb2e8f9f7 | 159 | #endif |