Amit Gandhi / mbed-dev

test

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
150:02e0a0aed4ec
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file rfAna.c
<> 149:156823d33999 4 * @brief Implementation of rfAna hw module functions
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3445 $
<> 149:156823d33999 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rfAna
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 *
<> 149:156823d33999 31 * <h1> Reference document(s) </h1>
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 /*************************************************************************************************
<> 149:156823d33999 35 * *
<> 149:156823d33999 36 * Header files *
<> 149:156823d33999 37 * *
<> 149:156823d33999 38 *************************************************************************************************/
<> 149:156823d33999 39
<> 149:156823d33999 40 #include "memory_map.h"
<> 149:156823d33999 41 #include "rfAna.h"
<> 149:156823d33999 42 #include "clock.h"
<> 149:156823d33999 43
<> 149:156823d33999 44 #ifdef REVA
<> 149:156823d33999 45 #include "test.h"
<> 149:156823d33999 46 #endif
<> 149:156823d33999 47
<> 149:156823d33999 48 /*************************************************************************************************
<> 149:156823d33999 49 * *
<> 149:156823d33999 50 * Global variables *
<> 149:156823d33999 51 * *
<> 149:156823d33999 52 *************************************************************************************************/
<> 149:156823d33999 53
<> 149:156823d33999 54 /** Rf channel and tx power lookup tables (constant)
<> 149:156823d33999 55 * @details
<> 149:156823d33999 56 *
<> 149:156823d33999 57 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
<> 149:156823d33999 58 * It has 16 entries corresponding to 16 15.4 channels.
<> 149:156823d33999 59 * Entry 1 <-> Channel 11
<> 149:156823d33999 60 * ...
<> 149:156823d33999 61 * Entry 16 <-> Channel 26
<> 149:156823d33999 62 *
<> 149:156823d33999 63 * Each entry is compound of 4 items.
<> 149:156823d33999 64 * Item 0: Rx Frequency integer divide portion
<> 149:156823d33999 65 * Item 1: Rx Frequency fractional divide portion
<> 149:156823d33999 66 * Item 2: Tx Frequency integer divide portion
<> 149:156823d33999 67 * Item 3: Tx Frequency fractional divide portion
<> 149:156823d33999 68 *
<> 149:156823d33999 69 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
<> 149:156823d33999 70 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
<> 149:156823d33999 71 * Entry 1 <-> -32dB
<> 149:156823d33999 72 * Entry 2 <-> -31dB
<> 149:156823d33999 73 * ...
<> 149:156823d33999 74 * Entry 2 <-> 9dB
<> 149:156823d33999 75 * Entry 43 <-> +10dB
<> 149:156823d33999 76 *
<> 149:156823d33999 77 * Each entry is compound of 1 byte.
<> 149:156823d33999 78 */
<> 149:156823d33999 79
<> 149:156823d33999 80 // RR: Making high side injection changes to RevD
<> 149:156823d33999 81 #ifdef REVD
<> 149:156823d33999 82
<> 149:156823d33999 83 /** This rf LUT is built for high side injection, using low side injection
<> 149:156823d33999 84 * would requiere to change this LUT. */
<> 149:156823d33999 85 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
<> 149:156823d33999 86 {0x50,0x017F52,0x4B,0x014001},
<> 149:156823d33999 87 {0x51,0xFE29FB,0x4B,0x01E001},
<> 149:156823d33999 88 {0x51,0xFED4A6,0x4C,0xFE7FFF},
<> 149:156823d33999 89 {0x51,0xFF7F51,0x4C,0xFF1FFF},
<> 149:156823d33999 90 {0x51,0x0029FC,0x4C,0xFFC000},
<> 149:156823d33999 91 {0x51,0x00D4A7,0x4C,0x006000},
<> 149:156823d33999 92 {0x51,0x017F52,0x4C,0x010001},
<> 149:156823d33999 93 {0x52,0xFE29FB,0x4C,0x01A001},
<> 149:156823d33999 94 {0x52,0xFED4A6,0x4D,0xFE3FFF},
<> 149:156823d33999 95 {0x52,0xFF7F51,0x4D,0xFEDFFF},
<> 149:156823d33999 96 {0x52,0x0029FC,0x4D,0xFF8000},
<> 149:156823d33999 97 {0x52,0x00D4A7,0x4D,0x002000},
<> 149:156823d33999 98 {0x52,0x017F52,0x4D,0x00C001},
<> 149:156823d33999 99 {0x53,0xFE29FB,0x4D,0x016001},
<> 149:156823d33999 100 {0x53,0xFED4A6,0x4E,0xFDFFFE}
<> 149:156823d33999 101 };
<> 149:156823d33999 102
<> 149:156823d33999 103 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 149:156823d33999 104 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 149:156823d33999 105 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
<> 149:156823d33999 106 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
<> 149:156823d33999 107 13,14,15,16,17,18,19,20,20,20
<> 149:156823d33999 108 }; // +1dBm to +10 dBm
<> 149:156823d33999 109
<> 149:156823d33999 110 #endif /* REVD */
<> 149:156823d33999 111
<> 149:156823d33999 112 #ifdef REVC
<> 149:156823d33999 113 /** This rf LUT is built for low side injection, using high side injection
<> 149:156823d33999 114 * would requiere to change this LUT. */
<> 149:156823d33999 115 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
<> 149:156823d33999 116 {0x47,0xFFAC93,0x4B,0x014001},
<> 149:156823d33999 117 {0x47,0x00432A,0x4B,0x01E001},
<> 149:156823d33999 118 {0x47,0x00D9C1,0x4C,0xFE7FFF},
<> 149:156823d33999 119 {0x47,0x017058,0x4C,0xFF1FFF},
<> 149:156823d33999 120 {0x48,0xFE06EC,0x4C,0xFFC000},
<> 149:156823d33999 121 {0x48,0xFE9D83,0x4C,0x006000},
<> 149:156823d33999 122 {0x48,0xFF341A,0x4C,0x010001},
<> 149:156823d33999 123 {0x48,0xFFCAB1,0x4C,0x01A001},
<> 149:156823d33999 124 {0x48,0x006148,0x4D,0xFE3FFF},
<> 149:156823d33999 125 {0x48,0x00F7DF,0x4D,0xFEDFFF},
<> 149:156823d33999 126 {0x48,0x018E76,0x4D,0xFF8000},
<> 149:156823d33999 127 {0x49,0xFE250A,0x4D,0x002000},
<> 149:156823d33999 128 {0x49,0xFEBBA1,0x4D,0x00C001},
<> 149:156823d33999 129 {0x49,0xFF5238,0x4D,0x016001},
<> 149:156823d33999 130 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
<> 149:156823d33999 131 };
<> 149:156823d33999 132
<> 149:156823d33999 133 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 149:156823d33999 134 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 149:156823d33999 135 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
<> 149:156823d33999 136 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
<> 149:156823d33999 137 17,19,20,20,20,20,20,20,20,20
<> 149:156823d33999 138 }; // +1dBm to +10 dBm (clamp high at +3dB)
<> 149:156823d33999 139 #endif /* REVC */
<> 149:156823d33999 140
<> 149:156823d33999 141 #ifdef REVB
<> 149:156823d33999 142 /** This rf LUT is built for low side injection, using high side injection
<> 149:156823d33999 143 * would requiere to change this LUT. */
<> 149:156823d33999 144 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
<> 149:156823d33999 145 {0x47,0xFFAC93,0x4B,0x014001},
<> 149:156823d33999 146 {0x47,0x00432A,0x4B,0x01E001},
<> 149:156823d33999 147 {0x47,0x00D9C1,0x4C,0xFE7FFF},
<> 149:156823d33999 148 {0x47,0x017058,0x4C,0xFF1FFF},
<> 149:156823d33999 149 {0x48,0xFE06EC,0x4C,0xFFC000},
<> 149:156823d33999 150 {0x48,0xFE9D83,0x4C,0x006000},
<> 149:156823d33999 151 {0x48,0xFF341A,0x4C,0x010001},
<> 149:156823d33999 152 {0x48,0xFFCAB1,0x4C,0x01A001},
<> 149:156823d33999 153 {0x48,0x006148,0x4D,0xFE3FFF},
<> 149:156823d33999 154 {0x48,0x00F7DF,0x4D,0xFEDFFF},
<> 149:156823d33999 155 {0x48,0x018E76,0x4D,0xFF8000},
<> 149:156823d33999 156 {0x49,0xFE250A,0x4D,0x002000},
<> 149:156823d33999 157 {0x49,0xFEBBA1,0x4D,0x00C001},
<> 149:156823d33999 158 {0x49,0xFF5238,0x4D,0x016001},
<> 149:156823d33999 159 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
<> 149:156823d33999 160 };
<> 149:156823d33999 161
<> 149:156823d33999 162 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 149:156823d33999 163 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 149:156823d33999 164 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
<> 149:156823d33999 165 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
<> 149:156823d33999 166 17,19,20,20,20,20,20,20,20,20
<> 149:156823d33999 167 }; // +1dBm to +10 dBm (clamp high at +3dB)
<> 149:156823d33999 168 #endif
<> 149:156823d33999 169
<> 149:156823d33999 170 #ifdef REVA
<> 149:156823d33999 171 const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
<> 149:156823d33999 172 {0x57,0x0007DA,0x52,0xFE1FFF},
<> 149:156823d33999 173 {0x57,0x00B285,0x52,0xFEBFFF},
<> 149:156823d33999 174 {0x57,0x015D30,0x52,0xFF6000},
<> 149:156823d33999 175 {0x58,0xFE07D8,0x52,0x000000},
<> 149:156823d33999 176 {0x58,0xFEB283,0x52,0x00A000},
<> 149:156823d33999 177 {0x58,0xFF5D2F,0x52,0x014001},
<> 149:156823d33999 178 {0x58,0x0007DA,0x52,0x01E001},
<> 149:156823d33999 179 {0x58,0x00B285,0x53,0xFE7FFF},
<> 149:156823d33999 180 {0x58,0x015D30,0x53,0xFF1FFF},
<> 149:156823d33999 181 {0x59,0xFE07D8,0x53,0xFFC000},
<> 149:156823d33999 182 {0x59,0xFEB283,0x53,0x006000},
<> 149:156823d33999 183 {0x59,0xFF5D2F,0x53,0x010001},
<> 149:156823d33999 184 {0x59,0x0007DA,0x53,0x01A001},
<> 149:156823d33999 185 {0x59,0x00B285,0x53,0xFE3FFF},
<> 149:156823d33999 186 {0x59,0x015D30,0x53,0xFEDFFF}
<> 149:156823d33999 187 };
<> 149:156823d33999 188
<> 149:156823d33999 189 const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
<> 149:156823d33999 190 4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
<> 149:156823d33999 191 5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
<> 149:156823d33999 192 5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
<> 149:156823d33999 193 5,5,5,5,5,5,5,5,5,5
<> 149:156823d33999 194 }; // +1dBm to +10 dBm
<> 149:156823d33999 195 #endif
<> 149:156823d33999 196
<> 149:156823d33999 197 /*************************************************************************************************
<> 149:156823d33999 198 * *
<> 149:156823d33999 199 * Functions *
<> 149:156823d33999 200 * *
<> 149:156823d33999 201 *************************************************************************************************/
<> 149:156823d33999 202
<> 149:156823d33999 203 void fRfAnaInit()
<> 149:156823d33999 204 {
<> 149:156823d33999 205 // Enable rfana clock
<> 149:156823d33999 206 CLOCK_ENABLE(CLOCK_RFANA);
<> 149:156823d33999 207
<> 149:156823d33999 208 #ifdef REVA
<> 149:156823d33999 209 // Force Pll lock (it shouldn't be needed for either silicon if the part is configured/trimmed properly)
<> 149:156823d33999 210 fTestForcePllLock();
<> 149:156823d33999 211 // Bypass Pll regulator
<> 149:156823d33999 212 fTestBypassPllReg();
<> 149:156823d33999 213 #endif
<> 149:156823d33999 214
<> 149:156823d33999 215 // Set PLL timing
<> 149:156823d33999 216 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
<> 149:156823d33999 217 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
<> 149:156823d33999 218
<> 149:156823d33999 219 // Set other parameters
<> 149:156823d33999 220 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
<> 149:156823d33999 221 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
<> 149:156823d33999 222 }
<> 149:156823d33999 223
<> 149:156823d33999 224 boolean fRfAnaIoctl (uint32_t request, void *argument)
<> 149:156823d33999 225 {
<> 149:156823d33999 226 uint8_t channel, txPower;
<> 149:156823d33999 227
<> 149:156823d33999 228 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
<> 149:156823d33999 229 CLOCK_ENABLE(CLOCK_RFANA);
<> 149:156823d33999 230
<> 149:156823d33999 231 switch(request) {
<> 149:156823d33999 232 case SET_RF_CHANNEL:
<> 149:156823d33999 233 channel = *(uint8_t*)argument;
<> 149:156823d33999 234
<> 149:156823d33999 235 // Set tx/rx integer/fractional divide portions
<> 149:156823d33999 236 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
<> 149:156823d33999 237 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
<> 149:156823d33999 238 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
<> 149:156823d33999 239 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
<> 149:156823d33999 240
<> 149:156823d33999 241 // Set tx/rx vco trims
<> 149:156823d33999 242 #ifdef REVB
<> 149:156823d33999 243 /** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 149:156823d33999 244 * from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
<> 149:156823d33999 245 if (channel < 19) {
<> 149:156823d33999 246 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
<> 149:156823d33999 247 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
<> 149:156823d33999 248 } else {
<> 149:156823d33999 249 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
<> 149:156823d33999 250 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
<> 149:156823d33999 251 }
<> 149:156823d33999 252 #endif /* REVB */
<> 149:156823d33999 253 #ifdef REVC
<> 149:156823d33999 254 /** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 149:156823d33999 255 * from trims stored in dedicated registers available in digital.*/
<> 149:156823d33999 256 if (channel < 19) {
<> 149:156823d33999 257 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 258 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 259 } else {
<> 149:156823d33999 260 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 261 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 262 }
<> 149:156823d33999 263 #endif /* REVC */
<> 149:156823d33999 264 #ifdef REVD
<> 149:156823d33999 265 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 149:156823d33999 266 * from trims stored in dedicated registers available in digital.*/
<> 149:156823d33999 267 if (channel < 19) {
<> 149:156823d33999 268 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 269 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 149:156823d33999 270 } else {
<> 149:156823d33999 271 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 272 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 149:156823d33999 273 }
<> 149:156823d33999 274 #endif /* REVD */
<> 149:156823d33999 275 break;
<> 149:156823d33999 276 case SET_TX_POWER:
<> 149:156823d33999 277 txPower = *(uint8_t*)argument;
<> 149:156823d33999 278
<> 149:156823d33999 279 // Set tx power register
<> 149:156823d33999 280 if ((txPower & 0x20) == 0) {
<> 149:156823d33999 281 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
<> 149:156823d33999 282 } else {
<> 149:156823d33999 283 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
<> 149:156823d33999 284 }
<> 149:156823d33999 285
<> 149:156823d33999 286 break;
<> 149:156823d33999 287 default:
<> 149:156823d33999 288 return False;
<> 149:156823d33999 289 }
<> 149:156823d33999 290 return True;
<> 149:156823d33999 291 }