Amir Chaudhary / SX1276Lib

Hexmodal SX1276lib

Dependents:   LoRaWAN-hello-world_Class_C_Anish

sx1276/sx1276-hal.cpp@25:3778e6204cc1, 2016-05-13 (annotated)

Committer:
mluis
Date:
Fri May 13 15:09:10 2016 +0000
Revision:
25:3778e6204cc1
Parent:
22:7f3aab69cca9 
Synchronized with https://github.com/Lora-net/LoRaMac-node radio drivers git revision 55d16ca8949c09ee241c87b7600e2a8bc90d3743

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
GregCr 0:e6ceb13d2d05 22 PinName antSwitch )
mluis 21:2e496deb7858 23 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
GregCr 0:e6ceb13d2d05 24 antSwitch( antSwitch ),
GregCr 12:aa5b3bf7fdf4 25 #if( defined ( TARGET_NUCLEO_L152RE ) )
mluis 25:3778e6204cc1 26 fake( D8 )
GregCr 12:aa5b3bf7fdf4 27 #else
GregCr 0:e6ceb13d2d05 28 fake( A3 )
GregCr 0:e6ceb13d2d05 29 #endif
GregCr 0:e6ceb13d2d05 30 {
mluis 21:2e496deb7858 31 this->RadioEvents = events;
mluis 21:2e496deb7858 32
GregCr 0:e6ceb13d2d05 33 Reset( );
mluis 25:3778e6204cc1 34
GregCr 0:e6ceb13d2d05 35 RxChainCalibration( );
mluis 25:3778e6204cc1 36
GregCr 0:e6ceb13d2d05 37 IoInit( );
mluis 25:3778e6204cc1 38
GregCr 0:e6ceb13d2d05 39 SetOpMode( RF_OPMODE_SLEEP );
mluis 25:3778e6204cc1 40
GregCr 0:e6ceb13d2d05 41 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 42
GregCr 0:e6ceb13d2d05 43 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 44
GregCr 0:e6ceb13d2d05 45 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 46
mluis 21:2e496deb7858 47 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 48 }
GregCr 0:e6ceb13d2d05 49
mluis 25:3778e6204cc1 50 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 51 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 52 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
GregCr 0:e6ceb13d2d05 53 antSwitch( A4 ),
GregCr 0:e6ceb13d2d05 54 fake( D8 )
mluis 20:e05596ba4166 55 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 56 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 20:e05596ba4166 57 antSwitch( P0_23 ),
mluis 20:e05596ba4166 58 fake( A3 )
GregCr 0:e6ceb13d2d05 59 #else
mluis 21:2e496deb7858 60 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
GregCr 12:aa5b3bf7fdf4 61 antSwitch( A4 ),
GregCr 12:aa5b3bf7fdf4 62 fake( A3 )
GregCr 0:e6ceb13d2d05 63 #endif
GregCr 0:e6ceb13d2d05 64 {
mluis 21:2e496deb7858 65 this->RadioEvents = events;
mluis 21:2e496deb7858 66
GregCr 0:e6ceb13d2d05 67 Reset( );
mluis 25:3778e6204cc1 68
GregCr 5:11ec8a6ba4f0 69 boardConnected = UNKNOWN;
mluis 25:3778e6204cc1 70
GregCr 1:f979673946c0 71 DetectBoardType( );
mluis 25:3778e6204cc1 72
GregCr 0:e6ceb13d2d05 73 RxChainCalibration( );
mluis 25:3778e6204cc1 74
GregCr 0:e6ceb13d2d05 75 IoInit( );
mluis 25:3778e6204cc1 76
GregCr 0:e6ceb13d2d05 77 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 78 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 79
GregCr 0:e6ceb13d2d05 80 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 81
GregCr 0:e6ceb13d2d05 82 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 83
mluis 21:2e496deb7858 84 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 85 }
GregCr 0:e6ceb13d2d05 86
GregCr 0:e6ceb13d2d05 87 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 88 // Board relative functions
GregCr 0:e6ceb13d2d05 89 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 90 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 91 {
GregCr 5:11ec8a6ba4f0 92 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 93 {
GregCr 5:11ec8a6ba4f0 94 antSwitch.input( );
GregCr 5:11ec8a6ba4f0 95 wait_ms( 1 );
GregCr 5:11ec8a6ba4f0 96 if( antSwitch == 1 )
GregCr 5:11ec8a6ba4f0 97 {
GregCr 5:11ec8a6ba4f0 98 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 99 }
GregCr 5:11ec8a6ba4f0 100 else
GregCr 5:11ec8a6ba4f0 101 {
GregCr 5:11ec8a6ba4f0 102 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 103 }
GregCr 5:11ec8a6ba4f0 104 antSwitch.output( );
GregCr 5:11ec8a6ba4f0 105 wait_ms( 1 );
GregCr 1:f979673946c0 106 }
GregCr 2:5eb3066446dd 107 return ( boardConnected );
GregCr 1:f979673946c0 108 }
GregCr 0:e6ceb13d2d05 109
GregCr 0:e6ceb13d2d05 110 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 111 {
GregCr 0:e6ceb13d2d05 112 AntSwInit( );
GregCr 0:e6ceb13d2d05 113 SpiInit( );
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
mluis 22:7f3aab69cca9 116 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 117 {
GregCr 0:e6ceb13d2d05 118 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 119 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 120 {
GregCr 0:e6ceb13d2d05 121 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 122 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 123 }
GregCr 0:e6ceb13d2d05 124 }
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 127 {
GregCr 0:e6ceb13d2d05 128 nss = 1;
GregCr 0:e6ceb13d2d05 129 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 130 uint32_t frequencyToSet = 8000000;
GregCr 0:e6ceb13d2d05 131 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
GregCr 0:e6ceb13d2d05 132 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 133 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 134 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 135 #else
GregCr 0:e6ceb13d2d05 136 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 137 #endif
GregCr 0:e6ceb13d2d05 138 wait(0.1);
GregCr 0:e6ceb13d2d05 139 }
GregCr 0:e6ceb13d2d05 140
GregCr 0:e6ceb13d2d05 141 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 142 {
mluis 25:3778e6204cc1 143 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 25:3778e6204cc1 144 dio0.mode( PullDown );
mluis 25:3778e6204cc1 145 dio1.mode( PullDown );
mluis 25:3778e6204cc1 146 dio2.mode( PullDown );
mluis 25:3778e6204cc1 147 dio3.mode( PullDown );
mluis 25:3778e6204cc1 148 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 149 #endif
GregCr 0:e6ceb13d2d05 150 dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) );
GregCr 0:e6ceb13d2d05 151 dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) );
GregCr 0:e6ceb13d2d05 152 dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) );
GregCr 0:e6ceb13d2d05 153 dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) );
GregCr 0:e6ceb13d2d05 154 dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) );
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 158 {
GregCr 0:e6ceb13d2d05 159 //nothing
GregCr 0:e6ceb13d2d05 160 }
GregCr 0:e6ceb13d2d05 161
GregCr 0:e6ceb13d2d05 162 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 163 {
GregCr 0:e6ceb13d2d05 164 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 165 {
GregCr 3:ca84be1f3fac 166 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 167 {
GregCr 1:f979673946c0 168 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 169 }
GregCr 1:f979673946c0 170 else
GregCr 1:f979673946c0 171 {
GregCr 1:f979673946c0 172 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 173 }
GregCr 0:e6ceb13d2d05 174 }
GregCr 0:e6ceb13d2d05 175 else
GregCr 0:e6ceb13d2d05 176 {
GregCr 0:e6ceb13d2d05 177 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 178 }
GregCr 0:e6ceb13d2d05 179 }
GregCr 0:e6ceb13d2d05 180
GregCr 0:e6ceb13d2d05 181 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 182 {
GregCr 0:e6ceb13d2d05 183 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 184 {
GregCr 0:e6ceb13d2d05 185 isRadioActive = status;
GregCr 0:e6ceb13d2d05 186
GregCr 0:e6ceb13d2d05 187 if( status == false )
GregCr 0:e6ceb13d2d05 188 {
GregCr 0:e6ceb13d2d05 189 AntSwInit( );
GregCr 0:e6ceb13d2d05 190 }
GregCr 0:e6ceb13d2d05 191 else
GregCr 0:e6ceb13d2d05 192 {
GregCr 0:e6ceb13d2d05 193 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 194 }
GregCr 0:e6ceb13d2d05 195 }
GregCr 0:e6ceb13d2d05 196 }
GregCr 0:e6ceb13d2d05 197
GregCr 0:e6ceb13d2d05 198 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 199 {
GregCr 0:e6ceb13d2d05 200 antSwitch = 0;
GregCr 0:e6ceb13d2d05 201 }
GregCr 0:e6ceb13d2d05 202
GregCr 0:e6ceb13d2d05 203 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 204 {
GregCr 0:e6ceb13d2d05 205 antSwitch = 0;
GregCr 0:e6ceb13d2d05 206 }
GregCr 0:e6ceb13d2d05 207
GregCr 0:e6ceb13d2d05 208 void SX1276MB1xAS::SetAntSw( uint8_t rxTx )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 this->rxTx = rxTx;
GregCr 0:e6ceb13d2d05 212
mluis 25:3778e6204cc1 213 // 1: Tx, 0: Rx
GregCr 0:e6ceb13d2d05 214 if( rxTx != 0 )
GregCr 0:e6ceb13d2d05 215 {
GregCr 0:e6ceb13d2d05 216 antSwitch = 1;
GregCr 0:e6ceb13d2d05 217 }
GregCr 0:e6ceb13d2d05 218 else
GregCr 0:e6ceb13d2d05 219 {
GregCr 0:e6ceb13d2d05 220 antSwitch = 0;
GregCr 0:e6ceb13d2d05 221 }
GregCr 0:e6ceb13d2d05 222 }
GregCr 0:e6ceb13d2d05 223
GregCr 0:e6ceb13d2d05 224 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 //TODO: Implement check, currently all frequencies are supported
GregCr 0:e6ceb13d2d05 227 return true;
GregCr 0:e6ceb13d2d05 228 }
GregCr 0:e6ceb13d2d05 229
GregCr 0:e6ceb13d2d05 230
GregCr 0:e6ceb13d2d05 231 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 232 {
GregCr 4:f0ce52e94d3f 233 reset.output();
GregCr 0:e6ceb13d2d05 234 reset = 0;
GregCr 0:e6ceb13d2d05 235 wait_ms( 1 );
GregCr 4:f0ce52e94d3f 236 reset.input();
GregCr 0:e6ceb13d2d05 237 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 238 }
GregCr 0:e6ceb13d2d05 239
GregCr 0:e6ceb13d2d05 240 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 241 {
GregCr 0:e6ceb13d2d05 242 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 243 }
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 246 {
GregCr 0:e6ceb13d2d05 247 uint8_t data;
GregCr 0:e6ceb13d2d05 248 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 249 return data;
GregCr 0:e6ceb13d2d05 250 }
GregCr 0:e6ceb13d2d05 251
GregCr 0:e6ceb13d2d05 252 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 253 {
GregCr 0:e6ceb13d2d05 254 uint8_t i;
GregCr 0:e6ceb13d2d05 255
GregCr 0:e6ceb13d2d05 256 nss = 0;
GregCr 0:e6ceb13d2d05 257 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 258 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 259 {
GregCr 0:e6ceb13d2d05 260 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 261 }
GregCr 0:e6ceb13d2d05 262 nss = 1;
GregCr 0:e6ceb13d2d05 263 }
GregCr 0:e6ceb13d2d05 264
GregCr 0:e6ceb13d2d05 265 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 uint8_t i;
GregCr 0:e6ceb13d2d05 268
GregCr 0:e6ceb13d2d05 269 nss = 0;
GregCr 0:e6ceb13d2d05 270 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 271 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 272 {
GregCr 0:e6ceb13d2d05 273 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275 nss = 1;
GregCr 0:e6ceb13d2d05 276 }
GregCr 0:e6ceb13d2d05 277
GregCr 0:e6ceb13d2d05 278 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 279 {
GregCr 0:e6ceb13d2d05 280 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 281 }
GregCr 0:e6ceb13d2d05 282
GregCr 0:e6ceb13d2d05 283 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 284 {
GregCr 0:e6ceb13d2d05 285 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 286 }