Ruprecht Altenburger / Mbed OS mirror_actuator_V1

Mirror actuator for RT2 lab

Dependencies:   FastPWM

Library_Misc/EncoderCounter.cpp@16:28b6bb8a4b7f, 2021-05-02 (annotated)

Committer:
altb2
Date:
Sun May 02 08:55:44 2021 +0000
Revision:
16:28b6bb8a4b7f
Parent:
15:9f32f64eee5b 
Final commit 4 students

Who changed what in which revision?

UserRevisionLine numberNew contents of line
altb2 15:9f32f64eee5b 1 /*
altb2 15:9f32f64eee5b 2 * EncoderCounter.cpp
altb2 15:9f32f64eee5b 3 * Copyright (c) 2017, ZHAW
altb2 15:9f32f64eee5b 4 * All rights reserved.
altb2 15:9f32f64eee5b 5 */
altb2 15:9f32f64eee5b 6
altb2 15:9f32f64eee5b 7 #include "EncoderCounter.h"
altb2 15:9f32f64eee5b 8
altb2 15:9f32f64eee5b 9
altb2 15:9f32f64eee5b 10 using namespace std;
altb2 15:9f32f64eee5b 11
altb2 15:9f32f64eee5b 12 /**
altb2 15:9f32f64eee5b 13 * Creates and initializes the driver to read the quadrature
altb2 15:9f32f64eee5b 14 * encoder counter of the STM32 microcontroller.
altb2 15:9f32f64eee5b 15 * @param a the input pin for the channel A.
altb2 15:9f32f64eee5b 16 * @param b the input pin for the channel B.
altb2 15:9f32f64eee5b 17 */
altb2 15:9f32f64eee5b 18 EncoderCounter::EncoderCounter(PinName a, PinName b) {
altb2 15:9f32f64eee5b 19
altb2 15:9f32f64eee5b 20 // check pins
altb2 15:9f32f64eee5b 21
altb2 15:9f32f64eee5b 22 if ((a == PA_6) && (b == PC_7)) {
altb2 15:9f32f64eee5b 23
altb2 15:9f32f64eee5b 24 // pinmap OK for TIM3 CH1 and CH2
altb2 15:9f32f64eee5b 25
altb2 15:9f32f64eee5b 26 TIM = TIM3;
altb2 15:9f32f64eee5b 27
altb2 15:9f32f64eee5b 28 // configure reset and clock control registers
altb2 15:9f32f64eee5b 29
altb2 15:9f32f64eee5b 30 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
altb2 15:9f32f64eee5b 31
altb2 15:9f32f64eee5b 32 // configure general purpose I/O registers
altb2 15:9f32f64eee5b 33
altb2 15:9f32f64eee5b 34 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
altb2 15:9f32f64eee5b 35 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
altb2 15:9f32f64eee5b 36 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
altb2 15:9f32f64eee5b 37 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
altb2 15:9f32f64eee5b 38 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
altb2 15:9f32f64eee5b 39 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
altb2 15:9f32f64eee5b 40
altb2 15:9f32f64eee5b 41 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
altb2 15:9f32f64eee5b 42 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
altb2 15:9f32f64eee5b 43 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
altb2 15:9f32f64eee5b 44 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
altb2 15:9f32f64eee5b 45 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
altb2 15:9f32f64eee5b 46 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
altb2 15:9f32f64eee5b 47
altb2 15:9f32f64eee5b 48 // configure reset and clock control registers
altb2 15:9f32f64eee5b 49
altb2 15:9f32f64eee5b 50 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
altb2 15:9f32f64eee5b 51 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
altb2 15:9f32f64eee5b 52
altb2 15:9f32f64eee5b 53 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
altb2 15:9f32f64eee5b 54
altb2 15:9f32f64eee5b 55 } else if ((a == PB_6) && (b == PB_7)) {
altb2 15:9f32f64eee5b 56
altb2 15:9f32f64eee5b 57 // pinmap OK for TIM4 CH1 and CH2
altb2 15:9f32f64eee5b 58
altb2 15:9f32f64eee5b 59 TIM = TIM4;
altb2 15:9f32f64eee5b 60
altb2 15:9f32f64eee5b 61 // configure reset and clock control registers
altb2 15:9f32f64eee5b 62
altb2 15:9f32f64eee5b 63 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
altb2 15:9f32f64eee5b 64
altb2 15:9f32f64eee5b 65 // configure general purpose I/O registers
altb2 15:9f32f64eee5b 66
altb2 15:9f32f64eee5b 67 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
altb2 15:9f32f64eee5b 68 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
altb2 15:9f32f64eee5b 69 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
altb2 15:9f32f64eee5b 70 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
altb2 15:9f32f64eee5b 71 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
altb2 15:9f32f64eee5b 72 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
altb2 15:9f32f64eee5b 73
altb2 15:9f32f64eee5b 74 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
altb2 15:9f32f64eee5b 75 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
altb2 15:9f32f64eee5b 76 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
altb2 15:9f32f64eee5b 77 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
altb2 15:9f32f64eee5b 78 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
altb2 15:9f32f64eee5b 79 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
altb2 15:9f32f64eee5b 80
altb2 15:9f32f64eee5b 81 // configure reset and clock control registers
altb2 15:9f32f64eee5b 82
altb2 15:9f32f64eee5b 83 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
altb2 15:9f32f64eee5b 84 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
altb2 15:9f32f64eee5b 85
altb2 15:9f32f64eee5b 86 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
altb2 15:9f32f64eee5b 87
altb2 15:9f32f64eee5b 88 } else {
altb2 15:9f32f64eee5b 89
altb2 15:9f32f64eee5b 90 printf("pinmap not found for peripheral\n");
altb2 15:9f32f64eee5b 91 }
altb2 15:9f32f64eee5b 92
altb2 15:9f32f64eee5b 93 // configure general purpose timer 3 or 4
altb2 15:9f32f64eee5b 94
altb2 15:9f32f64eee5b 95 TIM->CR1 = 0x0000; // counter disable
altb2 15:9f32f64eee5b 96 TIM->CR2 = 0x0000; // reset master mode selection
altb2 15:9f32f64eee5b 97 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
altb2 15:9f32f64eee5b 98 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
altb2 15:9f32f64eee5b 99 TIM->CCMR2 = 0x0000; // reset capture mode register 2
altb2 15:9f32f64eee5b 100 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
altb2 15:9f32f64eee5b 101 TIM->CNT = 0x0000; // reset counter value
altb2 15:9f32f64eee5b 102 TIM->ARR = 0xFFFF; // auto reload register
altb2 15:9f32f64eee5b 103 TIM->CR1 = TIM_CR1_CEN; // counter enable
altb2 15:9f32f64eee5b 104 }
altb2 15:9f32f64eee5b 105
altb2 15:9f32f64eee5b 106 EncoderCounter::~EncoderCounter() {}
altb2 15:9f32f64eee5b 107
altb2 15:9f32f64eee5b 108 /**
altb2 15:9f32f64eee5b 109 * Resets the counter value to zero.
altb2 15:9f32f64eee5b 110 */
altb2 15:9f32f64eee5b 111 void EncoderCounter::reset() {
altb2 15:9f32f64eee5b 112
altb2 15:9f32f64eee5b 113 TIM->CNT = 0x0000;
altb2 15:9f32f64eee5b 114 }
altb2 15:9f32f64eee5b 115
altb2 15:9f32f64eee5b 116 /**
altb2 15:9f32f64eee5b 117 * Resets the counter value to a given offset value.
altb2 15:9f32f64eee5b 118 * @param offset the offset value to reset the counter to.
altb2 15:9f32f64eee5b 119 */
altb2 15:9f32f64eee5b 120 void EncoderCounter::reset(short offset) {
altb2 15:9f32f64eee5b 121
altb2 15:9f32f64eee5b 122 TIM->CNT = -offset;
altb2 15:9f32f64eee5b 123 }
altb2 15:9f32f64eee5b 124
altb2 15:9f32f64eee5b 125 /**
altb2 15:9f32f64eee5b 126 * Reads the quadrature encoder counter value.
altb2 15:9f32f64eee5b 127 * @return the quadrature encoder counter as a signed 16-bit integer value.
altb2 15:9f32f64eee5b 128 */
altb2 15:9f32f64eee5b 129 short EncoderCounter::read() {
altb2 15:9f32f64eee5b 130
altb2 15:9f32f64eee5b 131 return (short)(-TIM->CNT);
altb2 15:9f32f64eee5b 132 }
altb2 15:9f32f64eee5b 133
altb2 15:9f32f64eee5b 134 /**
altb2 15:9f32f64eee5b 135 * The empty operator is a shorthand notation of the <code>read()</code> method.
altb2 15:9f32f64eee5b 136 */
altb2 15:9f32f64eee5b 137 EncoderCounter::operator short() {
altb2 15:9f32f64eee5b 138
altb2 15:9f32f64eee5b 139 return read();
altb2 15:9f32f64eee5b 140 }