Ivano Calabrese / ST-DEVKIT-LRWAN

ST-DEVKIT-LRWAN

Dependents:   DISCO-L072CZ-LRWAN1-base

Fork of SX1276GenericLib by Helmut Tschemernjak

sx1276/sx1276.cpp@22:7f3aab69cca9, 2015-11-26 (annotated)

Committer:
mluis
Date:
Thu Nov 26 16:55:15 2015 +0000
Revision:
22:7f3aab69cca9
Parent:
21:2e496deb7858
Child:
23:1e143575df0f
Synchronized the drivers with GitHub version.; Mainly added errata note recommendations

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
mluis 21:2e496deb7858 44 SX1276::SX1276( RadioEvents_t *events,
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 21:2e496deb7858 47 : Radio( events ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
mluis 13:618826a997e2 56 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 57 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 21:2e496deb7858 59 this->RadioEvents = events;
mluis 21:2e496deb7858 60
mluis 13:618826a997e2 61 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 62
mluis 13:618826a997e2 63 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 64 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 65 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 66 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 67 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 68 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 69
mluis 21:2e496deb7858 70 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 71 }
GregCr 0:e6ceb13d2d05 72
GregCr 0:e6ceb13d2d05 73 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 74 {
mluis 13:618826a997e2 75 delete this->rxBuffer;
mluis 13:618826a997e2 76 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
mluis 21:2e496deb7858 79 void SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 80 {
mluis 21:2e496deb7858 81 this->RadioEvents = events;
mluis 21:2e496deb7858 82 }
mluis 21:2e496deb7858 83
GregCr 19:71a47bb03fbb 84 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 85 {
GregCr 0:e6ceb13d2d05 86 return this->settings.State;
GregCr 0:e6ceb13d2d05 87 }
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 90 {
GregCr 0:e6ceb13d2d05 91 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 96 }
GregCr 0:e6ceb13d2d05 97
mluis 22:7f3aab69cca9 98 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 99 {
GregCr 7:2b555111463f 100 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 101
GregCr 0:e6ceb13d2d05 102 SetModem( modem );
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 SetChannel( freq );
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 107
GregCr 4:f0ce52e94d3f 108 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 109
GregCr 0:e6ceb13d2d05 110 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 Sleep( );
GregCr 0:e6ceb13d2d05 113
mluis 22:7f3aab69cca9 114 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 115 {
GregCr 0:e6ceb13d2d05 116 return false;
GregCr 0:e6ceb13d2d05 117 }
GregCr 0:e6ceb13d2d05 118 return true;
GregCr 0:e6ceb13d2d05 119 }
GregCr 0:e6ceb13d2d05 120
GregCr 0:e6ceb13d2d05 121 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 122 {
GregCr 0:e6ceb13d2d05 123 uint8_t i;
GregCr 0:e6ceb13d2d05 124 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 /*
GregCr 0:e6ceb13d2d05 127 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 128 */
GregCr 0:e6ceb13d2d05 129 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 130 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 134 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 143 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 146 {
GregCr 4:f0ce52e94d3f 147 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 148 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151
GregCr 0:e6ceb13d2d05 152 Sleep( );
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 return rnd;
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 /*!
mluis 22:7f3aab69cca9 158 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 159 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 160 * default values
mluis 22:7f3aab69cca9 161 */
mluis 22:7f3aab69cca9 162 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 163 {
mluis 22:7f3aab69cca9 164 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 165 uint32_t initialFreq;
mluis 22:7f3aab69cca9 166
mluis 22:7f3aab69cca9 167 // Save context
mluis 22:7f3aab69cca9 168 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 169 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 170 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 171 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 172
mluis 22:7f3aab69cca9 173 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 174 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 175
mluis 22:7f3aab69cca9 176 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 177 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 178 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 179 {
mluis 22:7f3aab69cca9 180 }
mluis 22:7f3aab69cca9 181
mluis 22:7f3aab69cca9 182 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 183 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 184
mluis 22:7f3aab69cca9 185 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 186 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 187 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 188 {
mluis 22:7f3aab69cca9 189 }
mluis 22:7f3aab69cca9 190
mluis 22:7f3aab69cca9 191 // Restore context
mluis 22:7f3aab69cca9 192 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 193 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 194 }
mluis 22:7f3aab69cca9 195
mluis 22:7f3aab69cca9 196 /*!
GregCr 0:e6ceb13d2d05 197 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 198 *
GregCr 0:e6ceb13d2d05 199 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 200 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 201 */
GregCr 0:e6ceb13d2d05 202 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 uint8_t i;
GregCr 0:e6ceb13d2d05 205
GregCr 0:e6ceb13d2d05 206 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 207 {
GregCr 0:e6ceb13d2d05 208 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 211 }
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 214 while( 1 );
GregCr 0:e6ceb13d2d05 215 }
GregCr 0:e6ceb13d2d05 216
mluis 22:7f3aab69cca9 217 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 218 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 219 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 220 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 221 uint8_t payloadLen,
mluis 13:618826a997e2 222 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 223 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 SetModem( modem );
GregCr 0:e6ceb13d2d05 226
GregCr 0:e6ceb13d2d05 227 switch( modem )
GregCr 0:e6ceb13d2d05 228 {
GregCr 0:e6ceb13d2d05 229 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 234 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 235 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 236 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 240
GregCr 0:e6ceb13d2d05 241 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 242 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 243 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 246 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 247
mluis 14:8552d0b840be 248 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 249 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 22:7f3aab69cca9 250
mluis 22:7f3aab69cca9 251 if( fixLen == 1 )
mluis 22:7f3aab69cca9 252 {
mluis 22:7f3aab69cca9 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 254 }
GregCr 0:e6ceb13d2d05 255
GregCr 0:e6ceb13d2d05 256 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 257 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 258 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 259 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 260 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 261 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 262 }
GregCr 0:e6ceb13d2d05 263 break;
GregCr 0:e6ceb13d2d05 264 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 265 {
GregCr 0:e6ceb13d2d05 266 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 267 {
GregCr 0:e6ceb13d2d05 268 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 269 while( 1 );
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271 bandwidth += 7;
GregCr 0:e6ceb13d2d05 272 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 273 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 274 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 275 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 276 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 277 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 279 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 280 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 281 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 283
GregCr 0:e6ceb13d2d05 284 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 285 {
GregCr 0:e6ceb13d2d05 286 datarate = 12;
GregCr 0:e6ceb13d2d05 287 }
GregCr 0:e6ceb13d2d05 288 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 datarate = 6;
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292
GregCr 0:e6ceb13d2d05 293 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 294 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 295 {
GregCr 0:e6ceb13d2d05 296 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 297 }
GregCr 0:e6ceb13d2d05 298 else
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 301 }
GregCr 0:e6ceb13d2d05 302
GregCr 0:e6ceb13d2d05 303 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 304 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 305 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 306 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 307 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 308 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 309 fixLen );
GregCr 0:e6ceb13d2d05 310
GregCr 0:e6ceb13d2d05 311 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 312 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 313 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 314 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 315 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 316 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 317 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 318
GregCr 0:e6ceb13d2d05 319 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 320 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 321 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 322 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 323
GregCr 0:e6ceb13d2d05 324 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 325
GregCr 0:e6ceb13d2d05 326 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 327 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 328
mluis 13:618826a997e2 329 if( fixLen == 1 )
mluis 13:618826a997e2 330 {
mluis 13:618826a997e2 331 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 332 }
mluis 13:618826a997e2 333
GregCr 6:e7f02929cd3d 334 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 335 {
GregCr 6:e7f02929cd3d 336 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 337 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 338 }
GregCr 6:e7f02929cd3d 339
mluis 22:7f3aab69cca9 340 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 341 {
mluis 22:7f3aab69cca9 342 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 343 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 344 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 345 }
mluis 22:7f3aab69cca9 346 else if( bandwidth == 9 )
mluis 22:7f3aab69cca9 347 {
mluis 22:7f3aab69cca9 348 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 349 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 350 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 351 }
mluis 22:7f3aab69cca9 352 else
mluis 22:7f3aab69cca9 353 {
mluis 22:7f3aab69cca9 354 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 355 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 356 }
mluis 22:7f3aab69cca9 357
GregCr 0:e6ceb13d2d05 358 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 359 {
GregCr 0:e6ceb13d2d05 360 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 361 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 362 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 363 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 364 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 365 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 366 }
GregCr 0:e6ceb13d2d05 367 else
GregCr 0:e6ceb13d2d05 368 {
GregCr 0:e6ceb13d2d05 369 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 370 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 371 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 372 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 373 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 374 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 375 }
GregCr 0:e6ceb13d2d05 376 }
GregCr 0:e6ceb13d2d05 377 break;
GregCr 0:e6ceb13d2d05 378 }
GregCr 0:e6ceb13d2d05 379 }
GregCr 0:e6ceb13d2d05 380
mluis 22:7f3aab69cca9 381 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 382 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 383 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 384 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 385 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 386 {
GregCr 0:e6ceb13d2d05 387 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 388 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 389
GregCr 0:e6ceb13d2d05 390 SetModem( modem );
GregCr 0:e6ceb13d2d05 391
GregCr 0:e6ceb13d2d05 392 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 393 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 394
GregCr 0:e6ceb13d2d05 395 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 396 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 397
GregCr 0:e6ceb13d2d05 398 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 399 {
GregCr 0:e6ceb13d2d05 400 if( power > 17 )
GregCr 0:e6ceb13d2d05 401 {
GregCr 0:e6ceb13d2d05 402 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 403 }
GregCr 0:e6ceb13d2d05 404 else
GregCr 0:e6ceb13d2d05 405 {
GregCr 0:e6ceb13d2d05 406 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 407 }
GregCr 0:e6ceb13d2d05 408 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 409 {
GregCr 0:e6ceb13d2d05 410 if( power < 5 )
GregCr 0:e6ceb13d2d05 411 {
GregCr 0:e6ceb13d2d05 412 power = 5;
GregCr 0:e6ceb13d2d05 413 }
GregCr 0:e6ceb13d2d05 414 if( power > 20 )
GregCr 0:e6ceb13d2d05 415 {
GregCr 0:e6ceb13d2d05 416 power = 20;
GregCr 0:e6ceb13d2d05 417 }
GregCr 0:e6ceb13d2d05 418 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 419 }
GregCr 0:e6ceb13d2d05 420 else
GregCr 0:e6ceb13d2d05 421 {
GregCr 0:e6ceb13d2d05 422 if( power < 2 )
GregCr 0:e6ceb13d2d05 423 {
GregCr 0:e6ceb13d2d05 424 power = 2;
GregCr 0:e6ceb13d2d05 425 }
GregCr 0:e6ceb13d2d05 426 if( power > 17 )
GregCr 0:e6ceb13d2d05 427 {
GregCr 0:e6ceb13d2d05 428 power = 17;
GregCr 0:e6ceb13d2d05 429 }
GregCr 0:e6ceb13d2d05 430 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 431 }
GregCr 0:e6ceb13d2d05 432 }
GregCr 0:e6ceb13d2d05 433 else
GregCr 0:e6ceb13d2d05 434 {
GregCr 0:e6ceb13d2d05 435 if( power < -1 )
GregCr 0:e6ceb13d2d05 436 {
GregCr 0:e6ceb13d2d05 437 power = -1;
GregCr 0:e6ceb13d2d05 438 }
GregCr 0:e6ceb13d2d05 439 if( power > 14 )
GregCr 0:e6ceb13d2d05 440 {
GregCr 0:e6ceb13d2d05 441 power = 14;
GregCr 0:e6ceb13d2d05 442 }
GregCr 0:e6ceb13d2d05 443 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 444 }
GregCr 0:e6ceb13d2d05 445 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 446 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 447
GregCr 0:e6ceb13d2d05 448 switch( modem )
GregCr 0:e6ceb13d2d05 449 {
GregCr 0:e6ceb13d2d05 450 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 451 {
GregCr 0:e6ceb13d2d05 452 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 453 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 454 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 455 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 456 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 457 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 458 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 459 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 460 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 461
GregCr 0:e6ceb13d2d05 462 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 463 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 464 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 465
GregCr 0:e6ceb13d2d05 466 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 467 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 468 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 469
GregCr 0:e6ceb13d2d05 470 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 471 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 472
GregCr 0:e6ceb13d2d05 473 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 474 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 475 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 476 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 477 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 478 ( crcOn << 4 ) );
mluis 22:7f3aab69cca9 479
GregCr 0:e6ceb13d2d05 480 }
GregCr 0:e6ceb13d2d05 481 break;
GregCr 0:e6ceb13d2d05 482 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 483 {
GregCr 0:e6ceb13d2d05 484 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 485 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 486 {
GregCr 0:e6ceb13d2d05 487 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 488 while( 1 );
GregCr 0:e6ceb13d2d05 489 }
GregCr 0:e6ceb13d2d05 490 bandwidth += 7;
GregCr 0:e6ceb13d2d05 491 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 492 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 493 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 494 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 495 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 496 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 497 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 498 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 499 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 500 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 501
GregCr 0:e6ceb13d2d05 502 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 503 {
GregCr 0:e6ceb13d2d05 504 datarate = 12;
GregCr 0:e6ceb13d2d05 505 }
GregCr 0:e6ceb13d2d05 506 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 507 {
GregCr 0:e6ceb13d2d05 508 datarate = 6;
GregCr 0:e6ceb13d2d05 509 }
GregCr 0:e6ceb13d2d05 510 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 511 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 512 {
GregCr 0:e6ceb13d2d05 513 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 514 }
GregCr 0:e6ceb13d2d05 515 else
GregCr 0:e6ceb13d2d05 516 {
GregCr 0:e6ceb13d2d05 517 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 518 }
mluis 22:7f3aab69cca9 519
GregCr 6:e7f02929cd3d 520 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 521 {
GregCr 6:e7f02929cd3d 522 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 523 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 524 }
mluis 22:7f3aab69cca9 525
GregCr 0:e6ceb13d2d05 526 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 527 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 528 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 529 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 530 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 531 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 532 fixLen );
GregCr 0:e6ceb13d2d05 533
GregCr 0:e6ceb13d2d05 534 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 535 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 536 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 537 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 538 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 539
GregCr 0:e6ceb13d2d05 540 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 541 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 542 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 543 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 544
GregCr 0:e6ceb13d2d05 545 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 546 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 547
GregCr 0:e6ceb13d2d05 548 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 549 {
GregCr 0:e6ceb13d2d05 550 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 551 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 552 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 553 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 554 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 555 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 556 }
GregCr 0:e6ceb13d2d05 557 else
GregCr 0:e6ceb13d2d05 558 {
GregCr 0:e6ceb13d2d05 559 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 560 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 561 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 562 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 563 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 564 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 565 }
GregCr 0:e6ceb13d2d05 566 }
GregCr 0:e6ceb13d2d05 567 break;
GregCr 0:e6ceb13d2d05 568 }
GregCr 0:e6ceb13d2d05 569 }
GregCr 0:e6ceb13d2d05 570
mluis 22:7f3aab69cca9 571 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 572 {
mluis 22:7f3aab69cca9 573 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 574
GregCr 0:e6ceb13d2d05 575 switch( modem )
GregCr 0:e6ceb13d2d05 576 {
GregCr 0:e6ceb13d2d05 577 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 578 {
mluis 22:7f3aab69cca9 579 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 580 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 581 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 582 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 583 pktLen +
GregCr 0:e6ceb13d2d05 584 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 585 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 586 }
GregCr 0:e6ceb13d2d05 587 break;
GregCr 0:e6ceb13d2d05 588 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 589 {
GregCr 0:e6ceb13d2d05 590 double bw = 0.0;
GregCr 0:e6ceb13d2d05 591 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 592 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 593 {
GregCr 0:e6ceb13d2d05 594 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 595 // bw = 78e2;
GregCr 0:e6ceb13d2d05 596 // break;
GregCr 0:e6ceb13d2d05 597 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 598 // bw = 104e2;
GregCr 0:e6ceb13d2d05 599 // break;
GregCr 0:e6ceb13d2d05 600 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 601 // bw = 156e2;
GregCr 0:e6ceb13d2d05 602 // break;
GregCr 0:e6ceb13d2d05 603 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 604 // bw = 208e2;
GregCr 0:e6ceb13d2d05 605 // break;
GregCr 0:e6ceb13d2d05 606 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 607 // bw = 312e2;
GregCr 0:e6ceb13d2d05 608 // break;
GregCr 0:e6ceb13d2d05 609 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 610 // bw = 414e2;
GregCr 0:e6ceb13d2d05 611 // break;
GregCr 0:e6ceb13d2d05 612 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 613 // bw = 625e2;
GregCr 0:e6ceb13d2d05 614 // break;
GregCr 0:e6ceb13d2d05 615 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 616 bw = 125e3;
GregCr 0:e6ceb13d2d05 617 break;
GregCr 0:e6ceb13d2d05 618 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 619 bw = 250e3;
GregCr 0:e6ceb13d2d05 620 break;
GregCr 0:e6ceb13d2d05 621 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 622 bw = 500e3;
GregCr 0:e6ceb13d2d05 623 break;
GregCr 0:e6ceb13d2d05 624 }
GregCr 0:e6ceb13d2d05 625
GregCr 0:e6ceb13d2d05 626 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 627 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 628 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 629 // time of preamble
GregCr 0:e6ceb13d2d05 630 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 631 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 632 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 633 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 634 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 635 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 22:7f3aab69cca9 636 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 637 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 638 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 639 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 640 // Time on air
GregCr 0:e6ceb13d2d05 641 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 642 // return us secs
GregCr 0:e6ceb13d2d05 643 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 644 }
GregCr 0:e6ceb13d2d05 645 break;
GregCr 0:e6ceb13d2d05 646 }
GregCr 0:e6ceb13d2d05 647 return airTime;
GregCr 0:e6ceb13d2d05 648 }
GregCr 0:e6ceb13d2d05 649
GregCr 0:e6ceb13d2d05 650 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 651 {
GregCr 0:e6ceb13d2d05 652 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 653
GregCr 0:e6ceb13d2d05 654 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 655 {
GregCr 0:e6ceb13d2d05 656 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 657 {
GregCr 0:e6ceb13d2d05 658 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 659 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 660
GregCr 0:e6ceb13d2d05 661 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 662 {
GregCr 0:e6ceb13d2d05 663 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 664 }
GregCr 0:e6ceb13d2d05 665 else
GregCr 0:e6ceb13d2d05 666 {
GregCr 0:e6ceb13d2d05 667 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 668 }
GregCr 0:e6ceb13d2d05 669
GregCr 0:e6ceb13d2d05 670 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 671 {
GregCr 0:e6ceb13d2d05 672 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 673 }
GregCr 0:e6ceb13d2d05 674 else
GregCr 0:e6ceb13d2d05 675 {
GregCr 0:e6ceb13d2d05 676 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 677 }
GregCr 0:e6ceb13d2d05 678
GregCr 0:e6ceb13d2d05 679 // Write payload buffer
GregCr 0:e6ceb13d2d05 680 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 681 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 682 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 683 }
GregCr 0:e6ceb13d2d05 684 break;
GregCr 0:e6ceb13d2d05 685 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 686 {
GregCr 0:e6ceb13d2d05 687 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 688 {
GregCr 0:e6ceb13d2d05 689 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 690 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 691 }
GregCr 0:e6ceb13d2d05 692 else
GregCr 0:e6ceb13d2d05 693 {
GregCr 0:e6ceb13d2d05 694 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 695 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697
GregCr 0:e6ceb13d2d05 698 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 699
GregCr 0:e6ceb13d2d05 700 // Initializes the payload size
GregCr 0:e6ceb13d2d05 701 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 702
GregCr 0:e6ceb13d2d05 703 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 704 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 705 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 706
GregCr 0:e6ceb13d2d05 707 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 708 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 709 {
GregCr 0:e6ceb13d2d05 710 Standby( );
GregCr 4:f0ce52e94d3f 711 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 712 }
GregCr 0:e6ceb13d2d05 713 // Write payload buffer
GregCr 0:e6ceb13d2d05 714 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 715 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 716 }
GregCr 0:e6ceb13d2d05 717 break;
GregCr 0:e6ceb13d2d05 718 }
GregCr 0:e6ceb13d2d05 719
GregCr 0:e6ceb13d2d05 720 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 721 }
GregCr 0:e6ceb13d2d05 722
GregCr 0:e6ceb13d2d05 723 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 724 {
mluis 13:618826a997e2 725 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 726 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 727
GregCr 0:e6ceb13d2d05 728 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 729 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 730 }
GregCr 0:e6ceb13d2d05 731
GregCr 0:e6ceb13d2d05 732 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 733 {
GregCr 0:e6ceb13d2d05 734 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 735 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 736
GregCr 0:e6ceb13d2d05 737 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 738 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 739 }
GregCr 0:e6ceb13d2d05 740
GregCr 0:e6ceb13d2d05 741 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 742 {
GregCr 0:e6ceb13d2d05 743 bool rxContinuous = false;
mluis 22:7f3aab69cca9 744
GregCr 0:e6ceb13d2d05 745 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 746 {
GregCr 0:e6ceb13d2d05 747 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 748 {
GregCr 0:e6ceb13d2d05 749 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 750
GregCr 0:e6ceb13d2d05 751 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 752 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 753 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 754 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 755 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 756 // DIO5=ModeReady
mluis 22:7f3aab69cca9 757 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 758 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 759 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 760 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 761
GregCr 0:e6ceb13d2d05 762 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 763 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 764 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 765 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 766
GregCr 0:e6ceb13d2d05 767 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 768
GregCr 0:e6ceb13d2d05 769 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 770 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 771 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 772 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 773 }
GregCr 0:e6ceb13d2d05 774 break;
GregCr 0:e6ceb13d2d05 775 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 776 {
GregCr 0:e6ceb13d2d05 777 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 778 {
GregCr 0:e6ceb13d2d05 779 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 780 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 781 }
GregCr 0:e6ceb13d2d05 782 else
GregCr 0:e6ceb13d2d05 783 {
GregCr 0:e6ceb13d2d05 784 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 785 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 786 }
GregCr 0:e6ceb13d2d05 787
mluis 22:7f3aab69cca9 788
mluis 22:7f3aab69cca9 789 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
mluis 22:7f3aab69cca9 790 if( this->settings.LoRa.Bandwidth < 9 )
mluis 22:7f3aab69cca9 791 {
mluis 22:7f3aab69cca9 792 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 793 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 794 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 795 {
mluis 22:7f3aab69cca9 796 case 0: // 7.8 kHz
mluis 22:7f3aab69cca9 797 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 798 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 799 break;
mluis 22:7f3aab69cca9 800 case 1: // 10.4 kHz
mluis 22:7f3aab69cca9 801 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 802 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 803 break;
mluis 22:7f3aab69cca9 804 case 2: // 15.6 kHz
mluis 22:7f3aab69cca9 805 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 806 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 807 break;
mluis 22:7f3aab69cca9 808 case 3: // 20.8 kHz
mluis 22:7f3aab69cca9 809 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 810 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 811 break;
mluis 22:7f3aab69cca9 812 case 4: // 31.2 kHz
mluis 22:7f3aab69cca9 813 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 814 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 815 break;
mluis 22:7f3aab69cca9 816 case 5: // 41.4 kHz
mluis 22:7f3aab69cca9 817 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 818 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 819 break;
mluis 22:7f3aab69cca9 820 case 6: // 62.5 kHz
mluis 22:7f3aab69cca9 821 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 822 break;
mluis 22:7f3aab69cca9 823 case 7: // 125 kHz
mluis 22:7f3aab69cca9 824 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 825 break;
mluis 22:7f3aab69cca9 826 case 8: // 250 kHz
mluis 22:7f3aab69cca9 827 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 828 break;
mluis 22:7f3aab69cca9 829 }
mluis 22:7f3aab69cca9 830 }
mluis 22:7f3aab69cca9 831 else
mluis 22:7f3aab69cca9 832 {
mluis 22:7f3aab69cca9 833 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 834 }
mluis 22:7f3aab69cca9 835
GregCr 0:e6ceb13d2d05 836 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 837
GregCr 6:e7f02929cd3d 838 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 839 {
GregCr 6:e7f02929cd3d 840 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 841 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 842 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 843 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 844 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 845 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 846 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 847 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 848
mluis 13:618826a997e2 849 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 850 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 851 }
GregCr 6:e7f02929cd3d 852 else
GregCr 6:e7f02929cd3d 853 {
GregCr 6:e7f02929cd3d 854 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 855 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 856 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 857 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 858 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 859 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 860 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 861 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 862
GregCr 6:e7f02929cd3d 863 // DIO0=RxDone
GregCr 6:e7f02929cd3d 864 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 865 }
GregCr 0:e6ceb13d2d05 866 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 867 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 868 }
GregCr 0:e6ceb13d2d05 869 break;
GregCr 0:e6ceb13d2d05 870 }
GregCr 0:e6ceb13d2d05 871
GregCr 0:e6ceb13d2d05 872 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 873
mluis 21:2e496deb7858 874 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 875 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 876 {
GregCr 0:e6ceb13d2d05 877 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 878 }
GregCr 0:e6ceb13d2d05 879
GregCr 0:e6ceb13d2d05 880 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 881 {
GregCr 0:e6ceb13d2d05 882 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 883
GregCr 0:e6ceb13d2d05 884 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 885 {
GregCr 0:e6ceb13d2d05 886 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 887 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 888 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 889 1.0 ) + 10.0 ) /
mluis 22:7f3aab69cca9 890 ( double )this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 891 }
GregCr 0:e6ceb13d2d05 892 }
GregCr 0:e6ceb13d2d05 893 else
GregCr 0:e6ceb13d2d05 894 {
GregCr 0:e6ceb13d2d05 895 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 896 {
GregCr 0:e6ceb13d2d05 897 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 898 }
GregCr 0:e6ceb13d2d05 899 else
GregCr 0:e6ceb13d2d05 900 {
GregCr 0:e6ceb13d2d05 901 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 902 }
GregCr 0:e6ceb13d2d05 903 }
GregCr 0:e6ceb13d2d05 904 }
GregCr 0:e6ceb13d2d05 905
GregCr 0:e6ceb13d2d05 906 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 907 {
mluis 22:7f3aab69cca9 908
GregCr 0:e6ceb13d2d05 909 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 910 {
GregCr 0:e6ceb13d2d05 911 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 912 {
GregCr 0:e6ceb13d2d05 913 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 914 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 915 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 916 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 917 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 918 // DIO5=ModeReady
mluis 22:7f3aab69cca9 919 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 920 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 921
GregCr 0:e6ceb13d2d05 922 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 923 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 924 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 925 }
GregCr 0:e6ceb13d2d05 926 break;
GregCr 0:e6ceb13d2d05 927 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 928 {
GregCr 6:e7f02929cd3d 929 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 930 {
GregCr 6:e7f02929cd3d 931 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 932 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 933 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 934 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 935 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 936 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 937 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 938 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 939
mluis 22:7f3aab69cca9 940 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 941 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 942 }
GregCr 6:e7f02929cd3d 943 else
GregCr 6:e7f02929cd3d 944 {
GregCr 6:e7f02929cd3d 945 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 946 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 947 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 948 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 949 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 950 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 951 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 952 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 953
GregCr 6:e7f02929cd3d 954 // DIO0=TxDone
mluis 22:7f3aab69cca9 955 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 956 }
GregCr 0:e6ceb13d2d05 957 }
GregCr 0:e6ceb13d2d05 958 break;
GregCr 0:e6ceb13d2d05 959 }
GregCr 0:e6ceb13d2d05 960
mluis 21:2e496deb7858 961 this->settings.State = RF_TX_RUNNING;
mluis 13:618826a997e2 962 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 963 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 964 }
GregCr 0:e6ceb13d2d05 965
GregCr 7:2b555111463f 966 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 967 {
GregCr 7:2b555111463f 968 switch( this->settings.Modem )
GregCr 7:2b555111463f 969 {
GregCr 7:2b555111463f 970 case MODEM_FSK:
GregCr 7:2b555111463f 971 {
GregCr 7:2b555111463f 972
GregCr 7:2b555111463f 973 }
GregCr 7:2b555111463f 974 break;
GregCr 7:2b555111463f 975 case MODEM_LORA:
GregCr 7:2b555111463f 976 {
GregCr 7:2b555111463f 977 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 978 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 979 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 980 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 981 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 982 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 983 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 984 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 985 );
GregCr 7:2b555111463f 986
GregCr 7:2b555111463f 987 // DIO3=CADDone
GregCr 7:2b555111463f 988 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 989
mluis 21:2e496deb7858 990 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 991 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 992 }
GregCr 7:2b555111463f 993 break;
GregCr 7:2b555111463f 994 default:
GregCr 7:2b555111463f 995 break;
GregCr 7:2b555111463f 996 }
GregCr 7:2b555111463f 997 }
GregCr 7:2b555111463f 998
mluis 22:7f3aab69cca9 999 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1000 {
GregCr 7:2b555111463f 1001 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1002
GregCr 0:e6ceb13d2d05 1003 switch( modem )
GregCr 0:e6ceb13d2d05 1004 {
GregCr 0:e6ceb13d2d05 1005 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1006 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1007 break;
GregCr 0:e6ceb13d2d05 1008 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1009 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1010 {
GregCr 0:e6ceb13d2d05 1011 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1012 }
GregCr 0:e6ceb13d2d05 1013 else
GregCr 0:e6ceb13d2d05 1014 {
GregCr 0:e6ceb13d2d05 1015 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1016 }
GregCr 0:e6ceb13d2d05 1017 break;
GregCr 0:e6ceb13d2d05 1018 default:
GregCr 0:e6ceb13d2d05 1019 rssi = -1;
GregCr 0:e6ceb13d2d05 1020 break;
GregCr 0:e6ceb13d2d05 1021 }
GregCr 0:e6ceb13d2d05 1022 return rssi;
GregCr 0:e6ceb13d2d05 1023 }
GregCr 0:e6ceb13d2d05 1024
GregCr 0:e6ceb13d2d05 1025 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1026 {
GregCr 0:e6ceb13d2d05 1027 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 1028 {
GregCr 0:e6ceb13d2d05 1029 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 1030 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1031 {
GregCr 0:e6ceb13d2d05 1032 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 1033 }
GregCr 0:e6ceb13d2d05 1034 else
GregCr 0:e6ceb13d2d05 1035 {
GregCr 0:e6ceb13d2d05 1036 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 1037 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1038 {
GregCr 0:e6ceb13d2d05 1039 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1040 }
GregCr 0:e6ceb13d2d05 1041 else
GregCr 0:e6ceb13d2d05 1042 {
GregCr 0:e6ceb13d2d05 1043 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1044 }
GregCr 0:e6ceb13d2d05 1045 }
GregCr 0:e6ceb13d2d05 1046 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1047 }
GregCr 0:e6ceb13d2d05 1048 }
GregCr 0:e6ceb13d2d05 1049
mluis 22:7f3aab69cca9 1050 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1051 {
mluis 22:7f3aab69cca9 1052 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1053 {
mluis 22:7f3aab69cca9 1054 return;
mluis 22:7f3aab69cca9 1055 }
mluis 22:7f3aab69cca9 1056
mluis 22:7f3aab69cca9 1057 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1058 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1059 {
mluis 22:7f3aab69cca9 1060 default:
mluis 22:7f3aab69cca9 1061 case MODEM_FSK:
mluis 22:7f3aab69cca9 1062 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1063 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1064
mluis 22:7f3aab69cca9 1065 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1066 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1067 break;
mluis 22:7f3aab69cca9 1068 case MODEM_LORA:
mluis 22:7f3aab69cca9 1069 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1070 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1071
mluis 22:7f3aab69cca9 1072 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1073 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1074 break;
GregCr 0:e6ceb13d2d05 1075 }
GregCr 0:e6ceb13d2d05 1076 }
GregCr 0:e6ceb13d2d05 1077
mluis 22:7f3aab69cca9 1078 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1079 {
mluis 20:e05596ba4166 1080 this->SetModem( modem );
mluis 20:e05596ba4166 1081
mluis 20:e05596ba4166 1082 switch( modem )
mluis 20:e05596ba4166 1083 {
mluis 20:e05596ba4166 1084 case MODEM_FSK:
mluis 20:e05596ba4166 1085 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1086 {
mluis 20:e05596ba4166 1087 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1088 }
mluis 20:e05596ba4166 1089 break;
mluis 20:e05596ba4166 1090 case MODEM_LORA:
mluis 20:e05596ba4166 1091 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1092 break;
mluis 20:e05596ba4166 1093 }
mluis 20:e05596ba4166 1094 }
mluis 20:e05596ba4166 1095
GregCr 0:e6ceb13d2d05 1096 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1097 {
GregCr 0:e6ceb13d2d05 1098 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1099 {
mluis 21:2e496deb7858 1100 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1101 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1102 {
GregCr 0:e6ceb13d2d05 1103 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1104 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1105 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1106 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1107
GregCr 0:e6ceb13d2d05 1108 // Clear Irqs
GregCr 0:e6ceb13d2d05 1109 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1110 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1111 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1112 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1113
GregCr 0:e6ceb13d2d05 1114 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1115 {
GregCr 0:e6ceb13d2d05 1116 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1117 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1118 }
GregCr 0:e6ceb13d2d05 1119 else
GregCr 0:e6ceb13d2d05 1120 {
mluis 21:2e496deb7858 1121 this->settings.State = RF_IDLE;
GregCr 5:11ec8a6ba4f0 1122 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1123 }
GregCr 0:e6ceb13d2d05 1124 }
mluis 22:7f3aab69cca9 1125 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1126 {
mluis 21:2e496deb7858 1127 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1128 }
GregCr 0:e6ceb13d2d05 1129 break;
mluis 21:2e496deb7858 1130 case RF_TX_RUNNING:
mluis 21:2e496deb7858 1131 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1132 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1133 {
mluis 21:2e496deb7858 1134 this->RadioEvents->TxTimeout( );
GregCr 0:e6ceb13d2d05 1135 }
GregCr 0:e6ceb13d2d05 1136 break;
GregCr 0:e6ceb13d2d05 1137 default:
GregCr 0:e6ceb13d2d05 1138 break;
GregCr 0:e6ceb13d2d05 1139 }
GregCr 0:e6ceb13d2d05 1140 }
GregCr 0:e6ceb13d2d05 1141
GregCr 0:e6ceb13d2d05 1142 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1143 {
mluis 20:e05596ba4166 1144 volatile uint8_t irqFlags = 0;
mluis 22:7f3aab69cca9 1145
GregCr 0:e6ceb13d2d05 1146 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1147 {
mluis 21:2e496deb7858 1148 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1149 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1150 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1151 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1152 {
GregCr 0:e6ceb13d2d05 1153 case MODEM_FSK:
GregCr 18:99c6e44c1672 1154 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1155 {
GregCr 18:99c6e44c1672 1156 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1157 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1158 {
GregCr 18:99c6e44c1672 1159 // Clear Irqs
GregCr 18:99c6e44c1672 1160 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1161 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1162 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1163 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 18:99c6e44c1672 1164
GregCr 18:99c6e44c1672 1165 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1166 {
mluis 21:2e496deb7858 1167 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1168 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 18:99c6e44c1672 1169 ( ( Read( REG_SYNCCONFIG ) &
GregCr 18:99c6e44c1672 1170 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1171 1.0 ) + 10.0 ) /
GregCr 18:99c6e44c1672 1172 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 18:99c6e44c1672 1173 }
GregCr 18:99c6e44c1672 1174 else
GregCr 18:99c6e44c1672 1175 {
GregCr 18:99c6e44c1672 1176 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1177 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 18:99c6e44c1672 1178 }
GregCr 18:99c6e44c1672 1179 rxTimeoutTimer.detach( );
GregCr 18:99c6e44c1672 1180
mluis 22:7f3aab69cca9 1181 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 18:99c6e44c1672 1182 {
mluis 22:7f3aab69cca9 1183 this->RadioEvents->RxError( );
GregCr 18:99c6e44c1672 1184 }
GregCr 18:99c6e44c1672 1185 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1186 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1187 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1188 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1189 break;
GregCr 0:e6ceb13d2d05 1190 }
GregCr 0:e6ceb13d2d05 1191 }
GregCr 18:99c6e44c1672 1192
GregCr 0:e6ceb13d2d05 1193 // Read received packet size
GregCr 0:e6ceb13d2d05 1194 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1195 {
GregCr 0:e6ceb13d2d05 1196 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1197 {
GregCr 0:e6ceb13d2d05 1198 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1199 }
GregCr 0:e6ceb13d2d05 1200 else
GregCr 0:e6ceb13d2d05 1201 {
GregCr 0:e6ceb13d2d05 1202 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1203 }
GregCr 0:e6ceb13d2d05 1204 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1205 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1206 }
GregCr 0:e6ceb13d2d05 1207 else
GregCr 0:e6ceb13d2d05 1208 {
GregCr 0:e6ceb13d2d05 1209 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1210 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1211 }
GregCr 0:e6ceb13d2d05 1212
GregCr 0:e6ceb13d2d05 1213 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1214 {
mluis 21:2e496deb7858 1215 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1216 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1217 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1218 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1219 1.0 ) + 10.0 ) /
GregCr 0:e6ceb13d2d05 1220 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1221 }
GregCr 0:e6ceb13d2d05 1222 else
GregCr 0:e6ceb13d2d05 1223 {
GregCr 0:e6ceb13d2d05 1224 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1225 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1226 }
GregCr 0:e6ceb13d2d05 1227 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1228
mluis 22:7f3aab69cca9 1229 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1230 {
mluis 21:2e496deb7858 1231 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1232 }
GregCr 0:e6ceb13d2d05 1233 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1234 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1235 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1236 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1237 break;
GregCr 0:e6ceb13d2d05 1238 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1239 {
mluis 22:7f3aab69cca9 1240 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1241
GregCr 0:e6ceb13d2d05 1242 // Clear Irq
GregCr 0:e6ceb13d2d05 1243 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1244
GregCr 0:e6ceb13d2d05 1245 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1246 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1247 {
GregCr 0:e6ceb13d2d05 1248 // Clear Irq
GregCr 0:e6ceb13d2d05 1249 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1250
GregCr 0:e6ceb13d2d05 1251 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1252 {
mluis 21:2e496deb7858 1253 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1254 }
GregCr 0:e6ceb13d2d05 1255 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1256
mluis 22:7f3aab69cca9 1257 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 0:e6ceb13d2d05 1258 {
mluis 22:7f3aab69cca9 1259 this->RadioEvents->RxError( );
GregCr 0:e6ceb13d2d05 1260 }
GregCr 0:e6ceb13d2d05 1261 break;
GregCr 0:e6ceb13d2d05 1262 }
GregCr 0:e6ceb13d2d05 1263
GregCr 0:e6ceb13d2d05 1264 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1265 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1266 {
GregCr 0:e6ceb13d2d05 1267 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1268 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1269 snr = -snr;
GregCr 0:e6ceb13d2d05 1270 }
GregCr 0:e6ceb13d2d05 1271 else
GregCr 0:e6ceb13d2d05 1272 {
GregCr 0:e6ceb13d2d05 1273 // Divide by 4
GregCr 0:e6ceb13d2d05 1274 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1275 }
GregCr 0:e6ceb13d2d05 1276
GregCr 7:2b555111463f 1277 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1278 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1279 {
GregCr 0:e6ceb13d2d05 1280 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1281 {
GregCr 0:e6ceb13d2d05 1282 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1283 snr;
GregCr 0:e6ceb13d2d05 1284 }
GregCr 0:e6ceb13d2d05 1285 else
GregCr 0:e6ceb13d2d05 1286 {
GregCr 0:e6ceb13d2d05 1287 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1288 snr;
GregCr 0:e6ceb13d2d05 1289 }
GregCr 0:e6ceb13d2d05 1290 }
GregCr 0:e6ceb13d2d05 1291 else
GregCr 0:e6ceb13d2d05 1292 {
GregCr 0:e6ceb13d2d05 1293 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1294 {
GregCr 0:e6ceb13d2d05 1295 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1296 }
GregCr 0:e6ceb13d2d05 1297 else
GregCr 0:e6ceb13d2d05 1298 {
GregCr 0:e6ceb13d2d05 1299 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1300 }
GregCr 0:e6ceb13d2d05 1301 }
GregCr 0:e6ceb13d2d05 1302
GregCr 0:e6ceb13d2d05 1303 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1304 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1305
GregCr 0:e6ceb13d2d05 1306 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1307 {
mluis 21:2e496deb7858 1308 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1309 }
GregCr 0:e6ceb13d2d05 1310 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1311
mluis 22:7f3aab69cca9 1312 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1313 {
mluis 21:2e496deb7858 1314 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1315 }
GregCr 0:e6ceb13d2d05 1316 }
GregCr 0:e6ceb13d2d05 1317 break;
GregCr 0:e6ceb13d2d05 1318 default:
GregCr 0:e6ceb13d2d05 1319 break;
GregCr 0:e6ceb13d2d05 1320 }
GregCr 0:e6ceb13d2d05 1321 break;
mluis 21:2e496deb7858 1322 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1323 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1324 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1325 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1326 {
GregCr 0:e6ceb13d2d05 1327 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1328 // Clear Irq
GregCr 0:e6ceb13d2d05 1329 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1330 // Intentional fall through
GregCr 0:e6ceb13d2d05 1331 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1332 default:
mluis 21:2e496deb7858 1333 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1334 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1335 {
mluis 22:7f3aab69cca9 1336 this->RadioEvents->TxDone( );
GregCr 0:e6ceb13d2d05 1337 }
GregCr 0:e6ceb13d2d05 1338 break;
GregCr 0:e6ceb13d2d05 1339 }
GregCr 0:e6ceb13d2d05 1340 break;
GregCr 0:e6ceb13d2d05 1341 default:
GregCr 0:e6ceb13d2d05 1342 break;
GregCr 0:e6ceb13d2d05 1343 }
GregCr 0:e6ceb13d2d05 1344 }
GregCr 0:e6ceb13d2d05 1345
GregCr 0:e6ceb13d2d05 1346 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1347 {
GregCr 0:e6ceb13d2d05 1348 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1349 {
mluis 21:2e496deb7858 1350 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1351 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1352 {
GregCr 0:e6ceb13d2d05 1353 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1354 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1355 // Read received packet size
GregCr 0:e6ceb13d2d05 1356 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1357 {
GregCr 0:e6ceb13d2d05 1358 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1359 {
GregCr 0:e6ceb13d2d05 1360 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1361 }
GregCr 0:e6ceb13d2d05 1362 else
GregCr 0:e6ceb13d2d05 1363 {
GregCr 0:e6ceb13d2d05 1364 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1365 }
GregCr 0:e6ceb13d2d05 1366 }
GregCr 0:e6ceb13d2d05 1367
GregCr 0:e6ceb13d2d05 1368 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1369 {
GregCr 0:e6ceb13d2d05 1370 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1371 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1372 }
GregCr 0:e6ceb13d2d05 1373 else
GregCr 0:e6ceb13d2d05 1374 {
GregCr 0:e6ceb13d2d05 1375 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1376 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1377 }
GregCr 0:e6ceb13d2d05 1378 break;
GregCr 0:e6ceb13d2d05 1379 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1380 // Sync time out
GregCr 0:e6ceb13d2d05 1381 rxTimeoutTimer.detach( );
mluis 21:2e496deb7858 1382 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1383 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1384 {
mluis 21:2e496deb7858 1385 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1386 }
GregCr 0:e6ceb13d2d05 1387 break;
GregCr 0:e6ceb13d2d05 1388 default:
GregCr 0:e6ceb13d2d05 1389 break;
GregCr 0:e6ceb13d2d05 1390 }
GregCr 0:e6ceb13d2d05 1391 break;
mluis 21:2e496deb7858 1392 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1393 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1394 {
GregCr 0:e6ceb13d2d05 1395 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1396 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1397 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1398 {
GregCr 0:e6ceb13d2d05 1399 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1400 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1401 }
GregCr 0:e6ceb13d2d05 1402 else
GregCr 0:e6ceb13d2d05 1403 {
GregCr 0:e6ceb13d2d05 1404 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1405 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1406 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1407 }
GregCr 0:e6ceb13d2d05 1408 break;
GregCr 0:e6ceb13d2d05 1409 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1410 break;
GregCr 0:e6ceb13d2d05 1411 default:
GregCr 0:e6ceb13d2d05 1412 break;
GregCr 0:e6ceb13d2d05 1413 }
mluis 22:7f3aab69cca9 1414 break;
GregCr 0:e6ceb13d2d05 1415 default:
GregCr 0:e6ceb13d2d05 1416 break;
GregCr 0:e6ceb13d2d05 1417 }
GregCr 0:e6ceb13d2d05 1418 }
GregCr 0:e6ceb13d2d05 1419
GregCr 0:e6ceb13d2d05 1420 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1421 {
GregCr 0:e6ceb13d2d05 1422 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1423 {
mluis 21:2e496deb7858 1424 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1425 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1426 {
GregCr 0:e6ceb13d2d05 1427 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1428 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1429 {
GregCr 0:e6ceb13d2d05 1430 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1431
GregCr 0:e6ceb13d2d05 1432 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1433
GregCr 0:e6ceb13d2d05 1434 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1435
GregCr 0:e6ceb13d2d05 1436 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1437 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1438 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1439 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1440 }
GregCr 0:e6ceb13d2d05 1441 break;
GregCr 0:e6ceb13d2d05 1442 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1443 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1444 {
GregCr 6:e7f02929cd3d 1445 // Clear Irq
GregCr 6:e7f02929cd3d 1446 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1447
mluis 22:7f3aab69cca9 1448 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1449 {
mluis 21:2e496deb7858 1450 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1451 }
mluis 22:7f3aab69cca9 1452 }
GregCr 0:e6ceb13d2d05 1453 break;
GregCr 0:e6ceb13d2d05 1454 default:
GregCr 0:e6ceb13d2d05 1455 break;
GregCr 0:e6ceb13d2d05 1456 }
GregCr 0:e6ceb13d2d05 1457 break;
mluis 21:2e496deb7858 1458 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1459 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1460 {
GregCr 0:e6ceb13d2d05 1461 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1462 break;
GregCr 0:e6ceb13d2d05 1463 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1464 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1465 {
GregCr 6:e7f02929cd3d 1466 // Clear Irq
GregCr 6:e7f02929cd3d 1467 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1468
mluis 22:7f3aab69cca9 1469 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1470 {
mluis 21:2e496deb7858 1471 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1472 }
mluis 22:7f3aab69cca9 1473 }
GregCr 0:e6ceb13d2d05 1474 break;
GregCr 0:e6ceb13d2d05 1475 default:
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 }
mluis 22:7f3aab69cca9 1478 break;
GregCr 0:e6ceb13d2d05 1479 default:
GregCr 0:e6ceb13d2d05 1480 break;
GregCr 0:e6ceb13d2d05 1481 }
GregCr 0:e6ceb13d2d05 1482 }
GregCr 0:e6ceb13d2d05 1483
GregCr 0:e6ceb13d2d05 1484 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1485 {
GregCr 0:e6ceb13d2d05 1486 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1487 {
GregCr 0:e6ceb13d2d05 1488 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1489 break;
GregCr 0:e6ceb13d2d05 1490 case MODEM_LORA:
mluis 22:7f3aab69cca9 1491 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1492 {
mluis 13:618826a997e2 1493 // Clear Irq
mluis 22:7f3aab69cca9 1494 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1495 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1496 {
mluis 21:2e496deb7858 1497 this->RadioEvents->CadDone( true );
mluis 13:618826a997e2 1498 }
GregCr 12:aa5b3bf7fdf4 1499 }
GregCr 12:aa5b3bf7fdf4 1500 else
mluis 13:618826a997e2 1501 {
mluis 13:618826a997e2 1502 // Clear Irq
mluis 13:618826a997e2 1503 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1504 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1505 {
mluis 21:2e496deb7858 1506 this->RadioEvents->CadDone( false );
mluis 13:618826a997e2 1507 }
GregCr 7:2b555111463f 1508 }
GregCr 0:e6ceb13d2d05 1509 break;
GregCr 0:e6ceb13d2d05 1510 default:
GregCr 0:e6ceb13d2d05 1511 break;
GregCr 0:e6ceb13d2d05 1512 }
GregCr 0:e6ceb13d2d05 1513 }
GregCr 0:e6ceb13d2d05 1514
GregCr 0:e6ceb13d2d05 1515 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1516 {
GregCr 0:e6ceb13d2d05 1517 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1518 {
GregCr 0:e6ceb13d2d05 1519 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1520 {
GregCr 0:e6ceb13d2d05 1521 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1522 {
GregCr 0:e6ceb13d2d05 1523 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1524 }
GregCr 0:e6ceb13d2d05 1525 }
GregCr 0:e6ceb13d2d05 1526 break;
GregCr 0:e6ceb13d2d05 1527 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1528 break;
GregCr 0:e6ceb13d2d05 1529 default:
GregCr 0:e6ceb13d2d05 1530 break;
GregCr 0:e6ceb13d2d05 1531 }
GregCr 0:e6ceb13d2d05 1532 }
GregCr 0:e6ceb13d2d05 1533
GregCr 0:e6ceb13d2d05 1534 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1535 {
GregCr 0:e6ceb13d2d05 1536 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1537 {
GregCr 0:e6ceb13d2d05 1538 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1539 break;
GregCr 0:e6ceb13d2d05 1540 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1541 break;
GregCr 0:e6ceb13d2d05 1542 default:
GregCr 0:e6ceb13d2d05 1543 break;
GregCr 0:e6ceb13d2d05 1544 }
mluis 13:618826a997e2 1545 }