Ivano Calabrese / ST-DEVKIT-LRWAN

ST-DEVKIT-LRWAN

Dependents:   DISCO-L072CZ-LRWAN1-base

Fork of SX1276GenericLib by Helmut Tschemernjak

sx1276/sx1276.cpp@91:0bf084e4d983, 2017-12-04 (annotated)

Committer:
alphaemmeo
Date:
Mon Dec 04 14:21:04 2017 +0000
Revision:
91:0bf084e4d983
Parent:
89:b0203b4a36ec 
base test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
Helmut Tschemernjak 34:07e89f23c734 15
Helmut Tschemernjak 34:07e89f23c734 16 /*
Helmut Tschemernjak 38:d9189d958db8 17 * additional development to make it more generic across multiple OS versions
Helmut Tschemernjak 34:07e89f23c734 18 * (c) 2017 Helmut Tschemernjak
Helmut Tschemernjak 34:07e89f23c734 19 * 30826 Garbsen (Hannover) Germany
Helmut Tschemernjak 34:07e89f23c734 20 */
Helmut Tschemernjak 34:07e89f23c734 21
GregCr 0:e6ceb13d2d05 22 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 23
alphaemmeo 91:0bf084e4d983 24 #include "main.h"
alphaemmeo 91:0bf084e4d983 25
Helmut Tschemernjak 38:d9189d958db8 26
Helmut Tschemernjak 38:d9189d958db8 27
Helmut Tschemernjak 55:00c1f5b83920 28 const SX1276::BandwidthMap SX1276::FskBandwidths[] =
Helmut Tschemernjak 31:e50929bd3f32 29 {
GregCr 0:e6ceb13d2d05 30 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 31 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 32 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 33 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 34 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 35 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 36 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 37 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 38 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 39 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 40 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 41 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 42 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 43 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 44 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 45 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 46 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 47 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 48 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 49 { 200000, 0x09 },
mluis 15:04374b1c33fa 50 { 250000, 0x01 },
Helmut Tschemernjak 31:e50929bd3f32 51 { 300000, 0x00 }, // Invalid Bandwidth
GregCr 0:e6ceb13d2d05 52 };
GregCr 0:e6ceb13d2d05 53
Helmut Tschemernjak 55:00c1f5b83920 54 const SX1276::BandwidthMap SX1276::LoRaBandwidths[] =
Helmut Tschemernjak 55:00c1f5b83920 55 {
Helmut Tschemernjak 55:00c1f5b83920 56 { 7800, 0 }, // 7.8 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 57 { 10400, 1 }, // 10.4 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 58 { 15600, 2 }, // 15.6 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 59 { 20800, 3 }, // 20.8 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 60 { 31250, 4 }, // 31.25 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 61 { 41700, 5 }, // 41.7 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 62 { 62500, 6 }, // 62.5 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 63 { 125000, 7 }, // 125 kHz the LoRa protocol default
Helmut Tschemernjak 82:b93c4169ce41 64 { 250000, 8 }, // 250 kHz
Helmut Tschemernjak 82:b93c4169ce41 65 { 500000, 9 }, // 500 kHz
Helmut Tschemernjak 62:835c5e20834e 66 { 600000, 10 }, // Invalid Bandwidth, reserved
Helmut Tschemernjak 55:00c1f5b83920 67 };
Helmut Tschemernjak 55:00c1f5b83920 68
GregCr 0:e6ceb13d2d05 69
Helmut Tschemernjak 38:d9189d958db8 70
Helmut Tschemernjak 38:d9189d958db8 71 /*!
Helmut Tschemernjak 38:d9189d958db8 72 * @brief Radio hardware registers initialization definition
Helmut Tschemernjak 38:d9189d958db8 73 *
Helmut Tschemernjak 38:d9189d958db8 74 * @remark Can be automatically generated by the SX1276 GUI (not yet implemented)
Helmut Tschemernjak 38:d9189d958db8 75 */
Helmut Tschemernjak 38:d9189d958db8 76
Helmut Tschemernjak 55:00c1f5b83920 77 const SX1276::RadioRegisters SX1276::RadioRegsInit[] = {
Helmut Tschemernjak 38:d9189d958db8 78 { MODEM_FSK , REG_LNA , 0x23 },
Helmut Tschemernjak 38:d9189d958db8 79 { MODEM_FSK , REG_RXCONFIG , 0x1E },
Helmut Tschemernjak 38:d9189d958db8 80 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
Helmut Tschemernjak 38:d9189d958db8 81 { MODEM_FSK , REG_AFCFEI , 0x01 },
Helmut Tschemernjak 38:d9189d958db8 82 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
Helmut Tschemernjak 38:d9189d958db8 83 { MODEM_FSK , REG_OSC , 0x07 },
Helmut Tschemernjak 38:d9189d958db8 84 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
Helmut Tschemernjak 38:d9189d958db8 85 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
Helmut Tschemernjak 38:d9189d958db8 86 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
Helmut Tschemernjak 38:d9189d958db8 87 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
Helmut Tschemernjak 38:d9189d958db8 88 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },
Helmut Tschemernjak 38:d9189d958db8 89 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
Helmut Tschemernjak 38:d9189d958db8 90 { MODEM_FSK , REG_IMAGECAL , 0x02 },
Helmut Tschemernjak 38:d9189d958db8 91 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
Helmut Tschemernjak 38:d9189d958db8 92 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
Helmut Tschemernjak 38:d9189d958db8 93 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
Helmut Tschemernjak 38:d9189d958db8 94
Helmut Tschemernjak 38:d9189d958db8 95 };
Helmut Tschemernjak 38:d9189d958db8 96
Helmut Tschemernjak 38:d9189d958db8 97
Helmut Tschemernjak 34:07e89f23c734 98 SX1276::SX1276( RadioEvents_t *events) : Radio( events ), isRadioActive( false )
GregCr 0:e6ceb13d2d05 99 {
GregCr 23:1e143575df0f 100 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 101
mluis 21:2e496deb7858 102 this->RadioEvents = events;
mluis 21:2e496deb7858 103
mluis 13:618826a997e2 104 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 105
mluis 13:618826a997e2 106 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 107 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 108 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 109 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 110 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 111 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 112
mluis 21:2e496deb7858 113 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 114 }
GregCr 0:e6ceb13d2d05 115
GregCr 0:e6ceb13d2d05 116 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 117 {
GregCr 23:1e143575df0f 118 delete this->rxtxBuffer;
mluis 13:618826a997e2 119 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
Helmut Tschemernjak 54:0d8ea87fbab9 122 bool SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 123 {
Helmut Tschemernjak 54:0d8ea87fbab9 124 if (Read(REG_VERSION) == 0x00)
Helmut Tschemernjak 54:0d8ea87fbab9 125 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 126
mluis 21:2e496deb7858 127 this->RadioEvents = events;
Helmut Tschemernjak 54:0d8ea87fbab9 128 return true;
mluis 21:2e496deb7858 129 }
mluis 21:2e496deb7858 130
Helmut Tschemernjak 38:d9189d958db8 131
Helmut Tschemernjak 38:d9189d958db8 132 void SX1276::RadioRegistersInit( )
Helmut Tschemernjak 38:d9189d958db8 133 {
Helmut Tschemernjak 38:d9189d958db8 134 uint8_t i = 0;
Helmut Tschemernjak 55:00c1f5b83920 135 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters ); i++ )
Helmut Tschemernjak 38:d9189d958db8 136 {
Helmut Tschemernjak 38:d9189d958db8 137 SetModem( RadioRegsInit[i].Modem );
Helmut Tschemernjak 38:d9189d958db8 138 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
Helmut Tschemernjak 38:d9189d958db8 139 }
Helmut Tschemernjak 38:d9189d958db8 140 }
Helmut Tschemernjak 38:d9189d958db8 141
Helmut Tschemernjak 38:d9189d958db8 142
GregCr 19:71a47bb03fbb 143 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 144 {
GregCr 0:e6ceb13d2d05 145 return this->settings.State;
GregCr 0:e6ceb13d2d05 146 }
GregCr 0:e6ceb13d2d05 147
GregCr 0:e6ceb13d2d05 148 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 149 {
GregCr 0:e6ceb13d2d05 150 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 151 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 152 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 153 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 154 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
mluis 22:7f3aab69cca9 157 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 158 {
GregCr 7:2b555111463f 159 int16_t rssi = 0;
mluis 25:3778e6204cc1 160
GregCr 0:e6ceb13d2d05 161 SetModem( modem );
GregCr 0:e6ceb13d2d05 162
GregCr 0:e6ceb13d2d05 163 SetChannel( freq );
mluis 25:3778e6204cc1 164
GregCr 0:e6ceb13d2d05 165 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 166
Helmut Tschemernjak 64:b721e6ab656a 167 Sleep_ms( 1 );
mluis 25:3778e6204cc1 168
GregCr 0:e6ceb13d2d05 169 rssi = GetRssi( modem );
mluis 25:3778e6204cc1 170
GregCr 0:e6ceb13d2d05 171 Sleep( );
mluis 25:3778e6204cc1 172
mluis 22:7f3aab69cca9 173 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 174 {
GregCr 0:e6ceb13d2d05 175 return false;
GregCr 0:e6ceb13d2d05 176 }
GregCr 0:e6ceb13d2d05 177 return true;
GregCr 0:e6ceb13d2d05 178 }
GregCr 0:e6ceb13d2d05 179
GregCr 0:e6ceb13d2d05 180 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 181 {
GregCr 0:e6ceb13d2d05 182 uint8_t i;
GregCr 0:e6ceb13d2d05 183 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 184
GregCr 0:e6ceb13d2d05 185 /*
mluis 25:3778e6204cc1 186 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 187 */
GregCr 0:e6ceb13d2d05 188 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 189 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 190
GregCr 0:e6ceb13d2d05 191 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 192 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 193 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 194 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 195 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 196 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 197 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 198 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 199 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 200
GregCr 0:e6ceb13d2d05 201 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 202 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 203
GregCr 0:e6ceb13d2d05 204 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 205 {
Helmut Tschemernjak 64:b721e6ab656a 206 Sleep_ms( 1 );
GregCr 0:e6ceb13d2d05 207 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 208 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 209 }
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 Sleep( );
GregCr 0:e6ceb13d2d05 212
GregCr 0:e6ceb13d2d05 213 return rnd;
GregCr 0:e6ceb13d2d05 214 }
GregCr 0:e6ceb13d2d05 215
GregCr 0:e6ceb13d2d05 216 /*!
mluis 22:7f3aab69cca9 217 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 218 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 219 * default values
mluis 22:7f3aab69cca9 220 */
mluis 22:7f3aab69cca9 221 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 222 {
mluis 22:7f3aab69cca9 223 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 224 uint32_t initialFreq;
mluis 22:7f3aab69cca9 225
mluis 22:7f3aab69cca9 226 // Save context
mluis 22:7f3aab69cca9 227 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 228 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 229 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 230 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 231
mluis 22:7f3aab69cca9 232 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 233 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 234
mluis 22:7f3aab69cca9 235 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 236 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 237 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 238 {
mluis 22:7f3aab69cca9 239 }
mluis 22:7f3aab69cca9 240
mluis 22:7f3aab69cca9 241 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 242 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 243
Helmut Tschemernjak 31:e50929bd3f32 244 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 245 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 246 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 247 {
mluis 22:7f3aab69cca9 248 }
mluis 22:7f3aab69cca9 249
mluis 22:7f3aab69cca9 250 // Restore context
mluis 22:7f3aab69cca9 251 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 252 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 253 }
mluis 22:7f3aab69cca9 254
mluis 22:7f3aab69cca9 255 /*!
GregCr 0:e6ceb13d2d05 256 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 257 *
GregCr 0:e6ceb13d2d05 258 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 259 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 260 */
GregCr 0:e6ceb13d2d05 261 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 262 {
GregCr 0:e6ceb13d2d05 263 uint8_t i;
GregCr 0:e6ceb13d2d05 264
Helmut Tschemernjak 55:00c1f5b83920 265 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 268 {
GregCr 0:e6ceb13d2d05 269 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 270 }
GregCr 0:e6ceb13d2d05 271 }
GregCr 0:e6ceb13d2d05 272 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 273 while( 1 );
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275
Helmut Tschemernjak 55:00c1f5b83920 276 /*!
Helmut Tschemernjak 55:00c1f5b83920 277 * Returns the known LoRa bandwidth registers value
Helmut Tschemernjak 55:00c1f5b83920 278 *
Helmut Tschemernjak 55:00c1f5b83920 279 * \param [IN] bandwidth Bandwidth value in Hz
Helmut Tschemernjak 55:00c1f5b83920 280 * \retval regValue Bandwidth register value.
Helmut Tschemernjak 55:00c1f5b83920 281 */
Helmut Tschemernjak 55:00c1f5b83920 282 uint8_t SX1276::GetLoRaBandwidthRegValue( uint32_t bandwidth )
Helmut Tschemernjak 55:00c1f5b83920 283 {
Helmut Tschemernjak 55:00c1f5b83920 284 uint8_t i;
Helmut Tschemernjak 55:00c1f5b83920 285
Helmut Tschemernjak 55:00c1f5b83920 286 for( i = 0; i < ( sizeof( LoRaBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
Helmut Tschemernjak 55:00c1f5b83920 287 {
Helmut Tschemernjak 55:00c1f5b83920 288 if( ( bandwidth >= LoRaBandwidths[i].bandwidth ) && ( bandwidth < LoRaBandwidths[i + 1].bandwidth ) )
Helmut Tschemernjak 55:00c1f5b83920 289 {
Helmut Tschemernjak 55:00c1f5b83920 290 return LoRaBandwidths[i].RegValue;
Helmut Tschemernjak 55:00c1f5b83920 291 }
Helmut Tschemernjak 55:00c1f5b83920 292 }
Helmut Tschemernjak 55:00c1f5b83920 293 // ERROR: Value not found
Helmut Tschemernjak 55:00c1f5b83920 294 while( 1 );
Helmut Tschemernjak 55:00c1f5b83920 295 }
Helmut Tschemernjak 55:00c1f5b83920 296
mluis 22:7f3aab69cca9 297 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 298 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 299 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 300 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 301 uint8_t payloadLen,
mluis 13:618826a997e2 302 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 303 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 304 {
GregCr 0:e6ceb13d2d05 305 SetModem( modem );
GregCr 0:e6ceb13d2d05 306
GregCr 0:e6ceb13d2d05 307 switch( modem )
GregCr 0:e6ceb13d2d05 308 {
GregCr 0:e6ceb13d2d05 309 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 310 {
GregCr 0:e6ceb13d2d05 311 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 312 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 313 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 314 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 315 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 316 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 317 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 318 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 319 this->settings.Fsk.PreambleLen = preambleLen;
Helmut Tschemernjak 31:e50929bd3f32 320 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
Helmut Tschemernjak 31:e50929bd3f32 321
mluis 25:3778e6204cc1 322
GregCr 0:e6ceb13d2d05 323 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 324 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 325 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 326
GregCr 0:e6ceb13d2d05 327 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 328 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 329
mluis 14:8552d0b840be 330 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 331 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 25:3778e6204cc1 332
mluis 22:7f3aab69cca9 333 if( fixLen == 1 )
mluis 22:7f3aab69cca9 334 {
mluis 22:7f3aab69cca9 335 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 336 }
GregCr 23:1e143575df0f 337 else
GregCr 23:1e143575df0f 338 {
mluis 25:3778e6204cc1 339 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
GregCr 23:1e143575df0f 340 }
GregCr 23:1e143575df0f 341
GregCr 0:e6ceb13d2d05 342 Write( REG_PACKETCONFIG1,
Helmut Tschemernjak 31:e50929bd3f32 343 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 344 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 345 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 346 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 347 ( crcOn << 4 ) );
Helmut Tschemernjak 31:e50929bd3f32 348 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
GregCr 0:e6ceb13d2d05 349 }
GregCr 0:e6ceb13d2d05 350 break;
GregCr 0:e6ceb13d2d05 351 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 352 {
Helmut Tschemernjak 56:4fddac05ac07 353 if (bandwidth > 11) // specified in Hz, needs mapping
Helmut Tschemernjak 56:4fddac05ac07 354 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
Helmut Tschemernjak 33:5db0d1e716b1 355 if( bandwidth > LORA_BANKWIDTH_500kHz )
GregCr 0:e6ceb13d2d05 356 {
GregCr 0:e6ceb13d2d05 357 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 358 while( 1 );
GregCr 0:e6ceb13d2d05 359 }
GregCr 0:e6ceb13d2d05 360 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 361 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 362 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 363 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 364 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 365 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 366 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 367 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 368 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 369 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 370 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 371
Helmut Tschemernjak 33:5db0d1e716b1 372 if( datarate > LORA_SF12 )
GregCr 0:e6ceb13d2d05 373 {
Helmut Tschemernjak 33:5db0d1e716b1 374 datarate = LORA_SF12;
GregCr 0:e6ceb13d2d05 375 }
Helmut Tschemernjak 33:5db0d1e716b1 376 else if( datarate < LORA_SF6 )
GregCr 0:e6ceb13d2d05 377 {
Helmut Tschemernjak 33:5db0d1e716b1 378 datarate = LORA_SF6;
GregCr 0:e6ceb13d2d05 379 }
mluis 25:3778e6204cc1 380
Helmut Tschemernjak 33:5db0d1e716b1 381 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
Helmut Tschemernjak 33:5db0d1e716b1 382 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
GregCr 0:e6ceb13d2d05 383 {
GregCr 0:e6ceb13d2d05 384 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 385 }
GregCr 0:e6ceb13d2d05 386 else
GregCr 0:e6ceb13d2d05 387 {
GregCr 0:e6ceb13d2d05 388 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 389 }
GregCr 0:e6ceb13d2d05 390
Helmut Tschemernjak 31:e50929bd3f32 391 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 392 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 393 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 394 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 395 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 396 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 397 fixLen );
mluis 25:3778e6204cc1 398
GregCr 0:e6ceb13d2d05 399 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 400 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 401 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 402 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 403 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 404 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 405 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 406
Helmut Tschemernjak 31:e50929bd3f32 407 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 408 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 409 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 410 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 411
GregCr 0:e6ceb13d2d05 412 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 25:3778e6204cc1 413
GregCr 0:e6ceb13d2d05 414 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 415 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 416
mluis 13:618826a997e2 417 if( fixLen == 1 )
mluis 13:618826a997e2 418 {
mluis 13:618826a997e2 419 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 420 }
mluis 13:618826a997e2 421
GregCr 6:e7f02929cd3d 422 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 423 {
GregCr 6:e7f02929cd3d 424 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 425 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 426 }
GregCr 6:e7f02929cd3d 427
Helmut Tschemernjak 33:5db0d1e716b1 428 if( ( bandwidth == LORA_BANKWIDTH_500kHz ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 429 {
mluis 25:3778e6204cc1 430 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 431 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 432 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 433 }
Helmut Tschemernjak 33:5db0d1e716b1 434 else if( bandwidth == LORA_BANKWIDTH_500kHz )
mluis 22:7f3aab69cca9 435 {
mluis 22:7f3aab69cca9 436 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 437 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 438 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 439 }
mluis 22:7f3aab69cca9 440 else
mluis 22:7f3aab69cca9 441 {
mluis 22:7f3aab69cca9 442 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 443 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 444 }
mluis 25:3778e6204cc1 445
Helmut Tschemernjak 33:5db0d1e716b1 446 if( datarate == LORA_SF6 )
GregCr 0:e6ceb13d2d05 447 {
Helmut Tschemernjak 31:e50929bd3f32 448 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 449 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 450 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 451 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 452 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 453 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 454 }
GregCr 0:e6ceb13d2d05 455 else
GregCr 0:e6ceb13d2d05 456 {
GregCr 0:e6ceb13d2d05 457 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 458 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 459 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 460 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
Helmut Tschemernjak 31:e50929bd3f32 461 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 462 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 463 }
GregCr 0:e6ceb13d2d05 464 }
GregCr 0:e6ceb13d2d05 465 break;
GregCr 0:e6ceb13d2d05 466 }
GregCr 0:e6ceb13d2d05 467 }
GregCr 0:e6ceb13d2d05 468
mluis 25:3778e6204cc1 469 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 470 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 471 uint8_t coderate, uint16_t preambleLen,
mluis 25:3778e6204cc1 472 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 473 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 474 {
GregCr 0:e6ceb13d2d05 475 SetModem( modem );
Helmut Tschemernjak 31:e50929bd3f32 476 SetRfTxPower( power );
GregCr 0:e6ceb13d2d05 477
Helmut Tschemernjak 31:e50929bd3f32 478 switch( modem )
GregCr 0:e6ceb13d2d05 479 {
GregCr 0:e6ceb13d2d05 480 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 481 {
GregCr 0:e6ceb13d2d05 482 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 483 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 484 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 485 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 486 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 487 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 488 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 489 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 490 this->settings.Fsk.TxTimeout = timeout;
mluis 25:3778e6204cc1 491
GregCr 0:e6ceb13d2d05 492 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 493 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 494 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 495
GregCr 0:e6ceb13d2d05 496 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 497 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 498 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 499
GregCr 0:e6ceb13d2d05 500 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 501 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 502
GregCr 0:e6ceb13d2d05 503 Write( REG_PACKETCONFIG1,
mluis 25:3778e6204cc1 504 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 505 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 506 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 507 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 508 ( crcOn << 4 ) );
Helmut Tschemernjak 31:e50929bd3f32 509 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
GregCr 0:e6ceb13d2d05 510 }
GregCr 0:e6ceb13d2d05 511 break;
GregCr 0:e6ceb13d2d05 512 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 513 {
GregCr 0:e6ceb13d2d05 514 this->settings.LoRa.Power = power;
Helmut Tschemernjak 56:4fddac05ac07 515 if (bandwidth > 11) // specified in Hz, needs mapping
Helmut Tschemernjak 56:4fddac05ac07 516 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
Helmut Tschemernjak 33:5db0d1e716b1 517 if( bandwidth > LORA_BANKWIDTH_500kHz )
GregCr 0:e6ceb13d2d05 518 {
GregCr 0:e6ceb13d2d05 519 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 520 while( 1 );
GregCr 0:e6ceb13d2d05 521 }
GregCr 0:e6ceb13d2d05 522 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 523 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 524 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 525 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 526 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 527 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 528 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 529 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 530 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 531 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 532
Helmut Tschemernjak 33:5db0d1e716b1 533 if( datarate > LORA_SF12 )
GregCr 0:e6ceb13d2d05 534 {
Helmut Tschemernjak 33:5db0d1e716b1 535 datarate = LORA_SF12;
GregCr 0:e6ceb13d2d05 536 }
Helmut Tschemernjak 33:5db0d1e716b1 537 else if( datarate < LORA_SF6 )
GregCr 0:e6ceb13d2d05 538 {
Helmut Tschemernjak 33:5db0d1e716b1 539 datarate = LORA_SF6;
GregCr 0:e6ceb13d2d05 540 }
Helmut Tschemernjak 33:5db0d1e716b1 541 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
Helmut Tschemernjak 33:5db0d1e716b1 542 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
GregCr 0:e6ceb13d2d05 543 {
GregCr 0:e6ceb13d2d05 544 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 545 }
GregCr 0:e6ceb13d2d05 546 else
GregCr 0:e6ceb13d2d05 547 {
GregCr 0:e6ceb13d2d05 548 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 549 }
mluis 22:7f3aab69cca9 550
GregCr 6:e7f02929cd3d 551 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 552 {
GregCr 6:e7f02929cd3d 553 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 554 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 555 }
mluis 22:7f3aab69cca9 556
mluis 25:3778e6204cc1 557 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 558 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 559 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 560 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 561 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 562 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 563 fixLen );
GregCr 0:e6ceb13d2d05 564
GregCr 0:e6ceb13d2d05 565 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 566 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 567 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 568 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 569 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 570
Helmut Tschemernjak 31:e50929bd3f32 571 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 572 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 573 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 574 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
mluis 25:3778e6204cc1 575
GregCr 0:e6ceb13d2d05 576 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 577 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 25:3778e6204cc1 578
Helmut Tschemernjak 33:5db0d1e716b1 579 if( datarate == LORA_SF6 )
GregCr 0:e6ceb13d2d05 580 {
mluis 25:3778e6204cc1 581 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 582 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 583 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 584 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 585 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 586 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 587 }
GregCr 0:e6ceb13d2d05 588 else
GregCr 0:e6ceb13d2d05 589 {
GregCr 0:e6ceb13d2d05 590 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 591 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 592 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 593 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 25:3778e6204cc1 594 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 595 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 596 }
GregCr 0:e6ceb13d2d05 597 }
GregCr 0:e6ceb13d2d05 598 break;
GregCr 0:e6ceb13d2d05 599 }
GregCr 0:e6ceb13d2d05 600 }
GregCr 0:e6ceb13d2d05 601
Helmut Tschemernjak 59:38e56c85fa44 602 uint32_t SX1276::TimeOnAir( RadioModems_t modem, int16_t pktLen )
GregCr 0:e6ceb13d2d05 603 {
mluis 22:7f3aab69cca9 604 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 605
GregCr 0:e6ceb13d2d05 606 switch( modem )
GregCr 0:e6ceb13d2d05 607 {
GregCr 0:e6ceb13d2d05 608 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 609 {
mluis 22:7f3aab69cca9 610 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 611 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 612 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 613 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 614 pktLen +
GregCr 0:e6ceb13d2d05 615 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
Helmut Tschemernjak 31:e50929bd3f32 616 this->settings.Fsk.Datarate ) * 1e3 );
GregCr 0:e6ceb13d2d05 617 }
GregCr 0:e6ceb13d2d05 618 break;
GregCr 0:e6ceb13d2d05 619 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 620 {
GregCr 0:e6ceb13d2d05 621 double bw = 0.0;
GregCr 0:e6ceb13d2d05 622 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 623 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 624 {
Helmut Tschemernjak 33:5db0d1e716b1 625 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
Helmut Tschemernjak 33:5db0d1e716b1 626 bw = 78e2;
Helmut Tschemernjak 33:5db0d1e716b1 627 break;
Helmut Tschemernjak 33:5db0d1e716b1 628 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
Helmut Tschemernjak 33:5db0d1e716b1 629 bw = 104e2;
Helmut Tschemernjak 33:5db0d1e716b1 630 break;
Helmut Tschemernjak 33:5db0d1e716b1 631 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
Helmut Tschemernjak 33:5db0d1e716b1 632 bw = 156e2;
Helmut Tschemernjak 33:5db0d1e716b1 633 break;
Helmut Tschemernjak 33:5db0d1e716b1 634 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
Helmut Tschemernjak 33:5db0d1e716b1 635 bw = 208e2;
Helmut Tschemernjak 33:5db0d1e716b1 636 break;
Helmut Tschemernjak 83:019da451b283 637 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
Helmut Tschemernjak 33:5db0d1e716b1 638 bw = 312e2;
Helmut Tschemernjak 33:5db0d1e716b1 639 break;
Helmut Tschemernjak 83:019da451b283 640 case LORA_BANKWIDTH_41kHz: // 41.7 kHz
Helmut Tschemernjak 33:5db0d1e716b1 641 bw = 414e2;
Helmut Tschemernjak 33:5db0d1e716b1 642 break;
Helmut Tschemernjak 33:5db0d1e716b1 643 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
Helmut Tschemernjak 33:5db0d1e716b1 644 bw = 625e2;
Helmut Tschemernjak 33:5db0d1e716b1 645 break;
Helmut Tschemernjak 33:5db0d1e716b1 646 case LORA_BANKWIDTH_125kHz: // 125 kHz
GregCr 0:e6ceb13d2d05 647 bw = 125e3;
GregCr 0:e6ceb13d2d05 648 break;
Helmut Tschemernjak 33:5db0d1e716b1 649 case LORA_BANKWIDTH_250kHz: // 250 kHz
GregCr 0:e6ceb13d2d05 650 bw = 250e3;
GregCr 0:e6ceb13d2d05 651 break;
Helmut Tschemernjak 33:5db0d1e716b1 652 case LORA_BANKWIDTH_500kHz: // 500 kHz
GregCr 0:e6ceb13d2d05 653 bw = 500e3;
GregCr 0:e6ceb13d2d05 654 break;
GregCr 0:e6ceb13d2d05 655 }
GregCr 0:e6ceb13d2d05 656
GregCr 0:e6ceb13d2d05 657 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 658 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 659 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 660 // time of preamble
GregCr 0:e6ceb13d2d05 661 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 662 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 663 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 664 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 665 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
Helmut Tschemernjak 31:e50929bd3f32 666 ( double )( 4 * ( this->settings.LoRa.Datarate -
Helmut Tschemernjak 31:e50929bd3f32 667 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
GregCr 0:e6ceb13d2d05 668 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 669 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 670 double tPayload = nPayload * ts;
mluis 25:3778e6204cc1 671 // Time on air
GregCr 0:e6ceb13d2d05 672 double tOnAir = tPreamble + tPayload;
Helmut Tschemernjak 31:e50929bd3f32 673 // return ms secs
Helmut Tschemernjak 31:e50929bd3f32 674 airTime = floor( tOnAir * 1e3 + 0.999 );
GregCr 0:e6ceb13d2d05 675 }
GregCr 0:e6ceb13d2d05 676 break;
GregCr 0:e6ceb13d2d05 677 }
GregCr 0:e6ceb13d2d05 678 return airTime;
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680
Helmut Tschemernjak 51:aef3234bcb71 681 void SX1276::Send( void *buffer, int16_t size, void *header, int16_t hsize )
GregCr 0:e6ceb13d2d05 682 {
GregCr 0:e6ceb13d2d05 683 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 684
GregCr 0:e6ceb13d2d05 685 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 686 {
GregCr 0:e6ceb13d2d05 687 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 688 {
GregCr 0:e6ceb13d2d05 689 this->settings.FskPacketHandler.NbBytes = 0;
Helmut Tschemernjak 50:43f7160e869c 690 this->settings.FskPacketHandler.Size = size + hsize;
GregCr 0:e6ceb13d2d05 691
GregCr 0:e6ceb13d2d05 692 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 693 {
Helmut Tschemernjak 50:43f7160e869c 694 uint8_t tmpsize = size + hsize;
Helmut Tschemernjak 50:43f7160e869c 695 WriteFifo( ( uint8_t* )&tmpsize, 1 );
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697 else
GregCr 0:e6ceb13d2d05 698 {
Helmut Tschemernjak 50:43f7160e869c 699 Write( REG_PAYLOADLENGTH, size + hsize);
Helmut Tschemernjak 31:e50929bd3f32 700 }
mluis 25:3778e6204cc1 701
Helmut Tschemernjak 50:43f7160e869c 702 if( ( size + hsize > 0 ) && ( size + hsize <= 64 ) )
GregCr 0:e6ceb13d2d05 703 {
Helmut Tschemernjak 50:43f7160e869c 704 this->settings.FskPacketHandler.ChunkSize = size + hsize;
GregCr 0:e6ceb13d2d05 705 }
GregCr 0:e6ceb13d2d05 706 else
GregCr 0:e6ceb13d2d05 707 {
Helmut Tschemernjak 50:43f7160e869c 708 if (header) {
Helmut Tschemernjak 50:43f7160e869c 709 WriteFifo( header, hsize );
Helmut Tschemernjak 50:43f7160e869c 710 memcpy( rxtxBuffer, header, hsize );
Helmut Tschemernjak 50:43f7160e869c 711 }
Helmut Tschemernjak 51:aef3234bcb71 712 memcpy( rxtxBuffer+hsize, (uint8_t *)buffer+hsize, size );
GregCr 0:e6ceb13d2d05 713 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 714 }
GregCr 0:e6ceb13d2d05 715
GregCr 0:e6ceb13d2d05 716 // Write payload buffer
Helmut Tschemernjak 50:43f7160e869c 717 if (header)
Helmut Tschemernjak 50:43f7160e869c 718 WriteFifo( header, hsize );
GregCr 0:e6ceb13d2d05 719 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 720 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 721 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 722 }
GregCr 0:e6ceb13d2d05 723 break;
GregCr 0:e6ceb13d2d05 724 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 725 {
alphaemmeo 91:0bf084e4d983 726 ser->printf("[SX1276] SX1276::Send MODEM_LORA\n\r");
GregCr 0:e6ceb13d2d05 727 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 728 {
GregCr 0:e6ceb13d2d05 729 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 730 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 731 }
GregCr 0:e6ceb13d2d05 732 else
GregCr 0:e6ceb13d2d05 733 {
GregCr 0:e6ceb13d2d05 734 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 735 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 25:3778e6204cc1 736 }
mluis 25:3778e6204cc1 737
Helmut Tschemernjak 50:43f7160e869c 738 this->settings.LoRaPacketHandler.Size = size + hsize;
GregCr 0:e6ceb13d2d05 739
GregCr 0:e6ceb13d2d05 740 // Initializes the payload size
Helmut Tschemernjak 50:43f7160e869c 741 Write( REG_LR_PAYLOADLENGTH, size + hsize);
GregCr 0:e6ceb13d2d05 742
mluis 25:3778e6204cc1 743 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 744 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 745 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 746
GregCr 0:e6ceb13d2d05 747 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 748 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 749 {
GregCr 0:e6ceb13d2d05 750 Standby( );
Helmut Tschemernjak 64:b721e6ab656a 751 Sleep_ms( 1 );
GregCr 0:e6ceb13d2d05 752 }
GregCr 0:e6ceb13d2d05 753 // Write payload buffer
Helmut Tschemernjak 50:43f7160e869c 754 if (header)
Helmut Tschemernjak 50:43f7160e869c 755 WriteFifo( header, hsize );
GregCr 0:e6ceb13d2d05 756 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 757 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 758 }
GregCr 0:e6ceb13d2d05 759 break;
GregCr 0:e6ceb13d2d05 760 }
GregCr 0:e6ceb13d2d05 761
GregCr 0:e6ceb13d2d05 762 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 763 }
GregCr 0:e6ceb13d2d05 764
GregCr 0:e6ceb13d2d05 765 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 766 {
Helmut Tschemernjak 44:544add59b26d 767 SetTimeout(TXTimeoutTimer, NULL);
Helmut Tschemernjak 44:544add59b26d 768 SetTimeout(RXTimeoutTimer, NULL);
mluis 22:7f3aab69cca9 769
GregCr 0:e6ceb13d2d05 770 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 771 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 772 }
GregCr 0:e6ceb13d2d05 773
GregCr 0:e6ceb13d2d05 774 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 775 {
Helmut Tschemernjak 44:544add59b26d 776 SetTimeout(TXTimeoutTimer, NULL);
Helmut Tschemernjak 44:544add59b26d 777 SetTimeout(RXTimeoutTimer, NULL);
mluis 22:7f3aab69cca9 778
GregCr 0:e6ceb13d2d05 779 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 780 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 781 }
GregCr 0:e6ceb13d2d05 782
GregCr 0:e6ceb13d2d05 783 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 784 {
GregCr 0:e6ceb13d2d05 785 bool rxContinuous = false;
mluis 22:7f3aab69cca9 786
GregCr 0:e6ceb13d2d05 787 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 788 {
GregCr 0:e6ceb13d2d05 789 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 790 {
GregCr 0:e6ceb13d2d05 791 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 25:3778e6204cc1 792
GregCr 0:e6ceb13d2d05 793 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 794 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 795 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 796 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 797 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 798 // DIO5=ModeReady
mluis 22:7f3aab69cca9 799 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 23:1e143575df0f 800 RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 801 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 802 RF_DIOMAPPING1_DIO0_00 |
mluis 25:3778e6204cc1 803 RF_DIOMAPPING1_DIO1_00 |
GregCr 0:e6ceb13d2d05 804 RF_DIOMAPPING1_DIO2_11 );
mluis 25:3778e6204cc1 805
GregCr 0:e6ceb13d2d05 806 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 25:3778e6204cc1 807 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 808 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 809 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 25:3778e6204cc1 810
GregCr 0:e6ceb13d2d05 811 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 25:3778e6204cc1 812
mluis 25:3778e6204cc1 813 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
mluis 25:3778e6204cc1 814
GregCr 0:e6ceb13d2d05 815 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 816 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 817 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 818 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 819 }
GregCr 0:e6ceb13d2d05 820 break;
GregCr 0:e6ceb13d2d05 821 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 822 {
GregCr 0:e6ceb13d2d05 823 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 824 {
GregCr 0:e6ceb13d2d05 825 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 826 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 827 }
GregCr 0:e6ceb13d2d05 828 else
GregCr 0:e6ceb13d2d05 829 {
GregCr 0:e6ceb13d2d05 830 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 831 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
Helmut Tschemernjak 31:e50929bd3f32 832 }
mluis 22:7f3aab69cca9 833
mluis 22:7f3aab69cca9 834 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
Helmut Tschemernjak 33:5db0d1e716b1 835 if( this->settings.LoRa.Bandwidth < LORA_BANKWIDTH_500kHz )
mluis 22:7f3aab69cca9 836 {
mluis 22:7f3aab69cca9 837 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 838 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 839 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 840 {
Helmut Tschemernjak 33:5db0d1e716b1 841 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
mluis 22:7f3aab69cca9 842 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 843 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 844 break;
Helmut Tschemernjak 33:5db0d1e716b1 845 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
mluis 22:7f3aab69cca9 846 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 847 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 848 break;
Helmut Tschemernjak 33:5db0d1e716b1 849 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
mluis 22:7f3aab69cca9 850 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 851 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 852 break;
Helmut Tschemernjak 33:5db0d1e716b1 853 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
mluis 22:7f3aab69cca9 854 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 855 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 856 break;
Helmut Tschemernjak 83:019da451b283 857 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
mluis 22:7f3aab69cca9 858 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 859 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 860 break;
Helmut Tschemernjak 33:5db0d1e716b1 861 case LORA_BANKWIDTH_41kHz: // 41.4 kHz
mluis 22:7f3aab69cca9 862 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 863 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 864 break;
Helmut Tschemernjak 33:5db0d1e716b1 865 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
mluis 22:7f3aab69cca9 866 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 867 break;
Helmut Tschemernjak 33:5db0d1e716b1 868 case LORA_BANKWIDTH_125kHz: // 125 kHz
mluis 22:7f3aab69cca9 869 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 870 break;
Helmut Tschemernjak 33:5db0d1e716b1 871 case LORA_BANKWIDTH_250kHz: // 250 kHz
mluis 22:7f3aab69cca9 872 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 873 break;
mluis 22:7f3aab69cca9 874 }
mluis 22:7f3aab69cca9 875 }
mluis 22:7f3aab69cca9 876 else
mluis 22:7f3aab69cca9 877 {
mluis 22:7f3aab69cca9 878 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 879 }
mluis 22:7f3aab69cca9 880
GregCr 0:e6ceb13d2d05 881 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 25:3778e6204cc1 882
GregCr 6:e7f02929cd3d 883 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 884 {
GregCr 6:e7f02929cd3d 885 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 886 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 887 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 888 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 889 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 890 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 891 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 892 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 893
mluis 13:618826a997e2 894 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 895 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 896 }
GregCr 6:e7f02929cd3d 897 else
GregCr 6:e7f02929cd3d 898 {
GregCr 6:e7f02929cd3d 899 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 900 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 901 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 902 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 903 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 904 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 905 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 906 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 907
GregCr 6:e7f02929cd3d 908 // DIO0=RxDone
GregCr 6:e7f02929cd3d 909 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 910 }
GregCr 0:e6ceb13d2d05 911 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 912 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 913 }
GregCr 0:e6ceb13d2d05 914 break;
GregCr 0:e6ceb13d2d05 915 }
Helmut Tschemernjak 58:113d2ef978d2 916
mluis 21:2e496deb7858 917 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 918 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 919 {
Helmut Tschemernjak 44:544add59b26d 920 SetTimeout(RXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
GregCr 0:e6ceb13d2d05 921 }
GregCr 0:e6ceb13d2d05 922
GregCr 0:e6ceb13d2d05 923 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 924 {
GregCr 0:e6ceb13d2d05 925 SetOpMode( RF_OPMODE_RECEIVER );
mluis 25:3778e6204cc1 926
GregCr 0:e6ceb13d2d05 927 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 928 {
Helmut Tschemernjak 53:6d3adad59633 929 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 0:e6ceb13d2d05 930 }
GregCr 0:e6ceb13d2d05 931 }
GregCr 0:e6ceb13d2d05 932 else
GregCr 0:e6ceb13d2d05 933 {
GregCr 0:e6ceb13d2d05 934 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 935 {
GregCr 0:e6ceb13d2d05 936 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 937 }
GregCr 0:e6ceb13d2d05 938 else
GregCr 0:e6ceb13d2d05 939 {
GregCr 0:e6ceb13d2d05 940 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 941 }
GregCr 0:e6ceb13d2d05 942 }
GregCr 0:e6ceb13d2d05 943 }
GregCr 0:e6ceb13d2d05 944
Helmut Tschemernjak 54:0d8ea87fbab9 945 bool SX1276::RxSignalPending()
Helmut Tschemernjak 54:0d8ea87fbab9 946 {
Helmut Tschemernjak 54:0d8ea87fbab9 947 if (this->settings.State != RF_RX_RUNNING)
Helmut Tschemernjak 54:0d8ea87fbab9 948 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 949
Helmut Tschemernjak 54:0d8ea87fbab9 950 switch( this->settings.Modem )
Helmut Tschemernjak 54:0d8ea87fbab9 951 {
Helmut Tschemernjak 54:0d8ea87fbab9 952 case MODEM_FSK:
Helmut Tschemernjak 54:0d8ea87fbab9 953 break;
Helmut Tschemernjak 54:0d8ea87fbab9 954 case MODEM_LORA:
Helmut Tschemernjak 81:d288917af0ce 955 if (Read(REG_LR_MODEMSTAT) & (RFLR_MODEMSTAT_SIGNAL_DETECTED|RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED|RFLR_MODEMSTAT_HEADERINFO_VALID|RFLR_MODEMSTAT_MODEM_CLEAR))
Helmut Tschemernjak 81:d288917af0ce 956 return true;
Helmut Tschemernjak 54:0d8ea87fbab9 957 break;
Helmut Tschemernjak 54:0d8ea87fbab9 958 }
Helmut Tschemernjak 54:0d8ea87fbab9 959 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 960 }
Helmut Tschemernjak 54:0d8ea87fbab9 961
GregCr 0:e6ceb13d2d05 962 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 963 {
mluis 22:7f3aab69cca9 964
GregCr 0:e6ceb13d2d05 965 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 966 {
GregCr 0:e6ceb13d2d05 967 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 968 {
GregCr 0:e6ceb13d2d05 969 // DIO0=PacketSent
GregCr 23:1e143575df0f 970 // DIO1=FifoEmpty
GregCr 0:e6ceb13d2d05 971 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 972 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 973 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 974 // DIO5=ModeReady
mluis 22:7f3aab69cca9 975 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
Helmut Tschemernjak 31:e50929bd3f32 976 RF_DIOMAPPING1_DIO1_MASK &
Helmut Tschemernjak 31:e50929bd3f32 977 RF_DIOMAPPING1_DIO2_MASK ) |
Helmut Tschemernjak 31:e50929bd3f32 978 RF_DIOMAPPING1_DIO1_01 );
GregCr 0:e6ceb13d2d05 979
GregCr 0:e6ceb13d2d05 980 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 981 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 982 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 983 }
GregCr 0:e6ceb13d2d05 984 break;
GregCr 0:e6ceb13d2d05 985 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 986 {
GregCr 6:e7f02929cd3d 987 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 988 {
GregCr 6:e7f02929cd3d 989 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 990 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 991 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 992 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 993 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 994 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 995 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 996 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 997
mluis 22:7f3aab69cca9 998 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 999 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 1000 }
GregCr 6:e7f02929cd3d 1001 else
GregCr 6:e7f02929cd3d 1002 {
GregCr 6:e7f02929cd3d 1003 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 1004 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 1005 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 1006 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 1007 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 1008 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 1009 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 1010 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 1011
GregCr 6:e7f02929cd3d 1012 // DIO0=TxDone
mluis 22:7f3aab69cca9 1013 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 1014 }
GregCr 0:e6ceb13d2d05 1015 }
GregCr 0:e6ceb13d2d05 1016 break;
GregCr 0:e6ceb13d2d05 1017 }
GregCr 0:e6ceb13d2d05 1018
mluis 21:2e496deb7858 1019 this->settings.State = RF_TX_RUNNING;
Helmut Tschemernjak 44:544add59b26d 1020 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
GregCr 0:e6ceb13d2d05 1021 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 1022 }
GregCr 0:e6ceb13d2d05 1023
GregCr 7:2b555111463f 1024 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 1025 {
GregCr 7:2b555111463f 1026 switch( this->settings.Modem )
GregCr 7:2b555111463f 1027 {
GregCr 7:2b555111463f 1028 case MODEM_FSK:
GregCr 7:2b555111463f 1029 {
mluis 25:3778e6204cc1 1030
GregCr 7:2b555111463f 1031 }
GregCr 7:2b555111463f 1032 break;
GregCr 7:2b555111463f 1033 case MODEM_LORA:
GregCr 7:2b555111463f 1034 {
GregCr 7:2b555111463f 1035 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 1036 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 1037 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 1038 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 1039 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 1040 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 1041 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
Helmut Tschemernjak 31:e50929bd3f32 1042 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 1043 );
mluis 25:3778e6204cc1 1044
GregCr 7:2b555111463f 1045 // DIO3=CADDone
Helmut Tschemernjak 31:e50929bd3f32 1046 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
mluis 25:3778e6204cc1 1047
mluis 21:2e496deb7858 1048 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 1049 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 1050 }
GregCr 7:2b555111463f 1051 break;
GregCr 7:2b555111463f 1052 default:
GregCr 7:2b555111463f 1053 break;
GregCr 7:2b555111463f 1054 }
GregCr 7:2b555111463f 1055 }
GregCr 7:2b555111463f 1056
Helmut Tschemernjak 31:e50929bd3f32 1057 void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
Helmut Tschemernjak 31:e50929bd3f32 1058 {
Helmut Tschemernjak 31:e50929bd3f32 1059 uint32_t timeout = ( uint32_t )( time * 1e6 );
Helmut Tschemernjak 31:e50929bd3f32 1060
Helmut Tschemernjak 31:e50929bd3f32 1061 SetChannel( freq );
Helmut Tschemernjak 31:e50929bd3f32 1062
Helmut Tschemernjak 31:e50929bd3f32 1063 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
Helmut Tschemernjak 31:e50929bd3f32 1064
Helmut Tschemernjak 31:e50929bd3f32 1065 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
Helmut Tschemernjak 31:e50929bd3f32 1066 // Disable radio interrupts
Helmut Tschemernjak 31:e50929bd3f32 1067 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
Helmut Tschemernjak 31:e50929bd3f32 1068 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
Helmut Tschemernjak 31:e50929bd3f32 1069
Helmut Tschemernjak 31:e50929bd3f32 1070 this->settings.State = RF_TX_RUNNING;
Helmut Tschemernjak 44:544add59b26d 1071 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout);
Helmut Tschemernjak 31:e50929bd3f32 1072 SetOpMode( RF_OPMODE_TRANSMITTER );
Helmut Tschemernjak 31:e50929bd3f32 1073 }
Helmut Tschemernjak 31:e50929bd3f32 1074
Helmut Tschemernjak 50:43f7160e869c 1075 int16_t SX1276::MaxMTUSize( RadioModems_t modem )
Helmut Tschemernjak 50:43f7160e869c 1076 {
Helmut Tschemernjak 50:43f7160e869c 1077 int16_t mtuSize = 0;
Helmut Tschemernjak 50:43f7160e869c 1078
Helmut Tschemernjak 50:43f7160e869c 1079 switch( modem )
Helmut Tschemernjak 50:43f7160e869c 1080 {
Helmut Tschemernjak 50:43f7160e869c 1081 case MODEM_FSK:
Helmut Tschemernjak 50:43f7160e869c 1082 mtuSize = RX_BUFFER_SIZE;
Helmut Tschemernjak 50:43f7160e869c 1083 case MODEM_LORA:
Helmut Tschemernjak 50:43f7160e869c 1084 mtuSize = RX_BUFFER_SIZE;
Helmut Tschemernjak 50:43f7160e869c 1085 break;
Helmut Tschemernjak 50:43f7160e869c 1086 default:
Helmut Tschemernjak 50:43f7160e869c 1087 mtuSize = -1;
Helmut Tschemernjak 50:43f7160e869c 1088 break;
Helmut Tschemernjak 50:43f7160e869c 1089 }
Helmut Tschemernjak 50:43f7160e869c 1090 return mtuSize;
Helmut Tschemernjak 50:43f7160e869c 1091 }
Helmut Tschemernjak 50:43f7160e869c 1092
mluis 22:7f3aab69cca9 1093 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1094 {
GregCr 7:2b555111463f 1095 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1096
GregCr 0:e6ceb13d2d05 1097 switch( modem )
GregCr 0:e6ceb13d2d05 1098 {
GregCr 0:e6ceb13d2d05 1099 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1100 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1101 break;
GregCr 0:e6ceb13d2d05 1102 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1103 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1104 {
GregCr 0:e6ceb13d2d05 1105 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1106 }
GregCr 0:e6ceb13d2d05 1107 else
GregCr 0:e6ceb13d2d05 1108 {
GregCr 0:e6ceb13d2d05 1109 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1110 }
GregCr 0:e6ceb13d2d05 1111 break;
GregCr 0:e6ceb13d2d05 1112 default:
GregCr 0:e6ceb13d2d05 1113 rssi = -1;
GregCr 0:e6ceb13d2d05 1114 break;
GregCr 0:e6ceb13d2d05 1115 }
GregCr 0:e6ceb13d2d05 1116 return rssi;
GregCr 0:e6ceb13d2d05 1117 }
GregCr 0:e6ceb13d2d05 1118
Helmut Tschemernjak 83:019da451b283 1119 int32_t SX1276::GetFrequencyError(RadioModems_t modem )
Helmut Tschemernjak 83:019da451b283 1120 {
Helmut Tschemernjak 83:019da451b283 1121 int32_t val = 0;
Helmut Tschemernjak 83:019da451b283 1122
Helmut Tschemernjak 83:019da451b283 1123 if (modem != MODEM_LORA)
Helmut Tschemernjak 83:019da451b283 1124 return 0;
Helmut Tschemernjak 83:019da451b283 1125
Helmut Tschemernjak 83:019da451b283 1126 val = (Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only
Helmut Tschemernjak 89:b0203b4a36ec 1127 val |= ((Read(REG_LR_FEIMID) << 8) | Read(REG_LR_FEILSB)); // high byte, low byte
Helmut Tschemernjak 89:b0203b4a36ec 1128 if (val & 0x80000) //convert sign bit
Helmut Tschemernjak 83:019da451b283 1129 val |= 0xfff00000;
Helmut Tschemernjak 83:019da451b283 1130
Helmut Tschemernjak 83:019da451b283 1131 int32_t bandwidth = 0;
Helmut Tschemernjak 83:019da451b283 1132 for (int i = 0; i < (int)(sizeof(LoRaBandwidths) / sizeof(BandwidthMap)) -1; i++ ) {
Helmut Tschemernjak 83:019da451b283 1133 if (LoRaBandwidths[i].RegValue == this->settings.LoRa.Bandwidth) {
Helmut Tschemernjak 83:019da451b283 1134 bandwidth = LoRaBandwidths[i].bandwidth;
Helmut Tschemernjak 83:019da451b283 1135 break;
Helmut Tschemernjak 83:019da451b283 1136 }
Helmut Tschemernjak 83:019da451b283 1137 }
Helmut Tschemernjak 83:019da451b283 1138 if (!bandwidth)
Helmut Tschemernjak 83:019da451b283 1139 return 0;
Helmut Tschemernjak 83:019da451b283 1140
Helmut Tschemernjak 83:019da451b283 1141 float bandWidthkHz = (float)bandwidth/1000;
Helmut Tschemernjak 83:019da451b283 1142
Helmut Tschemernjak 83:019da451b283 1143 int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0);
Helmut Tschemernjak 83:019da451b283 1144
Helmut Tschemernjak 83:019da451b283 1145 return hz;
Helmut Tschemernjak 83:019da451b283 1146 }
Helmut Tschemernjak 83:019da451b283 1147
Helmut Tschemernjak 83:019da451b283 1148
GregCr 0:e6ceb13d2d05 1149 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1150 {
mluis 25:3778e6204cc1 1151 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1152 {
mluis 25:3778e6204cc1 1153 SetAntSwLowPower( true );
mluis 25:3778e6204cc1 1154 }
mluis 25:3778e6204cc1 1155 else
mluis 25:3778e6204cc1 1156 {
mluis 25:3778e6204cc1 1157 SetAntSwLowPower( false );
Helmut Tschemernjak 31:e50929bd3f32 1158 SetAntSw( opMode );
GregCr 0:e6ceb13d2d05 1159 }
mluis 25:3778e6204cc1 1160 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1161 }
GregCr 0:e6ceb13d2d05 1162
mluis 22:7f3aab69cca9 1163 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1164 {
Helmut Tschemernjak 31:e50929bd3f32 1165 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
Helmut Tschemernjak 31:e50929bd3f32 1166 {
Helmut Tschemernjak 31:e50929bd3f32 1167 this->settings.Modem = MODEM_LORA;
Helmut Tschemernjak 31:e50929bd3f32 1168 }
Helmut Tschemernjak 31:e50929bd3f32 1169 else
Helmut Tschemernjak 31:e50929bd3f32 1170 {
Helmut Tschemernjak 31:e50929bd3f32 1171 this->settings.Modem = MODEM_FSK;
Helmut Tschemernjak 31:e50929bd3f32 1172 }
Helmut Tschemernjak 31:e50929bd3f32 1173
mluis 22:7f3aab69cca9 1174 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1175 {
mluis 22:7f3aab69cca9 1176 return;
mluis 22:7f3aab69cca9 1177 }
mluis 22:7f3aab69cca9 1178
mluis 22:7f3aab69cca9 1179 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1180 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1181 {
mluis 22:7f3aab69cca9 1182 default:
mluis 22:7f3aab69cca9 1183 case MODEM_FSK:
Helmut Tschemernjak 31:e50929bd3f32 1184 Sleep( );
mluis 22:7f3aab69cca9 1185 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1186
mluis 22:7f3aab69cca9 1187 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1188 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1189 break;
mluis 22:7f3aab69cca9 1190 case MODEM_LORA:
Helmut Tschemernjak 31:e50929bd3f32 1191 Sleep( );
mluis 22:7f3aab69cca9 1192 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1193
mluis 22:7f3aab69cca9 1194 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1195 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1196 break;
GregCr 0:e6ceb13d2d05 1197 }
GregCr 0:e6ceb13d2d05 1198 }
GregCr 0:e6ceb13d2d05 1199
mluis 22:7f3aab69cca9 1200 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1201 {
mluis 20:e05596ba4166 1202 this->SetModem( modem );
mluis 20:e05596ba4166 1203
mluis 20:e05596ba4166 1204 switch( modem )
mluis 20:e05596ba4166 1205 {
mluis 20:e05596ba4166 1206 case MODEM_FSK:
mluis 20:e05596ba4166 1207 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1208 {
mluis 20:e05596ba4166 1209 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1210 }
mluis 20:e05596ba4166 1211 break;
mluis 20:e05596ba4166 1212 case MODEM_LORA:
mluis 20:e05596ba4166 1213 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1214 break;
mluis 20:e05596ba4166 1215 }
mluis 20:e05596ba4166 1216 }
mluis 20:e05596ba4166 1217
Helmut Tschemernjak 31:e50929bd3f32 1218 void SX1276::SetPublicNetwork( bool enable )
Helmut Tschemernjak 31:e50929bd3f32 1219 {
Helmut Tschemernjak 31:e50929bd3f32 1220 SetModem( MODEM_LORA );
Helmut Tschemernjak 31:e50929bd3f32 1221 this->settings.LoRa.PublicNetwork = enable;
Helmut Tschemernjak 31:e50929bd3f32 1222 if( enable == true )
Helmut Tschemernjak 31:e50929bd3f32 1223 {
Helmut Tschemernjak 31:e50929bd3f32 1224 // Change LoRa modem SyncWord
Helmut Tschemernjak 31:e50929bd3f32 1225 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
Helmut Tschemernjak 31:e50929bd3f32 1226 }
Helmut Tschemernjak 31:e50929bd3f32 1227 else
Helmut Tschemernjak 31:e50929bd3f32 1228 {
Helmut Tschemernjak 31:e50929bd3f32 1229 // Change LoRa modem SyncWord
Helmut Tschemernjak 31:e50929bd3f32 1230 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
Helmut Tschemernjak 31:e50929bd3f32 1231 }
Helmut Tschemernjak 31:e50929bd3f32 1232 }
Helmut Tschemernjak 31:e50929bd3f32 1233
Helmut Tschemernjak 31:e50929bd3f32 1234
GregCr 0:e6ceb13d2d05 1235 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1236 {
GregCr 0:e6ceb13d2d05 1237 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1238 {
mluis 21:2e496deb7858 1239 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1240 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1241 {
GregCr 0:e6ceb13d2d05 1242 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1243 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1244 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1245 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1246
GregCr 0:e6ceb13d2d05 1247 // Clear Irqs
Helmut Tschemernjak 31:e50929bd3f32 1248 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1249 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1250 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1251 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1252
GregCr 0:e6ceb13d2d05 1253 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1254 {
GregCr 0:e6ceb13d2d05 1255 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1256 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1257 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 0:e6ceb13d2d05 1258 }
GregCr 0:e6ceb13d2d05 1259 else
GregCr 0:e6ceb13d2d05 1260 {
mluis 21:2e496deb7858 1261 this->settings.State = RF_IDLE;
Helmut Tschemernjak 53:6d3adad59633 1262 SetTimeout(RXTimeoutSyncWordTimer, NULL);
GregCr 0:e6ceb13d2d05 1263 }
GregCr 0:e6ceb13d2d05 1264 }
Helmut Tschemernjak 63:5b9d391244dc 1265 if (this->RadioEvents && this->RadioEvents->RxTimeout)
GregCr 0:e6ceb13d2d05 1266 {
Helmut Tschemernjak 63:5b9d391244dc 1267 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1268 }
GregCr 0:e6ceb13d2d05 1269 break;
mluis 21:2e496deb7858 1270 case RF_TX_RUNNING:
Helmut Tschemernjak 31:e50929bd3f32 1271 // Tx timeout shouldn't happen.
Helmut Tschemernjak 31:e50929bd3f32 1272 // But it has been observed that when it happens it is a result of a corrupted SPI transfer
Helmut Tschemernjak 31:e50929bd3f32 1273 // it depends on the platform design.
Helmut Tschemernjak 31:e50929bd3f32 1274 //
Helmut Tschemernjak 31:e50929bd3f32 1275 // The workaround is to put the radio in a known state. Thus, we re-initialize it.
Helmut Tschemernjak 31:e50929bd3f32 1276 // BEGIN WORKAROUND
Helmut Tschemernjak 31:e50929bd3f32 1277
Helmut Tschemernjak 31:e50929bd3f32 1278 // Reset the radio
Helmut Tschemernjak 31:e50929bd3f32 1279 Reset( );
Helmut Tschemernjak 31:e50929bd3f32 1280
Helmut Tschemernjak 31:e50929bd3f32 1281 // Calibrate Rx chain
Helmut Tschemernjak 31:e50929bd3f32 1282 RxChainCalibration( );
Helmut Tschemernjak 31:e50929bd3f32 1283
Helmut Tschemernjak 31:e50929bd3f32 1284 // Initialize radio default values
Helmut Tschemernjak 31:e50929bd3f32 1285 SetOpMode( RF_OPMODE_SLEEP );
Helmut Tschemernjak 31:e50929bd3f32 1286
Helmut Tschemernjak 31:e50929bd3f32 1287 RadioRegistersInit( );
Helmut Tschemernjak 31:e50929bd3f32 1288
Helmut Tschemernjak 31:e50929bd3f32 1289 SetModem( MODEM_FSK );
Helmut Tschemernjak 31:e50929bd3f32 1290
Helmut Tschemernjak 31:e50929bd3f32 1291 // Restore previous network type setting.
Helmut Tschemernjak 31:e50929bd3f32 1292 SetPublicNetwork( this->settings.LoRa.PublicNetwork );
Helmut Tschemernjak 31:e50929bd3f32 1293 // END WORKAROUND
Helmut Tschemernjak 31:e50929bd3f32 1294
mluis 21:2e496deb7858 1295 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1296 if (this->RadioEvents && this->RadioEvents->TxTimeout)
GregCr 0:e6ceb13d2d05 1297 {
Helmut Tschemernjak 63:5b9d391244dc 1298 this->RadioEvents->TxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1299 }
GregCr 0:e6ceb13d2d05 1300 break;
GregCr 0:e6ceb13d2d05 1301 default:
GregCr 0:e6ceb13d2d05 1302 break;
GregCr 0:e6ceb13d2d05 1303 }
GregCr 0:e6ceb13d2d05 1304 }
GregCr 0:e6ceb13d2d05 1305
GregCr 0:e6ceb13d2d05 1306 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1307 {
mluis 20:e05596ba4166 1308 volatile uint8_t irqFlags = 0;
mluis 22:7f3aab69cca9 1309
GregCr 0:e6ceb13d2d05 1310 switch( this->settings.State )
mluis 25:3778e6204cc1 1311 {
mluis 21:2e496deb7858 1312 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1313 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1314 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1315 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 0:e6ceb13d2d05 1317 case MODEM_FSK:
GregCr 18:99c6e44c1672 1318 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1319 {
GregCr 18:99c6e44c1672 1320 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1321 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1322 {
GregCr 18:99c6e44c1672 1323 // Clear Irqs
mluis 25:3778e6204cc1 1324 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1325 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1326 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1327 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 25:3778e6204cc1 1328
Helmut Tschemernjak 44:544add59b26d 1329 SetTimeout(RXTimeoutTimer, NULL);
mluis 25:3778e6204cc1 1330
GregCr 18:99c6e44c1672 1331 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1332 {
Helmut Tschemernjak 53:6d3adad59633 1333 SetTimeout(RXTimeoutSyncWordTimer, NULL);
mluis 21:2e496deb7858 1334 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1335 }
GregCr 18:99c6e44c1672 1336 else
GregCr 18:99c6e44c1672 1337 {
GregCr 18:99c6e44c1672 1338 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1339 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1340 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 18:99c6e44c1672 1341 }
mluis 25:3778e6204cc1 1342
Helmut Tschemernjak 63:5b9d391244dc 1343 if (this->RadioEvents && this->RadioEvents->RxError)
GregCr 18:99c6e44c1672 1344 {
Helmut Tschemernjak 63:5b9d391244dc 1345 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 18:99c6e44c1672 1346 }
GregCr 18:99c6e44c1672 1347 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1348 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1349 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1350 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1351 break;
GregCr 0:e6ceb13d2d05 1352 }
GregCr 0:e6ceb13d2d05 1353 }
mluis 25:3778e6204cc1 1354
GregCr 0:e6ceb13d2d05 1355 // Read received packet size
GregCr 0:e6ceb13d2d05 1356 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1357 {
GregCr 0:e6ceb13d2d05 1358 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1359 {
GregCr 0:e6ceb13d2d05 1360 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1361 }
GregCr 0:e6ceb13d2d05 1362 else
GregCr 0:e6ceb13d2d05 1363 {
GregCr 0:e6ceb13d2d05 1364 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1365 }
GregCr 23:1e143575df0f 1366 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1367 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1368 }
GregCr 0:e6ceb13d2d05 1369 else
GregCr 0:e6ceb13d2d05 1370 {
GregCr 23:1e143575df0f 1371 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1372 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1373 }
GregCr 0:e6ceb13d2d05 1374
Helmut Tschemernjak 44:544add59b26d 1375 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1376
GregCr 0:e6ceb13d2d05 1377 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1378 {
mluis 21:2e496deb7858 1379 this->settings.State = RF_IDLE;
Helmut Tschemernjak 53:6d3adad59633 1380 SetTimeout(RXTimeoutSyncWordTimer, NULL);
GregCr 0:e6ceb13d2d05 1381 }
GregCr 0:e6ceb13d2d05 1382 else
GregCr 0:e6ceb13d2d05 1383 {
GregCr 0:e6ceb13d2d05 1384 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1385 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1386 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
Helmut Tschemernjak 31:e50929bd3f32 1387 }
GregCr 0:e6ceb13d2d05 1388
Helmut Tschemernjak 63:5b9d391244dc 1389 if (this->RadioEvents && this->RadioEvents->RxDone)
GregCr 0:e6ceb13d2d05 1390 {
Helmut Tschemernjak 63:5b9d391244dc 1391 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 25:3778e6204cc1 1392 }
GregCr 0:e6ceb13d2d05 1393 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1394 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1395 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1396 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1397 break;
GregCr 0:e6ceb13d2d05 1398 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1399 {
mluis 22:7f3aab69cca9 1400 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1401
GregCr 0:e6ceb13d2d05 1402 // Clear Irq
GregCr 0:e6ceb13d2d05 1403 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1404
GregCr 0:e6ceb13d2d05 1405 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1406 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1407 {
GregCr 0:e6ceb13d2d05 1408 // Clear Irq
GregCr 0:e6ceb13d2d05 1409 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1410
GregCr 0:e6ceb13d2d05 1411 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1412 {
mluis 21:2e496deb7858 1413 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1414 }
Helmut Tschemernjak 44:544add59b26d 1415 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1416
Helmut Tschemernjak 63:5b9d391244dc 1417 if(this->RadioEvents && this->RadioEvents->RxError)
GregCr 0:e6ceb13d2d05 1418 {
Helmut Tschemernjak 63:5b9d391244dc 1419 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1420 }
GregCr 0:e6ceb13d2d05 1421 break;
GregCr 0:e6ceb13d2d05 1422 }
GregCr 0:e6ceb13d2d05 1423
GregCr 0:e6ceb13d2d05 1424 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1425 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1426 {
GregCr 0:e6ceb13d2d05 1427 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1428 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1429 snr = -snr;
GregCr 0:e6ceb13d2d05 1430 }
GregCr 0:e6ceb13d2d05 1431 else
GregCr 0:e6ceb13d2d05 1432 {
GregCr 0:e6ceb13d2d05 1433 // Divide by 4
GregCr 0:e6ceb13d2d05 1434 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1435 }
GregCr 0:e6ceb13d2d05 1436
GregCr 7:2b555111463f 1437 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1438 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1439 {
GregCr 0:e6ceb13d2d05 1440 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1441 {
GregCr 0:e6ceb13d2d05 1442 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1443 snr;
GregCr 0:e6ceb13d2d05 1444 }
GregCr 0:e6ceb13d2d05 1445 else
GregCr 0:e6ceb13d2d05 1446 {
GregCr 0:e6ceb13d2d05 1447 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1448 snr;
GregCr 0:e6ceb13d2d05 1449 }
GregCr 0:e6ceb13d2d05 1450 }
GregCr 0:e6ceb13d2d05 1451 else
mluis 25:3778e6204cc1 1452 {
GregCr 0:e6ceb13d2d05 1453 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1454 {
GregCr 0:e6ceb13d2d05 1455 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1456 }
GregCr 0:e6ceb13d2d05 1457 else
GregCr 0:e6ceb13d2d05 1458 {
GregCr 0:e6ceb13d2d05 1459 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1460 }
GregCr 0:e6ceb13d2d05 1461 }
GregCr 0:e6ceb13d2d05 1462
GregCr 0:e6ceb13d2d05 1463 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 23:1e143575df0f 1464 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 25:3778e6204cc1 1465
GregCr 0:e6ceb13d2d05 1466 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1467 {
mluis 21:2e496deb7858 1468 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1469 }
Helmut Tschemernjak 44:544add59b26d 1470 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1471
Helmut Tschemernjak 63:5b9d391244dc 1472 if(this->RadioEvents && this->RadioEvents->RxDone)
GregCr 0:e6ceb13d2d05 1473 {
Helmut Tschemernjak 63:5b9d391244dc 1474 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1475 }
GregCr 0:e6ceb13d2d05 1476 }
GregCr 0:e6ceb13d2d05 1477 break;
GregCr 0:e6ceb13d2d05 1478 default:
GregCr 0:e6ceb13d2d05 1479 break;
GregCr 0:e6ceb13d2d05 1480 }
GregCr 0:e6ceb13d2d05 1481 break;
mluis 21:2e496deb7858 1482 case RF_TX_RUNNING:
Helmut Tschemernjak 44:544add59b26d 1483 SetTimeout(TXTimeoutTimer, NULL);
GregCr 0:e6ceb13d2d05 1484 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1485 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1486 {
GregCr 0:e6ceb13d2d05 1487 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1488 // Clear Irq
GregCr 0:e6ceb13d2d05 1489 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1490 // Intentional fall through
GregCr 0:e6ceb13d2d05 1491 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1492 default:
mluis 21:2e496deb7858 1493 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1494 if (this->RadioEvents && this->RadioEvents->TxDone)
GregCr 0:e6ceb13d2d05 1495 {
Helmut Tschemernjak 63:5b9d391244dc 1496 this->RadioEvents->TxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
mluis 25:3778e6204cc1 1497 }
GregCr 0:e6ceb13d2d05 1498 break;
GregCr 0:e6ceb13d2d05 1499 }
GregCr 0:e6ceb13d2d05 1500 break;
GregCr 0:e6ceb13d2d05 1501 default:
GregCr 0:e6ceb13d2d05 1502 break;
GregCr 0:e6ceb13d2d05 1503 }
GregCr 0:e6ceb13d2d05 1504 }
GregCr 0:e6ceb13d2d05 1505
GregCr 0:e6ceb13d2d05 1506 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1507 {
GregCr 0:e6ceb13d2d05 1508 switch( this->settings.State )
mluis 25:3778e6204cc1 1509 {
mluis 21:2e496deb7858 1510 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1511 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1512 {
GregCr 0:e6ceb13d2d05 1513 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1514 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1515 // Read received packet size
GregCr 0:e6ceb13d2d05 1516 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1517 {
GregCr 0:e6ceb13d2d05 1518 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1519 {
GregCr 0:e6ceb13d2d05 1520 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1521 }
GregCr 0:e6ceb13d2d05 1522 else
GregCr 0:e6ceb13d2d05 1523 {
GregCr 0:e6ceb13d2d05 1524 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1525 }
GregCr 0:e6ceb13d2d05 1526 }
GregCr 0:e6ceb13d2d05 1527
GregCr 0:e6ceb13d2d05 1528 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1529 {
GregCr 23:1e143575df0f 1530 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1531 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1532 }
GregCr 0:e6ceb13d2d05 1533 else
GregCr 0:e6ceb13d2d05 1534 {
GregCr 23:1e143575df0f 1535 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1536 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1537 }
GregCr 0:e6ceb13d2d05 1538 break;
GregCr 0:e6ceb13d2d05 1539 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1540 // Sync time out
Helmut Tschemernjak 44:544add59b26d 1541 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1542 // Clear Irq
Helmut Tschemernjak 31:e50929bd3f32 1543 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
Helmut Tschemernjak 31:e50929bd3f32 1544
mluis 21:2e496deb7858 1545 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1546 if (this->RadioEvents && this->RadioEvents->RxTimeout)
GregCr 0:e6ceb13d2d05 1547 {
Helmut Tschemernjak 63:5b9d391244dc 1548 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1549 }
GregCr 0:e6ceb13d2d05 1550 break;
GregCr 0:e6ceb13d2d05 1551 default:
GregCr 0:e6ceb13d2d05 1552 break;
GregCr 0:e6ceb13d2d05 1553 }
GregCr 0:e6ceb13d2d05 1554 break;
mluis 21:2e496deb7858 1555 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1556 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1557 {
GregCr 0:e6ceb13d2d05 1558 case MODEM_FSK:
mluis 25:3778e6204cc1 1559 // FifoEmpty interrupt
GregCr 0:e6ceb13d2d05 1560 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1561 {
GregCr 23:1e143575df0f 1562 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1563 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1564 }
mluis 25:3778e6204cc1 1565 else
GregCr 0:e6ceb13d2d05 1566 {
GregCr 0:e6ceb13d2d05 1567 // Write the last chunk of data
GregCr 23:1e143575df0f 1568 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1569 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1570 }
GregCr 0:e6ceb13d2d05 1571 break;
GregCr 0:e6ceb13d2d05 1572 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1573 break;
GregCr 0:e6ceb13d2d05 1574 default:
GregCr 0:e6ceb13d2d05 1575 break;
GregCr 0:e6ceb13d2d05 1576 }
mluis 22:7f3aab69cca9 1577 break;
GregCr 0:e6ceb13d2d05 1578 default:
GregCr 0:e6ceb13d2d05 1579 break;
GregCr 0:e6ceb13d2d05 1580 }
GregCr 0:e6ceb13d2d05 1581 }
GregCr 0:e6ceb13d2d05 1582
GregCr 0:e6ceb13d2d05 1583 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1584 {
GregCr 0:e6ceb13d2d05 1585 switch( this->settings.State )
mluis 25:3778e6204cc1 1586 {
mluis 21:2e496deb7858 1587 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1588 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1589 {
GregCr 0:e6ceb13d2d05 1590 case MODEM_FSK:
Helmut Tschemernjak 31:e50929bd3f32 1591 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
Helmut Tschemernjak 31:e50929bd3f32 1592 if( this->dioIrq[4] == NULL )
Helmut Tschemernjak 31:e50929bd3f32 1593 {
Helmut Tschemernjak 31:e50929bd3f32 1594 this->settings.FskPacketHandler.PreambleDetected = true;
Helmut Tschemernjak 31:e50929bd3f32 1595 }
Helmut Tschemernjak 31:e50929bd3f32 1596
GregCr 0:e6ceb13d2d05 1597 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1598 {
Helmut Tschemernjak 53:6d3adad59633 1599 SetTimeout(RXTimeoutSyncWordTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1600
GregCr 0:e6ceb13d2d05 1601 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 25:3778e6204cc1 1602
GregCr 0:e6ceb13d2d05 1603 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1604
GregCr 0:e6ceb13d2d05 1605 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1606 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1607 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1608 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1609 }
GregCr 0:e6ceb13d2d05 1610 break;
GregCr 0:e6ceb13d2d05 1611 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1612 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1613 {
GregCr 6:e7f02929cd3d 1614 // Clear Irq
GregCr 6:e7f02929cd3d 1615 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1616
Helmut Tschemernjak 63:5b9d391244dc 1617 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
mluis 13:618826a997e2 1618 {
Helmut Tschemernjak 63:5b9d391244dc 1619 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1620 }
mluis 22:7f3aab69cca9 1621 }
GregCr 0:e6ceb13d2d05 1622 break;
GregCr 0:e6ceb13d2d05 1623 default:
GregCr 0:e6ceb13d2d05 1624 break;
GregCr 0:e6ceb13d2d05 1625 }
GregCr 0:e6ceb13d2d05 1626 break;
mluis 21:2e496deb7858 1627 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1628 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1629 {
GregCr 0:e6ceb13d2d05 1630 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1631 break;
GregCr 0:e6ceb13d2d05 1632 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1633 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1634 {
GregCr 6:e7f02929cd3d 1635 // Clear Irq
GregCr 6:e7f02929cd3d 1636 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1637
Helmut Tschemernjak 63:5b9d391244dc 1638 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
mluis 13:618826a997e2 1639 {
Helmut Tschemernjak 63:5b9d391244dc 1640 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1641 }
mluis 22:7f3aab69cca9 1642 }
GregCr 0:e6ceb13d2d05 1643 break;
GregCr 0:e6ceb13d2d05 1644 default:
GregCr 0:e6ceb13d2d05 1645 break;
GregCr 0:e6ceb13d2d05 1646 }
mluis 22:7f3aab69cca9 1647 break;
GregCr 0:e6ceb13d2d05 1648 default:
GregCr 0:e6ceb13d2d05 1649 break;
GregCr 0:e6ceb13d2d05 1650 }
GregCr 0:e6ceb13d2d05 1651 }
GregCr 0:e6ceb13d2d05 1652
GregCr 0:e6ceb13d2d05 1653 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1654 {
GregCr 0:e6ceb13d2d05 1655 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1656 {
GregCr 0:e6ceb13d2d05 1657 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1658 break;
GregCr 0:e6ceb13d2d05 1659 case MODEM_LORA:
mluis 22:7f3aab69cca9 1660 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1661 {
mluis 13:618826a997e2 1662 // Clear Irq
mluis 22:7f3aab69cca9 1663 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
Helmut Tschemernjak 63:5b9d391244dc 1664 if (this->RadioEvents && this->RadioEvents->CadDone)
mluis 13:618826a997e2 1665 {
Helmut Tschemernjak 63:5b9d391244dc 1666 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, true );
mluis 13:618826a997e2 1667 }
GregCr 12:aa5b3bf7fdf4 1668 }
GregCr 12:aa5b3bf7fdf4 1669 else
mluis 25:3778e6204cc1 1670 {
mluis 13:618826a997e2 1671 // Clear Irq
mluis 13:618826a997e2 1672 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
Helmut Tschemernjak 63:5b9d391244dc 1673 if (this->RadioEvents && this->RadioEvents->CadDone)
mluis 13:618826a997e2 1674 {
Helmut Tschemernjak 63:5b9d391244dc 1675 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, false );
mluis 13:618826a997e2 1676 }
GregCr 7:2b555111463f 1677 }
GregCr 0:e6ceb13d2d05 1678 break;
GregCr 0:e6ceb13d2d05 1679 default:
GregCr 0:e6ceb13d2d05 1680 break;
GregCr 0:e6ceb13d2d05 1681 }
GregCr 0:e6ceb13d2d05 1682 }
GregCr 0:e6ceb13d2d05 1683
GregCr 0:e6ceb13d2d05 1684 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1685 {
GregCr 0:e6ceb13d2d05 1686 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1687 {
GregCr 0:e6ceb13d2d05 1688 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1689 {
GregCr 0:e6ceb13d2d05 1690 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1691 {
GregCr 0:e6ceb13d2d05 1692 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 25:3778e6204cc1 1693 }
GregCr 0:e6ceb13d2d05 1694 }
GregCr 0:e6ceb13d2d05 1695 break;
GregCr 0:e6ceb13d2d05 1696 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1697 break;
GregCr 0:e6ceb13d2d05 1698 default:
GregCr 0:e6ceb13d2d05 1699 break;
GregCr 0:e6ceb13d2d05 1700 }
GregCr 0:e6ceb13d2d05 1701 }
GregCr 0:e6ceb13d2d05 1702
GregCr 0:e6ceb13d2d05 1703 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1704 {
GregCr 0:e6ceb13d2d05 1705 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1706 {
GregCr 0:e6ceb13d2d05 1707 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1708 break;
GregCr 0:e6ceb13d2d05 1709 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1710 break;
GregCr 0:e6ceb13d2d05 1711 default:
GregCr 0:e6ceb13d2d05 1712 break;
GregCr 0:e6ceb13d2d05 1713 }
mluis 13:618826a997e2 1714 }