202hm2_master_generation - //EE 202 hm2 //This is a program built for the mb…

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Yujing Qian / Mbed 2 deprecated 202hm2_master_generation

//EE 202 hm2 //This is a program built for the mbed1(master mbed) in generation mode //This code has been tested and should be function, if you has any problem, //please mail me.

Dependencies: mbed

Fork of 202hm2_master by Yujing Qian

MKL46Z4.h@0:fac0542384d7, 2014-03-13 (annotated)

Committer:: allonq
Date:: Thu Mar 13 21:28:39 2014 +0000
Revision:: 0:fac0542384d7

hm2_master(mbed1)

Who changed what in which revision?

User	Revision	Line number	New contents of line
allonq	0:fac0542384d7	1	/*
allonq	0:fac0542384d7	2	** ###################################################################
allonq	0:fac0542384d7	3	** Processors: MKL46Z256VLH4
allonq	0:fac0542384d7	4	** MKL46Z128VLH4
allonq	0:fac0542384d7	5	** MKL46Z256VLL4
allonq	0:fac0542384d7	6	** MKL46Z128VLL4
allonq	0:fac0542384d7	7	** MKL46Z256VMC4
allonq	0:fac0542384d7	8	** MKL46Z128VMC4
allonq	0:fac0542384d7	9	**
allonq	0:fac0542384d7	10	** Compilers: ARM Compiler
allonq	0:fac0542384d7	11	** Freescale C/C++ for Embedded ARM
allonq	0:fac0542384d7	12	** GNU C Compiler
allonq	0:fac0542384d7	13	** IAR ANSI C/C++ Compiler for ARM
allonq	0:fac0542384d7	14	**
allonq	0:fac0542384d7	15	** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
allonq	0:fac0542384d7	16	** Version: rev. 2.2, 2013-04-12
allonq	0:fac0542384d7	17	**
allonq	0:fac0542384d7	18	** Abstract:
allonq	0:fac0542384d7	19	** CMSIS Peripheral Access Layer for MKL46Z4
allonq	0:fac0542384d7	20	**
allonq	0:fac0542384d7	21	** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
allonq	0:fac0542384d7	22	**
allonq	0:fac0542384d7	23	** http: www.freescale.com
allonq	0:fac0542384d7	24	** mail: support@freescale.com
allonq	0:fac0542384d7	25	**
allonq	0:fac0542384d7	26	** Revisions:
allonq	0:fac0542384d7	27	** - rev. 1.0 (2012-10-16)
allonq	0:fac0542384d7	28	** Initial version.
allonq	0:fac0542384d7	29	** - rev. 2.0 (2012-12-12)
allonq	0:fac0542384d7	30	** Update to reference manual rev. 1.
allonq	0:fac0542384d7	31	** - rev. 2.1 (2013-04-05)
allonq	0:fac0542384d7	32	** Changed start of doxygen comment.
allonq	0:fac0542384d7	33	** - rev. 2.2 (2013-04-12)
allonq	0:fac0542384d7	34	** SystemInit function fixed for clock configuration 1.
allonq	0:fac0542384d7	35	** Name of the interrupt num. 31 updated to reflect proper function.
allonq	0:fac0542384d7	36	**
allonq	0:fac0542384d7	37	** ###################################################################
allonq	0:fac0542384d7	38	*/
allonq	0:fac0542384d7	39
allonq	0:fac0542384d7	40	/*!
allonq	0:fac0542384d7	41	* @file MKL46Z4.h
allonq	0:fac0542384d7	42	* @version 2.2
allonq	0:fac0542384d7	43	* @date 2013-04-12
allonq	0:fac0542384d7	44	* @brief CMSIS Peripheral Access Layer for MKL46Z4
allonq	0:fac0542384d7	45	*
allonq	0:fac0542384d7	46	* CMSIS Peripheral Access Layer for MKL46Z4
allonq	0:fac0542384d7	47	*/
allonq	0:fac0542384d7	48
allonq	0:fac0542384d7	49	#if !defined(MKL46Z4_H_)
allonq	0:fac0542384d7	50	#define MKL46Z4_H_ /*< Symbol preventing repeated inclusion /
allonq	0:fac0542384d7	51
allonq	0:fac0542384d7	52	/** Memory map major version (memory maps with equal major version number are
allonq	0:fac0542384d7	53	* compatible) */
allonq	0:fac0542384d7	54	#define MCU_MEM_MAP_VERSION 0x0200u
allonq	0:fac0542384d7	55	/** Memory map minor version */
allonq	0:fac0542384d7	56	#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
allonq	0:fac0542384d7	57
allonq	0:fac0542384d7	58
allonq	0:fac0542384d7	59	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	60	-- Interrupt vector numbers
allonq	0:fac0542384d7	61	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	62
allonq	0:fac0542384d7	63	/*!
allonq	0:fac0542384d7	64	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
allonq	0:fac0542384d7	65	* @{
allonq	0:fac0542384d7	66	*/
allonq	0:fac0542384d7	67
allonq	0:fac0542384d7	68	/** Interrupt Number Definitions */
allonq	0:fac0542384d7	69	typedef enum IRQn {
allonq	0:fac0542384d7	70	/* Core interrupts */
allonq	0:fac0542384d7	71	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
allonq	0:fac0542384d7	72	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
allonq	0:fac0542384d7	73	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
allonq	0:fac0542384d7	74	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
allonq	0:fac0542384d7	75	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
allonq	0:fac0542384d7	76
allonq	0:fac0542384d7	77	/* Device specific interrupts */
allonq	0:fac0542384d7	78	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete/error interrupt /
allonq	0:fac0542384d7	79	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete/error interrupt /
allonq	0:fac0542384d7	80	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete/error interrupt /
allonq	0:fac0542384d7	81	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete/error interrupt /
allonq	0:fac0542384d7	82	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
allonq	0:fac0542384d7	83	FTFA_IRQn = 5, /*< FTFA command complete/read collision interrupt /
allonq	0:fac0542384d7	84	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
allonq	0:fac0542384d7	85	LLW_IRQn = 7, /*< Low Leakage Wakeup /
allonq	0:fac0542384d7	86	I2C0_IRQn = 8, /*< I2C0 interrupt /
allonq	0:fac0542384d7	87	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
allonq	0:fac0542384d7	88	SPI0_IRQn = 10, /*< SPI0 interrupt /
allonq	0:fac0542384d7	89	SPI1_IRQn = 11, /*< SPI1 interrupt /
allonq	0:fac0542384d7	90	UART0_IRQn = 12, /*< UART0 status/error interrupt /
allonq	0:fac0542384d7	91	UART1_IRQn = 13, /*< UART1 status/error interrupt /
allonq	0:fac0542384d7	92	UART2_IRQn = 14, /*< UART2 status/error interrupt /
allonq	0:fac0542384d7	93	ADC0_IRQn = 15, /*< ADC0 interrupt /
allonq	0:fac0542384d7	94	CMP0_IRQn = 16, /*< CMP0 interrupt /
allonq	0:fac0542384d7	95	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
allonq	0:fac0542384d7	96	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
allonq	0:fac0542384d7	97	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
allonq	0:fac0542384d7	98	RTC_IRQn = 20, /*< RTC interrupt /
allonq	0:fac0542384d7	99	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
allonq	0:fac0542384d7	100	PIT_IRQn = 22, /*< PIT timer interrupt /
allonq	0:fac0542384d7	101	I2S0_IRQn = 23, /*< I2S0 transmit interrupt /
allonq	0:fac0542384d7	102	USB0_IRQn = 24, /*< USB0 interrupt /
allonq	0:fac0542384d7	103	DAC0_IRQn = 25, /*< DAC0 interrupt /
allonq	0:fac0542384d7	104	TSI0_IRQn = 26, /*< TSI0 interrupt /
allonq	0:fac0542384d7	105	MCG_IRQn = 27, /*< MCG interrupt /
allonq	0:fac0542384d7	106	LPTimer_IRQn = 28, /*< LPTimer interrupt /
allonq	0:fac0542384d7	107	LCD_IRQn = 29, /*< Segment LCD Interrupt /
allonq	0:fac0542384d7	108	PORTA_IRQn = 30, /*< Port A interrupt /
allonq	0:fac0542384d7	109	PORTC_PORTD_IRQn = 31 /*< Port C and port D interrupt /
allonq	0:fac0542384d7	110	} IRQn_Type;
allonq	0:fac0542384d7	111
allonq	0:fac0542384d7	112	/*!
allonq	0:fac0542384d7	113	* @}
allonq	0:fac0542384d7	114	/ / end of group Interrupt_vector_numbers */
allonq	0:fac0542384d7	115
allonq	0:fac0542384d7	116
allonq	0:fac0542384d7	117	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	118	-- Cortex M0 Core Configuration
allonq	0:fac0542384d7	119	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	120
allonq	0:fac0542384d7	121	/*!
allonq	0:fac0542384d7	122	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
allonq	0:fac0542384d7	123	* @{
allonq	0:fac0542384d7	124	*/
allonq	0:fac0542384d7	125
allonq	0:fac0542384d7	126	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
allonq	0:fac0542384d7	127	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
allonq	0:fac0542384d7	128	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
allonq	0:fac0542384d7	129	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
allonq	0:fac0542384d7	130	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
allonq	0:fac0542384d7	131
allonq	0:fac0542384d7	132	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
allonq	0:fac0542384d7	133	#include "system_MKL46Z4.h" /* Device specific configuration file */
allonq	0:fac0542384d7	134
allonq	0:fac0542384d7	135	/*!
allonq	0:fac0542384d7	136	* @}
allonq	0:fac0542384d7	137	/ / end of group Cortex_Core_Configuration */
allonq	0:fac0542384d7	138
allonq	0:fac0542384d7	139
allonq	0:fac0542384d7	140	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	141	-- Device Peripheral Access Layer
allonq	0:fac0542384d7	142	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	143
allonq	0:fac0542384d7	144	/*!
allonq	0:fac0542384d7	145	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
allonq	0:fac0542384d7	146	* @{
allonq	0:fac0542384d7	147	*/
allonq	0:fac0542384d7	148
allonq	0:fac0542384d7	149
allonq	0:fac0542384d7	150	/*
allonq	0:fac0542384d7	151	** Start of section using anonymous unions
allonq	0:fac0542384d7	152	*/
allonq	0:fac0542384d7	153
allonq	0:fac0542384d7	154	#if defined(__ARMCC_VERSION)
allonq	0:fac0542384d7	155	#pragma push
allonq	0:fac0542384d7	156	#pragma anon_unions
allonq	0:fac0542384d7	157	#elif defined(__CWCC__)
allonq	0:fac0542384d7	158	#pragma push
allonq	0:fac0542384d7	159	#pragma cpp_extensions on
allonq	0:fac0542384d7	160	#elif defined(__GNUC__)
allonq	0:fac0542384d7	161	/* anonymous unions are enabled by default */
allonq	0:fac0542384d7	162	#elif defined(__IAR_SYSTEMS_ICC__)
allonq	0:fac0542384d7	163	#pragma language=extended
allonq	0:fac0542384d7	164	#else
allonq	0:fac0542384d7	165	#error Not supported compiler type
allonq	0:fac0542384d7	166	#endif
allonq	0:fac0542384d7	167
allonq	0:fac0542384d7	168	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	169	-- ADC Peripheral Access Layer
allonq	0:fac0542384d7	170	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	171
allonq	0:fac0542384d7	172	/*!
allonq	0:fac0542384d7	173	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
allonq	0:fac0542384d7	174	* @{
allonq	0:fac0542384d7	175	*/
allonq	0:fac0542384d7	176
allonq	0:fac0542384d7	177	/** ADC - Register Layout Typedef */
allonq	0:fac0542384d7	178	typedef struct {
allonq	0:fac0542384d7	179	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
allonq	0:fac0542384d7	180	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
allonq	0:fac0542384d7	181	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
allonq	0:fac0542384d7	182	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
allonq	0:fac0542384d7	183	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
allonq	0:fac0542384d7	184	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
allonq	0:fac0542384d7	185	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
allonq	0:fac0542384d7	186	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
allonq	0:fac0542384d7	187	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
allonq	0:fac0542384d7	188	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
allonq	0:fac0542384d7	189	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
allonq	0:fac0542384d7	190	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
allonq	0:fac0542384d7	191	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
allonq	0:fac0542384d7	192	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
allonq	0:fac0542384d7	193	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
allonq	0:fac0542384d7	194	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
allonq	0:fac0542384d7	195	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
allonq	0:fac0542384d7	196	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
allonq	0:fac0542384d7	197	uint8_t RESERVED_0[4];
allonq	0:fac0542384d7	198	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
allonq	0:fac0542384d7	199	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
allonq	0:fac0542384d7	200	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
allonq	0:fac0542384d7	201	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
allonq	0:fac0542384d7	202	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
allonq	0:fac0542384d7	203	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
allonq	0:fac0542384d7	204	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
allonq	0:fac0542384d7	205	} ADC_Type;
allonq	0:fac0542384d7	206
allonq	0:fac0542384d7	207	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	208	-- ADC Register Masks
allonq	0:fac0542384d7	209	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	210
allonq	0:fac0542384d7	211	/*!
allonq	0:fac0542384d7	212	* @addtogroup ADC_Register_Masks ADC Register Masks
allonq	0:fac0542384d7	213	* @{
allonq	0:fac0542384d7	214	*/
allonq	0:fac0542384d7	215
allonq	0:fac0542384d7	216	/* SC1 Bit Fields */
allonq	0:fac0542384d7	217	#define ADC_SC1_ADCH_MASK 0x1Fu
allonq	0:fac0542384d7	218	#define ADC_SC1_ADCH_SHIFT 0
allonq	0:fac0542384d7	219	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
allonq	0:fac0542384d7	220	#define ADC_SC1_DIFF_MASK 0x20u
allonq	0:fac0542384d7	221	#define ADC_SC1_DIFF_SHIFT 5
allonq	0:fac0542384d7	222	#define ADC_SC1_AIEN_MASK 0x40u
allonq	0:fac0542384d7	223	#define ADC_SC1_AIEN_SHIFT 6
allonq	0:fac0542384d7	224	#define ADC_SC1_COCO_MASK 0x80u
allonq	0:fac0542384d7	225	#define ADC_SC1_COCO_SHIFT 7
allonq	0:fac0542384d7	226	/* CFG1 Bit Fields */
allonq	0:fac0542384d7	227	#define ADC_CFG1_ADICLK_MASK 0x3u
allonq	0:fac0542384d7	228	#define ADC_CFG1_ADICLK_SHIFT 0
allonq	0:fac0542384d7	229	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
allonq	0:fac0542384d7	230	#define ADC_CFG1_MODE_MASK 0xCu
allonq	0:fac0542384d7	231	#define ADC_CFG1_MODE_SHIFT 2
allonq	0:fac0542384d7	232	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
allonq	0:fac0542384d7	233	#define ADC_CFG1_ADLSMP_MASK 0x10u
allonq	0:fac0542384d7	234	#define ADC_CFG1_ADLSMP_SHIFT 4
allonq	0:fac0542384d7	235	#define ADC_CFG1_ADIV_MASK 0x60u
allonq	0:fac0542384d7	236	#define ADC_CFG1_ADIV_SHIFT 5
allonq	0:fac0542384d7	237	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
allonq	0:fac0542384d7	238	#define ADC_CFG1_ADLPC_MASK 0x80u
allonq	0:fac0542384d7	239	#define ADC_CFG1_ADLPC_SHIFT 7
allonq	0:fac0542384d7	240	/* CFG2 Bit Fields */
allonq	0:fac0542384d7	241	#define ADC_CFG2_ADLSTS_MASK 0x3u
allonq	0:fac0542384d7	242	#define ADC_CFG2_ADLSTS_SHIFT 0
allonq	0:fac0542384d7	243	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
allonq	0:fac0542384d7	244	#define ADC_CFG2_ADHSC_MASK 0x4u
allonq	0:fac0542384d7	245	#define ADC_CFG2_ADHSC_SHIFT 2
allonq	0:fac0542384d7	246	#define ADC_CFG2_ADACKEN_MASK 0x8u
allonq	0:fac0542384d7	247	#define ADC_CFG2_ADACKEN_SHIFT 3
allonq	0:fac0542384d7	248	#define ADC_CFG2_MUXSEL_MASK 0x10u
allonq	0:fac0542384d7	249	#define ADC_CFG2_MUXSEL_SHIFT 4
allonq	0:fac0542384d7	250	/* R Bit Fields */
allonq	0:fac0542384d7	251	#define ADC_R_D_MASK 0xFFFFu
allonq	0:fac0542384d7	252	#define ADC_R_D_SHIFT 0
allonq	0:fac0542384d7	253	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
allonq	0:fac0542384d7	254	/* CV1 Bit Fields */
allonq	0:fac0542384d7	255	#define ADC_CV1_CV_MASK 0xFFFFu
allonq	0:fac0542384d7	256	#define ADC_CV1_CV_SHIFT 0
allonq	0:fac0542384d7	257	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
allonq	0:fac0542384d7	258	/* CV2 Bit Fields */
allonq	0:fac0542384d7	259	#define ADC_CV2_CV_MASK 0xFFFFu
allonq	0:fac0542384d7	260	#define ADC_CV2_CV_SHIFT 0
allonq	0:fac0542384d7	261	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
allonq	0:fac0542384d7	262	/* SC2 Bit Fields */
allonq	0:fac0542384d7	263	#define ADC_SC2_REFSEL_MASK 0x3u
allonq	0:fac0542384d7	264	#define ADC_SC2_REFSEL_SHIFT 0
allonq	0:fac0542384d7	265	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
allonq	0:fac0542384d7	266	#define ADC_SC2_DMAEN_MASK 0x4u
allonq	0:fac0542384d7	267	#define ADC_SC2_DMAEN_SHIFT 2
allonq	0:fac0542384d7	268	#define ADC_SC2_ACREN_MASK 0x8u
allonq	0:fac0542384d7	269	#define ADC_SC2_ACREN_SHIFT 3
allonq	0:fac0542384d7	270	#define ADC_SC2_ACFGT_MASK 0x10u
allonq	0:fac0542384d7	271	#define ADC_SC2_ACFGT_SHIFT 4
allonq	0:fac0542384d7	272	#define ADC_SC2_ACFE_MASK 0x20u
allonq	0:fac0542384d7	273	#define ADC_SC2_ACFE_SHIFT 5
allonq	0:fac0542384d7	274	#define ADC_SC2_ADTRG_MASK 0x40u
allonq	0:fac0542384d7	275	#define ADC_SC2_ADTRG_SHIFT 6
allonq	0:fac0542384d7	276	#define ADC_SC2_ADACT_MASK 0x80u
allonq	0:fac0542384d7	277	#define ADC_SC2_ADACT_SHIFT 7
allonq	0:fac0542384d7	278	/* SC3 Bit Fields */
allonq	0:fac0542384d7	279	#define ADC_SC3_AVGS_MASK 0x3u
allonq	0:fac0542384d7	280	#define ADC_SC3_AVGS_SHIFT 0
allonq	0:fac0542384d7	281	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
allonq	0:fac0542384d7	282	#define ADC_SC3_AVGE_MASK 0x4u
allonq	0:fac0542384d7	283	#define ADC_SC3_AVGE_SHIFT 2
allonq	0:fac0542384d7	284	#define ADC_SC3_ADCO_MASK 0x8u
allonq	0:fac0542384d7	285	#define ADC_SC3_ADCO_SHIFT 3
allonq	0:fac0542384d7	286	#define ADC_SC3_CALF_MASK 0x40u
allonq	0:fac0542384d7	287	#define ADC_SC3_CALF_SHIFT 6
allonq	0:fac0542384d7	288	#define ADC_SC3_CAL_MASK 0x80u
allonq	0:fac0542384d7	289	#define ADC_SC3_CAL_SHIFT 7
allonq	0:fac0542384d7	290	/* OFS Bit Fields */
allonq	0:fac0542384d7	291	#define ADC_OFS_OFS_MASK 0xFFFFu
allonq	0:fac0542384d7	292	#define ADC_OFS_OFS_SHIFT 0
allonq	0:fac0542384d7	293	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
allonq	0:fac0542384d7	294	/* PG Bit Fields */
allonq	0:fac0542384d7	295	#define ADC_PG_PG_MASK 0xFFFFu
allonq	0:fac0542384d7	296	#define ADC_PG_PG_SHIFT 0
allonq	0:fac0542384d7	297	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
allonq	0:fac0542384d7	298	/* MG Bit Fields */
allonq	0:fac0542384d7	299	#define ADC_MG_MG_MASK 0xFFFFu
allonq	0:fac0542384d7	300	#define ADC_MG_MG_SHIFT 0
allonq	0:fac0542384d7	301	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
allonq	0:fac0542384d7	302	/* CLPD Bit Fields */
allonq	0:fac0542384d7	303	#define ADC_CLPD_CLPD_MASK 0x3Fu
allonq	0:fac0542384d7	304	#define ADC_CLPD_CLPD_SHIFT 0
allonq	0:fac0542384d7	305	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
allonq	0:fac0542384d7	306	/* CLPS Bit Fields */
allonq	0:fac0542384d7	307	#define ADC_CLPS_CLPS_MASK 0x3Fu
allonq	0:fac0542384d7	308	#define ADC_CLPS_CLPS_SHIFT 0
allonq	0:fac0542384d7	309	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
allonq	0:fac0542384d7	310	/* CLP4 Bit Fields */
allonq	0:fac0542384d7	311	#define ADC_CLP4_CLP4_MASK 0x3FFu
allonq	0:fac0542384d7	312	#define ADC_CLP4_CLP4_SHIFT 0
allonq	0:fac0542384d7	313	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
allonq	0:fac0542384d7	314	/* CLP3 Bit Fields */
allonq	0:fac0542384d7	315	#define ADC_CLP3_CLP3_MASK 0x1FFu
allonq	0:fac0542384d7	316	#define ADC_CLP3_CLP3_SHIFT 0
allonq	0:fac0542384d7	317	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
allonq	0:fac0542384d7	318	/* CLP2 Bit Fields */
allonq	0:fac0542384d7	319	#define ADC_CLP2_CLP2_MASK 0xFFu
allonq	0:fac0542384d7	320	#define ADC_CLP2_CLP2_SHIFT 0
allonq	0:fac0542384d7	321	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
allonq	0:fac0542384d7	322	/* CLP1 Bit Fields */
allonq	0:fac0542384d7	323	#define ADC_CLP1_CLP1_MASK 0x7Fu
allonq	0:fac0542384d7	324	#define ADC_CLP1_CLP1_SHIFT 0
allonq	0:fac0542384d7	325	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
allonq	0:fac0542384d7	326	/* CLP0 Bit Fields */
allonq	0:fac0542384d7	327	#define ADC_CLP0_CLP0_MASK 0x3Fu
allonq	0:fac0542384d7	328	#define ADC_CLP0_CLP0_SHIFT 0
allonq	0:fac0542384d7	329	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
allonq	0:fac0542384d7	330	/* CLMD Bit Fields */
allonq	0:fac0542384d7	331	#define ADC_CLMD_CLMD_MASK 0x3Fu
allonq	0:fac0542384d7	332	#define ADC_CLMD_CLMD_SHIFT 0
allonq	0:fac0542384d7	333	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
allonq	0:fac0542384d7	334	/* CLMS Bit Fields */
allonq	0:fac0542384d7	335	#define ADC_CLMS_CLMS_MASK 0x3Fu
allonq	0:fac0542384d7	336	#define ADC_CLMS_CLMS_SHIFT 0
allonq	0:fac0542384d7	337	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
allonq	0:fac0542384d7	338	/* CLM4 Bit Fields */
allonq	0:fac0542384d7	339	#define ADC_CLM4_CLM4_MASK 0x3FFu
allonq	0:fac0542384d7	340	#define ADC_CLM4_CLM4_SHIFT 0
allonq	0:fac0542384d7	341	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
allonq	0:fac0542384d7	342	/* CLM3 Bit Fields */
allonq	0:fac0542384d7	343	#define ADC_CLM3_CLM3_MASK 0x1FFu
allonq	0:fac0542384d7	344	#define ADC_CLM3_CLM3_SHIFT 0
allonq	0:fac0542384d7	345	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
allonq	0:fac0542384d7	346	/* CLM2 Bit Fields */
allonq	0:fac0542384d7	347	#define ADC_CLM2_CLM2_MASK 0xFFu
allonq	0:fac0542384d7	348	#define ADC_CLM2_CLM2_SHIFT 0
allonq	0:fac0542384d7	349	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
allonq	0:fac0542384d7	350	/* CLM1 Bit Fields */
allonq	0:fac0542384d7	351	#define ADC_CLM1_CLM1_MASK 0x7Fu
allonq	0:fac0542384d7	352	#define ADC_CLM1_CLM1_SHIFT 0
allonq	0:fac0542384d7	353	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
allonq	0:fac0542384d7	354	/* CLM0 Bit Fields */
allonq	0:fac0542384d7	355	#define ADC_CLM0_CLM0_MASK 0x3Fu
allonq	0:fac0542384d7	356	#define ADC_CLM0_CLM0_SHIFT 0
allonq	0:fac0542384d7	357	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
allonq	0:fac0542384d7	358
allonq	0:fac0542384d7	359	/*!
allonq	0:fac0542384d7	360	* @}
allonq	0:fac0542384d7	361	/ / end of group ADC_Register_Masks */
allonq	0:fac0542384d7	362
allonq	0:fac0542384d7	363
allonq	0:fac0542384d7	364	/* ADC - Peripheral instance base addresses */
allonq	0:fac0542384d7	365	/** Peripheral ADC0 base address */
allonq	0:fac0542384d7	366	#define ADC0_BASE (0x4003B000u)
allonq	0:fac0542384d7	367	/** Peripheral ADC0 base pointer */
allonq	0:fac0542384d7	368	#define ADC0 ((ADC_Type *)ADC0_BASE)
allonq	0:fac0542384d7	369	/** Array initializer of ADC peripheral base pointers */
allonq	0:fac0542384d7	370	#define ADC_BASES { ADC0 }
allonq	0:fac0542384d7	371
allonq	0:fac0542384d7	372	/*!
allonq	0:fac0542384d7	373	* @}
allonq	0:fac0542384d7	374	/ / end of group ADC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	375
allonq	0:fac0542384d7	376
allonq	0:fac0542384d7	377	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	378	-- CMP Peripheral Access Layer
allonq	0:fac0542384d7	379	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	380
allonq	0:fac0542384d7	381	/*!
allonq	0:fac0542384d7	382	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
allonq	0:fac0542384d7	383	* @{
allonq	0:fac0542384d7	384	*/
allonq	0:fac0542384d7	385
allonq	0:fac0542384d7	386	/** CMP - Register Layout Typedef */
allonq	0:fac0542384d7	387	typedef struct {
allonq	0:fac0542384d7	388	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
allonq	0:fac0542384d7	389	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
allonq	0:fac0542384d7	390	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
allonq	0:fac0542384d7	391	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
allonq	0:fac0542384d7	392	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
allonq	0:fac0542384d7	393	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
allonq	0:fac0542384d7	394	} CMP_Type;
allonq	0:fac0542384d7	395
allonq	0:fac0542384d7	396	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	397	-- CMP Register Masks
allonq	0:fac0542384d7	398	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	399
allonq	0:fac0542384d7	400	/*!
allonq	0:fac0542384d7	401	* @addtogroup CMP_Register_Masks CMP Register Masks
allonq	0:fac0542384d7	402	* @{
allonq	0:fac0542384d7	403	*/
allonq	0:fac0542384d7	404
allonq	0:fac0542384d7	405	/* CR0 Bit Fields */
allonq	0:fac0542384d7	406	#define CMP_CR0_HYSTCTR_MASK 0x3u
allonq	0:fac0542384d7	407	#define CMP_CR0_HYSTCTR_SHIFT 0
allonq	0:fac0542384d7	408	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
allonq	0:fac0542384d7	409	#define CMP_CR0_FILTER_CNT_MASK 0x70u
allonq	0:fac0542384d7	410	#define CMP_CR0_FILTER_CNT_SHIFT 4
allonq	0:fac0542384d7	411	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
allonq	0:fac0542384d7	412	/* CR1 Bit Fields */
allonq	0:fac0542384d7	413	#define CMP_CR1_EN_MASK 0x1u
allonq	0:fac0542384d7	414	#define CMP_CR1_EN_SHIFT 0
allonq	0:fac0542384d7	415	#define CMP_CR1_OPE_MASK 0x2u
allonq	0:fac0542384d7	416	#define CMP_CR1_OPE_SHIFT 1
allonq	0:fac0542384d7	417	#define CMP_CR1_COS_MASK 0x4u
allonq	0:fac0542384d7	418	#define CMP_CR1_COS_SHIFT 2
allonq	0:fac0542384d7	419	#define CMP_CR1_INV_MASK 0x8u
allonq	0:fac0542384d7	420	#define CMP_CR1_INV_SHIFT 3
allonq	0:fac0542384d7	421	#define CMP_CR1_PMODE_MASK 0x10u
allonq	0:fac0542384d7	422	#define CMP_CR1_PMODE_SHIFT 4
allonq	0:fac0542384d7	423	#define CMP_CR1_TRIGM_MASK 0x20u
allonq	0:fac0542384d7	424	#define CMP_CR1_TRIGM_SHIFT 5
allonq	0:fac0542384d7	425	#define CMP_CR1_WE_MASK 0x40u
allonq	0:fac0542384d7	426	#define CMP_CR1_WE_SHIFT 6
allonq	0:fac0542384d7	427	#define CMP_CR1_SE_MASK 0x80u
allonq	0:fac0542384d7	428	#define CMP_CR1_SE_SHIFT 7
allonq	0:fac0542384d7	429	/* FPR Bit Fields */
allonq	0:fac0542384d7	430	#define CMP_FPR_FILT_PER_MASK 0xFFu
allonq	0:fac0542384d7	431	#define CMP_FPR_FILT_PER_SHIFT 0
allonq	0:fac0542384d7	432	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
allonq	0:fac0542384d7	433	/* SCR Bit Fields */
allonq	0:fac0542384d7	434	#define CMP_SCR_COUT_MASK 0x1u
allonq	0:fac0542384d7	435	#define CMP_SCR_COUT_SHIFT 0
allonq	0:fac0542384d7	436	#define CMP_SCR_CFF_MASK 0x2u
allonq	0:fac0542384d7	437	#define CMP_SCR_CFF_SHIFT 1
allonq	0:fac0542384d7	438	#define CMP_SCR_CFR_MASK 0x4u
allonq	0:fac0542384d7	439	#define CMP_SCR_CFR_SHIFT 2
allonq	0:fac0542384d7	440	#define CMP_SCR_IEF_MASK 0x8u
allonq	0:fac0542384d7	441	#define CMP_SCR_IEF_SHIFT 3
allonq	0:fac0542384d7	442	#define CMP_SCR_IER_MASK 0x10u
allonq	0:fac0542384d7	443	#define CMP_SCR_IER_SHIFT 4
allonq	0:fac0542384d7	444	#define CMP_SCR_DMAEN_MASK 0x40u
allonq	0:fac0542384d7	445	#define CMP_SCR_DMAEN_SHIFT 6
allonq	0:fac0542384d7	446	/* DACCR Bit Fields */
allonq	0:fac0542384d7	447	#define CMP_DACCR_VOSEL_MASK 0x3Fu
allonq	0:fac0542384d7	448	#define CMP_DACCR_VOSEL_SHIFT 0
allonq	0:fac0542384d7	449	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
allonq	0:fac0542384d7	450	#define CMP_DACCR_VRSEL_MASK 0x40u
allonq	0:fac0542384d7	451	#define CMP_DACCR_VRSEL_SHIFT 6
allonq	0:fac0542384d7	452	#define CMP_DACCR_DACEN_MASK 0x80u
allonq	0:fac0542384d7	453	#define CMP_DACCR_DACEN_SHIFT 7
allonq	0:fac0542384d7	454	/* MUXCR Bit Fields */
allonq	0:fac0542384d7	455	#define CMP_MUXCR_MSEL_MASK 0x7u
allonq	0:fac0542384d7	456	#define CMP_MUXCR_MSEL_SHIFT 0
allonq	0:fac0542384d7	457	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
allonq	0:fac0542384d7	458	#define CMP_MUXCR_PSEL_MASK 0x38u
allonq	0:fac0542384d7	459	#define CMP_MUXCR_PSEL_SHIFT 3
allonq	0:fac0542384d7	460	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
allonq	0:fac0542384d7	461	#define CMP_MUXCR_PSTM_MASK 0x80u
allonq	0:fac0542384d7	462	#define CMP_MUXCR_PSTM_SHIFT 7
allonq	0:fac0542384d7	463
allonq	0:fac0542384d7	464	/*!
allonq	0:fac0542384d7	465	* @}
allonq	0:fac0542384d7	466	/ / end of group CMP_Register_Masks */
allonq	0:fac0542384d7	467
allonq	0:fac0542384d7	468
allonq	0:fac0542384d7	469	/* CMP - Peripheral instance base addresses */
allonq	0:fac0542384d7	470	/** Peripheral CMP0 base address */
allonq	0:fac0542384d7	471	#define CMP0_BASE (0x40073000u)
allonq	0:fac0542384d7	472	/** Peripheral CMP0 base pointer */
allonq	0:fac0542384d7	473	#define CMP0 ((CMP_Type *)CMP0_BASE)
allonq	0:fac0542384d7	474	/** Array initializer of CMP peripheral base pointers */
allonq	0:fac0542384d7	475	#define CMP_BASES { CMP0 }
allonq	0:fac0542384d7	476
allonq	0:fac0542384d7	477	/*!
allonq	0:fac0542384d7	478	* @}
allonq	0:fac0542384d7	479	/ / end of group CMP_Peripheral_Access_Layer */
allonq	0:fac0542384d7	480
allonq	0:fac0542384d7	481
allonq	0:fac0542384d7	482	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	483	-- DAC Peripheral Access Layer
allonq	0:fac0542384d7	484	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	485
allonq	0:fac0542384d7	486	/*!
allonq	0:fac0542384d7	487	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
allonq	0:fac0542384d7	488	* @{
allonq	0:fac0542384d7	489	*/
allonq	0:fac0542384d7	490
allonq	0:fac0542384d7	491	/** DAC - Register Layout Typedef */
allonq	0:fac0542384d7	492	typedef struct {
allonq	0:fac0542384d7	493	struct { /* offset: 0x0, array step: 0x2 */
allonq	0:fac0542384d7	494	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
allonq	0:fac0542384d7	495	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
allonq	0:fac0542384d7	496	} DAT[2];
allonq	0:fac0542384d7	497	uint8_t RESERVED_0[28];
allonq	0:fac0542384d7	498	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
allonq	0:fac0542384d7	499	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
allonq	0:fac0542384d7	500	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
allonq	0:fac0542384d7	501	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
allonq	0:fac0542384d7	502	} DAC_Type;
allonq	0:fac0542384d7	503
allonq	0:fac0542384d7	504	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	505	-- DAC Register Masks
allonq	0:fac0542384d7	506	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	507
allonq	0:fac0542384d7	508	/*!
allonq	0:fac0542384d7	509	* @addtogroup DAC_Register_Masks DAC Register Masks
allonq	0:fac0542384d7	510	* @{
allonq	0:fac0542384d7	511	*/
allonq	0:fac0542384d7	512
allonq	0:fac0542384d7	513	/* DATL Bit Fields */
allonq	0:fac0542384d7	514	#define DAC_DATL_DATA0_MASK 0xFFu
allonq	0:fac0542384d7	515	#define DAC_DATL_DATA0_SHIFT 0
allonq	0:fac0542384d7	516	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
allonq	0:fac0542384d7	517	/* DATH Bit Fields */
allonq	0:fac0542384d7	518	#define DAC_DATH_DATA1_MASK 0xFu
allonq	0:fac0542384d7	519	#define DAC_DATH_DATA1_SHIFT 0
allonq	0:fac0542384d7	520	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
allonq	0:fac0542384d7	521	/* SR Bit Fields */
allonq	0:fac0542384d7	522	#define DAC_SR_DACBFRPBF_MASK 0x1u
allonq	0:fac0542384d7	523	#define DAC_SR_DACBFRPBF_SHIFT 0
allonq	0:fac0542384d7	524	#define DAC_SR_DACBFRPTF_MASK 0x2u
allonq	0:fac0542384d7	525	#define DAC_SR_DACBFRPTF_SHIFT 1
allonq	0:fac0542384d7	526	/* C0 Bit Fields */
allonq	0:fac0542384d7	527	#define DAC_C0_DACBBIEN_MASK 0x1u
allonq	0:fac0542384d7	528	#define DAC_C0_DACBBIEN_SHIFT 0
allonq	0:fac0542384d7	529	#define DAC_C0_DACBTIEN_MASK 0x2u
allonq	0:fac0542384d7	530	#define DAC_C0_DACBTIEN_SHIFT 1
allonq	0:fac0542384d7	531	#define DAC_C0_LPEN_MASK 0x8u
allonq	0:fac0542384d7	532	#define DAC_C0_LPEN_SHIFT 3
allonq	0:fac0542384d7	533	#define DAC_C0_DACSWTRG_MASK 0x10u
allonq	0:fac0542384d7	534	#define DAC_C0_DACSWTRG_SHIFT 4
allonq	0:fac0542384d7	535	#define DAC_C0_DACTRGSEL_MASK 0x20u
allonq	0:fac0542384d7	536	#define DAC_C0_DACTRGSEL_SHIFT 5
allonq	0:fac0542384d7	537	#define DAC_C0_DACRFS_MASK 0x40u
allonq	0:fac0542384d7	538	#define DAC_C0_DACRFS_SHIFT 6
allonq	0:fac0542384d7	539	#define DAC_C0_DACEN_MASK 0x80u
allonq	0:fac0542384d7	540	#define DAC_C0_DACEN_SHIFT 7
allonq	0:fac0542384d7	541	/* C1 Bit Fields */
allonq	0:fac0542384d7	542	#define DAC_C1_DACBFEN_MASK 0x1u
allonq	0:fac0542384d7	543	#define DAC_C1_DACBFEN_SHIFT 0
allonq	0:fac0542384d7	544	#define DAC_C1_DACBFMD_MASK 0x4u
allonq	0:fac0542384d7	545	#define DAC_C1_DACBFMD_SHIFT 2
allonq	0:fac0542384d7	546	#define DAC_C1_DMAEN_MASK 0x80u
allonq	0:fac0542384d7	547	#define DAC_C1_DMAEN_SHIFT 7
allonq	0:fac0542384d7	548	/* C2 Bit Fields */
allonq	0:fac0542384d7	549	#define DAC_C2_DACBFUP_MASK 0x1u
allonq	0:fac0542384d7	550	#define DAC_C2_DACBFUP_SHIFT 0
allonq	0:fac0542384d7	551	#define DAC_C2_DACBFRP_MASK 0x10u
allonq	0:fac0542384d7	552	#define DAC_C2_DACBFRP_SHIFT 4
allonq	0:fac0542384d7	553
allonq	0:fac0542384d7	554	/*!
allonq	0:fac0542384d7	555	* @}
allonq	0:fac0542384d7	556	/ / end of group DAC_Register_Masks */
allonq	0:fac0542384d7	557
allonq	0:fac0542384d7	558
allonq	0:fac0542384d7	559	/* DAC - Peripheral instance base addresses */
allonq	0:fac0542384d7	560	/** Peripheral DAC0 base address */
allonq	0:fac0542384d7	561	#define DAC0_BASE (0x4003F000u)
allonq	0:fac0542384d7	562	/** Peripheral DAC0 base pointer */
allonq	0:fac0542384d7	563	#define DAC0 ((DAC_Type *)DAC0_BASE)
allonq	0:fac0542384d7	564	/** Array initializer of DAC peripheral base pointers */
allonq	0:fac0542384d7	565	#define DAC_BASES { DAC0 }
allonq	0:fac0542384d7	566
allonq	0:fac0542384d7	567	/*!
allonq	0:fac0542384d7	568	* @}
allonq	0:fac0542384d7	569	/ / end of group DAC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	570
allonq	0:fac0542384d7	571
allonq	0:fac0542384d7	572	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	573	-- DMA Peripheral Access Layer
allonq	0:fac0542384d7	574	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	575
allonq	0:fac0542384d7	576	/*!
allonq	0:fac0542384d7	577	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
allonq	0:fac0542384d7	578	* @{
allonq	0:fac0542384d7	579	*/
allonq	0:fac0542384d7	580
allonq	0:fac0542384d7	581	/** DMA - Register Layout Typedef */
allonq	0:fac0542384d7	582	typedef struct {
allonq	0:fac0542384d7	583	uint8_t RESERVED_0[256];
allonq	0:fac0542384d7	584	struct { /* offset: 0x100, array step: 0x10 */
allonq	0:fac0542384d7	585	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
allonq	0:fac0542384d7	586	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
allonq	0:fac0542384d7	587	union { /* offset: 0x108, array step: 0x10 */
allonq	0:fac0542384d7	588	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
allonq	0:fac0542384d7	589	struct { /* offset: 0x108, array step: 0x10 */
allonq	0:fac0542384d7	590	uint8_t RESERVED_0[3];
allonq	0:fac0542384d7	591	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
allonq	0:fac0542384d7	592	} DMA_DSR_ACCESS8BIT;
allonq	0:fac0542384d7	593	};
allonq	0:fac0542384d7	594	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
allonq	0:fac0542384d7	595	} DMA[4];
allonq	0:fac0542384d7	596	} DMA_Type;
allonq	0:fac0542384d7	597
allonq	0:fac0542384d7	598	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	599	-- DMA Register Masks
allonq	0:fac0542384d7	600	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	601
allonq	0:fac0542384d7	602	/*!
allonq	0:fac0542384d7	603	* @addtogroup DMA_Register_Masks DMA Register Masks
allonq	0:fac0542384d7	604	* @{
allonq	0:fac0542384d7	605	*/
allonq	0:fac0542384d7	606
allonq	0:fac0542384d7	607	/* SAR Bit Fields */
allonq	0:fac0542384d7	608	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	609	#define DMA_SAR_SAR_SHIFT 0
allonq	0:fac0542384d7	610	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
allonq	0:fac0542384d7	611	/* DAR Bit Fields */
allonq	0:fac0542384d7	612	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	613	#define DMA_DAR_DAR_SHIFT 0
allonq	0:fac0542384d7	614	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
allonq	0:fac0542384d7	615	/* DSR_BCR Bit Fields */
allonq	0:fac0542384d7	616	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
allonq	0:fac0542384d7	617	#define DMA_DSR_BCR_BCR_SHIFT 0
allonq	0:fac0542384d7	618	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
allonq	0:fac0542384d7	619	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
allonq	0:fac0542384d7	620	#define DMA_DSR_BCR_DONE_SHIFT 24
allonq	0:fac0542384d7	621	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
allonq	0:fac0542384d7	622	#define DMA_DSR_BCR_BSY_SHIFT 25
allonq	0:fac0542384d7	623	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
allonq	0:fac0542384d7	624	#define DMA_DSR_BCR_REQ_SHIFT 26
allonq	0:fac0542384d7	625	#define DMA_DSR_BCR_BED_MASK 0x10000000u
allonq	0:fac0542384d7	626	#define DMA_DSR_BCR_BED_SHIFT 28
allonq	0:fac0542384d7	627	#define DMA_DSR_BCR_BES_MASK 0x20000000u
allonq	0:fac0542384d7	628	#define DMA_DSR_BCR_BES_SHIFT 29
allonq	0:fac0542384d7	629	#define DMA_DSR_BCR_CE_MASK 0x40000000u
allonq	0:fac0542384d7	630	#define DMA_DSR_BCR_CE_SHIFT 30
allonq	0:fac0542384d7	631	/* DCR Bit Fields */
allonq	0:fac0542384d7	632	#define DMA_DCR_LCH2_MASK 0x3u
allonq	0:fac0542384d7	633	#define DMA_DCR_LCH2_SHIFT 0
allonq	0:fac0542384d7	634	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
allonq	0:fac0542384d7	635	#define DMA_DCR_LCH1_MASK 0xCu
allonq	0:fac0542384d7	636	#define DMA_DCR_LCH1_SHIFT 2
allonq	0:fac0542384d7	637	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
allonq	0:fac0542384d7	638	#define DMA_DCR_LINKCC_MASK 0x30u
allonq	0:fac0542384d7	639	#define DMA_DCR_LINKCC_SHIFT 4
allonq	0:fac0542384d7	640	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
allonq	0:fac0542384d7	641	#define DMA_DCR_D_REQ_MASK 0x80u
allonq	0:fac0542384d7	642	#define DMA_DCR_D_REQ_SHIFT 7
allonq	0:fac0542384d7	643	#define DMA_DCR_DMOD_MASK 0xF00u
allonq	0:fac0542384d7	644	#define DMA_DCR_DMOD_SHIFT 8
allonq	0:fac0542384d7	645	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
allonq	0:fac0542384d7	646	#define DMA_DCR_SMOD_MASK 0xF000u
allonq	0:fac0542384d7	647	#define DMA_DCR_SMOD_SHIFT 12
allonq	0:fac0542384d7	648	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
allonq	0:fac0542384d7	649	#define DMA_DCR_START_MASK 0x10000u
allonq	0:fac0542384d7	650	#define DMA_DCR_START_SHIFT 16
allonq	0:fac0542384d7	651	#define DMA_DCR_DSIZE_MASK 0x60000u
allonq	0:fac0542384d7	652	#define DMA_DCR_DSIZE_SHIFT 17
allonq	0:fac0542384d7	653	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
allonq	0:fac0542384d7	654	#define DMA_DCR_DINC_MASK 0x80000u
allonq	0:fac0542384d7	655	#define DMA_DCR_DINC_SHIFT 19
allonq	0:fac0542384d7	656	#define DMA_DCR_SSIZE_MASK 0x300000u
allonq	0:fac0542384d7	657	#define DMA_DCR_SSIZE_SHIFT 20
allonq	0:fac0542384d7	658	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
allonq	0:fac0542384d7	659	#define DMA_DCR_SINC_MASK 0x400000u
allonq	0:fac0542384d7	660	#define DMA_DCR_SINC_SHIFT 22
allonq	0:fac0542384d7	661	#define DMA_DCR_EADREQ_MASK 0x800000u
allonq	0:fac0542384d7	662	#define DMA_DCR_EADREQ_SHIFT 23
allonq	0:fac0542384d7	663	#define DMA_DCR_AA_MASK 0x10000000u
allonq	0:fac0542384d7	664	#define DMA_DCR_AA_SHIFT 28
allonq	0:fac0542384d7	665	#define DMA_DCR_CS_MASK 0x20000000u
allonq	0:fac0542384d7	666	#define DMA_DCR_CS_SHIFT 29
allonq	0:fac0542384d7	667	#define DMA_DCR_ERQ_MASK 0x40000000u
allonq	0:fac0542384d7	668	#define DMA_DCR_ERQ_SHIFT 30
allonq	0:fac0542384d7	669	#define DMA_DCR_EINT_MASK 0x80000000u
allonq	0:fac0542384d7	670	#define DMA_DCR_EINT_SHIFT 31
allonq	0:fac0542384d7	671
allonq	0:fac0542384d7	672	/*!
allonq	0:fac0542384d7	673	* @}
allonq	0:fac0542384d7	674	/ / end of group DMA_Register_Masks */
allonq	0:fac0542384d7	675
allonq	0:fac0542384d7	676
allonq	0:fac0542384d7	677	/* DMA - Peripheral instance base addresses */
allonq	0:fac0542384d7	678	/** Peripheral DMA base address */
allonq	0:fac0542384d7	679	#define DMA_BASE (0x40008000u)
allonq	0:fac0542384d7	680	/** Peripheral DMA base pointer */
allonq	0:fac0542384d7	681	#define DMA0 ((DMA_Type *)DMA_BASE)
allonq	0:fac0542384d7	682	/** Array initializer of DMA peripheral base pointers */
allonq	0:fac0542384d7	683	#define DMA_BASES { DMA0 }
allonq	0:fac0542384d7	684
allonq	0:fac0542384d7	685	/*!
allonq	0:fac0542384d7	686	* @}
allonq	0:fac0542384d7	687	/ / end of group DMA_Peripheral_Access_Layer */
allonq	0:fac0542384d7	688
allonq	0:fac0542384d7	689
allonq	0:fac0542384d7	690	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	691	-- DMAMUX Peripheral Access Layer
allonq	0:fac0542384d7	692	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	693
allonq	0:fac0542384d7	694	/*!
allonq	0:fac0542384d7	695	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
allonq	0:fac0542384d7	696	* @{
allonq	0:fac0542384d7	697	*/
allonq	0:fac0542384d7	698
allonq	0:fac0542384d7	699	/** DMAMUX - Register Layout Typedef */
allonq	0:fac0542384d7	700	typedef struct {
allonq	0:fac0542384d7	701	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
allonq	0:fac0542384d7	702	} DMAMUX_Type;
allonq	0:fac0542384d7	703
allonq	0:fac0542384d7	704	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	705	-- DMAMUX Register Masks
allonq	0:fac0542384d7	706	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	707
allonq	0:fac0542384d7	708	/*!
allonq	0:fac0542384d7	709	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
allonq	0:fac0542384d7	710	* @{
allonq	0:fac0542384d7	711	*/
allonq	0:fac0542384d7	712
allonq	0:fac0542384d7	713	/* CHCFG Bit Fields */
allonq	0:fac0542384d7	714	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
allonq	0:fac0542384d7	715	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
allonq	0:fac0542384d7	716	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
allonq	0:fac0542384d7	717	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
allonq	0:fac0542384d7	718	#define DMAMUX_CHCFG_TRIG_SHIFT 6
allonq	0:fac0542384d7	719	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
allonq	0:fac0542384d7	720	#define DMAMUX_CHCFG_ENBL_SHIFT 7
allonq	0:fac0542384d7	721
allonq	0:fac0542384d7	722	/*!
allonq	0:fac0542384d7	723	* @}
allonq	0:fac0542384d7	724	/ / end of group DMAMUX_Register_Masks */
allonq	0:fac0542384d7	725
allonq	0:fac0542384d7	726
allonq	0:fac0542384d7	727	/* DMAMUX - Peripheral instance base addresses */
allonq	0:fac0542384d7	728	/** Peripheral DMAMUX0 base address */
allonq	0:fac0542384d7	729	#define DMAMUX0_BASE (0x40021000u)
allonq	0:fac0542384d7	730	/** Peripheral DMAMUX0 base pointer */
allonq	0:fac0542384d7	731	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
allonq	0:fac0542384d7	732	/** Array initializer of DMAMUX peripheral base pointers */
allonq	0:fac0542384d7	733	#define DMAMUX_BASES { DMAMUX0 }
allonq	0:fac0542384d7	734
allonq	0:fac0542384d7	735	/*!
allonq	0:fac0542384d7	736	* @}
allonq	0:fac0542384d7	737	/ / end of group DMAMUX_Peripheral_Access_Layer */
allonq	0:fac0542384d7	738
allonq	0:fac0542384d7	739
allonq	0:fac0542384d7	740	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	741	-- FGPIO Peripheral Access Layer
allonq	0:fac0542384d7	742	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	743
allonq	0:fac0542384d7	744	/*!
allonq	0:fac0542384d7	745	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
allonq	0:fac0542384d7	746	* @{
allonq	0:fac0542384d7	747	*/
allonq	0:fac0542384d7	748
allonq	0:fac0542384d7	749	/** FGPIO - Register Layout Typedef */
allonq	0:fac0542384d7	750	typedef struct {
allonq	0:fac0542384d7	751	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
allonq	0:fac0542384d7	752	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
allonq	0:fac0542384d7	753	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
allonq	0:fac0542384d7	754	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
allonq	0:fac0542384d7	755	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
allonq	0:fac0542384d7	756	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
allonq	0:fac0542384d7	757	} FGPIO_Type;
allonq	0:fac0542384d7	758
allonq	0:fac0542384d7	759	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	760	-- FGPIO Register Masks
allonq	0:fac0542384d7	761	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	762
allonq	0:fac0542384d7	763	/*!
allonq	0:fac0542384d7	764	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
allonq	0:fac0542384d7	765	* @{
allonq	0:fac0542384d7	766	*/
allonq	0:fac0542384d7	767
allonq	0:fac0542384d7	768	/* PDOR Bit Fields */
allonq	0:fac0542384d7	769	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	770	#define FGPIO_PDOR_PDO_SHIFT 0
allonq	0:fac0542384d7	771	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
allonq	0:fac0542384d7	772	/* PSOR Bit Fields */
allonq	0:fac0542384d7	773	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	774	#define FGPIO_PSOR_PTSO_SHIFT 0
allonq	0:fac0542384d7	775	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
allonq	0:fac0542384d7	776	/* PCOR Bit Fields */
allonq	0:fac0542384d7	777	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	778	#define FGPIO_PCOR_PTCO_SHIFT 0
allonq	0:fac0542384d7	779	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
allonq	0:fac0542384d7	780	/* PTOR Bit Fields */
allonq	0:fac0542384d7	781	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	782	#define FGPIO_PTOR_PTTO_SHIFT 0
allonq	0:fac0542384d7	783	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
allonq	0:fac0542384d7	784	/* PDIR Bit Fields */
allonq	0:fac0542384d7	785	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	786	#define FGPIO_PDIR_PDI_SHIFT 0
allonq	0:fac0542384d7	787	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
allonq	0:fac0542384d7	788	/* PDDR Bit Fields */
allonq	0:fac0542384d7	789	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	790	#define FGPIO_PDDR_PDD_SHIFT 0
allonq	0:fac0542384d7	791	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
allonq	0:fac0542384d7	792
allonq	0:fac0542384d7	793	/*!
allonq	0:fac0542384d7	794	* @}
allonq	0:fac0542384d7	795	/ / end of group FGPIO_Register_Masks */
allonq	0:fac0542384d7	796
allonq	0:fac0542384d7	797
allonq	0:fac0542384d7	798	/* FGPIO - Peripheral instance base addresses */
allonq	0:fac0542384d7	799	/** Peripheral FPTA base address */
allonq	0:fac0542384d7	800	#define FPTA_BASE (0xF80FF000u)
allonq	0:fac0542384d7	801	/** Peripheral FPTA base pointer */
allonq	0:fac0542384d7	802	#define FPTA ((FGPIO_Type *)FPTA_BASE)
allonq	0:fac0542384d7	803	/** Peripheral FPTB base address */
allonq	0:fac0542384d7	804	#define FPTB_BASE (0xF80FF040u)
allonq	0:fac0542384d7	805	/** Peripheral FPTB base pointer */
allonq	0:fac0542384d7	806	#define FPTB ((FGPIO_Type *)FPTB_BASE)
allonq	0:fac0542384d7	807	/** Peripheral FPTC base address */
allonq	0:fac0542384d7	808	#define FPTC_BASE (0xF80FF080u)
allonq	0:fac0542384d7	809	/** Peripheral FPTC base pointer */
allonq	0:fac0542384d7	810	#define FPTC ((FGPIO_Type *)FPTC_BASE)
allonq	0:fac0542384d7	811	/** Peripheral FPTD base address */
allonq	0:fac0542384d7	812	#define FPTD_BASE (0xF80FF0C0u)
allonq	0:fac0542384d7	813	/** Peripheral FPTD base pointer */
allonq	0:fac0542384d7	814	#define FPTD ((FGPIO_Type *)FPTD_BASE)
allonq	0:fac0542384d7	815	/** Peripheral FPTE base address */
allonq	0:fac0542384d7	816	#define FPTE_BASE (0xF80FF100u)
allonq	0:fac0542384d7	817	/** Peripheral FPTE base pointer */
allonq	0:fac0542384d7	818	#define FPTE ((FGPIO_Type *)FPTE_BASE)
allonq	0:fac0542384d7	819	/** Array initializer of FGPIO peripheral base pointers */
allonq	0:fac0542384d7	820	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
allonq	0:fac0542384d7	821
allonq	0:fac0542384d7	822	/*!
allonq	0:fac0542384d7	823	* @}
allonq	0:fac0542384d7	824	/ / end of group FGPIO_Peripheral_Access_Layer */
allonq	0:fac0542384d7	825
allonq	0:fac0542384d7	826
allonq	0:fac0542384d7	827	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	828	-- FTFA Peripheral Access Layer
allonq	0:fac0542384d7	829	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	830
allonq	0:fac0542384d7	831	/*!
allonq	0:fac0542384d7	832	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
allonq	0:fac0542384d7	833	* @{
allonq	0:fac0542384d7	834	*/
allonq	0:fac0542384d7	835
allonq	0:fac0542384d7	836	/** FTFA - Register Layout Typedef */
allonq	0:fac0542384d7	837	typedef struct {
allonq	0:fac0542384d7	838	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
allonq	0:fac0542384d7	839	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
allonq	0:fac0542384d7	840	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
allonq	0:fac0542384d7	841	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
allonq	0:fac0542384d7	842	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
allonq	0:fac0542384d7	843	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
allonq	0:fac0542384d7	844	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
allonq	0:fac0542384d7	845	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
allonq	0:fac0542384d7	846	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
allonq	0:fac0542384d7	847	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
allonq	0:fac0542384d7	848	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
allonq	0:fac0542384d7	849	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
allonq	0:fac0542384d7	850	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
allonq	0:fac0542384d7	851	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
allonq	0:fac0542384d7	852	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
allonq	0:fac0542384d7	853	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
allonq	0:fac0542384d7	854	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
allonq	0:fac0542384d7	855	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
allonq	0:fac0542384d7	856	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
allonq	0:fac0542384d7	857	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
allonq	0:fac0542384d7	858	} FTFA_Type;
allonq	0:fac0542384d7	859
allonq	0:fac0542384d7	860	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	861	-- FTFA Register Masks
allonq	0:fac0542384d7	862	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	863
allonq	0:fac0542384d7	864	/*!
allonq	0:fac0542384d7	865	* @addtogroup FTFA_Register_Masks FTFA Register Masks
allonq	0:fac0542384d7	866	* @{
allonq	0:fac0542384d7	867	*/
allonq	0:fac0542384d7	868
allonq	0:fac0542384d7	869	/* FSTAT Bit Fields */
allonq	0:fac0542384d7	870	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
allonq	0:fac0542384d7	871	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
allonq	0:fac0542384d7	872	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
allonq	0:fac0542384d7	873	#define FTFA_FSTAT_FPVIOL_SHIFT 4
allonq	0:fac0542384d7	874	#define FTFA_FSTAT_ACCERR_MASK 0x20u
allonq	0:fac0542384d7	875	#define FTFA_FSTAT_ACCERR_SHIFT 5
allonq	0:fac0542384d7	876	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
allonq	0:fac0542384d7	877	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
allonq	0:fac0542384d7	878	#define FTFA_FSTAT_CCIF_MASK 0x80u
allonq	0:fac0542384d7	879	#define FTFA_FSTAT_CCIF_SHIFT 7
allonq	0:fac0542384d7	880	/* FCNFG Bit Fields */
allonq	0:fac0542384d7	881	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
allonq	0:fac0542384d7	882	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
allonq	0:fac0542384d7	883	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
allonq	0:fac0542384d7	884	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
allonq	0:fac0542384d7	885	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
allonq	0:fac0542384d7	886	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
allonq	0:fac0542384d7	887	#define FTFA_FCNFG_CCIE_MASK 0x80u
allonq	0:fac0542384d7	888	#define FTFA_FCNFG_CCIE_SHIFT 7
allonq	0:fac0542384d7	889	/* FSEC Bit Fields */
allonq	0:fac0542384d7	890	#define FTFA_FSEC_SEC_MASK 0x3u
allonq	0:fac0542384d7	891	#define FTFA_FSEC_SEC_SHIFT 0
allonq	0:fac0542384d7	892	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
allonq	0:fac0542384d7	893	#define FTFA_FSEC_FSLACC_MASK 0xCu
allonq	0:fac0542384d7	894	#define FTFA_FSEC_FSLACC_SHIFT 2
allonq	0:fac0542384d7	895	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
allonq	0:fac0542384d7	896	#define FTFA_FSEC_MEEN_MASK 0x30u
allonq	0:fac0542384d7	897	#define FTFA_FSEC_MEEN_SHIFT 4
allonq	0:fac0542384d7	898	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
allonq	0:fac0542384d7	899	#define FTFA_FSEC_KEYEN_MASK 0xC0u
allonq	0:fac0542384d7	900	#define FTFA_FSEC_KEYEN_SHIFT 6
allonq	0:fac0542384d7	901	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
allonq	0:fac0542384d7	902	/* FOPT Bit Fields */
allonq	0:fac0542384d7	903	#define FTFA_FOPT_OPT_MASK 0xFFu
allonq	0:fac0542384d7	904	#define FTFA_FOPT_OPT_SHIFT 0
allonq	0:fac0542384d7	905	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
allonq	0:fac0542384d7	906	/* FCCOB3 Bit Fields */
allonq	0:fac0542384d7	907	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	908	#define FTFA_FCCOB3_CCOBn_SHIFT 0
allonq	0:fac0542384d7	909	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
allonq	0:fac0542384d7	910	/* FCCOB2 Bit Fields */
allonq	0:fac0542384d7	911	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	912	#define FTFA_FCCOB2_CCOBn_SHIFT 0
allonq	0:fac0542384d7	913	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
allonq	0:fac0542384d7	914	/* FCCOB1 Bit Fields */
allonq	0:fac0542384d7	915	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	916	#define FTFA_FCCOB1_CCOBn_SHIFT 0
allonq	0:fac0542384d7	917	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
allonq	0:fac0542384d7	918	/* FCCOB0 Bit Fields */
allonq	0:fac0542384d7	919	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	920	#define FTFA_FCCOB0_CCOBn_SHIFT 0
allonq	0:fac0542384d7	921	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
allonq	0:fac0542384d7	922	/* FCCOB7 Bit Fields */
allonq	0:fac0542384d7	923	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	924	#define FTFA_FCCOB7_CCOBn_SHIFT 0
allonq	0:fac0542384d7	925	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
allonq	0:fac0542384d7	926	/* FCCOB6 Bit Fields */
allonq	0:fac0542384d7	927	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	928	#define FTFA_FCCOB6_CCOBn_SHIFT 0
allonq	0:fac0542384d7	929	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
allonq	0:fac0542384d7	930	/* FCCOB5 Bit Fields */
allonq	0:fac0542384d7	931	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	932	#define FTFA_FCCOB5_CCOBn_SHIFT 0
allonq	0:fac0542384d7	933	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
allonq	0:fac0542384d7	934	/* FCCOB4 Bit Fields */
allonq	0:fac0542384d7	935	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	936	#define FTFA_FCCOB4_CCOBn_SHIFT 0
allonq	0:fac0542384d7	937	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
allonq	0:fac0542384d7	938	/* FCCOBB Bit Fields */
allonq	0:fac0542384d7	939	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	940	#define FTFA_FCCOBB_CCOBn_SHIFT 0
allonq	0:fac0542384d7	941	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
allonq	0:fac0542384d7	942	/* FCCOBA Bit Fields */
allonq	0:fac0542384d7	943	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	944	#define FTFA_FCCOBA_CCOBn_SHIFT 0
allonq	0:fac0542384d7	945	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
allonq	0:fac0542384d7	946	/* FCCOB9 Bit Fields */
allonq	0:fac0542384d7	947	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	948	#define FTFA_FCCOB9_CCOBn_SHIFT 0
allonq	0:fac0542384d7	949	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
allonq	0:fac0542384d7	950	/* FCCOB8 Bit Fields */
allonq	0:fac0542384d7	951	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
allonq	0:fac0542384d7	952	#define FTFA_FCCOB8_CCOBn_SHIFT 0
allonq	0:fac0542384d7	953	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
allonq	0:fac0542384d7	954	/* FPROT3 Bit Fields */
allonq	0:fac0542384d7	955	#define FTFA_FPROT3_PROT_MASK 0xFFu
allonq	0:fac0542384d7	956	#define FTFA_FPROT3_PROT_SHIFT 0
allonq	0:fac0542384d7	957	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
allonq	0:fac0542384d7	958	/* FPROT2 Bit Fields */
allonq	0:fac0542384d7	959	#define FTFA_FPROT2_PROT_MASK 0xFFu
allonq	0:fac0542384d7	960	#define FTFA_FPROT2_PROT_SHIFT 0
allonq	0:fac0542384d7	961	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
allonq	0:fac0542384d7	962	/* FPROT1 Bit Fields */
allonq	0:fac0542384d7	963	#define FTFA_FPROT1_PROT_MASK 0xFFu
allonq	0:fac0542384d7	964	#define FTFA_FPROT1_PROT_SHIFT 0
allonq	0:fac0542384d7	965	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
allonq	0:fac0542384d7	966	/* FPROT0 Bit Fields */
allonq	0:fac0542384d7	967	#define FTFA_FPROT0_PROT_MASK 0xFFu
allonq	0:fac0542384d7	968	#define FTFA_FPROT0_PROT_SHIFT 0
allonq	0:fac0542384d7	969	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
allonq	0:fac0542384d7	970
allonq	0:fac0542384d7	971	/*!
allonq	0:fac0542384d7	972	* @}
allonq	0:fac0542384d7	973	/ / end of group FTFA_Register_Masks */
allonq	0:fac0542384d7	974
allonq	0:fac0542384d7	975
allonq	0:fac0542384d7	976	/* FTFA - Peripheral instance base addresses */
allonq	0:fac0542384d7	977	/** Peripheral FTFA base address */
allonq	0:fac0542384d7	978	#define FTFA_BASE (0x40020000u)
allonq	0:fac0542384d7	979	/** Peripheral FTFA base pointer */
allonq	0:fac0542384d7	980	#define FTFA ((FTFA_Type *)FTFA_BASE)
allonq	0:fac0542384d7	981	/** Array initializer of FTFA peripheral base pointers */
allonq	0:fac0542384d7	982	#define FTFA_BASES { FTFA }
allonq	0:fac0542384d7	983
allonq	0:fac0542384d7	984	/*!
allonq	0:fac0542384d7	985	* @}
allonq	0:fac0542384d7	986	/ / end of group FTFA_Peripheral_Access_Layer */
allonq	0:fac0542384d7	987
allonq	0:fac0542384d7	988
allonq	0:fac0542384d7	989	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	990	-- GPIO Peripheral Access Layer
allonq	0:fac0542384d7	991	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	992
allonq	0:fac0542384d7	993	/*!
allonq	0:fac0542384d7	994	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
allonq	0:fac0542384d7	995	* @{
allonq	0:fac0542384d7	996	*/
allonq	0:fac0542384d7	997
allonq	0:fac0542384d7	998	/** GPIO - Register Layout Typedef */
allonq	0:fac0542384d7	999	typedef struct {
allonq	0:fac0542384d7	1000	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
allonq	0:fac0542384d7	1001	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
allonq	0:fac0542384d7	1002	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
allonq	0:fac0542384d7	1003	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
allonq	0:fac0542384d7	1004	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
allonq	0:fac0542384d7	1005	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
allonq	0:fac0542384d7	1006	} GPIO_Type;
allonq	0:fac0542384d7	1007
allonq	0:fac0542384d7	1008	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1009	-- GPIO Register Masks
allonq	0:fac0542384d7	1010	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1011
allonq	0:fac0542384d7	1012	/*!
allonq	0:fac0542384d7	1013	* @addtogroup GPIO_Register_Masks GPIO Register Masks
allonq	0:fac0542384d7	1014	* @{
allonq	0:fac0542384d7	1015	*/
allonq	0:fac0542384d7	1016
allonq	0:fac0542384d7	1017	/* PDOR Bit Fields */
allonq	0:fac0542384d7	1018	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1019	#define GPIO_PDOR_PDO_SHIFT 0
allonq	0:fac0542384d7	1020	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
allonq	0:fac0542384d7	1021	/* PSOR Bit Fields */
allonq	0:fac0542384d7	1022	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1023	#define GPIO_PSOR_PTSO_SHIFT 0
allonq	0:fac0542384d7	1024	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
allonq	0:fac0542384d7	1025	/* PCOR Bit Fields */
allonq	0:fac0542384d7	1026	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1027	#define GPIO_PCOR_PTCO_SHIFT 0
allonq	0:fac0542384d7	1028	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
allonq	0:fac0542384d7	1029	/* PTOR Bit Fields */
allonq	0:fac0542384d7	1030	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1031	#define GPIO_PTOR_PTTO_SHIFT 0
allonq	0:fac0542384d7	1032	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
allonq	0:fac0542384d7	1033	/* PDIR Bit Fields */
allonq	0:fac0542384d7	1034	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1035	#define GPIO_PDIR_PDI_SHIFT 0
allonq	0:fac0542384d7	1036	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
allonq	0:fac0542384d7	1037	/* PDDR Bit Fields */
allonq	0:fac0542384d7	1038	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1039	#define GPIO_PDDR_PDD_SHIFT 0
allonq	0:fac0542384d7	1040	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
allonq	0:fac0542384d7	1041
allonq	0:fac0542384d7	1042	/*!
allonq	0:fac0542384d7	1043	* @}
allonq	0:fac0542384d7	1044	/ / end of group GPIO_Register_Masks */
allonq	0:fac0542384d7	1045
allonq	0:fac0542384d7	1046
allonq	0:fac0542384d7	1047	/* GPIO - Peripheral instance base addresses */
allonq	0:fac0542384d7	1048	/** Peripheral PTA base address */
allonq	0:fac0542384d7	1049	#define PTA_BASE (0x400FF000u)
allonq	0:fac0542384d7	1050	/** Peripheral PTA base pointer */
allonq	0:fac0542384d7	1051	#define PTA ((GPIO_Type *)PTA_BASE)
allonq	0:fac0542384d7	1052	/** Peripheral PTB base address */
allonq	0:fac0542384d7	1053	#define PTB_BASE (0x400FF040u)
allonq	0:fac0542384d7	1054	/** Peripheral PTB base pointer */
allonq	0:fac0542384d7	1055	#define PTB ((GPIO_Type *)PTB_BASE)
allonq	0:fac0542384d7	1056	/** Peripheral PTC base address */
allonq	0:fac0542384d7	1057	#define PTC_BASE (0x400FF080u)
allonq	0:fac0542384d7	1058	/** Peripheral PTC base pointer */
allonq	0:fac0542384d7	1059	#define PTC ((GPIO_Type *)PTC_BASE)
allonq	0:fac0542384d7	1060	/** Peripheral PTD base address */
allonq	0:fac0542384d7	1061	#define PTD_BASE (0x400FF0C0u)
allonq	0:fac0542384d7	1062	/** Peripheral PTD base pointer */
allonq	0:fac0542384d7	1063	#define PTD ((GPIO_Type *)PTD_BASE)
allonq	0:fac0542384d7	1064	/** Peripheral PTE base address */
allonq	0:fac0542384d7	1065	#define PTE_BASE (0x400FF100u)
allonq	0:fac0542384d7	1066	/** Peripheral PTE base pointer */
allonq	0:fac0542384d7	1067	#define PTE ((GPIO_Type *)PTE_BASE)
allonq	0:fac0542384d7	1068	/** Array initializer of GPIO peripheral base pointers */
allonq	0:fac0542384d7	1069	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
allonq	0:fac0542384d7	1070
allonq	0:fac0542384d7	1071	/*!
allonq	0:fac0542384d7	1072	* @}
allonq	0:fac0542384d7	1073	/ / end of group GPIO_Peripheral_Access_Layer */
allonq	0:fac0542384d7	1074
allonq	0:fac0542384d7	1075
allonq	0:fac0542384d7	1076	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1077	-- I2C Peripheral Access Layer
allonq	0:fac0542384d7	1078	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1079
allonq	0:fac0542384d7	1080	/*!
allonq	0:fac0542384d7	1081	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
allonq	0:fac0542384d7	1082	* @{
allonq	0:fac0542384d7	1083	*/
allonq	0:fac0542384d7	1084
allonq	0:fac0542384d7	1085	/** I2C - Register Layout Typedef */
allonq	0:fac0542384d7	1086	typedef struct {
allonq	0:fac0542384d7	1087	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
allonq	0:fac0542384d7	1088	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
allonq	0:fac0542384d7	1089	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
allonq	0:fac0542384d7	1090	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
allonq	0:fac0542384d7	1091	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
allonq	0:fac0542384d7	1092	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
allonq	0:fac0542384d7	1093	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
allonq	0:fac0542384d7	1094	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
allonq	0:fac0542384d7	1095	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
allonq	0:fac0542384d7	1096	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
allonq	0:fac0542384d7	1097	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
allonq	0:fac0542384d7	1098	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
allonq	0:fac0542384d7	1099	} I2C_Type;
allonq	0:fac0542384d7	1100
allonq	0:fac0542384d7	1101	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1102	-- I2C Register Masks
allonq	0:fac0542384d7	1103	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1104
allonq	0:fac0542384d7	1105	/*!
allonq	0:fac0542384d7	1106	* @addtogroup I2C_Register_Masks I2C Register Masks
allonq	0:fac0542384d7	1107	* @{
allonq	0:fac0542384d7	1108	*/
allonq	0:fac0542384d7	1109
allonq	0:fac0542384d7	1110	/* A1 Bit Fields */
allonq	0:fac0542384d7	1111	#define I2C_A1_AD_MASK 0xFEu
allonq	0:fac0542384d7	1112	#define I2C_A1_AD_SHIFT 1
allonq	0:fac0542384d7	1113	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
allonq	0:fac0542384d7	1114	/* F Bit Fields */
allonq	0:fac0542384d7	1115	#define I2C_F_ICR_MASK 0x3Fu
allonq	0:fac0542384d7	1116	#define I2C_F_ICR_SHIFT 0
allonq	0:fac0542384d7	1117	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
allonq	0:fac0542384d7	1118	#define I2C_F_MULT_MASK 0xC0u
allonq	0:fac0542384d7	1119	#define I2C_F_MULT_SHIFT 6
allonq	0:fac0542384d7	1120	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
allonq	0:fac0542384d7	1121	/* C1 Bit Fields */
allonq	0:fac0542384d7	1122	#define I2C_C1_DMAEN_MASK 0x1u
allonq	0:fac0542384d7	1123	#define I2C_C1_DMAEN_SHIFT 0
allonq	0:fac0542384d7	1124	#define I2C_C1_WUEN_MASK 0x2u
allonq	0:fac0542384d7	1125	#define I2C_C1_WUEN_SHIFT 1
allonq	0:fac0542384d7	1126	#define I2C_C1_RSTA_MASK 0x4u
allonq	0:fac0542384d7	1127	#define I2C_C1_RSTA_SHIFT 2
allonq	0:fac0542384d7	1128	#define I2C_C1_TXAK_MASK 0x8u
allonq	0:fac0542384d7	1129	#define I2C_C1_TXAK_SHIFT 3
allonq	0:fac0542384d7	1130	#define I2C_C1_TX_MASK 0x10u
allonq	0:fac0542384d7	1131	#define I2C_C1_TX_SHIFT 4
allonq	0:fac0542384d7	1132	#define I2C_C1_MST_MASK 0x20u
allonq	0:fac0542384d7	1133	#define I2C_C1_MST_SHIFT 5
allonq	0:fac0542384d7	1134	#define I2C_C1_IICIE_MASK 0x40u
allonq	0:fac0542384d7	1135	#define I2C_C1_IICIE_SHIFT 6
allonq	0:fac0542384d7	1136	#define I2C_C1_IICEN_MASK 0x80u
allonq	0:fac0542384d7	1137	#define I2C_C1_IICEN_SHIFT 7
allonq	0:fac0542384d7	1138	/* S Bit Fields */
allonq	0:fac0542384d7	1139	#define I2C_S_RXAK_MASK 0x1u
allonq	0:fac0542384d7	1140	#define I2C_S_RXAK_SHIFT 0
allonq	0:fac0542384d7	1141	#define I2C_S_IICIF_MASK 0x2u
allonq	0:fac0542384d7	1142	#define I2C_S_IICIF_SHIFT 1
allonq	0:fac0542384d7	1143	#define I2C_S_SRW_MASK 0x4u
allonq	0:fac0542384d7	1144	#define I2C_S_SRW_SHIFT 2
allonq	0:fac0542384d7	1145	#define I2C_S_RAM_MASK 0x8u
allonq	0:fac0542384d7	1146	#define I2C_S_RAM_SHIFT 3
allonq	0:fac0542384d7	1147	#define I2C_S_ARBL_MASK 0x10u
allonq	0:fac0542384d7	1148	#define I2C_S_ARBL_SHIFT 4
allonq	0:fac0542384d7	1149	#define I2C_S_BUSY_MASK 0x20u
allonq	0:fac0542384d7	1150	#define I2C_S_BUSY_SHIFT 5
allonq	0:fac0542384d7	1151	#define I2C_S_IAAS_MASK 0x40u
allonq	0:fac0542384d7	1152	#define I2C_S_IAAS_SHIFT 6
allonq	0:fac0542384d7	1153	#define I2C_S_TCF_MASK 0x80u
allonq	0:fac0542384d7	1154	#define I2C_S_TCF_SHIFT 7
allonq	0:fac0542384d7	1155	/* D Bit Fields */
allonq	0:fac0542384d7	1156	#define I2C_D_DATA_MASK 0xFFu
allonq	0:fac0542384d7	1157	#define I2C_D_DATA_SHIFT 0
allonq	0:fac0542384d7	1158	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
allonq	0:fac0542384d7	1159	/* C2 Bit Fields */
allonq	0:fac0542384d7	1160	#define I2C_C2_AD_MASK 0x7u
allonq	0:fac0542384d7	1161	#define I2C_C2_AD_SHIFT 0
allonq	0:fac0542384d7	1162	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
allonq	0:fac0542384d7	1163	#define I2C_C2_RMEN_MASK 0x8u
allonq	0:fac0542384d7	1164	#define I2C_C2_RMEN_SHIFT 3
allonq	0:fac0542384d7	1165	#define I2C_C2_SBRC_MASK 0x10u
allonq	0:fac0542384d7	1166	#define I2C_C2_SBRC_SHIFT 4
allonq	0:fac0542384d7	1167	#define I2C_C2_HDRS_MASK 0x20u
allonq	0:fac0542384d7	1168	#define I2C_C2_HDRS_SHIFT 5
allonq	0:fac0542384d7	1169	#define I2C_C2_ADEXT_MASK 0x40u
allonq	0:fac0542384d7	1170	#define I2C_C2_ADEXT_SHIFT 6
allonq	0:fac0542384d7	1171	#define I2C_C2_GCAEN_MASK 0x80u
allonq	0:fac0542384d7	1172	#define I2C_C2_GCAEN_SHIFT 7
allonq	0:fac0542384d7	1173	/* FLT Bit Fields */
allonq	0:fac0542384d7	1174	#define I2C_FLT_FLT_MASK 0x1Fu
allonq	0:fac0542384d7	1175	#define I2C_FLT_FLT_SHIFT 0
allonq	0:fac0542384d7	1176	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
allonq	0:fac0542384d7	1177	#define I2C_FLT_STOPIE_MASK 0x20u
allonq	0:fac0542384d7	1178	#define I2C_FLT_STOPIE_SHIFT 5
allonq	0:fac0542384d7	1179	#define I2C_FLT_STOPF_MASK 0x40u
allonq	0:fac0542384d7	1180	#define I2C_FLT_STOPF_SHIFT 6
allonq	0:fac0542384d7	1181	#define I2C_FLT_SHEN_MASK 0x80u
allonq	0:fac0542384d7	1182	#define I2C_FLT_SHEN_SHIFT 7
allonq	0:fac0542384d7	1183	/* RA Bit Fields */
allonq	0:fac0542384d7	1184	#define I2C_RA_RAD_MASK 0xFEu
allonq	0:fac0542384d7	1185	#define I2C_RA_RAD_SHIFT 1
allonq	0:fac0542384d7	1186	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
allonq	0:fac0542384d7	1187	/* SMB Bit Fields */
allonq	0:fac0542384d7	1188	#define I2C_SMB_SHTF2IE_MASK 0x1u
allonq	0:fac0542384d7	1189	#define I2C_SMB_SHTF2IE_SHIFT 0
allonq	0:fac0542384d7	1190	#define I2C_SMB_SHTF2_MASK 0x2u
allonq	0:fac0542384d7	1191	#define I2C_SMB_SHTF2_SHIFT 1
allonq	0:fac0542384d7	1192	#define I2C_SMB_SHTF1_MASK 0x4u
allonq	0:fac0542384d7	1193	#define I2C_SMB_SHTF1_SHIFT 2
allonq	0:fac0542384d7	1194	#define I2C_SMB_SLTF_MASK 0x8u
allonq	0:fac0542384d7	1195	#define I2C_SMB_SLTF_SHIFT 3
allonq	0:fac0542384d7	1196	#define I2C_SMB_TCKSEL_MASK 0x10u
allonq	0:fac0542384d7	1197	#define I2C_SMB_TCKSEL_SHIFT 4
allonq	0:fac0542384d7	1198	#define I2C_SMB_SIICAEN_MASK 0x20u
allonq	0:fac0542384d7	1199	#define I2C_SMB_SIICAEN_SHIFT 5
allonq	0:fac0542384d7	1200	#define I2C_SMB_ALERTEN_MASK 0x40u
allonq	0:fac0542384d7	1201	#define I2C_SMB_ALERTEN_SHIFT 6
allonq	0:fac0542384d7	1202	#define I2C_SMB_FACK_MASK 0x80u
allonq	0:fac0542384d7	1203	#define I2C_SMB_FACK_SHIFT 7
allonq	0:fac0542384d7	1204	/* A2 Bit Fields */
allonq	0:fac0542384d7	1205	#define I2C_A2_SAD_MASK 0xFEu
allonq	0:fac0542384d7	1206	#define I2C_A2_SAD_SHIFT 1
allonq	0:fac0542384d7	1207	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
allonq	0:fac0542384d7	1208	/* SLTH Bit Fields */
allonq	0:fac0542384d7	1209	#define I2C_SLTH_SSLT_MASK 0xFFu
allonq	0:fac0542384d7	1210	#define I2C_SLTH_SSLT_SHIFT 0
allonq	0:fac0542384d7	1211	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
allonq	0:fac0542384d7	1212	/* SLTL Bit Fields */
allonq	0:fac0542384d7	1213	#define I2C_SLTL_SSLT_MASK 0xFFu
allonq	0:fac0542384d7	1214	#define I2C_SLTL_SSLT_SHIFT 0
allonq	0:fac0542384d7	1215	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
allonq	0:fac0542384d7	1216
allonq	0:fac0542384d7	1217	/*!
allonq	0:fac0542384d7	1218	* @}
allonq	0:fac0542384d7	1219	/ / end of group I2C_Register_Masks */
allonq	0:fac0542384d7	1220
allonq	0:fac0542384d7	1221
allonq	0:fac0542384d7	1222	/* I2C - Peripheral instance base addresses */
allonq	0:fac0542384d7	1223	/** Peripheral I2C0 base address */
allonq	0:fac0542384d7	1224	#define I2C0_BASE (0x40066000u)
allonq	0:fac0542384d7	1225	/** Peripheral I2C0 base pointer */
allonq	0:fac0542384d7	1226	#define I2C0 ((I2C_Type *)I2C0_BASE)
allonq	0:fac0542384d7	1227	/** Peripheral I2C1 base address */
allonq	0:fac0542384d7	1228	#define I2C1_BASE (0x40067000u)
allonq	0:fac0542384d7	1229	/** Peripheral I2C1 base pointer */
allonq	0:fac0542384d7	1230	#define I2C1 ((I2C_Type *)I2C1_BASE)
allonq	0:fac0542384d7	1231	/** Array initializer of I2C peripheral base pointers */
allonq	0:fac0542384d7	1232	#define I2C_BASES { I2C0, I2C1 }
allonq	0:fac0542384d7	1233
allonq	0:fac0542384d7	1234	/*!
allonq	0:fac0542384d7	1235	* @}
allonq	0:fac0542384d7	1236	/ / end of group I2C_Peripheral_Access_Layer */
allonq	0:fac0542384d7	1237
allonq	0:fac0542384d7	1238
allonq	0:fac0542384d7	1239	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1240	-- I2S Peripheral Access Layer
allonq	0:fac0542384d7	1241	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1242
allonq	0:fac0542384d7	1243	/*!
allonq	0:fac0542384d7	1244	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
allonq	0:fac0542384d7	1245	* @{
allonq	0:fac0542384d7	1246	*/
allonq	0:fac0542384d7	1247
allonq	0:fac0542384d7	1248	/** I2S - Register Layout Typedef */
allonq	0:fac0542384d7	1249	typedef struct {
allonq	0:fac0542384d7	1250	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
allonq	0:fac0542384d7	1251	uint8_t RESERVED_0[4];
allonq	0:fac0542384d7	1252	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
allonq	0:fac0542384d7	1253	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
allonq	0:fac0542384d7	1254	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
allonq	0:fac0542384d7	1255	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
allonq	0:fac0542384d7	1256	uint8_t RESERVED_1[8];
allonq	0:fac0542384d7	1257	__O uint32_t TDR[1]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
allonq	0:fac0542384d7	1258	uint8_t RESERVED_2[60];
allonq	0:fac0542384d7	1259	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
allonq	0:fac0542384d7	1260	uint8_t RESERVED_3[28];
allonq	0:fac0542384d7	1261	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
allonq	0:fac0542384d7	1262	uint8_t RESERVED_4[4];
allonq	0:fac0542384d7	1263	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
allonq	0:fac0542384d7	1264	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
allonq	0:fac0542384d7	1265	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
allonq	0:fac0542384d7	1266	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
allonq	0:fac0542384d7	1267	uint8_t RESERVED_5[8];
allonq	0:fac0542384d7	1268	__I uint32_t RDR[1]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
allonq	0:fac0542384d7	1269	uint8_t RESERVED_6[60];
allonq	0:fac0542384d7	1270	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
allonq	0:fac0542384d7	1271	uint8_t RESERVED_7[28];
allonq	0:fac0542384d7	1272	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
allonq	0:fac0542384d7	1273	__IO uint32_t MDR; /*< SAI MCLK Divide Register, offset: 0x104 /
allonq	0:fac0542384d7	1274	} I2S_Type;
allonq	0:fac0542384d7	1275
allonq	0:fac0542384d7	1276	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1277	-- I2S Register Masks
allonq	0:fac0542384d7	1278	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1279
allonq	0:fac0542384d7	1280	/*!
allonq	0:fac0542384d7	1281	* @addtogroup I2S_Register_Masks I2S Register Masks
allonq	0:fac0542384d7	1282	* @{
allonq	0:fac0542384d7	1283	*/
allonq	0:fac0542384d7	1284
allonq	0:fac0542384d7	1285	/* TCSR Bit Fields */
allonq	0:fac0542384d7	1286	#define I2S_TCSR_FWDE_MASK 0x2u
allonq	0:fac0542384d7	1287	#define I2S_TCSR_FWDE_SHIFT 1
allonq	0:fac0542384d7	1288	#define I2S_TCSR_FWIE_MASK 0x200u
allonq	0:fac0542384d7	1289	#define I2S_TCSR_FWIE_SHIFT 9
allonq	0:fac0542384d7	1290	#define I2S_TCSR_FEIE_MASK 0x400u
allonq	0:fac0542384d7	1291	#define I2S_TCSR_FEIE_SHIFT 10
allonq	0:fac0542384d7	1292	#define I2S_TCSR_SEIE_MASK 0x800u
allonq	0:fac0542384d7	1293	#define I2S_TCSR_SEIE_SHIFT 11
allonq	0:fac0542384d7	1294	#define I2S_TCSR_WSIE_MASK 0x1000u
allonq	0:fac0542384d7	1295	#define I2S_TCSR_WSIE_SHIFT 12
allonq	0:fac0542384d7	1296	#define I2S_TCSR_FWF_MASK 0x20000u
allonq	0:fac0542384d7	1297	#define I2S_TCSR_FWF_SHIFT 17
allonq	0:fac0542384d7	1298	#define I2S_TCSR_FEF_MASK 0x40000u
allonq	0:fac0542384d7	1299	#define I2S_TCSR_FEF_SHIFT 18
allonq	0:fac0542384d7	1300	#define I2S_TCSR_SEF_MASK 0x80000u
allonq	0:fac0542384d7	1301	#define I2S_TCSR_SEF_SHIFT 19
allonq	0:fac0542384d7	1302	#define I2S_TCSR_WSF_MASK 0x100000u
allonq	0:fac0542384d7	1303	#define I2S_TCSR_WSF_SHIFT 20
allonq	0:fac0542384d7	1304	#define I2S_TCSR_SR_MASK 0x1000000u
allonq	0:fac0542384d7	1305	#define I2S_TCSR_SR_SHIFT 24
allonq	0:fac0542384d7	1306	#define I2S_TCSR_FR_MASK 0x2000000u
allonq	0:fac0542384d7	1307	#define I2S_TCSR_FR_SHIFT 25
allonq	0:fac0542384d7	1308	#define I2S_TCSR_BCE_MASK 0x10000000u
allonq	0:fac0542384d7	1309	#define I2S_TCSR_BCE_SHIFT 28
allonq	0:fac0542384d7	1310	#define I2S_TCSR_DBGE_MASK 0x20000000u
allonq	0:fac0542384d7	1311	#define I2S_TCSR_DBGE_SHIFT 29
allonq	0:fac0542384d7	1312	#define I2S_TCSR_STOPE_MASK 0x40000000u
allonq	0:fac0542384d7	1313	#define I2S_TCSR_STOPE_SHIFT 30
allonq	0:fac0542384d7	1314	#define I2S_TCSR_TE_MASK 0x80000000u
allonq	0:fac0542384d7	1315	#define I2S_TCSR_TE_SHIFT 31
allonq	0:fac0542384d7	1316	/* TCR2 Bit Fields */
allonq	0:fac0542384d7	1317	#define I2S_TCR2_DIV_MASK 0xFFu
allonq	0:fac0542384d7	1318	#define I2S_TCR2_DIV_SHIFT 0
allonq	0:fac0542384d7	1319	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
allonq	0:fac0542384d7	1320	#define I2S_TCR2_BCD_MASK 0x1000000u
allonq	0:fac0542384d7	1321	#define I2S_TCR2_BCD_SHIFT 24
allonq	0:fac0542384d7	1322	#define I2S_TCR2_BCP_MASK 0x2000000u
allonq	0:fac0542384d7	1323	#define I2S_TCR2_BCP_SHIFT 25
allonq	0:fac0542384d7	1324	#define I2S_TCR2_CLKMODE_MASK 0xC000000u
allonq	0:fac0542384d7	1325	#define I2S_TCR2_CLKMODE_SHIFT 26
allonq	0:fac0542384d7	1326	#define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
allonq	0:fac0542384d7	1327	/* TCR3 Bit Fields */
allonq	0:fac0542384d7	1328	#define I2S_TCR3_WDFL_MASK 0x1u
allonq	0:fac0542384d7	1329	#define I2S_TCR3_WDFL_SHIFT 0
allonq	0:fac0542384d7	1330	#define I2S_TCR3_TCE_MASK 0x10000u
allonq	0:fac0542384d7	1331	#define I2S_TCR3_TCE_SHIFT 16
allonq	0:fac0542384d7	1332	/* TCR4 Bit Fields */
allonq	0:fac0542384d7	1333	#define I2S_TCR4_FSD_MASK 0x1u
allonq	0:fac0542384d7	1334	#define I2S_TCR4_FSD_SHIFT 0
allonq	0:fac0542384d7	1335	#define I2S_TCR4_FSP_MASK 0x2u
allonq	0:fac0542384d7	1336	#define I2S_TCR4_FSP_SHIFT 1
allonq	0:fac0542384d7	1337	#define I2S_TCR4_FSE_MASK 0x8u
allonq	0:fac0542384d7	1338	#define I2S_TCR4_FSE_SHIFT 3
allonq	0:fac0542384d7	1339	#define I2S_TCR4_MF_MASK 0x10u
allonq	0:fac0542384d7	1340	#define I2S_TCR4_MF_SHIFT 4
allonq	0:fac0542384d7	1341	#define I2S_TCR4_SYWD_MASK 0x1F00u
allonq	0:fac0542384d7	1342	#define I2S_TCR4_SYWD_SHIFT 8
allonq	0:fac0542384d7	1343	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
allonq	0:fac0542384d7	1344	#define I2S_TCR4_FRSZ_MASK 0x10000u
allonq	0:fac0542384d7	1345	#define I2S_TCR4_FRSZ_SHIFT 16
allonq	0:fac0542384d7	1346	/* TCR5 Bit Fields */
allonq	0:fac0542384d7	1347	#define I2S_TCR5_FBT_MASK 0x1F00u
allonq	0:fac0542384d7	1348	#define I2S_TCR5_FBT_SHIFT 8
allonq	0:fac0542384d7	1349	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
allonq	0:fac0542384d7	1350	#define I2S_TCR5_W0W_MASK 0x1F0000u
allonq	0:fac0542384d7	1351	#define I2S_TCR5_W0W_SHIFT 16
allonq	0:fac0542384d7	1352	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
allonq	0:fac0542384d7	1353	#define I2S_TCR5_WNW_MASK 0x1F000000u
allonq	0:fac0542384d7	1354	#define I2S_TCR5_WNW_SHIFT 24
allonq	0:fac0542384d7	1355	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
allonq	0:fac0542384d7	1356	/* TDR Bit Fields */
allonq	0:fac0542384d7	1357	#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1358	#define I2S_TDR_TDR_SHIFT 0
allonq	0:fac0542384d7	1359	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
allonq	0:fac0542384d7	1360	/* TMR Bit Fields */
allonq	0:fac0542384d7	1361	#define I2S_TMR_TWM_MASK 0x3u
allonq	0:fac0542384d7	1362	#define I2S_TMR_TWM_SHIFT 0
allonq	0:fac0542384d7	1363	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
allonq	0:fac0542384d7	1364	/* RCSR Bit Fields */
allonq	0:fac0542384d7	1365	#define I2S_RCSR_FWDE_MASK 0x2u
allonq	0:fac0542384d7	1366	#define I2S_RCSR_FWDE_SHIFT 1
allonq	0:fac0542384d7	1367	#define I2S_RCSR_FWIE_MASK 0x200u
allonq	0:fac0542384d7	1368	#define I2S_RCSR_FWIE_SHIFT 9
allonq	0:fac0542384d7	1369	#define I2S_RCSR_FEIE_MASK 0x400u
allonq	0:fac0542384d7	1370	#define I2S_RCSR_FEIE_SHIFT 10
allonq	0:fac0542384d7	1371	#define I2S_RCSR_SEIE_MASK 0x800u
allonq	0:fac0542384d7	1372	#define I2S_RCSR_SEIE_SHIFT 11
allonq	0:fac0542384d7	1373	#define I2S_RCSR_WSIE_MASK 0x1000u
allonq	0:fac0542384d7	1374	#define I2S_RCSR_WSIE_SHIFT 12
allonq	0:fac0542384d7	1375	#define I2S_RCSR_FWF_MASK 0x20000u
allonq	0:fac0542384d7	1376	#define I2S_RCSR_FWF_SHIFT 17
allonq	0:fac0542384d7	1377	#define I2S_RCSR_FEF_MASK 0x40000u
allonq	0:fac0542384d7	1378	#define I2S_RCSR_FEF_SHIFT 18
allonq	0:fac0542384d7	1379	#define I2S_RCSR_SEF_MASK 0x80000u
allonq	0:fac0542384d7	1380	#define I2S_RCSR_SEF_SHIFT 19
allonq	0:fac0542384d7	1381	#define I2S_RCSR_WSF_MASK 0x100000u
allonq	0:fac0542384d7	1382	#define I2S_RCSR_WSF_SHIFT 20
allonq	0:fac0542384d7	1383	#define I2S_RCSR_SR_MASK 0x1000000u
allonq	0:fac0542384d7	1384	#define I2S_RCSR_SR_SHIFT 24
allonq	0:fac0542384d7	1385	#define I2S_RCSR_FR_MASK 0x2000000u
allonq	0:fac0542384d7	1386	#define I2S_RCSR_FR_SHIFT 25
allonq	0:fac0542384d7	1387	#define I2S_RCSR_BCE_MASK 0x10000000u
allonq	0:fac0542384d7	1388	#define I2S_RCSR_BCE_SHIFT 28
allonq	0:fac0542384d7	1389	#define I2S_RCSR_DBGE_MASK 0x20000000u
allonq	0:fac0542384d7	1390	#define I2S_RCSR_DBGE_SHIFT 29
allonq	0:fac0542384d7	1391	#define I2S_RCSR_STOPE_MASK 0x40000000u
allonq	0:fac0542384d7	1392	#define I2S_RCSR_STOPE_SHIFT 30
allonq	0:fac0542384d7	1393	#define I2S_RCSR_RE_MASK 0x80000000u
allonq	0:fac0542384d7	1394	#define I2S_RCSR_RE_SHIFT 31
allonq	0:fac0542384d7	1395	/* RCR2 Bit Fields */
allonq	0:fac0542384d7	1396	#define I2S_RCR2_DIV_MASK 0xFFu
allonq	0:fac0542384d7	1397	#define I2S_RCR2_DIV_SHIFT 0
allonq	0:fac0542384d7	1398	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
allonq	0:fac0542384d7	1399	#define I2S_RCR2_BCD_MASK 0x1000000u
allonq	0:fac0542384d7	1400	#define I2S_RCR2_BCD_SHIFT 24
allonq	0:fac0542384d7	1401	#define I2S_RCR2_BCP_MASK 0x2000000u
allonq	0:fac0542384d7	1402	#define I2S_RCR2_BCP_SHIFT 25
allonq	0:fac0542384d7	1403	#define I2S_RCR2_CLKMODE_MASK 0xC000000u
allonq	0:fac0542384d7	1404	#define I2S_RCR2_CLKMODE_SHIFT 26
allonq	0:fac0542384d7	1405	#define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
allonq	0:fac0542384d7	1406	/* RCR3 Bit Fields */
allonq	0:fac0542384d7	1407	#define I2S_RCR3_WDFL_MASK 0x1u
allonq	0:fac0542384d7	1408	#define I2S_RCR3_WDFL_SHIFT 0
allonq	0:fac0542384d7	1409	#define I2S_RCR3_RCE_MASK 0x10000u
allonq	0:fac0542384d7	1410	#define I2S_RCR3_RCE_SHIFT 16
allonq	0:fac0542384d7	1411	/* RCR4 Bit Fields */
allonq	0:fac0542384d7	1412	#define I2S_RCR4_FSD_MASK 0x1u
allonq	0:fac0542384d7	1413	#define I2S_RCR4_FSD_SHIFT 0
allonq	0:fac0542384d7	1414	#define I2S_RCR4_FSP_MASK 0x2u
allonq	0:fac0542384d7	1415	#define I2S_RCR4_FSP_SHIFT 1
allonq	0:fac0542384d7	1416	#define I2S_RCR4_FSE_MASK 0x8u
allonq	0:fac0542384d7	1417	#define I2S_RCR4_FSE_SHIFT 3
allonq	0:fac0542384d7	1418	#define I2S_RCR4_MF_MASK 0x10u
allonq	0:fac0542384d7	1419	#define I2S_RCR4_MF_SHIFT 4
allonq	0:fac0542384d7	1420	#define I2S_RCR4_SYWD_MASK 0x1F00u
allonq	0:fac0542384d7	1421	#define I2S_RCR4_SYWD_SHIFT 8
allonq	0:fac0542384d7	1422	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
allonq	0:fac0542384d7	1423	#define I2S_RCR4_FRSZ_MASK 0x10000u
allonq	0:fac0542384d7	1424	#define I2S_RCR4_FRSZ_SHIFT 16
allonq	0:fac0542384d7	1425	/* RCR5 Bit Fields */
allonq	0:fac0542384d7	1426	#define I2S_RCR5_FBT_MASK 0x1F00u
allonq	0:fac0542384d7	1427	#define I2S_RCR5_FBT_SHIFT 8
allonq	0:fac0542384d7	1428	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
allonq	0:fac0542384d7	1429	#define I2S_RCR5_W0W_MASK 0x1F0000u
allonq	0:fac0542384d7	1430	#define I2S_RCR5_W0W_SHIFT 16
allonq	0:fac0542384d7	1431	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
allonq	0:fac0542384d7	1432	#define I2S_RCR5_WNW_MASK 0x1F000000u
allonq	0:fac0542384d7	1433	#define I2S_RCR5_WNW_SHIFT 24
allonq	0:fac0542384d7	1434	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
allonq	0:fac0542384d7	1435	/* RDR Bit Fields */
allonq	0:fac0542384d7	1436	#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1437	#define I2S_RDR_RDR_SHIFT 0
allonq	0:fac0542384d7	1438	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
allonq	0:fac0542384d7	1439	/* RMR Bit Fields */
allonq	0:fac0542384d7	1440	#define I2S_RMR_RWM_MASK 0x3u
allonq	0:fac0542384d7	1441	#define I2S_RMR_RWM_SHIFT 0
allonq	0:fac0542384d7	1442	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
allonq	0:fac0542384d7	1443	/* MCR Bit Fields */
allonq	0:fac0542384d7	1444	#define I2S_MCR_MICS_MASK 0x3000000u
allonq	0:fac0542384d7	1445	#define I2S_MCR_MICS_SHIFT 24
allonq	0:fac0542384d7	1446	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
allonq	0:fac0542384d7	1447	#define I2S_MCR_MOE_MASK 0x40000000u
allonq	0:fac0542384d7	1448	#define I2S_MCR_MOE_SHIFT 30
allonq	0:fac0542384d7	1449	#define I2S_MCR_DUF_MASK 0x80000000u
allonq	0:fac0542384d7	1450	#define I2S_MCR_DUF_SHIFT 31
allonq	0:fac0542384d7	1451	/* MDR Bit Fields */
allonq	0:fac0542384d7	1452	#define I2S_MDR_DIVIDE_MASK 0xFFFu
allonq	0:fac0542384d7	1453	#define I2S_MDR_DIVIDE_SHIFT 0
allonq	0:fac0542384d7	1454	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
allonq	0:fac0542384d7	1455	#define I2S_MDR_FRACT_MASK 0xFF000u
allonq	0:fac0542384d7	1456	#define I2S_MDR_FRACT_SHIFT 12
allonq	0:fac0542384d7	1457	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
allonq	0:fac0542384d7	1458
allonq	0:fac0542384d7	1459	/*!
allonq	0:fac0542384d7	1460	* @}
allonq	0:fac0542384d7	1461	/ / end of group I2S_Register_Masks */
allonq	0:fac0542384d7	1462
allonq	0:fac0542384d7	1463
allonq	0:fac0542384d7	1464	/* I2S - Peripheral instance base addresses */
allonq	0:fac0542384d7	1465	/** Peripheral I2S0 base address */
allonq	0:fac0542384d7	1466	#define I2S0_BASE (0x4002F000u)
allonq	0:fac0542384d7	1467	/** Peripheral I2S0 base pointer */
allonq	0:fac0542384d7	1468	#define I2S0 ((I2S_Type *)I2S0_BASE)
allonq	0:fac0542384d7	1469	/** Array initializer of I2S peripheral base pointers */
allonq	0:fac0542384d7	1470	#define I2S_BASES { I2S0 }
allonq	0:fac0542384d7	1471
allonq	0:fac0542384d7	1472	/*!
allonq	0:fac0542384d7	1473	* @}
allonq	0:fac0542384d7	1474	/ / end of group I2S_Peripheral_Access_Layer */
allonq	0:fac0542384d7	1475
allonq	0:fac0542384d7	1476
allonq	0:fac0542384d7	1477	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1478	-- LCD Peripheral Access Layer
allonq	0:fac0542384d7	1479	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1480
allonq	0:fac0542384d7	1481	/*!
allonq	0:fac0542384d7	1482	* @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
allonq	0:fac0542384d7	1483	* @{
allonq	0:fac0542384d7	1484	*/
allonq	0:fac0542384d7	1485
allonq	0:fac0542384d7	1486	/** LCD - Register Layout Typedef */
allonq	0:fac0542384d7	1487	typedef struct {
allonq	0:fac0542384d7	1488	__IO uint32_t GCR; /*< LCD General Control Register, offset: 0x0 /
allonq	0:fac0542384d7	1489	__IO uint32_t AR; /*< LCD Auxiliary Register, offset: 0x4 /
allonq	0:fac0542384d7	1490	__IO uint32_t FDCR; /*< LCD Fault Detect Control Register, offset: 0x8 /
allonq	0:fac0542384d7	1491	__IO uint32_t FDSR; /*< LCD Fault Detect Status Register, offset: 0xC /
allonq	0:fac0542384d7	1492	__IO uint32_t PEN[2]; /*< LCD Pin Enable register, array offset: 0x10, array step: 0x4 /
allonq	0:fac0542384d7	1493	__IO uint32_t BPEN[2]; /*< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 /
allonq	0:fac0542384d7	1494	union { /* offset: 0x20 */
allonq	0:fac0542384d7	1495	__IO uint32_t WF[16]; /*< LCD Waveform register, array offset: 0x20, array step: 0x4 /
allonq	0:fac0542384d7	1496	__IO uint8_t WF8B[64]; /*< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 /
allonq	0:fac0542384d7	1497	};
allonq	0:fac0542384d7	1498	} LCD_Type;
allonq	0:fac0542384d7	1499
allonq	0:fac0542384d7	1500	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	1501	-- LCD Register Masks
allonq	0:fac0542384d7	1502	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	1503
allonq	0:fac0542384d7	1504	/*!
allonq	0:fac0542384d7	1505	* @addtogroup LCD_Register_Masks LCD Register Masks
allonq	0:fac0542384d7	1506	* @{
allonq	0:fac0542384d7	1507	*/
allonq	0:fac0542384d7	1508
allonq	0:fac0542384d7	1509	/* GCR Bit Fields */
allonq	0:fac0542384d7	1510	#define LCD_GCR_DUTY_MASK 0x7u
allonq	0:fac0542384d7	1511	#define LCD_GCR_DUTY_SHIFT 0
allonq	0:fac0542384d7	1512	#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
allonq	0:fac0542384d7	1513	#define LCD_GCR_LCLK_MASK 0x38u
allonq	0:fac0542384d7	1514	#define LCD_GCR_LCLK_SHIFT 3
allonq	0:fac0542384d7	1515	#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
allonq	0:fac0542384d7	1516	#define LCD_GCR_SOURCE_MASK 0x40u
allonq	0:fac0542384d7	1517	#define LCD_GCR_SOURCE_SHIFT 6
allonq	0:fac0542384d7	1518	#define LCD_GCR_LCDEN_MASK 0x80u
allonq	0:fac0542384d7	1519	#define LCD_GCR_LCDEN_SHIFT 7
allonq	0:fac0542384d7	1520	#define LCD_GCR_LCDSTP_MASK 0x100u
allonq	0:fac0542384d7	1521	#define LCD_GCR_LCDSTP_SHIFT 8
allonq	0:fac0542384d7	1522	#define LCD_GCR_LCDDOZE_MASK 0x200u
allonq	0:fac0542384d7	1523	#define LCD_GCR_LCDDOZE_SHIFT 9
allonq	0:fac0542384d7	1524	#define LCD_GCR_FFR_MASK 0x400u
allonq	0:fac0542384d7	1525	#define LCD_GCR_FFR_SHIFT 10
allonq	0:fac0542384d7	1526	#define LCD_GCR_ALTSOURCE_MASK 0x800u
allonq	0:fac0542384d7	1527	#define LCD_GCR_ALTSOURCE_SHIFT 11
allonq	0:fac0542384d7	1528	#define LCD_GCR_ALTDIV_MASK 0x3000u
allonq	0:fac0542384d7	1529	#define LCD_GCR_ALTDIV_SHIFT 12
allonq	0:fac0542384d7	1530	#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
allonq	0:fac0542384d7	1531	#define LCD_GCR_FDCIEN_MASK 0x4000u
allonq	0:fac0542384d7	1532	#define LCD_GCR_FDCIEN_SHIFT 14
allonq	0:fac0542384d7	1533	#define LCD_GCR_PADSAFE_MASK 0x8000u
allonq	0:fac0542384d7	1534	#define LCD_GCR_PADSAFE_SHIFT 15
allonq	0:fac0542384d7	1535	#define LCD_GCR_VSUPPLY_MASK 0x20000u
allonq	0:fac0542384d7	1536	#define LCD_GCR_VSUPPLY_SHIFT 17
allonq	0:fac0542384d7	1537	#define LCD_GCR_LADJ_MASK 0x300000u
allonq	0:fac0542384d7	1538	#define LCD_GCR_LADJ_SHIFT 20
allonq	0:fac0542384d7	1539	#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
allonq	0:fac0542384d7	1540	#define LCD_GCR_CPSEL_MASK 0x800000u
allonq	0:fac0542384d7	1541	#define LCD_GCR_CPSEL_SHIFT 23
allonq	0:fac0542384d7	1542	#define LCD_GCR_RVTRIM_MASK 0xF000000u
allonq	0:fac0542384d7	1543	#define LCD_GCR_RVTRIM_SHIFT 24
allonq	0:fac0542384d7	1544	#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
allonq	0:fac0542384d7	1545	#define LCD_GCR_RVEN_MASK 0x80000000u
allonq	0:fac0542384d7	1546	#define LCD_GCR_RVEN_SHIFT 31
allonq	0:fac0542384d7	1547	/* AR Bit Fields */
allonq	0:fac0542384d7	1548	#define LCD_AR_BRATE_MASK 0x7u
allonq	0:fac0542384d7	1549	#define LCD_AR_BRATE_SHIFT 0
allonq	0:fac0542384d7	1550	#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
allonq	0:fac0542384d7	1551	#define LCD_AR_BMODE_MASK 0x8u
allonq	0:fac0542384d7	1552	#define LCD_AR_BMODE_SHIFT 3
allonq	0:fac0542384d7	1553	#define LCD_AR_BLANK_MASK 0x20u
allonq	0:fac0542384d7	1554	#define LCD_AR_BLANK_SHIFT 5
allonq	0:fac0542384d7	1555	#define LCD_AR_ALT_MASK 0x40u
allonq	0:fac0542384d7	1556	#define LCD_AR_ALT_SHIFT 6
allonq	0:fac0542384d7	1557	#define LCD_AR_BLINK_MASK 0x80u
allonq	0:fac0542384d7	1558	#define LCD_AR_BLINK_SHIFT 7
allonq	0:fac0542384d7	1559	/* FDCR Bit Fields */
allonq	0:fac0542384d7	1560	#define LCD_FDCR_FDPINID_MASK 0x3Fu
allonq	0:fac0542384d7	1561	#define LCD_FDCR_FDPINID_SHIFT 0
allonq	0:fac0542384d7	1562	#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
allonq	0:fac0542384d7	1563	#define LCD_FDCR_FDBPEN_MASK 0x40u
allonq	0:fac0542384d7	1564	#define LCD_FDCR_FDBPEN_SHIFT 6
allonq	0:fac0542384d7	1565	#define LCD_FDCR_FDEN_MASK 0x80u
allonq	0:fac0542384d7	1566	#define LCD_FDCR_FDEN_SHIFT 7
allonq	0:fac0542384d7	1567	#define LCD_FDCR_FDSWW_MASK 0xE00u
allonq	0:fac0542384d7	1568	#define LCD_FDCR_FDSWW_SHIFT 9
allonq	0:fac0542384d7	1569	#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
allonq	0:fac0542384d7	1570	#define LCD_FDCR_FDPRS_MASK 0x7000u
allonq	0:fac0542384d7	1571	#define LCD_FDCR_FDPRS_SHIFT 12
allonq	0:fac0542384d7	1572	#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
allonq	0:fac0542384d7	1573	/* FDSR Bit Fields */
allonq	0:fac0542384d7	1574	#define LCD_FDSR_FDCNT_MASK 0xFFu
allonq	0:fac0542384d7	1575	#define LCD_FDSR_FDCNT_SHIFT 0
allonq	0:fac0542384d7	1576	#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
allonq	0:fac0542384d7	1577	#define LCD_FDSR_FDCF_MASK 0x8000u
allonq	0:fac0542384d7	1578	#define LCD_FDSR_FDCF_SHIFT 15
allonq	0:fac0542384d7	1579	/* PEN Bit Fields */
allonq	0:fac0542384d7	1580	#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1581	#define LCD_PEN_PEN_SHIFT 0
allonq	0:fac0542384d7	1582	#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
allonq	0:fac0542384d7	1583	/* BPEN Bit Fields */
allonq	0:fac0542384d7	1584	#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	1585	#define LCD_BPEN_BPEN_SHIFT 0
allonq	0:fac0542384d7	1586	#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
allonq	0:fac0542384d7	1587	/* WF Bit Fields */
allonq	0:fac0542384d7	1588	#define LCD_WF_WF0_MASK 0xFFu
allonq	0:fac0542384d7	1589	#define LCD_WF_WF0_SHIFT 0
allonq	0:fac0542384d7	1590	#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
allonq	0:fac0542384d7	1591	#define LCD_WF_WF60_MASK 0xFFu
allonq	0:fac0542384d7	1592	#define LCD_WF_WF60_SHIFT 0
allonq	0:fac0542384d7	1593	#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
allonq	0:fac0542384d7	1594	#define LCD_WF_WF56_MASK 0xFFu
allonq	0:fac0542384d7	1595	#define LCD_WF_WF56_SHIFT 0
allonq	0:fac0542384d7	1596	#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
allonq	0:fac0542384d7	1597	#define LCD_WF_WF52_MASK 0xFFu
allonq	0:fac0542384d7	1598	#define LCD_WF_WF52_SHIFT 0
allonq	0:fac0542384d7	1599	#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
allonq	0:fac0542384d7	1600	#define LCD_WF_WF4_MASK 0xFFu
allonq	0:fac0542384d7	1601	#define LCD_WF_WF4_SHIFT 0
allonq	0:fac0542384d7	1602	#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
allonq	0:fac0542384d7	1603	#define LCD_WF_WF48_MASK 0xFFu
allonq	0:fac0542384d7	1604	#define LCD_WF_WF48_SHIFT 0
allonq	0:fac0542384d7	1605	#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
allonq	0:fac0542384d7	1606	#define LCD_WF_WF44_MASK 0xFFu
allonq	0:fac0542384d7	1607	#define LCD_WF_WF44_SHIFT 0
allonq	0:fac0542384d7	1608	#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
allonq	0:fac0542384d7	1609	#define LCD_WF_WF40_MASK 0xFFu
allonq	0:fac0542384d7	1610	#define LCD_WF_WF40_SHIFT 0
allonq	0:fac0542384d7	1611	#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
allonq	0:fac0542384d7	1612	#define LCD_WF_WF8_MASK 0xFFu
allonq	0:fac0542384d7	1613	#define LCD_WF_WF8_SHIFT 0
allonq	0:fac0542384d7	1614	#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
allonq	0:fac0542384d7	1615	#define LCD_WF_WF36_MASK 0xFFu
allonq	0:fac0542384d7	1616	#define LCD_WF_WF36_SHIFT 0
allonq	0:fac0542384d7	1617	#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
allonq	0:fac0542384d7	1618	#define LCD_WF_WF32_MASK 0xFFu
allonq	0:fac0542384d7	1619	#define LCD_WF_WF32_SHIFT 0
allonq	0:fac0542384d7	1620	#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
allonq	0:fac0542384d7	1621	#define LCD_WF_WF28_MASK 0xFFu
allonq	0:fac0542384d7	1622	#define LCD_WF_WF28_SHIFT 0
allonq	0:fac0542384d7	1623	#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
allonq	0:fac0542384d7	1624	#define LCD_WF_WF12_MASK 0xFFu
allonq	0:fac0542384d7	1625	#define LCD_WF_WF12_SHIFT 0
allonq	0:fac0542384d7	1626	#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
allonq	0:fac0542384d7	1627	#define LCD_WF_WF24_MASK 0xFFu
allonq	0:fac0542384d7	1628	#define LCD_WF_WF24_SHIFT 0
allonq	0:fac0542384d7	1629	#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
allonq	0:fac0542384d7	1630	#define LCD_WF_WF20_MASK 0xFFu
allonq	0:fac0542384d7	1631	#define LCD_WF_WF20_SHIFT 0
allonq	0:fac0542384d7	1632	#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
allonq	0:fac0542384d7	1633	#define LCD_WF_WF16_MASK 0xFFu
allonq	0:fac0542384d7	1634	#define LCD_WF_WF16_SHIFT 0
allonq	0:fac0542384d7	1635	#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
allonq	0:fac0542384d7	1636	#define LCD_WF_WF5_MASK 0xFF00u
allonq	0:fac0542384d7	1637	#define LCD_WF_WF5_SHIFT 8
allonq	0:fac0542384d7	1638	#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
allonq	0:fac0542384d7	1639	#define LCD_WF_WF49_MASK 0xFF00u
allonq	0:fac0542384d7	1640	#define LCD_WF_WF49_SHIFT 8
allonq	0:fac0542384d7	1641	#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
allonq	0:fac0542384d7	1642	#define LCD_WF_WF45_MASK 0xFF00u
allonq	0:fac0542384d7	1643	#define LCD_WF_WF45_SHIFT 8
allonq	0:fac0542384d7	1644	#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
allonq	0:fac0542384d7	1645	#define LCD_WF_WF61_MASK 0xFF00u
allonq	0:fac0542384d7	1646	#define LCD_WF_WF61_SHIFT 8
allonq	0:fac0542384d7	1647	#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
allonq	0:fac0542384d7	1648	#define LCD_WF_WF25_MASK 0xFF00u
allonq	0:fac0542384d7	1649	#define LCD_WF_WF25_SHIFT 8
allonq	0:fac0542384d7	1650	#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
allonq	0:fac0542384d7	1651	#define LCD_WF_WF17_MASK 0xFF00u
allonq	0:fac0542384d7	1652	#define LCD_WF_WF17_SHIFT 8
allonq	0:fac0542384d7	1653	#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
allonq	0:fac0542384d7	1654	#define LCD_WF_WF41_MASK 0xFF00u
allonq	0:fac0542384d7	1655	#define LCD_WF_WF41_SHIFT 8
allonq	0:fac0542384d7	1656	#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
allonq	0:fac0542384d7	1657	#define LCD_WF_WF13_MASK 0xFF00u
allonq	0:fac0542384d7	1658	#define LCD_WF_WF13_SHIFT 8
allonq	0:fac0542384d7	1659	#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
allonq	0:fac0542384d7	1660	#define LCD_WF_WF57_MASK 0xFF00u
allonq	0:fac0542384d7	1661	#define LCD_WF_WF57_SHIFT 8
allonq	0:fac0542384d7	1662	#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
allonq	0:fac0542384d7	1663	#define LCD_WF_WF53_MASK 0xFF00u
allonq	0:fac0542384d7	1664	#define LCD_WF_WF53_SHIFT 8
allonq	0:fac0542384d7	1665	#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
allonq	0:fac0542384d7	1666	#define LCD_WF_WF37_MASK 0xFF00u
allonq	0:fac0542384d7	1667	#define LCD_WF_WF37_SHIFT 8
allonq	0:fac0542384d7	1668	#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
allonq	0:fac0542384d7	1669	#define LCD_WF_WF9_MASK 0xFF00u
allonq	0:fac0542384d7	1670	#define LCD_WF_WF9_SHIFT 8
allonq	0:fac0542384d7	1671	#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
allonq	0:fac0542384d7	1672	#define LCD_WF_WF1_MASK 0xFF00u
allonq	0:fac0542384d7	1673	#define LCD_WF_WF1_SHIFT 8
allonq	0:fac0542384d7	1674	#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
allonq	0:fac0542384d7	1675	#define LCD_WF_WF29_MASK 0xFF00u
allonq	0:fac0542384d7	1676	#define LCD_WF_WF29_SHIFT 8
allonq	0:fac0542384d7	1677	#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
allonq	0:fac0542384d7	1678	#define LCD_WF_WF33_MASK 0xFF00u
allonq	0:fac0542384d7	1679	#define LCD_WF_WF33_SHIFT 8
allonq	0:fac0542384d7	1680	#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
allonq	0:fac0542384d7	1681	#define LCD_WF_WF21_MASK 0xFF00u
allonq	0:fac0542384d7	1682	#define LCD_WF_WF21_SHIFT 8
allonq	0:fac0542384d7	1683	#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
allonq	0:fac0542384d7	1684	#define LCD_WF_WF26_MASK 0xFF0000u
allonq	0:fac0542384d7	1685	#define LCD_WF_WF26_SHIFT 16
allonq	0:fac0542384d7	1686	#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
allonq	0:fac0542384d7	1687	#define LCD_WF_WF46_MASK 0xFF0000u
allonq	0:fac0542384d7	1688	#define LCD_WF_WF46_SHIFT 16
allonq	0:fac0542384d7	1689	#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
allonq	0:fac0542384d7	1690	#define LCD_WF_WF6_MASK 0xFF0000u
allonq	0:fac0542384d7	1691	#define LCD_WF_WF6_SHIFT 16
allonq	0:fac0542384d7	1692	#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
allonq	0:fac0542384d7	1693	#define LCD_WF_WF42_MASK 0xFF0000u
allonq	0:fac0542384d7	1694	#define LCD_WF_WF42_SHIFT 16
allonq	0:fac0542384d7	1695	#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
allonq	0:fac0542384d7	1696	#define LCD_WF_WF18_MASK 0xFF0000u
allonq	0:fac0542384d7	1697	#define LCD_WF_WF18_SHIFT 16
allonq	0:fac0542384d7	1698	#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
allonq	0:fac0542384d7	1699	#define LCD_WF_WF38_MASK 0xFF0000u
allonq	0:fac0542384d7	1700	#define LCD_WF_WF38_SHIFT 16
allonq	0:fac0542384d7	1701	#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
allonq	0:fac0542384d7	1702	#define LCD_WF_WF22_MASK 0xFF0000u
allonq	0:fac0542384d7	1703	#define LCD_WF_WF22_SHIFT 16
allonq	0:fac0542384d7	1704	#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
allonq	0:fac0542384d7	1705	#define LCD_WF_WF34_MASK 0xFF0000u
allonq	0:fac0542384d7	1706	#define LCD_WF_WF34_SHIFT 16
allonq	0:fac0542384d7	1707	#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
allonq	0:fac0542384d7	1708	#define LCD_WF_WF50_MASK 0xFF0000u
allonq	0:fac0542384d7	1709	#define LCD_WF_WF50_SHIFT 16
allonq	0:fac0542384d7	1710	#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
allonq	0:fac0542384d7	1711	#define LCD_WF_WF14_MASK 0xFF0000u
allonq	0:fac0542384d7	1712	#define LCD_WF_WF14_SHIFT 16
allonq	0:fac0542384d7	1713	#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
allonq	0:fac0542384d7	1714	#define LCD_WF_WF54_MASK 0xFF0000u
allonq	0:fac0542384d7	1715	#define LCD_WF_WF54_SHIFT 16
allonq	0:fac0542384d7	1716	#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
allonq	0:fac0542384d7	1717	#define LCD_WF_WF2_MASK 0xFF0000u
allonq	0:fac0542384d7	1718	#define LCD_WF_WF2_SHIFT 16
allonq	0:fac0542384d7	1719	#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
allonq	0:fac0542384d7	1720	#define LCD_WF_WF58_MASK 0xFF0000u
allonq	0:fac0542384d7	1721	#define LCD_WF_WF58_SHIFT 16
allonq	0:fac0542384d7	1722	#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
allonq	0:fac0542384d7	1723	#define LCD_WF_WF30_MASK 0xFF0000u
allonq	0:fac0542384d7	1724	#define LCD_WF_WF30_SHIFT 16
allonq	0:fac0542384d7	1725	#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
allonq	0:fac0542384d7	1726	#define LCD_WF_WF62_MASK 0xFF0000u
allonq	0:fac0542384d7	1727	#define LCD_WF_WF62_SHIFT 16
allonq	0:fac0542384d7	1728	#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
allonq	0:fac0542384d7	1729	#define LCD_WF_WF10_MASK 0xFF0000u
allonq	0:fac0542384d7	1730	#define LCD_WF_WF10_SHIFT 16
allonq	0:fac0542384d7	1731	#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
allonq	0:fac0542384d7	1732	#define LCD_WF_WF63_MASK 0xFF000000u
allonq	0:fac0542384d7	1733	#define LCD_WF_WF63_SHIFT 24
allonq	0:fac0542384d7	1734	#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
allonq	0:fac0542384d7	1735	#define LCD_WF_WF59_MASK 0xFF000000u
allonq	0:fac0542384d7	1736	#define LCD_WF_WF59_SHIFT 24
allonq	0:fac0542384d7	1737	#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
allonq	0:fac0542384d7	1738	#define LCD_WF_WF55_MASK 0xFF000000u
allonq	0:fac0542384d7	1739	#define LCD_WF_WF55_SHIFT 24
allonq	0:fac0542384d7	1740	#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
allonq	0:fac0542384d7	1741	#define LCD_WF_WF3_MASK 0xFF000000u
allonq	0:fac0542384d7	1742	#define LCD_WF_WF3_SHIFT 24
allonq	0:fac0542384d7	1743	#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
allonq	0:fac0542384d7	1744	#define LCD_WF_WF51_MASK 0xFF000000u
allonq	0:fac0542384d7	1745	#define LCD_WF_WF51_SHIFT 24
allonq	0:fac0542384d7	1746	#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
allonq	0:fac0542384d7	1747	#define LCD_WF_WF47_MASK 0xFF000000u
allonq	0:fac0542384d7	1748	#define LCD_WF_WF47_SHIFT 24
allonq	0:fac0542384d7	1749	#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
allonq	0:fac0542384d7	1750	#define LCD_WF_WF43_MASK 0xFF000000u
allonq	0:fac0542384d7	1751	#define LCD_WF_WF43_SHIFT 24
allonq	0:fac0542384d7	1752	#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
allonq	0:fac0542384d7	1753	#define LCD_WF_WF7_MASK 0xFF000000u
allonq	0:fac0542384d7	1754	#define LCD_WF_WF7_SHIFT 24
allonq	0:fac0542384d7	1755	#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
allonq	0:fac0542384d7	1756	#define LCD_WF_WF39_MASK 0xFF000000u
allonq	0:fac0542384d7	1757	#define LCD_WF_WF39_SHIFT 24
allonq	0:fac0542384d7	1758	#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
allonq	0:fac0542384d7	1759	#define LCD_WF_WF35_MASK 0xFF000000u
allonq	0:fac0542384d7	1760	#define LCD_WF_WF35_SHIFT 24
allonq	0:fac0542384d7	1761	#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
allonq	0:fac0542384d7	1762	#define LCD_WF_WF31_MASK 0xFF000000u
allonq	0:fac0542384d7	1763	#define LCD_WF_WF31_SHIFT 24
allonq	0:fac0542384d7	1764	#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
allonq	0:fac0542384d7	1765	#define LCD_WF_WF11_MASK 0xFF000000u
allonq	0:fac0542384d7	1766	#define LCD_WF_WF11_SHIFT 24
allonq	0:fac0542384d7	1767	#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
allonq	0:fac0542384d7	1768	#define LCD_WF_WF27_MASK 0xFF000000u
allonq	0:fac0542384d7	1769	#define LCD_WF_WF27_SHIFT 24
allonq	0:fac0542384d7	1770	#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
allonq	0:fac0542384d7	1771	#define LCD_WF_WF23_MASK 0xFF000000u
allonq	0:fac0542384d7	1772	#define LCD_WF_WF23_SHIFT 24
allonq	0:fac0542384d7	1773	#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
allonq	0:fac0542384d7	1774	#define LCD_WF_WF19_MASK 0xFF000000u
allonq	0:fac0542384d7	1775	#define LCD_WF_WF19_SHIFT 24
allonq	0:fac0542384d7	1776	#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
allonq	0:fac0542384d7	1777	#define LCD_WF_WF15_MASK 0xFF000000u
allonq	0:fac0542384d7	1778	#define LCD_WF_WF15_SHIFT 24
allonq	0:fac0542384d7	1779	#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
allonq	0:fac0542384d7	1780	/* WF8B Bit Fields */
allonq	0:fac0542384d7	1781	#define LCD_WF8B_BPALCD0_MASK 0x1u
allonq	0:fac0542384d7	1782	#define LCD_WF8B_BPALCD0_SHIFT 0
allonq	0:fac0542384d7	1783	#define LCD_WF8B_BPALCD63_MASK 0x1u
allonq	0:fac0542384d7	1784	#define LCD_WF8B_BPALCD63_SHIFT 0
allonq	0:fac0542384d7	1785	#define LCD_WF8B_BPALCD62_MASK 0x1u
allonq	0:fac0542384d7	1786	#define LCD_WF8B_BPALCD62_SHIFT 0
allonq	0:fac0542384d7	1787	#define LCD_WF8B_BPALCD61_MASK 0x1u
allonq	0:fac0542384d7	1788	#define LCD_WF8B_BPALCD61_SHIFT 0
allonq	0:fac0542384d7	1789	#define LCD_WF8B_BPALCD60_MASK 0x1u
allonq	0:fac0542384d7	1790	#define LCD_WF8B_BPALCD60_SHIFT 0
allonq	0:fac0542384d7	1791	#define LCD_WF8B_BPALCD59_MASK 0x1u
allonq	0:fac0542384d7	1792	#define LCD_WF8B_BPALCD59_SHIFT 0
allonq	0:fac0542384d7	1793	#define LCD_WF8B_BPALCD58_MASK 0x1u
allonq	0:fac0542384d7	1794	#define LCD_WF8B_BPALCD58_SHIFT 0
allonq	0:fac0542384d7	1795	#define LCD_WF8B_BPALCD57_MASK 0x1u
allonq	0:fac0542384d7	1796	#define LCD_WF8B_BPALCD57_SHIFT 0
allonq	0:fac0542384d7	1797	#define LCD_WF8B_BPALCD1_MASK 0x1u
allonq	0:fac0542384d7	1798	#define LCD_WF8B_BPALCD1_SHIFT 0
allonq	0:fac0542384d7	1799	#define LCD_WF8B_BPALCD56_MASK 0x1u
allonq	0:fac0542384d7	1800	#define LCD_WF8B_BPALCD56_SHIFT 0
allonq	0:fac0542384d7	1801	#define LCD_WF8B_BPALCD55_MASK 0x1u
allonq	0:fac0542384d7	1802	#define LCD_WF8B_BPALCD55_SHIFT 0
allonq	0:fac0542384d7	1803	#define LCD_WF8B_BPALCD54_MASK 0x1u
allonq	0:fac0542384d7	1804	#define LCD_WF8B_BPALCD54_SHIFT 0
allonq	0:fac0542384d7	1805	#define LCD_WF8B_BPALCD53_MASK 0x1u
allonq	0:fac0542384d7	1806	#define LCD_WF8B_BPALCD53_SHIFT 0
allonq	0:fac0542384d7	1807	#define LCD_WF8B_BPALCD52_MASK 0x1u
allonq	0:fac0542384d7	1808	#define LCD_WF8B_BPALCD52_SHIFT 0
allonq	0:fac0542384d7	1809	#define LCD_WF8B_BPALCD51_MASK 0x1u
allonq	0:fac0542384d7	1810	#define LCD_WF8B_BPALCD51_SHIFT 0
allonq	0:fac0542384d7	1811	#define LCD_WF8B_BPALCD50_MASK 0x1u
allonq	0:fac0542384d7	1812	#define LCD_WF8B_BPALCD50_SHIFT 0
allonq	0:fac0542384d7	1813	#define LCD_WF8B_BPALCD2_MASK 0x1u
allonq	0:fac0542384d7	1814	#define LCD_WF8B_BPALCD2_SHIFT 0
allonq	0:fac0542384d7	1815	#define LCD_WF8B_BPALCD49_MASK 0x1u
allonq	0:fac0542384d7	1816	#define LCD_WF8B_BPALCD49_SHIFT 0
allonq	0:fac0542384d7	1817	#define LCD_WF8B_BPALCD48_MASK 0x1u
allonq	0:fac0542384d7	1818	#define LCD_WF8B_BPALCD48_SHIFT 0
allonq	0:fac0542384d7	1819	#define LCD_WF8B_BPALCD47_MASK 0x1u
allonq	0:fac0542384d7	1820	#define LCD_WF8B_BPALCD47_SHIFT 0
allonq	0:fac0542384d7	1821	#define LCD_WF8B_BPALCD46_MASK 0x1u
allonq	0:fac0542384d7	1822	#define LCD_WF8B_BPALCD46_SHIFT 0
allonq	0:fac0542384d7	1823	#define LCD_WF8B_BPALCD45_MASK 0x1u
allonq	0:fac0542384d7	1824	#define LCD_WF8B_BPALCD45_SHIFT 0
allonq	0:fac0542384d7	1825	#define LCD_WF8B_BPALCD44_MASK 0x1u
allonq	0:fac0542384d7	1826	#define LCD_WF8B_BPALCD44_SHIFT 0
allonq	0:fac0542384d7	1827	#define LCD_WF8B_BPALCD43_MASK 0x1u
allonq	0:fac0542384d7	1828	#define LCD_WF8B_BPALCD43_SHIFT 0
allonq	0:fac0542384d7	1829	#define LCD_WF8B_BPALCD3_MASK 0x1u
allonq	0:fac0542384d7	1830	#define LCD_WF8B_BPALCD3_SHIFT 0
allonq	0:fac0542384d7	1831	#define LCD_WF8B_BPALCD42_MASK 0x1u
allonq	0:fac0542384d7	1832	#define LCD_WF8B_BPALCD42_SHIFT 0
allonq	0:fac0542384d7	1833	#define LCD_WF8B_BPALCD41_MASK 0x1u
allonq	0:fac0542384d7	1834	#define LCD_WF8B_BPALCD41_SHIFT 0
allonq	0:fac0542384d7	1835	#define LCD_WF8B_BPALCD40_MASK 0x1u
allonq	0:fac0542384d7	1836	#define LCD_WF8B_BPALCD40_SHIFT 0
allonq	0:fac0542384d7	1837	#define LCD_WF8B_BPALCD39_MASK 0x1u
allonq	0:fac0542384d7	1838	#define LCD_WF8B_BPALCD39_SHIFT 0
allonq	0:fac0542384d7	1839	#define LCD_WF8B_BPALCD38_MASK 0x1u
allonq	0:fac0542384d7	1840	#define LCD_WF8B_BPALCD38_SHIFT 0
allonq	0:fac0542384d7	1841	#define LCD_WF8B_BPALCD37_MASK 0x1u
allonq	0:fac0542384d7	1842	#define LCD_WF8B_BPALCD37_SHIFT 0
allonq	0:fac0542384d7	1843	#define LCD_WF8B_BPALCD36_MASK 0x1u
allonq	0:fac0542384d7	1844	#define LCD_WF8B_BPALCD36_SHIFT 0
allonq	0:fac0542384d7	1845	#define LCD_WF8B_BPALCD4_MASK 0x1u
allonq	0:fac0542384d7	1846	#define LCD_WF8B_BPALCD4_SHIFT 0
allonq	0:fac0542384d7	1847	#define LCD_WF8B_BPALCD35_MASK 0x1u
allonq	0:fac0542384d7	1848	#define LCD_WF8B_BPALCD35_SHIFT 0
allonq	0:fac0542384d7	1849	#define LCD_WF8B_BPALCD34_MASK 0x1u
allonq	0:fac0542384d7	1850	#define LCD_WF8B_BPALCD34_SHIFT 0
allonq	0:fac0542384d7	1851	#define LCD_WF8B_BPALCD33_MASK 0x1u
allonq	0:fac0542384d7	1852	#define LCD_WF8B_BPALCD33_SHIFT 0
allonq	0:fac0542384d7	1853	#define LCD_WF8B_BPALCD32_MASK 0x1u
allonq	0:fac0542384d7	1854	#define LCD_WF8B_BPALCD32_SHIFT 0
allonq	0:fac0542384d7	1855	#define LCD_WF8B_BPALCD31_MASK 0x1u
allonq	0:fac0542384d7	1856	#define LCD_WF8B_BPALCD31_SHIFT 0
allonq	0:fac0542384d7	1857	#define LCD_WF8B_BPALCD30_MASK 0x1u
allonq	0:fac0542384d7	1858	#define LCD_WF8B_BPALCD30_SHIFT 0
allonq	0:fac0542384d7	1859	#define LCD_WF8B_BPALCD29_MASK 0x1u
allonq	0:fac0542384d7	1860	#define LCD_WF8B_BPALCD29_SHIFT 0
allonq	0:fac0542384d7	1861	#define LCD_WF8B_BPALCD5_MASK 0x1u
allonq	0:fac0542384d7	1862	#define LCD_WF8B_BPALCD5_SHIFT 0
allonq	0:fac0542384d7	1863	#define LCD_WF8B_BPALCD28_MASK 0x1u
allonq	0:fac0542384d7	1864	#define LCD_WF8B_BPALCD28_SHIFT 0
allonq	0:fac0542384d7	1865	#define LCD_WF8B_BPALCD27_MASK 0x1u
allonq	0:fac0542384d7	1866	#define LCD_WF8B_BPALCD27_SHIFT 0
allonq	0:fac0542384d7	1867	#define LCD_WF8B_BPALCD26_MASK 0x1u
allonq	0:fac0542384d7	1868	#define LCD_WF8B_BPALCD26_SHIFT 0
allonq	0:fac0542384d7	1869	#define LCD_WF8B_BPALCD25_MASK 0x1u
allonq	0:fac0542384d7	1870	#define LCD_WF8B_BPALCD25_SHIFT 0
allonq	0:fac0542384d7	1871	#define LCD_WF8B_BPALCD24_MASK 0x1u
allonq	0:fac0542384d7	1872	#define LCD_WF8B_BPALCD24_SHIFT 0
allonq	0:fac0542384d7	1873	#define LCD_WF8B_BPALCD23_MASK 0x1u
allonq	0:fac0542384d7	1874	#define LCD_WF8B_BPALCD23_SHIFT 0
allonq	0:fac0542384d7	1875	#define LCD_WF8B_BPALCD22_MASK 0x1u
allonq	0:fac0542384d7	1876	#define LCD_WF8B_BPALCD22_SHIFT 0
allonq	0:fac0542384d7	1877	#define LCD_WF8B_BPALCD6_MASK 0x1u
allonq	0:fac0542384d7	1878	#define LCD_WF8B_BPALCD6_SHIFT 0
allonq	0:fac0542384d7	1879	#define LCD_WF8B_BPALCD21_MASK 0x1u
allonq	0:fac0542384d7	1880	#define LCD_WF8B_BPALCD21_SHIFT 0
allonq	0:fac0542384d7	1881	#define LCD_WF8B_BPALCD20_MASK 0x1u
allonq	0:fac0542384d7	1882	#define LCD_WF8B_BPALCD20_SHIFT 0
allonq	0:fac0542384d7	1883	#define LCD_WF8B_BPALCD19_MASK 0x1u
allonq	0:fac0542384d7	1884	#define LCD_WF8B_BPALCD19_SHIFT 0
allonq	0:fac0542384d7	1885	#define LCD_WF8B_BPALCD18_MASK 0x1u
allonq	0:fac0542384d7	1886	#define LCD_WF8B_BPALCD18_SHIFT 0
allonq	0:fac0542384d7	1887	#define LCD_WF8B_BPALCD17_MASK 0x1u
allonq	0:fac0542384d7	1888	#define LCD_WF8B_BPALCD17_SHIFT 0
allonq	0:fac0542384d7	1889	#define LCD_WF8B_BPALCD16_MASK 0x1u
allonq	0:fac0542384d7	1890	#define LCD_WF8B_BPALCD16_SHIFT 0
allonq	0:fac0542384d7	1891	#define LCD_WF8B_BPALCD15_MASK 0x1u
allonq	0:fac0542384d7	1892	#define LCD_WF8B_BPALCD15_SHIFT 0
allonq	0:fac0542384d7	1893	#define LCD_WF8B_BPALCD7_MASK 0x1u
allonq	0:fac0542384d7	1894	#define LCD_WF8B_BPALCD7_SHIFT 0
allonq	0:fac0542384d7	1895	#define LCD_WF8B_BPALCD14_MASK 0x1u
allonq	0:fac0542384d7	1896	#define LCD_WF8B_BPALCD14_SHIFT 0
allonq	0:fac0542384d7	1897	#define LCD_WF8B_BPALCD13_MASK 0x1u
allonq	0:fac0542384d7	1898	#define LCD_WF8B_BPALCD13_SHIFT 0
allonq	0:fac0542384d7	1899	#define LCD_WF8B_BPALCD12_MASK 0x1u
allonq	0:fac0542384d7	1900	#define LCD_WF8B_BPALCD12_SHIFT 0
allonq	0:fac0542384d7	1901	#define LCD_WF8B_BPALCD11_MASK 0x1u
allonq	0:fac0542384d7	1902	#define LCD_WF8B_BPALCD11_SHIFT 0
allonq	0:fac0542384d7	1903	#define LCD_WF8B_BPALCD10_MASK 0x1u
allonq	0:fac0542384d7	1904	#define LCD_WF8B_BPALCD10_SHIFT 0
allonq	0:fac0542384d7	1905	#define LCD_WF8B_BPALCD9_MASK 0x1u
allonq	0:fac0542384d7	1906	#define LCD_WF8B_BPALCD9_SHIFT 0
allonq	0:fac0542384d7	1907	#define LCD_WF8B_BPALCD8_MASK 0x1u
allonq	0:fac0542384d7	1908	#define LCD_WF8B_BPALCD8_SHIFT 0
allonq	0:fac0542384d7	1909	#define LCD_WF8B_BPBLCD1_MASK 0x2u
allonq	0:fac0542384d7	1910	#define LCD_WF8B_BPBLCD1_SHIFT 1
allonq	0:fac0542384d7	1911	#define LCD_WF8B_BPBLCD32_MASK 0x2u
allonq	0:fac0542384d7	1912	#define LCD_WF8B_BPBLCD32_SHIFT 1
allonq	0:fac0542384d7	1913	#define LCD_WF8B_BPBLCD30_MASK 0x2u
allonq	0:fac0542384d7	1914	#define LCD_WF8B_BPBLCD30_SHIFT 1
allonq	0:fac0542384d7	1915	#define LCD_WF8B_BPBLCD60_MASK 0x2u
allonq	0:fac0542384d7	1916	#define LCD_WF8B_BPBLCD60_SHIFT 1
allonq	0:fac0542384d7	1917	#define LCD_WF8B_BPBLCD24_MASK 0x2u
allonq	0:fac0542384d7	1918	#define LCD_WF8B_BPBLCD24_SHIFT 1
allonq	0:fac0542384d7	1919	#define LCD_WF8B_BPBLCD28_MASK 0x2u
allonq	0:fac0542384d7	1920	#define LCD_WF8B_BPBLCD28_SHIFT 1
allonq	0:fac0542384d7	1921	#define LCD_WF8B_BPBLCD23_MASK 0x2u
allonq	0:fac0542384d7	1922	#define LCD_WF8B_BPBLCD23_SHIFT 1
allonq	0:fac0542384d7	1923	#define LCD_WF8B_BPBLCD48_MASK 0x2u
allonq	0:fac0542384d7	1924	#define LCD_WF8B_BPBLCD48_SHIFT 1
allonq	0:fac0542384d7	1925	#define LCD_WF8B_BPBLCD10_MASK 0x2u
allonq	0:fac0542384d7	1926	#define LCD_WF8B_BPBLCD10_SHIFT 1
allonq	0:fac0542384d7	1927	#define LCD_WF8B_BPBLCD15_MASK 0x2u
allonq	0:fac0542384d7	1928	#define LCD_WF8B_BPBLCD15_SHIFT 1
allonq	0:fac0542384d7	1929	#define LCD_WF8B_BPBLCD36_MASK 0x2u
allonq	0:fac0542384d7	1930	#define LCD_WF8B_BPBLCD36_SHIFT 1
allonq	0:fac0542384d7	1931	#define LCD_WF8B_BPBLCD44_MASK 0x2u
allonq	0:fac0542384d7	1932	#define LCD_WF8B_BPBLCD44_SHIFT 1
allonq	0:fac0542384d7	1933	#define LCD_WF8B_BPBLCD62_MASK 0x2u
allonq	0:fac0542384d7	1934	#define LCD_WF8B_BPBLCD62_SHIFT 1
allonq	0:fac0542384d7	1935	#define LCD_WF8B_BPBLCD53_MASK 0x2u
allonq	0:fac0542384d7	1936	#define LCD_WF8B_BPBLCD53_SHIFT 1
allonq	0:fac0542384d7	1937	#define LCD_WF8B_BPBLCD22_MASK 0x2u
allonq	0:fac0542384d7	1938	#define LCD_WF8B_BPBLCD22_SHIFT 1
allonq	0:fac0542384d7	1939	#define LCD_WF8B_BPBLCD47_MASK 0x2u
allonq	0:fac0542384d7	1940	#define LCD_WF8B_BPBLCD47_SHIFT 1
allonq	0:fac0542384d7	1941	#define LCD_WF8B_BPBLCD33_MASK 0x2u
allonq	0:fac0542384d7	1942	#define LCD_WF8B_BPBLCD33_SHIFT 1
allonq	0:fac0542384d7	1943	#define LCD_WF8B_BPBLCD2_MASK 0x2u
allonq	0:fac0542384d7	1944	#define LCD_WF8B_BPBLCD2_SHIFT 1
allonq	0:fac0542384d7	1945	#define LCD_WF8B_BPBLCD49_MASK 0x2u
allonq	0:fac0542384d7	1946	#define LCD_WF8B_BPBLCD49_SHIFT 1
allonq	0:fac0542384d7	1947	#define LCD_WF8B_BPBLCD0_MASK 0x2u
allonq	0:fac0542384d7	1948	#define LCD_WF8B_BPBLCD0_SHIFT 1
allonq	0:fac0542384d7	1949	#define LCD_WF8B_BPBLCD55_MASK 0x2u
allonq	0:fac0542384d7	1950	#define LCD_WF8B_BPBLCD55_SHIFT 1
allonq	0:fac0542384d7	1951	#define LCD_WF8B_BPBLCD56_MASK 0x2u
allonq	0:fac0542384d7	1952	#define LCD_WF8B_BPBLCD56_SHIFT 1
allonq	0:fac0542384d7	1953	#define LCD_WF8B_BPBLCD21_MASK 0x2u
allonq	0:fac0542384d7	1954	#define LCD_WF8B_BPBLCD21_SHIFT 1
allonq	0:fac0542384d7	1955	#define LCD_WF8B_BPBLCD6_MASK 0x2u
allonq	0:fac0542384d7	1956	#define LCD_WF8B_BPBLCD6_SHIFT 1
allonq	0:fac0542384d7	1957	#define LCD_WF8B_BPBLCD29_MASK 0x2u
allonq	0:fac0542384d7	1958	#define LCD_WF8B_BPBLCD29_SHIFT 1
allonq	0:fac0542384d7	1959	#define LCD_WF8B_BPBLCD25_MASK 0x2u
allonq	0:fac0542384d7	1960	#define LCD_WF8B_BPBLCD25_SHIFT 1
allonq	0:fac0542384d7	1961	#define LCD_WF8B_BPBLCD8_MASK 0x2u
allonq	0:fac0542384d7	1962	#define LCD_WF8B_BPBLCD8_SHIFT 1
allonq	0:fac0542384d7	1963	#define LCD_WF8B_BPBLCD54_MASK 0x2u
allonq	0:fac0542384d7	1964	#define LCD_WF8B_BPBLCD54_SHIFT 1
allonq	0:fac0542384d7	1965	#define LCD_WF8B_BPBLCD38_MASK 0x2u
allonq	0:fac0542384d7	1966	#define LCD_WF8B_BPBLCD38_SHIFT 1
allonq	0:fac0542384d7	1967	#define LCD_WF8B_BPBLCD43_MASK 0x2u
allonq	0:fac0542384d7	1968	#define LCD_WF8B_BPBLCD43_SHIFT 1
allonq	0:fac0542384d7	1969	#define LCD_WF8B_BPBLCD20_MASK 0x2u
allonq	0:fac0542384d7	1970	#define LCD_WF8B_BPBLCD20_SHIFT 1
allonq	0:fac0542384d7	1971	#define LCD_WF8B_BPBLCD9_MASK 0x2u
allonq	0:fac0542384d7	1972	#define LCD_WF8B_BPBLCD9_SHIFT 1
allonq	0:fac0542384d7	1973	#define LCD_WF8B_BPBLCD7_MASK 0x2u
allonq	0:fac0542384d7	1974	#define LCD_WF8B_BPBLCD7_SHIFT 1
allonq	0:fac0542384d7	1975	#define LCD_WF8B_BPBLCD50_MASK 0x2u
allonq	0:fac0542384d7	1976	#define LCD_WF8B_BPBLCD50_SHIFT 1
allonq	0:fac0542384d7	1977	#define LCD_WF8B_BPBLCD40_MASK 0x2u
allonq	0:fac0542384d7	1978	#define LCD_WF8B_BPBLCD40_SHIFT 1
allonq	0:fac0542384d7	1979	#define LCD_WF8B_BPBLCD63_MASK 0x2u
allonq	0:fac0542384d7	1980	#define LCD_WF8B_BPBLCD63_SHIFT 1
allonq	0:fac0542384d7	1981	#define LCD_WF8B_BPBLCD26_MASK 0x2u
allonq	0:fac0542384d7	1982	#define LCD_WF8B_BPBLCD26_SHIFT 1
allonq	0:fac0542384d7	1983	#define LCD_WF8B_BPBLCD12_MASK 0x2u
allonq	0:fac0542384d7	1984	#define LCD_WF8B_BPBLCD12_SHIFT 1
allonq	0:fac0542384d7	1985	#define LCD_WF8B_BPBLCD19_MASK 0x2u
allonq	0:fac0542384d7	1986	#define LCD_WF8B_BPBLCD19_SHIFT 1
allonq	0:fac0542384d7	1987	#define LCD_WF8B_BPBLCD34_MASK 0x2u
allonq	0:fac0542384d7	1988	#define LCD_WF8B_BPBLCD34_SHIFT 1
allonq	0:fac0542384d7	1989	#define LCD_WF8B_BPBLCD39_MASK 0x2u
allonq	0:fac0542384d7	1990	#define LCD_WF8B_BPBLCD39_SHIFT 1
allonq	0:fac0542384d7	1991	#define LCD_WF8B_BPBLCD59_MASK 0x2u
allonq	0:fac0542384d7	1992	#define LCD_WF8B_BPBLCD59_SHIFT 1
allonq	0:fac0542384d7	1993	#define LCD_WF8B_BPBLCD61_MASK 0x2u
allonq	0:fac0542384d7	1994	#define LCD_WF8B_BPBLCD61_SHIFT 1
allonq	0:fac0542384d7	1995	#define LCD_WF8B_BPBLCD37_MASK 0x2u
allonq	0:fac0542384d7	1996	#define LCD_WF8B_BPBLCD37_SHIFT 1
allonq	0:fac0542384d7	1997	#define LCD_WF8B_BPBLCD31_MASK 0x2u
allonq	0:fac0542384d7	1998	#define LCD_WF8B_BPBLCD31_SHIFT 1
allonq	0:fac0542384d7	1999	#define LCD_WF8B_BPBLCD58_MASK 0x2u
allonq	0:fac0542384d7	2000	#define LCD_WF8B_BPBLCD58_SHIFT 1
allonq	0:fac0542384d7	2001	#define LCD_WF8B_BPBLCD18_MASK 0x2u
allonq	0:fac0542384d7	2002	#define LCD_WF8B_BPBLCD18_SHIFT 1
allonq	0:fac0542384d7	2003	#define LCD_WF8B_BPBLCD45_MASK 0x2u
allonq	0:fac0542384d7	2004	#define LCD_WF8B_BPBLCD45_SHIFT 1
allonq	0:fac0542384d7	2005	#define LCD_WF8B_BPBLCD27_MASK 0x2u
allonq	0:fac0542384d7	2006	#define LCD_WF8B_BPBLCD27_SHIFT 1
allonq	0:fac0542384d7	2007	#define LCD_WF8B_BPBLCD14_MASK 0x2u
allonq	0:fac0542384d7	2008	#define LCD_WF8B_BPBLCD14_SHIFT 1
allonq	0:fac0542384d7	2009	#define LCD_WF8B_BPBLCD51_MASK 0x2u
allonq	0:fac0542384d7	2010	#define LCD_WF8B_BPBLCD51_SHIFT 1
allonq	0:fac0542384d7	2011	#define LCD_WF8B_BPBLCD52_MASK 0x2u
allonq	0:fac0542384d7	2012	#define LCD_WF8B_BPBLCD52_SHIFT 1
allonq	0:fac0542384d7	2013	#define LCD_WF8B_BPBLCD4_MASK 0x2u
allonq	0:fac0542384d7	2014	#define LCD_WF8B_BPBLCD4_SHIFT 1
allonq	0:fac0542384d7	2015	#define LCD_WF8B_BPBLCD35_MASK 0x2u
allonq	0:fac0542384d7	2016	#define LCD_WF8B_BPBLCD35_SHIFT 1
allonq	0:fac0542384d7	2017	#define LCD_WF8B_BPBLCD17_MASK 0x2u
allonq	0:fac0542384d7	2018	#define LCD_WF8B_BPBLCD17_SHIFT 1
allonq	0:fac0542384d7	2019	#define LCD_WF8B_BPBLCD41_MASK 0x2u
allonq	0:fac0542384d7	2020	#define LCD_WF8B_BPBLCD41_SHIFT 1
allonq	0:fac0542384d7	2021	#define LCD_WF8B_BPBLCD11_MASK 0x2u
allonq	0:fac0542384d7	2022	#define LCD_WF8B_BPBLCD11_SHIFT 1
allonq	0:fac0542384d7	2023	#define LCD_WF8B_BPBLCD46_MASK 0x2u
allonq	0:fac0542384d7	2024	#define LCD_WF8B_BPBLCD46_SHIFT 1
allonq	0:fac0542384d7	2025	#define LCD_WF8B_BPBLCD57_MASK 0x2u
allonq	0:fac0542384d7	2026	#define LCD_WF8B_BPBLCD57_SHIFT 1
allonq	0:fac0542384d7	2027	#define LCD_WF8B_BPBLCD42_MASK 0x2u
allonq	0:fac0542384d7	2028	#define LCD_WF8B_BPBLCD42_SHIFT 1
allonq	0:fac0542384d7	2029	#define LCD_WF8B_BPBLCD5_MASK 0x2u
allonq	0:fac0542384d7	2030	#define LCD_WF8B_BPBLCD5_SHIFT 1
allonq	0:fac0542384d7	2031	#define LCD_WF8B_BPBLCD3_MASK 0x2u
allonq	0:fac0542384d7	2032	#define LCD_WF8B_BPBLCD3_SHIFT 1
allonq	0:fac0542384d7	2033	#define LCD_WF8B_BPBLCD16_MASK 0x2u
allonq	0:fac0542384d7	2034	#define LCD_WF8B_BPBLCD16_SHIFT 1
allonq	0:fac0542384d7	2035	#define LCD_WF8B_BPBLCD13_MASK 0x2u
allonq	0:fac0542384d7	2036	#define LCD_WF8B_BPBLCD13_SHIFT 1
allonq	0:fac0542384d7	2037	#define LCD_WF8B_BPCLCD10_MASK 0x4u
allonq	0:fac0542384d7	2038	#define LCD_WF8B_BPCLCD10_SHIFT 2
allonq	0:fac0542384d7	2039	#define LCD_WF8B_BPCLCD55_MASK 0x4u
allonq	0:fac0542384d7	2040	#define LCD_WF8B_BPCLCD55_SHIFT 2
allonq	0:fac0542384d7	2041	#define LCD_WF8B_BPCLCD2_MASK 0x4u
allonq	0:fac0542384d7	2042	#define LCD_WF8B_BPCLCD2_SHIFT 2
allonq	0:fac0542384d7	2043	#define LCD_WF8B_BPCLCD23_MASK 0x4u
allonq	0:fac0542384d7	2044	#define LCD_WF8B_BPCLCD23_SHIFT 2
allonq	0:fac0542384d7	2045	#define LCD_WF8B_BPCLCD48_MASK 0x4u
allonq	0:fac0542384d7	2046	#define LCD_WF8B_BPCLCD48_SHIFT 2
allonq	0:fac0542384d7	2047	#define LCD_WF8B_BPCLCD24_MASK 0x4u
allonq	0:fac0542384d7	2048	#define LCD_WF8B_BPCLCD24_SHIFT 2
allonq	0:fac0542384d7	2049	#define LCD_WF8B_BPCLCD60_MASK 0x4u
allonq	0:fac0542384d7	2050	#define LCD_WF8B_BPCLCD60_SHIFT 2
allonq	0:fac0542384d7	2051	#define LCD_WF8B_BPCLCD47_MASK 0x4u
allonq	0:fac0542384d7	2052	#define LCD_WF8B_BPCLCD47_SHIFT 2
allonq	0:fac0542384d7	2053	#define LCD_WF8B_BPCLCD22_MASK 0x4u
allonq	0:fac0542384d7	2054	#define LCD_WF8B_BPCLCD22_SHIFT 2
allonq	0:fac0542384d7	2055	#define LCD_WF8B_BPCLCD8_MASK 0x4u
allonq	0:fac0542384d7	2056	#define LCD_WF8B_BPCLCD8_SHIFT 2
allonq	0:fac0542384d7	2057	#define LCD_WF8B_BPCLCD21_MASK 0x4u
allonq	0:fac0542384d7	2058	#define LCD_WF8B_BPCLCD21_SHIFT 2
allonq	0:fac0542384d7	2059	#define LCD_WF8B_BPCLCD49_MASK 0x4u
allonq	0:fac0542384d7	2060	#define LCD_WF8B_BPCLCD49_SHIFT 2
allonq	0:fac0542384d7	2061	#define LCD_WF8B_BPCLCD25_MASK 0x4u
allonq	0:fac0542384d7	2062	#define LCD_WF8B_BPCLCD25_SHIFT 2
allonq	0:fac0542384d7	2063	#define LCD_WF8B_BPCLCD1_MASK 0x4u
allonq	0:fac0542384d7	2064	#define LCD_WF8B_BPCLCD1_SHIFT 2
allonq	0:fac0542384d7	2065	#define LCD_WF8B_BPCLCD20_MASK 0x4u
allonq	0:fac0542384d7	2066	#define LCD_WF8B_BPCLCD20_SHIFT 2
allonq	0:fac0542384d7	2067	#define LCD_WF8B_BPCLCD50_MASK 0x4u
allonq	0:fac0542384d7	2068	#define LCD_WF8B_BPCLCD50_SHIFT 2
allonq	0:fac0542384d7	2069	#define LCD_WF8B_BPCLCD19_MASK 0x4u
allonq	0:fac0542384d7	2070	#define LCD_WF8B_BPCLCD19_SHIFT 2
allonq	0:fac0542384d7	2071	#define LCD_WF8B_BPCLCD26_MASK 0x4u
allonq	0:fac0542384d7	2072	#define LCD_WF8B_BPCLCD26_SHIFT 2
allonq	0:fac0542384d7	2073	#define LCD_WF8B_BPCLCD59_MASK 0x4u
allonq	0:fac0542384d7	2074	#define LCD_WF8B_BPCLCD59_SHIFT 2
allonq	0:fac0542384d7	2075	#define LCD_WF8B_BPCLCD61_MASK 0x4u
allonq	0:fac0542384d7	2076	#define LCD_WF8B_BPCLCD61_SHIFT 2
allonq	0:fac0542384d7	2077	#define LCD_WF8B_BPCLCD46_MASK 0x4u
allonq	0:fac0542384d7	2078	#define LCD_WF8B_BPCLCD46_SHIFT 2
allonq	0:fac0542384d7	2079	#define LCD_WF8B_BPCLCD18_MASK 0x4u
allonq	0:fac0542384d7	2080	#define LCD_WF8B_BPCLCD18_SHIFT 2
allonq	0:fac0542384d7	2081	#define LCD_WF8B_BPCLCD5_MASK 0x4u
allonq	0:fac0542384d7	2082	#define LCD_WF8B_BPCLCD5_SHIFT 2
allonq	0:fac0542384d7	2083	#define LCD_WF8B_BPCLCD63_MASK 0x4u
allonq	0:fac0542384d7	2084	#define LCD_WF8B_BPCLCD63_SHIFT 2
allonq	0:fac0542384d7	2085	#define LCD_WF8B_BPCLCD27_MASK 0x4u
allonq	0:fac0542384d7	2086	#define LCD_WF8B_BPCLCD27_SHIFT 2
allonq	0:fac0542384d7	2087	#define LCD_WF8B_BPCLCD17_MASK 0x4u
allonq	0:fac0542384d7	2088	#define LCD_WF8B_BPCLCD17_SHIFT 2
allonq	0:fac0542384d7	2089	#define LCD_WF8B_BPCLCD51_MASK 0x4u
allonq	0:fac0542384d7	2090	#define LCD_WF8B_BPCLCD51_SHIFT 2
allonq	0:fac0542384d7	2091	#define LCD_WF8B_BPCLCD9_MASK 0x4u
allonq	0:fac0542384d7	2092	#define LCD_WF8B_BPCLCD9_SHIFT 2
allonq	0:fac0542384d7	2093	#define LCD_WF8B_BPCLCD54_MASK 0x4u
allonq	0:fac0542384d7	2094	#define LCD_WF8B_BPCLCD54_SHIFT 2
allonq	0:fac0542384d7	2095	#define LCD_WF8B_BPCLCD15_MASK 0x4u
allonq	0:fac0542384d7	2096	#define LCD_WF8B_BPCLCD15_SHIFT 2
allonq	0:fac0542384d7	2097	#define LCD_WF8B_BPCLCD16_MASK 0x4u
allonq	0:fac0542384d7	2098	#define LCD_WF8B_BPCLCD16_SHIFT 2
allonq	0:fac0542384d7	2099	#define LCD_WF8B_BPCLCD14_MASK 0x4u
allonq	0:fac0542384d7	2100	#define LCD_WF8B_BPCLCD14_SHIFT 2
allonq	0:fac0542384d7	2101	#define LCD_WF8B_BPCLCD32_MASK 0x4u
allonq	0:fac0542384d7	2102	#define LCD_WF8B_BPCLCD32_SHIFT 2
allonq	0:fac0542384d7	2103	#define LCD_WF8B_BPCLCD28_MASK 0x4u
allonq	0:fac0542384d7	2104	#define LCD_WF8B_BPCLCD28_SHIFT 2
allonq	0:fac0542384d7	2105	#define LCD_WF8B_BPCLCD53_MASK 0x4u
allonq	0:fac0542384d7	2106	#define LCD_WF8B_BPCLCD53_SHIFT 2
allonq	0:fac0542384d7	2107	#define LCD_WF8B_BPCLCD33_MASK 0x4u
allonq	0:fac0542384d7	2108	#define LCD_WF8B_BPCLCD33_SHIFT 2
allonq	0:fac0542384d7	2109	#define LCD_WF8B_BPCLCD0_MASK 0x4u
allonq	0:fac0542384d7	2110	#define LCD_WF8B_BPCLCD0_SHIFT 2
allonq	0:fac0542384d7	2111	#define LCD_WF8B_BPCLCD43_MASK 0x4u
allonq	0:fac0542384d7	2112	#define LCD_WF8B_BPCLCD43_SHIFT 2
allonq	0:fac0542384d7	2113	#define LCD_WF8B_BPCLCD7_MASK 0x4u
allonq	0:fac0542384d7	2114	#define LCD_WF8B_BPCLCD7_SHIFT 2
allonq	0:fac0542384d7	2115	#define LCD_WF8B_BPCLCD4_MASK 0x4u
allonq	0:fac0542384d7	2116	#define LCD_WF8B_BPCLCD4_SHIFT 2
allonq	0:fac0542384d7	2117	#define LCD_WF8B_BPCLCD34_MASK 0x4u
allonq	0:fac0542384d7	2118	#define LCD_WF8B_BPCLCD34_SHIFT 2
allonq	0:fac0542384d7	2119	#define LCD_WF8B_BPCLCD29_MASK 0x4u
allonq	0:fac0542384d7	2120	#define LCD_WF8B_BPCLCD29_SHIFT 2
allonq	0:fac0542384d7	2121	#define LCD_WF8B_BPCLCD45_MASK 0x4u
allonq	0:fac0542384d7	2122	#define LCD_WF8B_BPCLCD45_SHIFT 2
allonq	0:fac0542384d7	2123	#define LCD_WF8B_BPCLCD57_MASK 0x4u
allonq	0:fac0542384d7	2124	#define LCD_WF8B_BPCLCD57_SHIFT 2
allonq	0:fac0542384d7	2125	#define LCD_WF8B_BPCLCD42_MASK 0x4u
allonq	0:fac0542384d7	2126	#define LCD_WF8B_BPCLCD42_SHIFT 2
allonq	0:fac0542384d7	2127	#define LCD_WF8B_BPCLCD35_MASK 0x4u
allonq	0:fac0542384d7	2128	#define LCD_WF8B_BPCLCD35_SHIFT 2
allonq	0:fac0542384d7	2129	#define LCD_WF8B_BPCLCD13_MASK 0x4u
allonq	0:fac0542384d7	2130	#define LCD_WF8B_BPCLCD13_SHIFT 2
allonq	0:fac0542384d7	2131	#define LCD_WF8B_BPCLCD36_MASK 0x4u
allonq	0:fac0542384d7	2132	#define LCD_WF8B_BPCLCD36_SHIFT 2
allonq	0:fac0542384d7	2133	#define LCD_WF8B_BPCLCD30_MASK 0x4u
allonq	0:fac0542384d7	2134	#define LCD_WF8B_BPCLCD30_SHIFT 2
allonq	0:fac0542384d7	2135	#define LCD_WF8B_BPCLCD52_MASK 0x4u
allonq	0:fac0542384d7	2136	#define LCD_WF8B_BPCLCD52_SHIFT 2
allonq	0:fac0542384d7	2137	#define LCD_WF8B_BPCLCD58_MASK 0x4u
allonq	0:fac0542384d7	2138	#define LCD_WF8B_BPCLCD58_SHIFT 2
allonq	0:fac0542384d7	2139	#define LCD_WF8B_BPCLCD41_MASK 0x4u
allonq	0:fac0542384d7	2140	#define LCD_WF8B_BPCLCD41_SHIFT 2
allonq	0:fac0542384d7	2141	#define LCD_WF8B_BPCLCD37_MASK 0x4u
allonq	0:fac0542384d7	2142	#define LCD_WF8B_BPCLCD37_SHIFT 2
allonq	0:fac0542384d7	2143	#define LCD_WF8B_BPCLCD3_MASK 0x4u
allonq	0:fac0542384d7	2144	#define LCD_WF8B_BPCLCD3_SHIFT 2
allonq	0:fac0542384d7	2145	#define LCD_WF8B_BPCLCD12_MASK 0x4u
allonq	0:fac0542384d7	2146	#define LCD_WF8B_BPCLCD12_SHIFT 2
allonq	0:fac0542384d7	2147	#define LCD_WF8B_BPCLCD11_MASK 0x4u
allonq	0:fac0542384d7	2148	#define LCD_WF8B_BPCLCD11_SHIFT 2
allonq	0:fac0542384d7	2149	#define LCD_WF8B_BPCLCD38_MASK 0x4u
allonq	0:fac0542384d7	2150	#define LCD_WF8B_BPCLCD38_SHIFT 2
allonq	0:fac0542384d7	2151	#define LCD_WF8B_BPCLCD44_MASK 0x4u
allonq	0:fac0542384d7	2152	#define LCD_WF8B_BPCLCD44_SHIFT 2
allonq	0:fac0542384d7	2153	#define LCD_WF8B_BPCLCD31_MASK 0x4u
allonq	0:fac0542384d7	2154	#define LCD_WF8B_BPCLCD31_SHIFT 2
allonq	0:fac0542384d7	2155	#define LCD_WF8B_BPCLCD40_MASK 0x4u
allonq	0:fac0542384d7	2156	#define LCD_WF8B_BPCLCD40_SHIFT 2
allonq	0:fac0542384d7	2157	#define LCD_WF8B_BPCLCD62_MASK 0x4u
allonq	0:fac0542384d7	2158	#define LCD_WF8B_BPCLCD62_SHIFT 2
allonq	0:fac0542384d7	2159	#define LCD_WF8B_BPCLCD56_MASK 0x4u
allonq	0:fac0542384d7	2160	#define LCD_WF8B_BPCLCD56_SHIFT 2
allonq	0:fac0542384d7	2161	#define LCD_WF8B_BPCLCD39_MASK 0x4u
allonq	0:fac0542384d7	2162	#define LCD_WF8B_BPCLCD39_SHIFT 2
allonq	0:fac0542384d7	2163	#define LCD_WF8B_BPCLCD6_MASK 0x4u
allonq	0:fac0542384d7	2164	#define LCD_WF8B_BPCLCD6_SHIFT 2
allonq	0:fac0542384d7	2165	#define LCD_WF8B_BPDLCD47_MASK 0x8u
allonq	0:fac0542384d7	2166	#define LCD_WF8B_BPDLCD47_SHIFT 3
allonq	0:fac0542384d7	2167	#define LCD_WF8B_BPDLCD23_MASK 0x8u
allonq	0:fac0542384d7	2168	#define LCD_WF8B_BPDLCD23_SHIFT 3
allonq	0:fac0542384d7	2169	#define LCD_WF8B_BPDLCD48_MASK 0x8u
allonq	0:fac0542384d7	2170	#define LCD_WF8B_BPDLCD48_SHIFT 3
allonq	0:fac0542384d7	2171	#define LCD_WF8B_BPDLCD24_MASK 0x8u
allonq	0:fac0542384d7	2172	#define LCD_WF8B_BPDLCD24_SHIFT 3
allonq	0:fac0542384d7	2173	#define LCD_WF8B_BPDLCD15_MASK 0x8u
allonq	0:fac0542384d7	2174	#define LCD_WF8B_BPDLCD15_SHIFT 3
allonq	0:fac0542384d7	2175	#define LCD_WF8B_BPDLCD22_MASK 0x8u
allonq	0:fac0542384d7	2176	#define LCD_WF8B_BPDLCD22_SHIFT 3
allonq	0:fac0542384d7	2177	#define LCD_WF8B_BPDLCD60_MASK 0x8u
allonq	0:fac0542384d7	2178	#define LCD_WF8B_BPDLCD60_SHIFT 3
allonq	0:fac0542384d7	2179	#define LCD_WF8B_BPDLCD10_MASK 0x8u
allonq	0:fac0542384d7	2180	#define LCD_WF8B_BPDLCD10_SHIFT 3
allonq	0:fac0542384d7	2181	#define LCD_WF8B_BPDLCD21_MASK 0x8u
allonq	0:fac0542384d7	2182	#define LCD_WF8B_BPDLCD21_SHIFT 3
allonq	0:fac0542384d7	2183	#define LCD_WF8B_BPDLCD49_MASK 0x8u
allonq	0:fac0542384d7	2184	#define LCD_WF8B_BPDLCD49_SHIFT 3
allonq	0:fac0542384d7	2185	#define LCD_WF8B_BPDLCD1_MASK 0x8u
allonq	0:fac0542384d7	2186	#define LCD_WF8B_BPDLCD1_SHIFT 3
allonq	0:fac0542384d7	2187	#define LCD_WF8B_BPDLCD25_MASK 0x8u
allonq	0:fac0542384d7	2188	#define LCD_WF8B_BPDLCD25_SHIFT 3
allonq	0:fac0542384d7	2189	#define LCD_WF8B_BPDLCD20_MASK 0x8u
allonq	0:fac0542384d7	2190	#define LCD_WF8B_BPDLCD20_SHIFT 3
allonq	0:fac0542384d7	2191	#define LCD_WF8B_BPDLCD2_MASK 0x8u
allonq	0:fac0542384d7	2192	#define LCD_WF8B_BPDLCD2_SHIFT 3
allonq	0:fac0542384d7	2193	#define LCD_WF8B_BPDLCD55_MASK 0x8u
allonq	0:fac0542384d7	2194	#define LCD_WF8B_BPDLCD55_SHIFT 3
allonq	0:fac0542384d7	2195	#define LCD_WF8B_BPDLCD59_MASK 0x8u
allonq	0:fac0542384d7	2196	#define LCD_WF8B_BPDLCD59_SHIFT 3
allonq	0:fac0542384d7	2197	#define LCD_WF8B_BPDLCD5_MASK 0x8u
allonq	0:fac0542384d7	2198	#define LCD_WF8B_BPDLCD5_SHIFT 3
allonq	0:fac0542384d7	2199	#define LCD_WF8B_BPDLCD19_MASK 0x8u
allonq	0:fac0542384d7	2200	#define LCD_WF8B_BPDLCD19_SHIFT 3
allonq	0:fac0542384d7	2201	#define LCD_WF8B_BPDLCD6_MASK 0x8u
allonq	0:fac0542384d7	2202	#define LCD_WF8B_BPDLCD6_SHIFT 3
allonq	0:fac0542384d7	2203	#define LCD_WF8B_BPDLCD26_MASK 0x8u
allonq	0:fac0542384d7	2204	#define LCD_WF8B_BPDLCD26_SHIFT 3
allonq	0:fac0542384d7	2205	#define LCD_WF8B_BPDLCD0_MASK 0x8u
allonq	0:fac0542384d7	2206	#define LCD_WF8B_BPDLCD0_SHIFT 3
allonq	0:fac0542384d7	2207	#define LCD_WF8B_BPDLCD50_MASK 0x8u
allonq	0:fac0542384d7	2208	#define LCD_WF8B_BPDLCD50_SHIFT 3
allonq	0:fac0542384d7	2209	#define LCD_WF8B_BPDLCD46_MASK 0x8u
allonq	0:fac0542384d7	2210	#define LCD_WF8B_BPDLCD46_SHIFT 3
allonq	0:fac0542384d7	2211	#define LCD_WF8B_BPDLCD18_MASK 0x8u
allonq	0:fac0542384d7	2212	#define LCD_WF8B_BPDLCD18_SHIFT 3
allonq	0:fac0542384d7	2213	#define LCD_WF8B_BPDLCD61_MASK 0x8u
allonq	0:fac0542384d7	2214	#define LCD_WF8B_BPDLCD61_SHIFT 3
allonq	0:fac0542384d7	2215	#define LCD_WF8B_BPDLCD9_MASK 0x8u
allonq	0:fac0542384d7	2216	#define LCD_WF8B_BPDLCD9_SHIFT 3
allonq	0:fac0542384d7	2217	#define LCD_WF8B_BPDLCD17_MASK 0x8u
allonq	0:fac0542384d7	2218	#define LCD_WF8B_BPDLCD17_SHIFT 3
allonq	0:fac0542384d7	2219	#define LCD_WF8B_BPDLCD27_MASK 0x8u
allonq	0:fac0542384d7	2220	#define LCD_WF8B_BPDLCD27_SHIFT 3
allonq	0:fac0542384d7	2221	#define LCD_WF8B_BPDLCD53_MASK 0x8u
allonq	0:fac0542384d7	2222	#define LCD_WF8B_BPDLCD53_SHIFT 3
allonq	0:fac0542384d7	2223	#define LCD_WF8B_BPDLCD51_MASK 0x8u
allonq	0:fac0542384d7	2224	#define LCD_WF8B_BPDLCD51_SHIFT 3
allonq	0:fac0542384d7	2225	#define LCD_WF8B_BPDLCD54_MASK 0x8u
allonq	0:fac0542384d7	2226	#define LCD_WF8B_BPDLCD54_SHIFT 3
allonq	0:fac0542384d7	2227	#define LCD_WF8B_BPDLCD13_MASK 0x8u
allonq	0:fac0542384d7	2228	#define LCD_WF8B_BPDLCD13_SHIFT 3
allonq	0:fac0542384d7	2229	#define LCD_WF8B_BPDLCD16_MASK 0x8u
allonq	0:fac0542384d7	2230	#define LCD_WF8B_BPDLCD16_SHIFT 3
allonq	0:fac0542384d7	2231	#define LCD_WF8B_BPDLCD32_MASK 0x8u
allonq	0:fac0542384d7	2232	#define LCD_WF8B_BPDLCD32_SHIFT 3
allonq	0:fac0542384d7	2233	#define LCD_WF8B_BPDLCD14_MASK 0x8u
allonq	0:fac0542384d7	2234	#define LCD_WF8B_BPDLCD14_SHIFT 3
allonq	0:fac0542384d7	2235	#define LCD_WF8B_BPDLCD28_MASK 0x8u
allonq	0:fac0542384d7	2236	#define LCD_WF8B_BPDLCD28_SHIFT 3
allonq	0:fac0542384d7	2237	#define LCD_WF8B_BPDLCD43_MASK 0x8u
allonq	0:fac0542384d7	2238	#define LCD_WF8B_BPDLCD43_SHIFT 3
allonq	0:fac0542384d7	2239	#define LCD_WF8B_BPDLCD4_MASK 0x8u
allonq	0:fac0542384d7	2240	#define LCD_WF8B_BPDLCD4_SHIFT 3
allonq	0:fac0542384d7	2241	#define LCD_WF8B_BPDLCD45_MASK 0x8u
allonq	0:fac0542384d7	2242	#define LCD_WF8B_BPDLCD45_SHIFT 3
allonq	0:fac0542384d7	2243	#define LCD_WF8B_BPDLCD8_MASK 0x8u
allonq	0:fac0542384d7	2244	#define LCD_WF8B_BPDLCD8_SHIFT 3
allonq	0:fac0542384d7	2245	#define LCD_WF8B_BPDLCD62_MASK 0x8u
allonq	0:fac0542384d7	2246	#define LCD_WF8B_BPDLCD62_SHIFT 3
allonq	0:fac0542384d7	2247	#define LCD_WF8B_BPDLCD33_MASK 0x8u
allonq	0:fac0542384d7	2248	#define LCD_WF8B_BPDLCD33_SHIFT 3
allonq	0:fac0542384d7	2249	#define LCD_WF8B_BPDLCD34_MASK 0x8u
allonq	0:fac0542384d7	2250	#define LCD_WF8B_BPDLCD34_SHIFT 3
allonq	0:fac0542384d7	2251	#define LCD_WF8B_BPDLCD29_MASK 0x8u
allonq	0:fac0542384d7	2252	#define LCD_WF8B_BPDLCD29_SHIFT 3
allonq	0:fac0542384d7	2253	#define LCD_WF8B_BPDLCD58_MASK 0x8u
allonq	0:fac0542384d7	2254	#define LCD_WF8B_BPDLCD58_SHIFT 3
allonq	0:fac0542384d7	2255	#define LCD_WF8B_BPDLCD57_MASK 0x8u
allonq	0:fac0542384d7	2256	#define LCD_WF8B_BPDLCD57_SHIFT 3
allonq	0:fac0542384d7	2257	#define LCD_WF8B_BPDLCD42_MASK 0x8u
allonq	0:fac0542384d7	2258	#define LCD_WF8B_BPDLCD42_SHIFT 3
allonq	0:fac0542384d7	2259	#define LCD_WF8B_BPDLCD35_MASK 0x8u
allonq	0:fac0542384d7	2260	#define LCD_WF8B_BPDLCD35_SHIFT 3
allonq	0:fac0542384d7	2261	#define LCD_WF8B_BPDLCD52_MASK 0x8u
allonq	0:fac0542384d7	2262	#define LCD_WF8B_BPDLCD52_SHIFT 3
allonq	0:fac0542384d7	2263	#define LCD_WF8B_BPDLCD7_MASK 0x8u
allonq	0:fac0542384d7	2264	#define LCD_WF8B_BPDLCD7_SHIFT 3
allonq	0:fac0542384d7	2265	#define LCD_WF8B_BPDLCD36_MASK 0x8u
allonq	0:fac0542384d7	2266	#define LCD_WF8B_BPDLCD36_SHIFT 3
allonq	0:fac0542384d7	2267	#define LCD_WF8B_BPDLCD30_MASK 0x8u
allonq	0:fac0542384d7	2268	#define LCD_WF8B_BPDLCD30_SHIFT 3
allonq	0:fac0542384d7	2269	#define LCD_WF8B_BPDLCD41_MASK 0x8u
allonq	0:fac0542384d7	2270	#define LCD_WF8B_BPDLCD41_SHIFT 3
allonq	0:fac0542384d7	2271	#define LCD_WF8B_BPDLCD37_MASK 0x8u
allonq	0:fac0542384d7	2272	#define LCD_WF8B_BPDLCD37_SHIFT 3
allonq	0:fac0542384d7	2273	#define LCD_WF8B_BPDLCD44_MASK 0x8u
allonq	0:fac0542384d7	2274	#define LCD_WF8B_BPDLCD44_SHIFT 3
allonq	0:fac0542384d7	2275	#define LCD_WF8B_BPDLCD63_MASK 0x8u
allonq	0:fac0542384d7	2276	#define LCD_WF8B_BPDLCD63_SHIFT 3
allonq	0:fac0542384d7	2277	#define LCD_WF8B_BPDLCD38_MASK 0x8u
allonq	0:fac0542384d7	2278	#define LCD_WF8B_BPDLCD38_SHIFT 3
allonq	0:fac0542384d7	2279	#define LCD_WF8B_BPDLCD56_MASK 0x8u
allonq	0:fac0542384d7	2280	#define LCD_WF8B_BPDLCD56_SHIFT 3
allonq	0:fac0542384d7	2281	#define LCD_WF8B_BPDLCD40_MASK 0x8u
allonq	0:fac0542384d7	2282	#define LCD_WF8B_BPDLCD40_SHIFT 3
allonq	0:fac0542384d7	2283	#define LCD_WF8B_BPDLCD31_MASK 0x8u
allonq	0:fac0542384d7	2284	#define LCD_WF8B_BPDLCD31_SHIFT 3
allonq	0:fac0542384d7	2285	#define LCD_WF8B_BPDLCD12_MASK 0x8u
allonq	0:fac0542384d7	2286	#define LCD_WF8B_BPDLCD12_SHIFT 3
allonq	0:fac0542384d7	2287	#define LCD_WF8B_BPDLCD39_MASK 0x8u
allonq	0:fac0542384d7	2288	#define LCD_WF8B_BPDLCD39_SHIFT 3
allonq	0:fac0542384d7	2289	#define LCD_WF8B_BPDLCD3_MASK 0x8u
allonq	0:fac0542384d7	2290	#define LCD_WF8B_BPDLCD3_SHIFT 3
allonq	0:fac0542384d7	2291	#define LCD_WF8B_BPDLCD11_MASK 0x8u
allonq	0:fac0542384d7	2292	#define LCD_WF8B_BPDLCD11_SHIFT 3
allonq	0:fac0542384d7	2293	#define LCD_WF8B_BPELCD12_MASK 0x10u
allonq	0:fac0542384d7	2294	#define LCD_WF8B_BPELCD12_SHIFT 4
allonq	0:fac0542384d7	2295	#define LCD_WF8B_BPELCD39_MASK 0x10u
allonq	0:fac0542384d7	2296	#define LCD_WF8B_BPELCD39_SHIFT 4
allonq	0:fac0542384d7	2297	#define LCD_WF8B_BPELCD3_MASK 0x10u
allonq	0:fac0542384d7	2298	#define LCD_WF8B_BPELCD3_SHIFT 4
allonq	0:fac0542384d7	2299	#define LCD_WF8B_BPELCD38_MASK 0x10u
allonq	0:fac0542384d7	2300	#define LCD_WF8B_BPELCD38_SHIFT 4
allonq	0:fac0542384d7	2301	#define LCD_WF8B_BPELCD40_MASK 0x10u
allonq	0:fac0542384d7	2302	#define LCD_WF8B_BPELCD40_SHIFT 4
allonq	0:fac0542384d7	2303	#define LCD_WF8B_BPELCD37_MASK 0x10u
allonq	0:fac0542384d7	2304	#define LCD_WF8B_BPELCD37_SHIFT 4
allonq	0:fac0542384d7	2305	#define LCD_WF8B_BPELCD41_MASK 0x10u
allonq	0:fac0542384d7	2306	#define LCD_WF8B_BPELCD41_SHIFT 4
allonq	0:fac0542384d7	2307	#define LCD_WF8B_BPELCD36_MASK 0x10u
allonq	0:fac0542384d7	2308	#define LCD_WF8B_BPELCD36_SHIFT 4
allonq	0:fac0542384d7	2309	#define LCD_WF8B_BPELCD8_MASK 0x10u
allonq	0:fac0542384d7	2310	#define LCD_WF8B_BPELCD8_SHIFT 4
allonq	0:fac0542384d7	2311	#define LCD_WF8B_BPELCD35_MASK 0x10u
allonq	0:fac0542384d7	2312	#define LCD_WF8B_BPELCD35_SHIFT 4
allonq	0:fac0542384d7	2313	#define LCD_WF8B_BPELCD42_MASK 0x10u
allonq	0:fac0542384d7	2314	#define LCD_WF8B_BPELCD42_SHIFT 4
allonq	0:fac0542384d7	2315	#define LCD_WF8B_BPELCD34_MASK 0x10u
allonq	0:fac0542384d7	2316	#define LCD_WF8B_BPELCD34_SHIFT 4
allonq	0:fac0542384d7	2317	#define LCD_WF8B_BPELCD33_MASK 0x10u
allonq	0:fac0542384d7	2318	#define LCD_WF8B_BPELCD33_SHIFT 4
allonq	0:fac0542384d7	2319	#define LCD_WF8B_BPELCD11_MASK 0x10u
allonq	0:fac0542384d7	2320	#define LCD_WF8B_BPELCD11_SHIFT 4
allonq	0:fac0542384d7	2321	#define LCD_WF8B_BPELCD43_MASK 0x10u
allonq	0:fac0542384d7	2322	#define LCD_WF8B_BPELCD43_SHIFT 4
allonq	0:fac0542384d7	2323	#define LCD_WF8B_BPELCD32_MASK 0x10u
allonq	0:fac0542384d7	2324	#define LCD_WF8B_BPELCD32_SHIFT 4
allonq	0:fac0542384d7	2325	#define LCD_WF8B_BPELCD31_MASK 0x10u
allonq	0:fac0542384d7	2326	#define LCD_WF8B_BPELCD31_SHIFT 4
allonq	0:fac0542384d7	2327	#define LCD_WF8B_BPELCD44_MASK 0x10u
allonq	0:fac0542384d7	2328	#define LCD_WF8B_BPELCD44_SHIFT 4
allonq	0:fac0542384d7	2329	#define LCD_WF8B_BPELCD30_MASK 0x10u
allonq	0:fac0542384d7	2330	#define LCD_WF8B_BPELCD30_SHIFT 4
allonq	0:fac0542384d7	2331	#define LCD_WF8B_BPELCD29_MASK 0x10u
allonq	0:fac0542384d7	2332	#define LCD_WF8B_BPELCD29_SHIFT 4
allonq	0:fac0542384d7	2333	#define LCD_WF8B_BPELCD7_MASK 0x10u
allonq	0:fac0542384d7	2334	#define LCD_WF8B_BPELCD7_SHIFT 4
allonq	0:fac0542384d7	2335	#define LCD_WF8B_BPELCD45_MASK 0x10u
allonq	0:fac0542384d7	2336	#define LCD_WF8B_BPELCD45_SHIFT 4
allonq	0:fac0542384d7	2337	#define LCD_WF8B_BPELCD28_MASK 0x10u
allonq	0:fac0542384d7	2338	#define LCD_WF8B_BPELCD28_SHIFT 4
allonq	0:fac0542384d7	2339	#define LCD_WF8B_BPELCD2_MASK 0x10u
allonq	0:fac0542384d7	2340	#define LCD_WF8B_BPELCD2_SHIFT 4
allonq	0:fac0542384d7	2341	#define LCD_WF8B_BPELCD27_MASK 0x10u
allonq	0:fac0542384d7	2342	#define LCD_WF8B_BPELCD27_SHIFT 4
allonq	0:fac0542384d7	2343	#define LCD_WF8B_BPELCD46_MASK 0x10u
allonq	0:fac0542384d7	2344	#define LCD_WF8B_BPELCD46_SHIFT 4
allonq	0:fac0542384d7	2345	#define LCD_WF8B_BPELCD26_MASK 0x10u
allonq	0:fac0542384d7	2346	#define LCD_WF8B_BPELCD26_SHIFT 4
allonq	0:fac0542384d7	2347	#define LCD_WF8B_BPELCD10_MASK 0x10u
allonq	0:fac0542384d7	2348	#define LCD_WF8B_BPELCD10_SHIFT 4
allonq	0:fac0542384d7	2349	#define LCD_WF8B_BPELCD13_MASK 0x10u
allonq	0:fac0542384d7	2350	#define LCD_WF8B_BPELCD13_SHIFT 4
allonq	0:fac0542384d7	2351	#define LCD_WF8B_BPELCD25_MASK 0x10u
allonq	0:fac0542384d7	2352	#define LCD_WF8B_BPELCD25_SHIFT 4
allonq	0:fac0542384d7	2353	#define LCD_WF8B_BPELCD5_MASK 0x10u
allonq	0:fac0542384d7	2354	#define LCD_WF8B_BPELCD5_SHIFT 4
allonq	0:fac0542384d7	2355	#define LCD_WF8B_BPELCD24_MASK 0x10u
allonq	0:fac0542384d7	2356	#define LCD_WF8B_BPELCD24_SHIFT 4
allonq	0:fac0542384d7	2357	#define LCD_WF8B_BPELCD47_MASK 0x10u
allonq	0:fac0542384d7	2358	#define LCD_WF8B_BPELCD47_SHIFT 4
allonq	0:fac0542384d7	2359	#define LCD_WF8B_BPELCD23_MASK 0x10u
allonq	0:fac0542384d7	2360	#define LCD_WF8B_BPELCD23_SHIFT 4
allonq	0:fac0542384d7	2361	#define LCD_WF8B_BPELCD22_MASK 0x10u
allonq	0:fac0542384d7	2362	#define LCD_WF8B_BPELCD22_SHIFT 4
allonq	0:fac0542384d7	2363	#define LCD_WF8B_BPELCD48_MASK 0x10u
allonq	0:fac0542384d7	2364	#define LCD_WF8B_BPELCD48_SHIFT 4
allonq	0:fac0542384d7	2365	#define LCD_WF8B_BPELCD21_MASK 0x10u
allonq	0:fac0542384d7	2366	#define LCD_WF8B_BPELCD21_SHIFT 4
allonq	0:fac0542384d7	2367	#define LCD_WF8B_BPELCD49_MASK 0x10u
allonq	0:fac0542384d7	2368	#define LCD_WF8B_BPELCD49_SHIFT 4
allonq	0:fac0542384d7	2369	#define LCD_WF8B_BPELCD20_MASK 0x10u
allonq	0:fac0542384d7	2370	#define LCD_WF8B_BPELCD20_SHIFT 4
allonq	0:fac0542384d7	2371	#define LCD_WF8B_BPELCD19_MASK 0x10u
allonq	0:fac0542384d7	2372	#define LCD_WF8B_BPELCD19_SHIFT 4
allonq	0:fac0542384d7	2373	#define LCD_WF8B_BPELCD9_MASK 0x10u
allonq	0:fac0542384d7	2374	#define LCD_WF8B_BPELCD9_SHIFT 4
allonq	0:fac0542384d7	2375	#define LCD_WF8B_BPELCD50_MASK 0x10u
allonq	0:fac0542384d7	2376	#define LCD_WF8B_BPELCD50_SHIFT 4
allonq	0:fac0542384d7	2377	#define LCD_WF8B_BPELCD18_MASK 0x10u
allonq	0:fac0542384d7	2378	#define LCD_WF8B_BPELCD18_SHIFT 4
allonq	0:fac0542384d7	2379	#define LCD_WF8B_BPELCD6_MASK 0x10u
allonq	0:fac0542384d7	2380	#define LCD_WF8B_BPELCD6_SHIFT 4
allonq	0:fac0542384d7	2381	#define LCD_WF8B_BPELCD17_MASK 0x10u
allonq	0:fac0542384d7	2382	#define LCD_WF8B_BPELCD17_SHIFT 4
allonq	0:fac0542384d7	2383	#define LCD_WF8B_BPELCD51_MASK 0x10u
allonq	0:fac0542384d7	2384	#define LCD_WF8B_BPELCD51_SHIFT 4
allonq	0:fac0542384d7	2385	#define LCD_WF8B_BPELCD16_MASK 0x10u
allonq	0:fac0542384d7	2386	#define LCD_WF8B_BPELCD16_SHIFT 4
allonq	0:fac0542384d7	2387	#define LCD_WF8B_BPELCD56_MASK 0x10u
allonq	0:fac0542384d7	2388	#define LCD_WF8B_BPELCD56_SHIFT 4
allonq	0:fac0542384d7	2389	#define LCD_WF8B_BPELCD57_MASK 0x10u
allonq	0:fac0542384d7	2390	#define LCD_WF8B_BPELCD57_SHIFT 4
allonq	0:fac0542384d7	2391	#define LCD_WF8B_BPELCD52_MASK 0x10u
allonq	0:fac0542384d7	2392	#define LCD_WF8B_BPELCD52_SHIFT 4
allonq	0:fac0542384d7	2393	#define LCD_WF8B_BPELCD1_MASK 0x10u
allonq	0:fac0542384d7	2394	#define LCD_WF8B_BPELCD1_SHIFT 4
allonq	0:fac0542384d7	2395	#define LCD_WF8B_BPELCD58_MASK 0x10u
allonq	0:fac0542384d7	2396	#define LCD_WF8B_BPELCD58_SHIFT 4
allonq	0:fac0542384d7	2397	#define LCD_WF8B_BPELCD59_MASK 0x10u
allonq	0:fac0542384d7	2398	#define LCD_WF8B_BPELCD59_SHIFT 4
allonq	0:fac0542384d7	2399	#define LCD_WF8B_BPELCD53_MASK 0x10u
allonq	0:fac0542384d7	2400	#define LCD_WF8B_BPELCD53_SHIFT 4
allonq	0:fac0542384d7	2401	#define LCD_WF8B_BPELCD14_MASK 0x10u
allonq	0:fac0542384d7	2402	#define LCD_WF8B_BPELCD14_SHIFT 4
allonq	0:fac0542384d7	2403	#define LCD_WF8B_BPELCD0_MASK 0x10u
allonq	0:fac0542384d7	2404	#define LCD_WF8B_BPELCD0_SHIFT 4
allonq	0:fac0542384d7	2405	#define LCD_WF8B_BPELCD60_MASK 0x10u
allonq	0:fac0542384d7	2406	#define LCD_WF8B_BPELCD60_SHIFT 4
allonq	0:fac0542384d7	2407	#define LCD_WF8B_BPELCD15_MASK 0x10u
allonq	0:fac0542384d7	2408	#define LCD_WF8B_BPELCD15_SHIFT 4
allonq	0:fac0542384d7	2409	#define LCD_WF8B_BPELCD61_MASK 0x10u
allonq	0:fac0542384d7	2410	#define LCD_WF8B_BPELCD61_SHIFT 4
allonq	0:fac0542384d7	2411	#define LCD_WF8B_BPELCD54_MASK 0x10u
allonq	0:fac0542384d7	2412	#define LCD_WF8B_BPELCD54_SHIFT 4
allonq	0:fac0542384d7	2413	#define LCD_WF8B_BPELCD62_MASK 0x10u
allonq	0:fac0542384d7	2414	#define LCD_WF8B_BPELCD62_SHIFT 4
allonq	0:fac0542384d7	2415	#define LCD_WF8B_BPELCD63_MASK 0x10u
allonq	0:fac0542384d7	2416	#define LCD_WF8B_BPELCD63_SHIFT 4
allonq	0:fac0542384d7	2417	#define LCD_WF8B_BPELCD55_MASK 0x10u
allonq	0:fac0542384d7	2418	#define LCD_WF8B_BPELCD55_SHIFT 4
allonq	0:fac0542384d7	2419	#define LCD_WF8B_BPELCD4_MASK 0x10u
allonq	0:fac0542384d7	2420	#define LCD_WF8B_BPELCD4_SHIFT 4
allonq	0:fac0542384d7	2421	#define LCD_WF8B_BPFLCD13_MASK 0x20u
allonq	0:fac0542384d7	2422	#define LCD_WF8B_BPFLCD13_SHIFT 5
allonq	0:fac0542384d7	2423	#define LCD_WF8B_BPFLCD39_MASK 0x20u
allonq	0:fac0542384d7	2424	#define LCD_WF8B_BPFLCD39_SHIFT 5
allonq	0:fac0542384d7	2425	#define LCD_WF8B_BPFLCD55_MASK 0x20u
allonq	0:fac0542384d7	2426	#define LCD_WF8B_BPFLCD55_SHIFT 5
allonq	0:fac0542384d7	2427	#define LCD_WF8B_BPFLCD47_MASK 0x20u
allonq	0:fac0542384d7	2428	#define LCD_WF8B_BPFLCD47_SHIFT 5
allonq	0:fac0542384d7	2429	#define LCD_WF8B_BPFLCD63_MASK 0x20u
allonq	0:fac0542384d7	2430	#define LCD_WF8B_BPFLCD63_SHIFT 5
allonq	0:fac0542384d7	2431	#define LCD_WF8B_BPFLCD43_MASK 0x20u
allonq	0:fac0542384d7	2432	#define LCD_WF8B_BPFLCD43_SHIFT 5
allonq	0:fac0542384d7	2433	#define LCD_WF8B_BPFLCD5_MASK 0x20u
allonq	0:fac0542384d7	2434	#define LCD_WF8B_BPFLCD5_SHIFT 5
allonq	0:fac0542384d7	2435	#define LCD_WF8B_BPFLCD62_MASK 0x20u
allonq	0:fac0542384d7	2436	#define LCD_WF8B_BPFLCD62_SHIFT 5
allonq	0:fac0542384d7	2437	#define LCD_WF8B_BPFLCD14_MASK 0x20u
allonq	0:fac0542384d7	2438	#define LCD_WF8B_BPFLCD14_SHIFT 5
allonq	0:fac0542384d7	2439	#define LCD_WF8B_BPFLCD24_MASK 0x20u
allonq	0:fac0542384d7	2440	#define LCD_WF8B_BPFLCD24_SHIFT 5
allonq	0:fac0542384d7	2441	#define LCD_WF8B_BPFLCD54_MASK 0x20u
allonq	0:fac0542384d7	2442	#define LCD_WF8B_BPFLCD54_SHIFT 5
allonq	0:fac0542384d7	2443	#define LCD_WF8B_BPFLCD15_MASK 0x20u
allonq	0:fac0542384d7	2444	#define LCD_WF8B_BPFLCD15_SHIFT 5
allonq	0:fac0542384d7	2445	#define LCD_WF8B_BPFLCD32_MASK 0x20u
allonq	0:fac0542384d7	2446	#define LCD_WF8B_BPFLCD32_SHIFT 5
allonq	0:fac0542384d7	2447	#define LCD_WF8B_BPFLCD61_MASK 0x20u
allonq	0:fac0542384d7	2448	#define LCD_WF8B_BPFLCD61_SHIFT 5
allonq	0:fac0542384d7	2449	#define LCD_WF8B_BPFLCD25_MASK 0x20u
allonq	0:fac0542384d7	2450	#define LCD_WF8B_BPFLCD25_SHIFT 5
allonq	0:fac0542384d7	2451	#define LCD_WF8B_BPFLCD60_MASK 0x20u
allonq	0:fac0542384d7	2452	#define LCD_WF8B_BPFLCD60_SHIFT 5
allonq	0:fac0542384d7	2453	#define LCD_WF8B_BPFLCD41_MASK 0x20u
allonq	0:fac0542384d7	2454	#define LCD_WF8B_BPFLCD41_SHIFT 5
allonq	0:fac0542384d7	2455	#define LCD_WF8B_BPFLCD33_MASK 0x20u
allonq	0:fac0542384d7	2456	#define LCD_WF8B_BPFLCD33_SHIFT 5
allonq	0:fac0542384d7	2457	#define LCD_WF8B_BPFLCD53_MASK 0x20u
allonq	0:fac0542384d7	2458	#define LCD_WF8B_BPFLCD53_SHIFT 5
allonq	0:fac0542384d7	2459	#define LCD_WF8B_BPFLCD59_MASK 0x20u
allonq	0:fac0542384d7	2460	#define LCD_WF8B_BPFLCD59_SHIFT 5
allonq	0:fac0542384d7	2461	#define LCD_WF8B_BPFLCD0_MASK 0x20u
allonq	0:fac0542384d7	2462	#define LCD_WF8B_BPFLCD0_SHIFT 5
allonq	0:fac0542384d7	2463	#define LCD_WF8B_BPFLCD46_MASK 0x20u
allonq	0:fac0542384d7	2464	#define LCD_WF8B_BPFLCD46_SHIFT 5
allonq	0:fac0542384d7	2465	#define LCD_WF8B_BPFLCD58_MASK 0x20u
allonq	0:fac0542384d7	2466	#define LCD_WF8B_BPFLCD58_SHIFT 5
allonq	0:fac0542384d7	2467	#define LCD_WF8B_BPFLCD26_MASK 0x20u
allonq	0:fac0542384d7	2468	#define LCD_WF8B_BPFLCD26_SHIFT 5
allonq	0:fac0542384d7	2469	#define LCD_WF8B_BPFLCD36_MASK 0x20u
allonq	0:fac0542384d7	2470	#define LCD_WF8B_BPFLCD36_SHIFT 5
allonq	0:fac0542384d7	2471	#define LCD_WF8B_BPFLCD10_MASK 0x20u
allonq	0:fac0542384d7	2472	#define LCD_WF8B_BPFLCD10_SHIFT 5
allonq	0:fac0542384d7	2473	#define LCD_WF8B_BPFLCD52_MASK 0x20u
allonq	0:fac0542384d7	2474	#define LCD_WF8B_BPFLCD52_SHIFT 5
allonq	0:fac0542384d7	2475	#define LCD_WF8B_BPFLCD57_MASK 0x20u
allonq	0:fac0542384d7	2476	#define LCD_WF8B_BPFLCD57_SHIFT 5
allonq	0:fac0542384d7	2477	#define LCD_WF8B_BPFLCD27_MASK 0x20u
allonq	0:fac0542384d7	2478	#define LCD_WF8B_BPFLCD27_SHIFT 5
allonq	0:fac0542384d7	2479	#define LCD_WF8B_BPFLCD11_MASK 0x20u
allonq	0:fac0542384d7	2480	#define LCD_WF8B_BPFLCD11_SHIFT 5
allonq	0:fac0542384d7	2481	#define LCD_WF8B_BPFLCD56_MASK 0x20u
allonq	0:fac0542384d7	2482	#define LCD_WF8B_BPFLCD56_SHIFT 5
allonq	0:fac0542384d7	2483	#define LCD_WF8B_BPFLCD1_MASK 0x20u
allonq	0:fac0542384d7	2484	#define LCD_WF8B_BPFLCD1_SHIFT 5
allonq	0:fac0542384d7	2485	#define LCD_WF8B_BPFLCD8_MASK 0x20u
allonq	0:fac0542384d7	2486	#define LCD_WF8B_BPFLCD8_SHIFT 5
allonq	0:fac0542384d7	2487	#define LCD_WF8B_BPFLCD40_MASK 0x20u
allonq	0:fac0542384d7	2488	#define LCD_WF8B_BPFLCD40_SHIFT 5
allonq	0:fac0542384d7	2489	#define LCD_WF8B_BPFLCD51_MASK 0x20u
allonq	0:fac0542384d7	2490	#define LCD_WF8B_BPFLCD51_SHIFT 5
allonq	0:fac0542384d7	2491	#define LCD_WF8B_BPFLCD16_MASK 0x20u
allonq	0:fac0542384d7	2492	#define LCD_WF8B_BPFLCD16_SHIFT 5
allonq	0:fac0542384d7	2493	#define LCD_WF8B_BPFLCD45_MASK 0x20u
allonq	0:fac0542384d7	2494	#define LCD_WF8B_BPFLCD45_SHIFT 5
allonq	0:fac0542384d7	2495	#define LCD_WF8B_BPFLCD6_MASK 0x20u
allonq	0:fac0542384d7	2496	#define LCD_WF8B_BPFLCD6_SHIFT 5
allonq	0:fac0542384d7	2497	#define LCD_WF8B_BPFLCD17_MASK 0x20u
allonq	0:fac0542384d7	2498	#define LCD_WF8B_BPFLCD17_SHIFT 5
allonq	0:fac0542384d7	2499	#define LCD_WF8B_BPFLCD28_MASK 0x20u
allonq	0:fac0542384d7	2500	#define LCD_WF8B_BPFLCD28_SHIFT 5
allonq	0:fac0542384d7	2501	#define LCD_WF8B_BPFLCD42_MASK 0x20u
allonq	0:fac0542384d7	2502	#define LCD_WF8B_BPFLCD42_SHIFT 5
allonq	0:fac0542384d7	2503	#define LCD_WF8B_BPFLCD29_MASK 0x20u
allonq	0:fac0542384d7	2504	#define LCD_WF8B_BPFLCD29_SHIFT 5
allonq	0:fac0542384d7	2505	#define LCD_WF8B_BPFLCD50_MASK 0x20u
allonq	0:fac0542384d7	2506	#define LCD_WF8B_BPFLCD50_SHIFT 5
allonq	0:fac0542384d7	2507	#define LCD_WF8B_BPFLCD18_MASK 0x20u
allonq	0:fac0542384d7	2508	#define LCD_WF8B_BPFLCD18_SHIFT 5
allonq	0:fac0542384d7	2509	#define LCD_WF8B_BPFLCD34_MASK 0x20u
allonq	0:fac0542384d7	2510	#define LCD_WF8B_BPFLCD34_SHIFT 5
allonq	0:fac0542384d7	2511	#define LCD_WF8B_BPFLCD19_MASK 0x20u
allonq	0:fac0542384d7	2512	#define LCD_WF8B_BPFLCD19_SHIFT 5
allonq	0:fac0542384d7	2513	#define LCD_WF8B_BPFLCD2_MASK 0x20u
allonq	0:fac0542384d7	2514	#define LCD_WF8B_BPFLCD2_SHIFT 5
allonq	0:fac0542384d7	2515	#define LCD_WF8B_BPFLCD9_MASK 0x20u
allonq	0:fac0542384d7	2516	#define LCD_WF8B_BPFLCD9_SHIFT 5
allonq	0:fac0542384d7	2517	#define LCD_WF8B_BPFLCD3_MASK 0x20u
allonq	0:fac0542384d7	2518	#define LCD_WF8B_BPFLCD3_SHIFT 5
allonq	0:fac0542384d7	2519	#define LCD_WF8B_BPFLCD37_MASK 0x20u
allonq	0:fac0542384d7	2520	#define LCD_WF8B_BPFLCD37_SHIFT 5
allonq	0:fac0542384d7	2521	#define LCD_WF8B_BPFLCD49_MASK 0x20u
allonq	0:fac0542384d7	2522	#define LCD_WF8B_BPFLCD49_SHIFT 5
allonq	0:fac0542384d7	2523	#define LCD_WF8B_BPFLCD20_MASK 0x20u
allonq	0:fac0542384d7	2524	#define LCD_WF8B_BPFLCD20_SHIFT 5
allonq	0:fac0542384d7	2525	#define LCD_WF8B_BPFLCD44_MASK 0x20u
allonq	0:fac0542384d7	2526	#define LCD_WF8B_BPFLCD44_SHIFT 5
allonq	0:fac0542384d7	2527	#define LCD_WF8B_BPFLCD30_MASK 0x20u
allonq	0:fac0542384d7	2528	#define LCD_WF8B_BPFLCD30_SHIFT 5
allonq	0:fac0542384d7	2529	#define LCD_WF8B_BPFLCD21_MASK 0x20u
allonq	0:fac0542384d7	2530	#define LCD_WF8B_BPFLCD21_SHIFT 5
allonq	0:fac0542384d7	2531	#define LCD_WF8B_BPFLCD35_MASK 0x20u
allonq	0:fac0542384d7	2532	#define LCD_WF8B_BPFLCD35_SHIFT 5
allonq	0:fac0542384d7	2533	#define LCD_WF8B_BPFLCD4_MASK 0x20u
allonq	0:fac0542384d7	2534	#define LCD_WF8B_BPFLCD4_SHIFT 5
allonq	0:fac0542384d7	2535	#define LCD_WF8B_BPFLCD31_MASK 0x20u
allonq	0:fac0542384d7	2536	#define LCD_WF8B_BPFLCD31_SHIFT 5
allonq	0:fac0542384d7	2537	#define LCD_WF8B_BPFLCD48_MASK 0x20u
allonq	0:fac0542384d7	2538	#define LCD_WF8B_BPFLCD48_SHIFT 5
allonq	0:fac0542384d7	2539	#define LCD_WF8B_BPFLCD7_MASK 0x20u
allonq	0:fac0542384d7	2540	#define LCD_WF8B_BPFLCD7_SHIFT 5
allonq	0:fac0542384d7	2541	#define LCD_WF8B_BPFLCD22_MASK 0x20u
allonq	0:fac0542384d7	2542	#define LCD_WF8B_BPFLCD22_SHIFT 5
allonq	0:fac0542384d7	2543	#define LCD_WF8B_BPFLCD38_MASK 0x20u
allonq	0:fac0542384d7	2544	#define LCD_WF8B_BPFLCD38_SHIFT 5
allonq	0:fac0542384d7	2545	#define LCD_WF8B_BPFLCD12_MASK 0x20u
allonq	0:fac0542384d7	2546	#define LCD_WF8B_BPFLCD12_SHIFT 5
allonq	0:fac0542384d7	2547	#define LCD_WF8B_BPFLCD23_MASK 0x20u
allonq	0:fac0542384d7	2548	#define LCD_WF8B_BPFLCD23_SHIFT 5
allonq	0:fac0542384d7	2549	#define LCD_WF8B_BPGLCD14_MASK 0x40u
allonq	0:fac0542384d7	2550	#define LCD_WF8B_BPGLCD14_SHIFT 6
allonq	0:fac0542384d7	2551	#define LCD_WF8B_BPGLCD55_MASK 0x40u
allonq	0:fac0542384d7	2552	#define LCD_WF8B_BPGLCD55_SHIFT 6
allonq	0:fac0542384d7	2553	#define LCD_WF8B_BPGLCD63_MASK 0x40u
allonq	0:fac0542384d7	2554	#define LCD_WF8B_BPGLCD63_SHIFT 6
allonq	0:fac0542384d7	2555	#define LCD_WF8B_BPGLCD15_MASK 0x40u
allonq	0:fac0542384d7	2556	#define LCD_WF8B_BPGLCD15_SHIFT 6
allonq	0:fac0542384d7	2557	#define LCD_WF8B_BPGLCD62_MASK 0x40u
allonq	0:fac0542384d7	2558	#define LCD_WF8B_BPGLCD62_SHIFT 6
allonq	0:fac0542384d7	2559	#define LCD_WF8B_BPGLCD54_MASK 0x40u
allonq	0:fac0542384d7	2560	#define LCD_WF8B_BPGLCD54_SHIFT 6
allonq	0:fac0542384d7	2561	#define LCD_WF8B_BPGLCD61_MASK 0x40u
allonq	0:fac0542384d7	2562	#define LCD_WF8B_BPGLCD61_SHIFT 6
allonq	0:fac0542384d7	2563	#define LCD_WF8B_BPGLCD60_MASK 0x40u
allonq	0:fac0542384d7	2564	#define LCD_WF8B_BPGLCD60_SHIFT 6
allonq	0:fac0542384d7	2565	#define LCD_WF8B_BPGLCD59_MASK 0x40u
allonq	0:fac0542384d7	2566	#define LCD_WF8B_BPGLCD59_SHIFT 6
allonq	0:fac0542384d7	2567	#define LCD_WF8B_BPGLCD53_MASK 0x40u
allonq	0:fac0542384d7	2568	#define LCD_WF8B_BPGLCD53_SHIFT 6
allonq	0:fac0542384d7	2569	#define LCD_WF8B_BPGLCD58_MASK 0x40u
allonq	0:fac0542384d7	2570	#define LCD_WF8B_BPGLCD58_SHIFT 6
allonq	0:fac0542384d7	2571	#define LCD_WF8B_BPGLCD0_MASK 0x40u
allonq	0:fac0542384d7	2572	#define LCD_WF8B_BPGLCD0_SHIFT 6
allonq	0:fac0542384d7	2573	#define LCD_WF8B_BPGLCD57_MASK 0x40u
allonq	0:fac0542384d7	2574	#define LCD_WF8B_BPGLCD57_SHIFT 6
allonq	0:fac0542384d7	2575	#define LCD_WF8B_BPGLCD52_MASK 0x40u
allonq	0:fac0542384d7	2576	#define LCD_WF8B_BPGLCD52_SHIFT 6
allonq	0:fac0542384d7	2577	#define LCD_WF8B_BPGLCD7_MASK 0x40u
allonq	0:fac0542384d7	2578	#define LCD_WF8B_BPGLCD7_SHIFT 6
allonq	0:fac0542384d7	2579	#define LCD_WF8B_BPGLCD56_MASK 0x40u
allonq	0:fac0542384d7	2580	#define LCD_WF8B_BPGLCD56_SHIFT 6
allonq	0:fac0542384d7	2581	#define LCD_WF8B_BPGLCD6_MASK 0x40u
allonq	0:fac0542384d7	2582	#define LCD_WF8B_BPGLCD6_SHIFT 6
allonq	0:fac0542384d7	2583	#define LCD_WF8B_BPGLCD51_MASK 0x40u
allonq	0:fac0542384d7	2584	#define LCD_WF8B_BPGLCD51_SHIFT 6
allonq	0:fac0542384d7	2585	#define LCD_WF8B_BPGLCD16_MASK 0x40u
allonq	0:fac0542384d7	2586	#define LCD_WF8B_BPGLCD16_SHIFT 6
allonq	0:fac0542384d7	2587	#define LCD_WF8B_BPGLCD1_MASK 0x40u
allonq	0:fac0542384d7	2588	#define LCD_WF8B_BPGLCD1_SHIFT 6
allonq	0:fac0542384d7	2589	#define LCD_WF8B_BPGLCD17_MASK 0x40u
allonq	0:fac0542384d7	2590	#define LCD_WF8B_BPGLCD17_SHIFT 6
allonq	0:fac0542384d7	2591	#define LCD_WF8B_BPGLCD50_MASK 0x40u
allonq	0:fac0542384d7	2592	#define LCD_WF8B_BPGLCD50_SHIFT 6
allonq	0:fac0542384d7	2593	#define LCD_WF8B_BPGLCD18_MASK 0x40u
allonq	0:fac0542384d7	2594	#define LCD_WF8B_BPGLCD18_SHIFT 6
allonq	0:fac0542384d7	2595	#define LCD_WF8B_BPGLCD19_MASK 0x40u
allonq	0:fac0542384d7	2596	#define LCD_WF8B_BPGLCD19_SHIFT 6
allonq	0:fac0542384d7	2597	#define LCD_WF8B_BPGLCD8_MASK 0x40u
allonq	0:fac0542384d7	2598	#define LCD_WF8B_BPGLCD8_SHIFT 6
allonq	0:fac0542384d7	2599	#define LCD_WF8B_BPGLCD49_MASK 0x40u
allonq	0:fac0542384d7	2600	#define LCD_WF8B_BPGLCD49_SHIFT 6
allonq	0:fac0542384d7	2601	#define LCD_WF8B_BPGLCD20_MASK 0x40u
allonq	0:fac0542384d7	2602	#define LCD_WF8B_BPGLCD20_SHIFT 6
allonq	0:fac0542384d7	2603	#define LCD_WF8B_BPGLCD9_MASK 0x40u
allonq	0:fac0542384d7	2604	#define LCD_WF8B_BPGLCD9_SHIFT 6
allonq	0:fac0542384d7	2605	#define LCD_WF8B_BPGLCD21_MASK 0x40u
allonq	0:fac0542384d7	2606	#define LCD_WF8B_BPGLCD21_SHIFT 6
allonq	0:fac0542384d7	2607	#define LCD_WF8B_BPGLCD13_MASK 0x40u
allonq	0:fac0542384d7	2608	#define LCD_WF8B_BPGLCD13_SHIFT 6
allonq	0:fac0542384d7	2609	#define LCD_WF8B_BPGLCD48_MASK 0x40u
allonq	0:fac0542384d7	2610	#define LCD_WF8B_BPGLCD48_SHIFT 6
allonq	0:fac0542384d7	2611	#define LCD_WF8B_BPGLCD22_MASK 0x40u
allonq	0:fac0542384d7	2612	#define LCD_WF8B_BPGLCD22_SHIFT 6
allonq	0:fac0542384d7	2613	#define LCD_WF8B_BPGLCD5_MASK 0x40u
allonq	0:fac0542384d7	2614	#define LCD_WF8B_BPGLCD5_SHIFT 6
allonq	0:fac0542384d7	2615	#define LCD_WF8B_BPGLCD47_MASK 0x40u
allonq	0:fac0542384d7	2616	#define LCD_WF8B_BPGLCD47_SHIFT 6
allonq	0:fac0542384d7	2617	#define LCD_WF8B_BPGLCD23_MASK 0x40u
allonq	0:fac0542384d7	2618	#define LCD_WF8B_BPGLCD23_SHIFT 6
allonq	0:fac0542384d7	2619	#define LCD_WF8B_BPGLCD24_MASK 0x40u
allonq	0:fac0542384d7	2620	#define LCD_WF8B_BPGLCD24_SHIFT 6
allonq	0:fac0542384d7	2621	#define LCD_WF8B_BPGLCD25_MASK 0x40u
allonq	0:fac0542384d7	2622	#define LCD_WF8B_BPGLCD25_SHIFT 6
allonq	0:fac0542384d7	2623	#define LCD_WF8B_BPGLCD46_MASK 0x40u
allonq	0:fac0542384d7	2624	#define LCD_WF8B_BPGLCD46_SHIFT 6
allonq	0:fac0542384d7	2625	#define LCD_WF8B_BPGLCD26_MASK 0x40u
allonq	0:fac0542384d7	2626	#define LCD_WF8B_BPGLCD26_SHIFT 6
allonq	0:fac0542384d7	2627	#define LCD_WF8B_BPGLCD27_MASK 0x40u
allonq	0:fac0542384d7	2628	#define LCD_WF8B_BPGLCD27_SHIFT 6
allonq	0:fac0542384d7	2629	#define LCD_WF8B_BPGLCD10_MASK 0x40u
allonq	0:fac0542384d7	2630	#define LCD_WF8B_BPGLCD10_SHIFT 6
allonq	0:fac0542384d7	2631	#define LCD_WF8B_BPGLCD45_MASK 0x40u
allonq	0:fac0542384d7	2632	#define LCD_WF8B_BPGLCD45_SHIFT 6
allonq	0:fac0542384d7	2633	#define LCD_WF8B_BPGLCD28_MASK 0x40u
allonq	0:fac0542384d7	2634	#define LCD_WF8B_BPGLCD28_SHIFT 6
allonq	0:fac0542384d7	2635	#define LCD_WF8B_BPGLCD29_MASK 0x40u
allonq	0:fac0542384d7	2636	#define LCD_WF8B_BPGLCD29_SHIFT 6
allonq	0:fac0542384d7	2637	#define LCD_WF8B_BPGLCD4_MASK 0x40u
allonq	0:fac0542384d7	2638	#define LCD_WF8B_BPGLCD4_SHIFT 6
allonq	0:fac0542384d7	2639	#define LCD_WF8B_BPGLCD44_MASK 0x40u
allonq	0:fac0542384d7	2640	#define LCD_WF8B_BPGLCD44_SHIFT 6
allonq	0:fac0542384d7	2641	#define LCD_WF8B_BPGLCD30_MASK 0x40u
allonq	0:fac0542384d7	2642	#define LCD_WF8B_BPGLCD30_SHIFT 6
allonq	0:fac0542384d7	2643	#define LCD_WF8B_BPGLCD2_MASK 0x40u
allonq	0:fac0542384d7	2644	#define LCD_WF8B_BPGLCD2_SHIFT 6
allonq	0:fac0542384d7	2645	#define LCD_WF8B_BPGLCD31_MASK 0x40u
allonq	0:fac0542384d7	2646	#define LCD_WF8B_BPGLCD31_SHIFT 6
allonq	0:fac0542384d7	2647	#define LCD_WF8B_BPGLCD43_MASK 0x40u
allonq	0:fac0542384d7	2648	#define LCD_WF8B_BPGLCD43_SHIFT 6
allonq	0:fac0542384d7	2649	#define LCD_WF8B_BPGLCD32_MASK 0x40u
allonq	0:fac0542384d7	2650	#define LCD_WF8B_BPGLCD32_SHIFT 6
allonq	0:fac0542384d7	2651	#define LCD_WF8B_BPGLCD33_MASK 0x40u
allonq	0:fac0542384d7	2652	#define LCD_WF8B_BPGLCD33_SHIFT 6
allonq	0:fac0542384d7	2653	#define LCD_WF8B_BPGLCD42_MASK 0x40u
allonq	0:fac0542384d7	2654	#define LCD_WF8B_BPGLCD42_SHIFT 6
allonq	0:fac0542384d7	2655	#define LCD_WF8B_BPGLCD34_MASK 0x40u
allonq	0:fac0542384d7	2656	#define LCD_WF8B_BPGLCD34_SHIFT 6
allonq	0:fac0542384d7	2657	#define LCD_WF8B_BPGLCD11_MASK 0x40u
allonq	0:fac0542384d7	2658	#define LCD_WF8B_BPGLCD11_SHIFT 6
allonq	0:fac0542384d7	2659	#define LCD_WF8B_BPGLCD35_MASK 0x40u
allonq	0:fac0542384d7	2660	#define LCD_WF8B_BPGLCD35_SHIFT 6
allonq	0:fac0542384d7	2661	#define LCD_WF8B_BPGLCD12_MASK 0x40u
allonq	0:fac0542384d7	2662	#define LCD_WF8B_BPGLCD12_SHIFT 6
allonq	0:fac0542384d7	2663	#define LCD_WF8B_BPGLCD41_MASK 0x40u
allonq	0:fac0542384d7	2664	#define LCD_WF8B_BPGLCD41_SHIFT 6
allonq	0:fac0542384d7	2665	#define LCD_WF8B_BPGLCD36_MASK 0x40u
allonq	0:fac0542384d7	2666	#define LCD_WF8B_BPGLCD36_SHIFT 6
allonq	0:fac0542384d7	2667	#define LCD_WF8B_BPGLCD3_MASK 0x40u
allonq	0:fac0542384d7	2668	#define LCD_WF8B_BPGLCD3_SHIFT 6
allonq	0:fac0542384d7	2669	#define LCD_WF8B_BPGLCD37_MASK 0x40u
allonq	0:fac0542384d7	2670	#define LCD_WF8B_BPGLCD37_SHIFT 6
allonq	0:fac0542384d7	2671	#define LCD_WF8B_BPGLCD40_MASK 0x40u
allonq	0:fac0542384d7	2672	#define LCD_WF8B_BPGLCD40_SHIFT 6
allonq	0:fac0542384d7	2673	#define LCD_WF8B_BPGLCD38_MASK 0x40u
allonq	0:fac0542384d7	2674	#define LCD_WF8B_BPGLCD38_SHIFT 6
allonq	0:fac0542384d7	2675	#define LCD_WF8B_BPGLCD39_MASK 0x40u
allonq	0:fac0542384d7	2676	#define LCD_WF8B_BPGLCD39_SHIFT 6
allonq	0:fac0542384d7	2677	#define LCD_WF8B_BPHLCD63_MASK 0x80u
allonq	0:fac0542384d7	2678	#define LCD_WF8B_BPHLCD63_SHIFT 7
allonq	0:fac0542384d7	2679	#define LCD_WF8B_BPHLCD62_MASK 0x80u
allonq	0:fac0542384d7	2680	#define LCD_WF8B_BPHLCD62_SHIFT 7
allonq	0:fac0542384d7	2681	#define LCD_WF8B_BPHLCD61_MASK 0x80u
allonq	0:fac0542384d7	2682	#define LCD_WF8B_BPHLCD61_SHIFT 7
allonq	0:fac0542384d7	2683	#define LCD_WF8B_BPHLCD60_MASK 0x80u
allonq	0:fac0542384d7	2684	#define LCD_WF8B_BPHLCD60_SHIFT 7
allonq	0:fac0542384d7	2685	#define LCD_WF8B_BPHLCD59_MASK 0x80u
allonq	0:fac0542384d7	2686	#define LCD_WF8B_BPHLCD59_SHIFT 7
allonq	0:fac0542384d7	2687	#define LCD_WF8B_BPHLCD58_MASK 0x80u
allonq	0:fac0542384d7	2688	#define LCD_WF8B_BPHLCD58_SHIFT 7
allonq	0:fac0542384d7	2689	#define LCD_WF8B_BPHLCD57_MASK 0x80u
allonq	0:fac0542384d7	2690	#define LCD_WF8B_BPHLCD57_SHIFT 7
allonq	0:fac0542384d7	2691	#define LCD_WF8B_BPHLCD0_MASK 0x80u
allonq	0:fac0542384d7	2692	#define LCD_WF8B_BPHLCD0_SHIFT 7
allonq	0:fac0542384d7	2693	#define LCD_WF8B_BPHLCD56_MASK 0x80u
allonq	0:fac0542384d7	2694	#define LCD_WF8B_BPHLCD56_SHIFT 7
allonq	0:fac0542384d7	2695	#define LCD_WF8B_BPHLCD55_MASK 0x80u
allonq	0:fac0542384d7	2696	#define LCD_WF8B_BPHLCD55_SHIFT 7
allonq	0:fac0542384d7	2697	#define LCD_WF8B_BPHLCD54_MASK 0x80u
allonq	0:fac0542384d7	2698	#define LCD_WF8B_BPHLCD54_SHIFT 7
allonq	0:fac0542384d7	2699	#define LCD_WF8B_BPHLCD53_MASK 0x80u
allonq	0:fac0542384d7	2700	#define LCD_WF8B_BPHLCD53_SHIFT 7
allonq	0:fac0542384d7	2701	#define LCD_WF8B_BPHLCD52_MASK 0x80u
allonq	0:fac0542384d7	2702	#define LCD_WF8B_BPHLCD52_SHIFT 7
allonq	0:fac0542384d7	2703	#define LCD_WF8B_BPHLCD51_MASK 0x80u
allonq	0:fac0542384d7	2704	#define LCD_WF8B_BPHLCD51_SHIFT 7
allonq	0:fac0542384d7	2705	#define LCD_WF8B_BPHLCD50_MASK 0x80u
allonq	0:fac0542384d7	2706	#define LCD_WF8B_BPHLCD50_SHIFT 7
allonq	0:fac0542384d7	2707	#define LCD_WF8B_BPHLCD1_MASK 0x80u
allonq	0:fac0542384d7	2708	#define LCD_WF8B_BPHLCD1_SHIFT 7
allonq	0:fac0542384d7	2709	#define LCD_WF8B_BPHLCD49_MASK 0x80u
allonq	0:fac0542384d7	2710	#define LCD_WF8B_BPHLCD49_SHIFT 7
allonq	0:fac0542384d7	2711	#define LCD_WF8B_BPHLCD48_MASK 0x80u
allonq	0:fac0542384d7	2712	#define LCD_WF8B_BPHLCD48_SHIFT 7
allonq	0:fac0542384d7	2713	#define LCD_WF8B_BPHLCD47_MASK 0x80u
allonq	0:fac0542384d7	2714	#define LCD_WF8B_BPHLCD47_SHIFT 7
allonq	0:fac0542384d7	2715	#define LCD_WF8B_BPHLCD46_MASK 0x80u
allonq	0:fac0542384d7	2716	#define LCD_WF8B_BPHLCD46_SHIFT 7
allonq	0:fac0542384d7	2717	#define LCD_WF8B_BPHLCD45_MASK 0x80u
allonq	0:fac0542384d7	2718	#define LCD_WF8B_BPHLCD45_SHIFT 7
allonq	0:fac0542384d7	2719	#define LCD_WF8B_BPHLCD44_MASK 0x80u
allonq	0:fac0542384d7	2720	#define LCD_WF8B_BPHLCD44_SHIFT 7
allonq	0:fac0542384d7	2721	#define LCD_WF8B_BPHLCD43_MASK 0x80u
allonq	0:fac0542384d7	2722	#define LCD_WF8B_BPHLCD43_SHIFT 7
allonq	0:fac0542384d7	2723	#define LCD_WF8B_BPHLCD2_MASK 0x80u
allonq	0:fac0542384d7	2724	#define LCD_WF8B_BPHLCD2_SHIFT 7
allonq	0:fac0542384d7	2725	#define LCD_WF8B_BPHLCD42_MASK 0x80u
allonq	0:fac0542384d7	2726	#define LCD_WF8B_BPHLCD42_SHIFT 7
allonq	0:fac0542384d7	2727	#define LCD_WF8B_BPHLCD41_MASK 0x80u
allonq	0:fac0542384d7	2728	#define LCD_WF8B_BPHLCD41_SHIFT 7
allonq	0:fac0542384d7	2729	#define LCD_WF8B_BPHLCD40_MASK 0x80u
allonq	0:fac0542384d7	2730	#define LCD_WF8B_BPHLCD40_SHIFT 7
allonq	0:fac0542384d7	2731	#define LCD_WF8B_BPHLCD39_MASK 0x80u
allonq	0:fac0542384d7	2732	#define LCD_WF8B_BPHLCD39_SHIFT 7
allonq	0:fac0542384d7	2733	#define LCD_WF8B_BPHLCD38_MASK 0x80u
allonq	0:fac0542384d7	2734	#define LCD_WF8B_BPHLCD38_SHIFT 7
allonq	0:fac0542384d7	2735	#define LCD_WF8B_BPHLCD37_MASK 0x80u
allonq	0:fac0542384d7	2736	#define LCD_WF8B_BPHLCD37_SHIFT 7
allonq	0:fac0542384d7	2737	#define LCD_WF8B_BPHLCD36_MASK 0x80u
allonq	0:fac0542384d7	2738	#define LCD_WF8B_BPHLCD36_SHIFT 7
allonq	0:fac0542384d7	2739	#define LCD_WF8B_BPHLCD3_MASK 0x80u
allonq	0:fac0542384d7	2740	#define LCD_WF8B_BPHLCD3_SHIFT 7
allonq	0:fac0542384d7	2741	#define LCD_WF8B_BPHLCD35_MASK 0x80u
allonq	0:fac0542384d7	2742	#define LCD_WF8B_BPHLCD35_SHIFT 7
allonq	0:fac0542384d7	2743	#define LCD_WF8B_BPHLCD34_MASK 0x80u
allonq	0:fac0542384d7	2744	#define LCD_WF8B_BPHLCD34_SHIFT 7
allonq	0:fac0542384d7	2745	#define LCD_WF8B_BPHLCD33_MASK 0x80u
allonq	0:fac0542384d7	2746	#define LCD_WF8B_BPHLCD33_SHIFT 7
allonq	0:fac0542384d7	2747	#define LCD_WF8B_BPHLCD32_MASK 0x80u
allonq	0:fac0542384d7	2748	#define LCD_WF8B_BPHLCD32_SHIFT 7
allonq	0:fac0542384d7	2749	#define LCD_WF8B_BPHLCD31_MASK 0x80u
allonq	0:fac0542384d7	2750	#define LCD_WF8B_BPHLCD31_SHIFT 7
allonq	0:fac0542384d7	2751	#define LCD_WF8B_BPHLCD30_MASK 0x80u
allonq	0:fac0542384d7	2752	#define LCD_WF8B_BPHLCD30_SHIFT 7
allonq	0:fac0542384d7	2753	#define LCD_WF8B_BPHLCD29_MASK 0x80u
allonq	0:fac0542384d7	2754	#define LCD_WF8B_BPHLCD29_SHIFT 7
allonq	0:fac0542384d7	2755	#define LCD_WF8B_BPHLCD4_MASK 0x80u
allonq	0:fac0542384d7	2756	#define LCD_WF8B_BPHLCD4_SHIFT 7
allonq	0:fac0542384d7	2757	#define LCD_WF8B_BPHLCD28_MASK 0x80u
allonq	0:fac0542384d7	2758	#define LCD_WF8B_BPHLCD28_SHIFT 7
allonq	0:fac0542384d7	2759	#define LCD_WF8B_BPHLCD27_MASK 0x80u
allonq	0:fac0542384d7	2760	#define LCD_WF8B_BPHLCD27_SHIFT 7
allonq	0:fac0542384d7	2761	#define LCD_WF8B_BPHLCD26_MASK 0x80u
allonq	0:fac0542384d7	2762	#define LCD_WF8B_BPHLCD26_SHIFT 7
allonq	0:fac0542384d7	2763	#define LCD_WF8B_BPHLCD25_MASK 0x80u
allonq	0:fac0542384d7	2764	#define LCD_WF8B_BPHLCD25_SHIFT 7
allonq	0:fac0542384d7	2765	#define LCD_WF8B_BPHLCD24_MASK 0x80u
allonq	0:fac0542384d7	2766	#define LCD_WF8B_BPHLCD24_SHIFT 7
allonq	0:fac0542384d7	2767	#define LCD_WF8B_BPHLCD23_MASK 0x80u
allonq	0:fac0542384d7	2768	#define LCD_WF8B_BPHLCD23_SHIFT 7
allonq	0:fac0542384d7	2769	#define LCD_WF8B_BPHLCD22_MASK 0x80u
allonq	0:fac0542384d7	2770	#define LCD_WF8B_BPHLCD22_SHIFT 7
allonq	0:fac0542384d7	2771	#define LCD_WF8B_BPHLCD5_MASK 0x80u
allonq	0:fac0542384d7	2772	#define LCD_WF8B_BPHLCD5_SHIFT 7
allonq	0:fac0542384d7	2773	#define LCD_WF8B_BPHLCD21_MASK 0x80u
allonq	0:fac0542384d7	2774	#define LCD_WF8B_BPHLCD21_SHIFT 7
allonq	0:fac0542384d7	2775	#define LCD_WF8B_BPHLCD20_MASK 0x80u
allonq	0:fac0542384d7	2776	#define LCD_WF8B_BPHLCD20_SHIFT 7
allonq	0:fac0542384d7	2777	#define LCD_WF8B_BPHLCD19_MASK 0x80u
allonq	0:fac0542384d7	2778	#define LCD_WF8B_BPHLCD19_SHIFT 7
allonq	0:fac0542384d7	2779	#define LCD_WF8B_BPHLCD18_MASK 0x80u
allonq	0:fac0542384d7	2780	#define LCD_WF8B_BPHLCD18_SHIFT 7
allonq	0:fac0542384d7	2781	#define LCD_WF8B_BPHLCD17_MASK 0x80u
allonq	0:fac0542384d7	2782	#define LCD_WF8B_BPHLCD17_SHIFT 7
allonq	0:fac0542384d7	2783	#define LCD_WF8B_BPHLCD16_MASK 0x80u
allonq	0:fac0542384d7	2784	#define LCD_WF8B_BPHLCD16_SHIFT 7
allonq	0:fac0542384d7	2785	#define LCD_WF8B_BPHLCD15_MASK 0x80u
allonq	0:fac0542384d7	2786	#define LCD_WF8B_BPHLCD15_SHIFT 7
allonq	0:fac0542384d7	2787	#define LCD_WF8B_BPHLCD6_MASK 0x80u
allonq	0:fac0542384d7	2788	#define LCD_WF8B_BPHLCD6_SHIFT 7
allonq	0:fac0542384d7	2789	#define LCD_WF8B_BPHLCD14_MASK 0x80u
allonq	0:fac0542384d7	2790	#define LCD_WF8B_BPHLCD14_SHIFT 7
allonq	0:fac0542384d7	2791	#define LCD_WF8B_BPHLCD13_MASK 0x80u
allonq	0:fac0542384d7	2792	#define LCD_WF8B_BPHLCD13_SHIFT 7
allonq	0:fac0542384d7	2793	#define LCD_WF8B_BPHLCD12_MASK 0x80u
allonq	0:fac0542384d7	2794	#define LCD_WF8B_BPHLCD12_SHIFT 7
allonq	0:fac0542384d7	2795	#define LCD_WF8B_BPHLCD11_MASK 0x80u
allonq	0:fac0542384d7	2796	#define LCD_WF8B_BPHLCD11_SHIFT 7
allonq	0:fac0542384d7	2797	#define LCD_WF8B_BPHLCD10_MASK 0x80u
allonq	0:fac0542384d7	2798	#define LCD_WF8B_BPHLCD10_SHIFT 7
allonq	0:fac0542384d7	2799	#define LCD_WF8B_BPHLCD9_MASK 0x80u
allonq	0:fac0542384d7	2800	#define LCD_WF8B_BPHLCD9_SHIFT 7
allonq	0:fac0542384d7	2801	#define LCD_WF8B_BPHLCD8_MASK 0x80u
allonq	0:fac0542384d7	2802	#define LCD_WF8B_BPHLCD8_SHIFT 7
allonq	0:fac0542384d7	2803	#define LCD_WF8B_BPHLCD7_MASK 0x80u
allonq	0:fac0542384d7	2804	#define LCD_WF8B_BPHLCD7_SHIFT 7
allonq	0:fac0542384d7	2805
allonq	0:fac0542384d7	2806	/*!
allonq	0:fac0542384d7	2807	* @}
allonq	0:fac0542384d7	2808	/ / end of group LCD_Register_Masks */
allonq	0:fac0542384d7	2809
allonq	0:fac0542384d7	2810
allonq	0:fac0542384d7	2811	/* LCD - Peripheral instance base addresses */
allonq	0:fac0542384d7	2812	/** Peripheral LCD base address */
allonq	0:fac0542384d7	2813	#define LCD_BASE (0x40053000u)
allonq	0:fac0542384d7	2814	/** Peripheral LCD base pointer */
allonq	0:fac0542384d7	2815	#define LCD ((LCD_Type *)LCD_BASE)
allonq	0:fac0542384d7	2816	/** Array initializer of LCD peripheral base pointers */
allonq	0:fac0542384d7	2817	#define LCD_BASES { LCD }
allonq	0:fac0542384d7	2818
allonq	0:fac0542384d7	2819	/*!
allonq	0:fac0542384d7	2820	* @}
allonq	0:fac0542384d7	2821	/ / end of group LCD_Peripheral_Access_Layer */
allonq	0:fac0542384d7	2822
allonq	0:fac0542384d7	2823
allonq	0:fac0542384d7	2824	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	2825	-- LLWU Peripheral Access Layer
allonq	0:fac0542384d7	2826	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	2827
allonq	0:fac0542384d7	2828	/*!
allonq	0:fac0542384d7	2829	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
allonq	0:fac0542384d7	2830	* @{
allonq	0:fac0542384d7	2831	*/
allonq	0:fac0542384d7	2832
allonq	0:fac0542384d7	2833	/** LLWU - Register Layout Typedef */
allonq	0:fac0542384d7	2834	typedef struct {
allonq	0:fac0542384d7	2835	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
allonq	0:fac0542384d7	2836	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
allonq	0:fac0542384d7	2837	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
allonq	0:fac0542384d7	2838	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
allonq	0:fac0542384d7	2839	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
allonq	0:fac0542384d7	2840	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
allonq	0:fac0542384d7	2841	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
allonq	0:fac0542384d7	2842	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
allonq	0:fac0542384d7	2843	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
allonq	0:fac0542384d7	2844	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
allonq	0:fac0542384d7	2845	} LLWU_Type;
allonq	0:fac0542384d7	2846
allonq	0:fac0542384d7	2847	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	2848	-- LLWU Register Masks
allonq	0:fac0542384d7	2849	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	2850
allonq	0:fac0542384d7	2851	/*!
allonq	0:fac0542384d7	2852	* @addtogroup LLWU_Register_Masks LLWU Register Masks
allonq	0:fac0542384d7	2853	* @{
allonq	0:fac0542384d7	2854	*/
allonq	0:fac0542384d7	2855
allonq	0:fac0542384d7	2856	/* PE1 Bit Fields */
allonq	0:fac0542384d7	2857	#define LLWU_PE1_WUPE0_MASK 0x3u
allonq	0:fac0542384d7	2858	#define LLWU_PE1_WUPE0_SHIFT 0
allonq	0:fac0542384d7	2859	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
allonq	0:fac0542384d7	2860	#define LLWU_PE1_WUPE1_MASK 0xCu
allonq	0:fac0542384d7	2861	#define LLWU_PE1_WUPE1_SHIFT 2
allonq	0:fac0542384d7	2862	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
allonq	0:fac0542384d7	2863	#define LLWU_PE1_WUPE2_MASK 0x30u
allonq	0:fac0542384d7	2864	#define LLWU_PE1_WUPE2_SHIFT 4
allonq	0:fac0542384d7	2865	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
allonq	0:fac0542384d7	2866	#define LLWU_PE1_WUPE3_MASK 0xC0u
allonq	0:fac0542384d7	2867	#define LLWU_PE1_WUPE3_SHIFT 6
allonq	0:fac0542384d7	2868	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
allonq	0:fac0542384d7	2869	/* PE2 Bit Fields */
allonq	0:fac0542384d7	2870	#define LLWU_PE2_WUPE4_MASK 0x3u
allonq	0:fac0542384d7	2871	#define LLWU_PE2_WUPE4_SHIFT 0
allonq	0:fac0542384d7	2872	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
allonq	0:fac0542384d7	2873	#define LLWU_PE2_WUPE5_MASK 0xCu
allonq	0:fac0542384d7	2874	#define LLWU_PE2_WUPE5_SHIFT 2
allonq	0:fac0542384d7	2875	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
allonq	0:fac0542384d7	2876	#define LLWU_PE2_WUPE6_MASK 0x30u
allonq	0:fac0542384d7	2877	#define LLWU_PE2_WUPE6_SHIFT 4
allonq	0:fac0542384d7	2878	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
allonq	0:fac0542384d7	2879	#define LLWU_PE2_WUPE7_MASK 0xC0u
allonq	0:fac0542384d7	2880	#define LLWU_PE2_WUPE7_SHIFT 6
allonq	0:fac0542384d7	2881	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
allonq	0:fac0542384d7	2882	/* PE3 Bit Fields */
allonq	0:fac0542384d7	2883	#define LLWU_PE3_WUPE8_MASK 0x3u
allonq	0:fac0542384d7	2884	#define LLWU_PE3_WUPE8_SHIFT 0
allonq	0:fac0542384d7	2885	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
allonq	0:fac0542384d7	2886	#define LLWU_PE3_WUPE9_MASK 0xCu
allonq	0:fac0542384d7	2887	#define LLWU_PE3_WUPE9_SHIFT 2
allonq	0:fac0542384d7	2888	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
allonq	0:fac0542384d7	2889	#define LLWU_PE3_WUPE10_MASK 0x30u
allonq	0:fac0542384d7	2890	#define LLWU_PE3_WUPE10_SHIFT 4
allonq	0:fac0542384d7	2891	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
allonq	0:fac0542384d7	2892	#define LLWU_PE3_WUPE11_MASK 0xC0u
allonq	0:fac0542384d7	2893	#define LLWU_PE3_WUPE11_SHIFT 6
allonq	0:fac0542384d7	2894	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
allonq	0:fac0542384d7	2895	/* PE4 Bit Fields */
allonq	0:fac0542384d7	2896	#define LLWU_PE4_WUPE12_MASK 0x3u
allonq	0:fac0542384d7	2897	#define LLWU_PE4_WUPE12_SHIFT 0
allonq	0:fac0542384d7	2898	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
allonq	0:fac0542384d7	2899	#define LLWU_PE4_WUPE13_MASK 0xCu
allonq	0:fac0542384d7	2900	#define LLWU_PE4_WUPE13_SHIFT 2
allonq	0:fac0542384d7	2901	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
allonq	0:fac0542384d7	2902	#define LLWU_PE4_WUPE14_MASK 0x30u
allonq	0:fac0542384d7	2903	#define LLWU_PE4_WUPE14_SHIFT 4
allonq	0:fac0542384d7	2904	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
allonq	0:fac0542384d7	2905	#define LLWU_PE4_WUPE15_MASK 0xC0u
allonq	0:fac0542384d7	2906	#define LLWU_PE4_WUPE15_SHIFT 6
allonq	0:fac0542384d7	2907	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
allonq	0:fac0542384d7	2908	/* ME Bit Fields */
allonq	0:fac0542384d7	2909	#define LLWU_ME_WUME0_MASK 0x1u
allonq	0:fac0542384d7	2910	#define LLWU_ME_WUME0_SHIFT 0
allonq	0:fac0542384d7	2911	#define LLWU_ME_WUME1_MASK 0x2u
allonq	0:fac0542384d7	2912	#define LLWU_ME_WUME1_SHIFT 1
allonq	0:fac0542384d7	2913	#define LLWU_ME_WUME2_MASK 0x4u
allonq	0:fac0542384d7	2914	#define LLWU_ME_WUME2_SHIFT 2
allonq	0:fac0542384d7	2915	#define LLWU_ME_WUME3_MASK 0x8u
allonq	0:fac0542384d7	2916	#define LLWU_ME_WUME3_SHIFT 3
allonq	0:fac0542384d7	2917	#define LLWU_ME_WUME4_MASK 0x10u
allonq	0:fac0542384d7	2918	#define LLWU_ME_WUME4_SHIFT 4
allonq	0:fac0542384d7	2919	#define LLWU_ME_WUME5_MASK 0x20u
allonq	0:fac0542384d7	2920	#define LLWU_ME_WUME5_SHIFT 5
allonq	0:fac0542384d7	2921	#define LLWU_ME_WUME6_MASK 0x40u
allonq	0:fac0542384d7	2922	#define LLWU_ME_WUME6_SHIFT 6
allonq	0:fac0542384d7	2923	#define LLWU_ME_WUME7_MASK 0x80u
allonq	0:fac0542384d7	2924	#define LLWU_ME_WUME7_SHIFT 7
allonq	0:fac0542384d7	2925	/* F1 Bit Fields */
allonq	0:fac0542384d7	2926	#define LLWU_F1_WUF0_MASK 0x1u
allonq	0:fac0542384d7	2927	#define LLWU_F1_WUF0_SHIFT 0
allonq	0:fac0542384d7	2928	#define LLWU_F1_WUF1_MASK 0x2u
allonq	0:fac0542384d7	2929	#define LLWU_F1_WUF1_SHIFT 1
allonq	0:fac0542384d7	2930	#define LLWU_F1_WUF2_MASK 0x4u
allonq	0:fac0542384d7	2931	#define LLWU_F1_WUF2_SHIFT 2
allonq	0:fac0542384d7	2932	#define LLWU_F1_WUF3_MASK 0x8u
allonq	0:fac0542384d7	2933	#define LLWU_F1_WUF3_SHIFT 3
allonq	0:fac0542384d7	2934	#define LLWU_F1_WUF4_MASK 0x10u
allonq	0:fac0542384d7	2935	#define LLWU_F1_WUF4_SHIFT 4
allonq	0:fac0542384d7	2936	#define LLWU_F1_WUF5_MASK 0x20u
allonq	0:fac0542384d7	2937	#define LLWU_F1_WUF5_SHIFT 5
allonq	0:fac0542384d7	2938	#define LLWU_F1_WUF6_MASK 0x40u
allonq	0:fac0542384d7	2939	#define LLWU_F1_WUF6_SHIFT 6
allonq	0:fac0542384d7	2940	#define LLWU_F1_WUF7_MASK 0x80u
allonq	0:fac0542384d7	2941	#define LLWU_F1_WUF7_SHIFT 7
allonq	0:fac0542384d7	2942	/* F2 Bit Fields */
allonq	0:fac0542384d7	2943	#define LLWU_F2_WUF8_MASK 0x1u
allonq	0:fac0542384d7	2944	#define LLWU_F2_WUF8_SHIFT 0
allonq	0:fac0542384d7	2945	#define LLWU_F2_WUF9_MASK 0x2u
allonq	0:fac0542384d7	2946	#define LLWU_F2_WUF9_SHIFT 1
allonq	0:fac0542384d7	2947	#define LLWU_F2_WUF10_MASK 0x4u
allonq	0:fac0542384d7	2948	#define LLWU_F2_WUF10_SHIFT 2
allonq	0:fac0542384d7	2949	#define LLWU_F2_WUF11_MASK 0x8u
allonq	0:fac0542384d7	2950	#define LLWU_F2_WUF11_SHIFT 3
allonq	0:fac0542384d7	2951	#define LLWU_F2_WUF12_MASK 0x10u
allonq	0:fac0542384d7	2952	#define LLWU_F2_WUF12_SHIFT 4
allonq	0:fac0542384d7	2953	#define LLWU_F2_WUF13_MASK 0x20u
allonq	0:fac0542384d7	2954	#define LLWU_F2_WUF13_SHIFT 5
allonq	0:fac0542384d7	2955	#define LLWU_F2_WUF14_MASK 0x40u
allonq	0:fac0542384d7	2956	#define LLWU_F2_WUF14_SHIFT 6
allonq	0:fac0542384d7	2957	#define LLWU_F2_WUF15_MASK 0x80u
allonq	0:fac0542384d7	2958	#define LLWU_F2_WUF15_SHIFT 7
allonq	0:fac0542384d7	2959	/* F3 Bit Fields */
allonq	0:fac0542384d7	2960	#define LLWU_F3_MWUF0_MASK 0x1u
allonq	0:fac0542384d7	2961	#define LLWU_F3_MWUF0_SHIFT 0
allonq	0:fac0542384d7	2962	#define LLWU_F3_MWUF1_MASK 0x2u
allonq	0:fac0542384d7	2963	#define LLWU_F3_MWUF1_SHIFT 1
allonq	0:fac0542384d7	2964	#define LLWU_F3_MWUF2_MASK 0x4u
allonq	0:fac0542384d7	2965	#define LLWU_F3_MWUF2_SHIFT 2
allonq	0:fac0542384d7	2966	#define LLWU_F3_MWUF3_MASK 0x8u
allonq	0:fac0542384d7	2967	#define LLWU_F3_MWUF3_SHIFT 3
allonq	0:fac0542384d7	2968	#define LLWU_F3_MWUF4_MASK 0x10u
allonq	0:fac0542384d7	2969	#define LLWU_F3_MWUF4_SHIFT 4
allonq	0:fac0542384d7	2970	#define LLWU_F3_MWUF5_MASK 0x20u
allonq	0:fac0542384d7	2971	#define LLWU_F3_MWUF5_SHIFT 5
allonq	0:fac0542384d7	2972	#define LLWU_F3_MWUF6_MASK 0x40u
allonq	0:fac0542384d7	2973	#define LLWU_F3_MWUF6_SHIFT 6
allonq	0:fac0542384d7	2974	#define LLWU_F3_MWUF7_MASK 0x80u
allonq	0:fac0542384d7	2975	#define LLWU_F3_MWUF7_SHIFT 7
allonq	0:fac0542384d7	2976	/* FILT1 Bit Fields */
allonq	0:fac0542384d7	2977	#define LLWU_FILT1_FILTSEL_MASK 0xFu
allonq	0:fac0542384d7	2978	#define LLWU_FILT1_FILTSEL_SHIFT 0
allonq	0:fac0542384d7	2979	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
allonq	0:fac0542384d7	2980	#define LLWU_FILT1_FILTE_MASK 0x60u
allonq	0:fac0542384d7	2981	#define LLWU_FILT1_FILTE_SHIFT 5
allonq	0:fac0542384d7	2982	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
allonq	0:fac0542384d7	2983	#define LLWU_FILT1_FILTF_MASK 0x80u
allonq	0:fac0542384d7	2984	#define LLWU_FILT1_FILTF_SHIFT 7
allonq	0:fac0542384d7	2985	/* FILT2 Bit Fields */
allonq	0:fac0542384d7	2986	#define LLWU_FILT2_FILTSEL_MASK 0xFu
allonq	0:fac0542384d7	2987	#define LLWU_FILT2_FILTSEL_SHIFT 0
allonq	0:fac0542384d7	2988	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
allonq	0:fac0542384d7	2989	#define LLWU_FILT2_FILTE_MASK 0x60u
allonq	0:fac0542384d7	2990	#define LLWU_FILT2_FILTE_SHIFT 5
allonq	0:fac0542384d7	2991	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
allonq	0:fac0542384d7	2992	#define LLWU_FILT2_FILTF_MASK 0x80u
allonq	0:fac0542384d7	2993	#define LLWU_FILT2_FILTF_SHIFT 7
allonq	0:fac0542384d7	2994
allonq	0:fac0542384d7	2995	/*!
allonq	0:fac0542384d7	2996	* @}
allonq	0:fac0542384d7	2997	/ / end of group LLWU_Register_Masks */
allonq	0:fac0542384d7	2998
allonq	0:fac0542384d7	2999
allonq	0:fac0542384d7	3000	/* LLWU - Peripheral instance base addresses */
allonq	0:fac0542384d7	3001	/** Peripheral LLWU base address */
allonq	0:fac0542384d7	3002	#define LLWU_BASE (0x4007C000u)
allonq	0:fac0542384d7	3003	/** Peripheral LLWU base pointer */
allonq	0:fac0542384d7	3004	#define LLWU ((LLWU_Type *)LLWU_BASE)
allonq	0:fac0542384d7	3005	/** Array initializer of LLWU peripheral base pointers */
allonq	0:fac0542384d7	3006	#define LLWU_BASES { LLWU }
allonq	0:fac0542384d7	3007
allonq	0:fac0542384d7	3008	/*!
allonq	0:fac0542384d7	3009	* @}
allonq	0:fac0542384d7	3010	/ / end of group LLWU_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3011
allonq	0:fac0542384d7	3012
allonq	0:fac0542384d7	3013	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3014	-- LPTMR Peripheral Access Layer
allonq	0:fac0542384d7	3015	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3016
allonq	0:fac0542384d7	3017	/*!
allonq	0:fac0542384d7	3018	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
allonq	0:fac0542384d7	3019	* @{
allonq	0:fac0542384d7	3020	*/
allonq	0:fac0542384d7	3021
allonq	0:fac0542384d7	3022	/** LPTMR - Register Layout Typedef */
allonq	0:fac0542384d7	3023	typedef struct {
allonq	0:fac0542384d7	3024	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
allonq	0:fac0542384d7	3025	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
allonq	0:fac0542384d7	3026	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
allonq	0:fac0542384d7	3027	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
allonq	0:fac0542384d7	3028	} LPTMR_Type;
allonq	0:fac0542384d7	3029
allonq	0:fac0542384d7	3030	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3031	-- LPTMR Register Masks
allonq	0:fac0542384d7	3032	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3033
allonq	0:fac0542384d7	3034	/*!
allonq	0:fac0542384d7	3035	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
allonq	0:fac0542384d7	3036	* @{
allonq	0:fac0542384d7	3037	*/
allonq	0:fac0542384d7	3038
allonq	0:fac0542384d7	3039	/* CSR Bit Fields */
allonq	0:fac0542384d7	3040	#define LPTMR_CSR_TEN_MASK 0x1u
allonq	0:fac0542384d7	3041	#define LPTMR_CSR_TEN_SHIFT 0
allonq	0:fac0542384d7	3042	#define LPTMR_CSR_TMS_MASK 0x2u
allonq	0:fac0542384d7	3043	#define LPTMR_CSR_TMS_SHIFT 1
allonq	0:fac0542384d7	3044	#define LPTMR_CSR_TFC_MASK 0x4u
allonq	0:fac0542384d7	3045	#define LPTMR_CSR_TFC_SHIFT 2
allonq	0:fac0542384d7	3046	#define LPTMR_CSR_TPP_MASK 0x8u
allonq	0:fac0542384d7	3047	#define LPTMR_CSR_TPP_SHIFT 3
allonq	0:fac0542384d7	3048	#define LPTMR_CSR_TPS_MASK 0x30u
allonq	0:fac0542384d7	3049	#define LPTMR_CSR_TPS_SHIFT 4
allonq	0:fac0542384d7	3050	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
allonq	0:fac0542384d7	3051	#define LPTMR_CSR_TIE_MASK 0x40u
allonq	0:fac0542384d7	3052	#define LPTMR_CSR_TIE_SHIFT 6
allonq	0:fac0542384d7	3053	#define LPTMR_CSR_TCF_MASK 0x80u
allonq	0:fac0542384d7	3054	#define LPTMR_CSR_TCF_SHIFT 7
allonq	0:fac0542384d7	3055	/* PSR Bit Fields */
allonq	0:fac0542384d7	3056	#define LPTMR_PSR_PCS_MASK 0x3u
allonq	0:fac0542384d7	3057	#define LPTMR_PSR_PCS_SHIFT 0
allonq	0:fac0542384d7	3058	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
allonq	0:fac0542384d7	3059	#define LPTMR_PSR_PBYP_MASK 0x4u
allonq	0:fac0542384d7	3060	#define LPTMR_PSR_PBYP_SHIFT 2
allonq	0:fac0542384d7	3061	#define LPTMR_PSR_PRESCALE_MASK 0x78u
allonq	0:fac0542384d7	3062	#define LPTMR_PSR_PRESCALE_SHIFT 3
allonq	0:fac0542384d7	3063	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
allonq	0:fac0542384d7	3064	/* CMR Bit Fields */
allonq	0:fac0542384d7	3065	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
allonq	0:fac0542384d7	3066	#define LPTMR_CMR_COMPARE_SHIFT 0
allonq	0:fac0542384d7	3067	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
allonq	0:fac0542384d7	3068	/* CNR Bit Fields */
allonq	0:fac0542384d7	3069	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
allonq	0:fac0542384d7	3070	#define LPTMR_CNR_COUNTER_SHIFT 0
allonq	0:fac0542384d7	3071	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
allonq	0:fac0542384d7	3072
allonq	0:fac0542384d7	3073	/*!
allonq	0:fac0542384d7	3074	* @}
allonq	0:fac0542384d7	3075	/ / end of group LPTMR_Register_Masks */
allonq	0:fac0542384d7	3076
allonq	0:fac0542384d7	3077
allonq	0:fac0542384d7	3078	/* LPTMR - Peripheral instance base addresses */
allonq	0:fac0542384d7	3079	/** Peripheral LPTMR0 base address */
allonq	0:fac0542384d7	3080	#define LPTMR0_BASE (0x40040000u)
allonq	0:fac0542384d7	3081	/** Peripheral LPTMR0 base pointer */
allonq	0:fac0542384d7	3082	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
allonq	0:fac0542384d7	3083	/** Array initializer of LPTMR peripheral base pointers */
allonq	0:fac0542384d7	3084	#define LPTMR_BASES { LPTMR0 }
allonq	0:fac0542384d7	3085
allonq	0:fac0542384d7	3086	/*!
allonq	0:fac0542384d7	3087	* @}
allonq	0:fac0542384d7	3088	/ / end of group LPTMR_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3089
allonq	0:fac0542384d7	3090
allonq	0:fac0542384d7	3091	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3092	-- MCG Peripheral Access Layer
allonq	0:fac0542384d7	3093	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3094
allonq	0:fac0542384d7	3095	/*!
allonq	0:fac0542384d7	3096	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
allonq	0:fac0542384d7	3097	* @{
allonq	0:fac0542384d7	3098	*/
allonq	0:fac0542384d7	3099
allonq	0:fac0542384d7	3100	/** MCG - Register Layout Typedef */
allonq	0:fac0542384d7	3101	typedef struct {
allonq	0:fac0542384d7	3102	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
allonq	0:fac0542384d7	3103	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
allonq	0:fac0542384d7	3104	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
allonq	0:fac0542384d7	3105	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
allonq	0:fac0542384d7	3106	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
allonq	0:fac0542384d7	3107	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
allonq	0:fac0542384d7	3108	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
allonq	0:fac0542384d7	3109	uint8_t RESERVED_0[1];
allonq	0:fac0542384d7	3110	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
allonq	0:fac0542384d7	3111	uint8_t RESERVED_1[1];
allonq	0:fac0542384d7	3112	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
allonq	0:fac0542384d7	3113	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
allonq	0:fac0542384d7	3114	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
allonq	0:fac0542384d7	3115	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
allonq	0:fac0542384d7	3116	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
allonq	0:fac0542384d7	3117	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
allonq	0:fac0542384d7	3118	} MCG_Type;
allonq	0:fac0542384d7	3119
allonq	0:fac0542384d7	3120	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3121	-- MCG Register Masks
allonq	0:fac0542384d7	3122	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3123
allonq	0:fac0542384d7	3124	/*!
allonq	0:fac0542384d7	3125	* @addtogroup MCG_Register_Masks MCG Register Masks
allonq	0:fac0542384d7	3126	* @{
allonq	0:fac0542384d7	3127	*/
allonq	0:fac0542384d7	3128
allonq	0:fac0542384d7	3129	/* C1 Bit Fields */
allonq	0:fac0542384d7	3130	#define MCG_C1_IREFSTEN_MASK 0x1u
allonq	0:fac0542384d7	3131	#define MCG_C1_IREFSTEN_SHIFT 0
allonq	0:fac0542384d7	3132	#define MCG_C1_IRCLKEN_MASK 0x2u
allonq	0:fac0542384d7	3133	#define MCG_C1_IRCLKEN_SHIFT 1
allonq	0:fac0542384d7	3134	#define MCG_C1_IREFS_MASK 0x4u
allonq	0:fac0542384d7	3135	#define MCG_C1_IREFS_SHIFT 2
allonq	0:fac0542384d7	3136	#define MCG_C1_FRDIV_MASK 0x38u
allonq	0:fac0542384d7	3137	#define MCG_C1_FRDIV_SHIFT 3
allonq	0:fac0542384d7	3138	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
allonq	0:fac0542384d7	3139	#define MCG_C1_CLKS_MASK 0xC0u
allonq	0:fac0542384d7	3140	#define MCG_C1_CLKS_SHIFT 6
allonq	0:fac0542384d7	3141	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
allonq	0:fac0542384d7	3142	/* C2 Bit Fields */
allonq	0:fac0542384d7	3143	#define MCG_C2_IRCS_MASK 0x1u
allonq	0:fac0542384d7	3144	#define MCG_C2_IRCS_SHIFT 0
allonq	0:fac0542384d7	3145	#define MCG_C2_LP_MASK 0x2u
allonq	0:fac0542384d7	3146	#define MCG_C2_LP_SHIFT 1
allonq	0:fac0542384d7	3147	#define MCG_C2_EREFS0_MASK 0x4u
allonq	0:fac0542384d7	3148	#define MCG_C2_EREFS0_SHIFT 2
allonq	0:fac0542384d7	3149	#define MCG_C2_HGO0_MASK 0x8u
allonq	0:fac0542384d7	3150	#define MCG_C2_HGO0_SHIFT 3
allonq	0:fac0542384d7	3151	#define MCG_C2_RANGE0_MASK 0x30u
allonq	0:fac0542384d7	3152	#define MCG_C2_RANGE0_SHIFT 4
allonq	0:fac0542384d7	3153	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
allonq	0:fac0542384d7	3154	#define MCG_C2_FCFTRIM_MASK 0x40u
allonq	0:fac0542384d7	3155	#define MCG_C2_FCFTRIM_SHIFT 6
allonq	0:fac0542384d7	3156	#define MCG_C2_LOCRE0_MASK 0x80u
allonq	0:fac0542384d7	3157	#define MCG_C2_LOCRE0_SHIFT 7
allonq	0:fac0542384d7	3158	/* C3 Bit Fields */
allonq	0:fac0542384d7	3159	#define MCG_C3_SCTRIM_MASK 0xFFu
allonq	0:fac0542384d7	3160	#define MCG_C3_SCTRIM_SHIFT 0
allonq	0:fac0542384d7	3161	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
allonq	0:fac0542384d7	3162	/* C4 Bit Fields */
allonq	0:fac0542384d7	3163	#define MCG_C4_SCFTRIM_MASK 0x1u
allonq	0:fac0542384d7	3164	#define MCG_C4_SCFTRIM_SHIFT 0
allonq	0:fac0542384d7	3165	#define MCG_C4_FCTRIM_MASK 0x1Eu
allonq	0:fac0542384d7	3166	#define MCG_C4_FCTRIM_SHIFT 1
allonq	0:fac0542384d7	3167	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
allonq	0:fac0542384d7	3168	#define MCG_C4_DRST_DRS_MASK 0x60u
allonq	0:fac0542384d7	3169	#define MCG_C4_DRST_DRS_SHIFT 5
allonq	0:fac0542384d7	3170	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
allonq	0:fac0542384d7	3171	#define MCG_C4_DMX32_MASK 0x80u
allonq	0:fac0542384d7	3172	#define MCG_C4_DMX32_SHIFT 7
allonq	0:fac0542384d7	3173	/* C5 Bit Fields */
allonq	0:fac0542384d7	3174	#define MCG_C5_PRDIV0_MASK 0x1Fu
allonq	0:fac0542384d7	3175	#define MCG_C5_PRDIV0_SHIFT 0
allonq	0:fac0542384d7	3176	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
allonq	0:fac0542384d7	3177	#define MCG_C5_PLLSTEN0_MASK 0x20u
allonq	0:fac0542384d7	3178	#define MCG_C5_PLLSTEN0_SHIFT 5
allonq	0:fac0542384d7	3179	#define MCG_C5_PLLCLKEN0_MASK 0x40u
allonq	0:fac0542384d7	3180	#define MCG_C5_PLLCLKEN0_SHIFT 6
allonq	0:fac0542384d7	3181	/* C6 Bit Fields */
allonq	0:fac0542384d7	3182	#define MCG_C6_VDIV0_MASK 0x1Fu
allonq	0:fac0542384d7	3183	#define MCG_C6_VDIV0_SHIFT 0
allonq	0:fac0542384d7	3184	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
allonq	0:fac0542384d7	3185	#define MCG_C6_CME0_MASK 0x20u
allonq	0:fac0542384d7	3186	#define MCG_C6_CME0_SHIFT 5
allonq	0:fac0542384d7	3187	#define MCG_C6_PLLS_MASK 0x40u
allonq	0:fac0542384d7	3188	#define MCG_C6_PLLS_SHIFT 6
allonq	0:fac0542384d7	3189	#define MCG_C6_LOLIE0_MASK 0x80u
allonq	0:fac0542384d7	3190	#define MCG_C6_LOLIE0_SHIFT 7
allonq	0:fac0542384d7	3191	/* S Bit Fields */
allonq	0:fac0542384d7	3192	#define MCG_S_IRCST_MASK 0x1u
allonq	0:fac0542384d7	3193	#define MCG_S_IRCST_SHIFT 0
allonq	0:fac0542384d7	3194	#define MCG_S_OSCINIT0_MASK 0x2u
allonq	0:fac0542384d7	3195	#define MCG_S_OSCINIT0_SHIFT 1
allonq	0:fac0542384d7	3196	#define MCG_S_CLKST_MASK 0xCu
allonq	0:fac0542384d7	3197	#define MCG_S_CLKST_SHIFT 2
allonq	0:fac0542384d7	3198	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
allonq	0:fac0542384d7	3199	#define MCG_S_IREFST_MASK 0x10u
allonq	0:fac0542384d7	3200	#define MCG_S_IREFST_SHIFT 4
allonq	0:fac0542384d7	3201	#define MCG_S_PLLST_MASK 0x20u
allonq	0:fac0542384d7	3202	#define MCG_S_PLLST_SHIFT 5
allonq	0:fac0542384d7	3203	#define MCG_S_LOCK0_MASK 0x40u
allonq	0:fac0542384d7	3204	#define MCG_S_LOCK0_SHIFT 6
allonq	0:fac0542384d7	3205	#define MCG_S_LOLS_MASK 0x80u
allonq	0:fac0542384d7	3206	#define MCG_S_LOLS_SHIFT 7
allonq	0:fac0542384d7	3207	/* SC Bit Fields */
allonq	0:fac0542384d7	3208	#define MCG_SC_LOCS0_MASK 0x1u
allonq	0:fac0542384d7	3209	#define MCG_SC_LOCS0_SHIFT 0
allonq	0:fac0542384d7	3210	#define MCG_SC_FCRDIV_MASK 0xEu
allonq	0:fac0542384d7	3211	#define MCG_SC_FCRDIV_SHIFT 1
allonq	0:fac0542384d7	3212	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
allonq	0:fac0542384d7	3213	#define MCG_SC_FLTPRSRV_MASK 0x10u
allonq	0:fac0542384d7	3214	#define MCG_SC_FLTPRSRV_SHIFT 4
allonq	0:fac0542384d7	3215	#define MCG_SC_ATMF_MASK 0x20u
allonq	0:fac0542384d7	3216	#define MCG_SC_ATMF_SHIFT 5
allonq	0:fac0542384d7	3217	#define MCG_SC_ATMS_MASK 0x40u
allonq	0:fac0542384d7	3218	#define MCG_SC_ATMS_SHIFT 6
allonq	0:fac0542384d7	3219	#define MCG_SC_ATME_MASK 0x80u
allonq	0:fac0542384d7	3220	#define MCG_SC_ATME_SHIFT 7
allonq	0:fac0542384d7	3221	/* ATCVH Bit Fields */
allonq	0:fac0542384d7	3222	#define MCG_ATCVH_ATCVH_MASK 0xFFu
allonq	0:fac0542384d7	3223	#define MCG_ATCVH_ATCVH_SHIFT 0
allonq	0:fac0542384d7	3224	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
allonq	0:fac0542384d7	3225	/* ATCVL Bit Fields */
allonq	0:fac0542384d7	3226	#define MCG_ATCVL_ATCVL_MASK 0xFFu
allonq	0:fac0542384d7	3227	#define MCG_ATCVL_ATCVL_SHIFT 0
allonq	0:fac0542384d7	3228	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
allonq	0:fac0542384d7	3229	/* C8 Bit Fields */
allonq	0:fac0542384d7	3230	#define MCG_C8_LOLRE_MASK 0x40u
allonq	0:fac0542384d7	3231	#define MCG_C8_LOLRE_SHIFT 6
allonq	0:fac0542384d7	3232
allonq	0:fac0542384d7	3233	/*!
allonq	0:fac0542384d7	3234	* @}
allonq	0:fac0542384d7	3235	/ / end of group MCG_Register_Masks */
allonq	0:fac0542384d7	3236
allonq	0:fac0542384d7	3237
allonq	0:fac0542384d7	3238	/* MCG - Peripheral instance base addresses */
allonq	0:fac0542384d7	3239	/** Peripheral MCG base address */
allonq	0:fac0542384d7	3240	#define MCG_BASE (0x40064000u)
allonq	0:fac0542384d7	3241	/** Peripheral MCG base pointer */
allonq	0:fac0542384d7	3242	#define MCG ((MCG_Type *)MCG_BASE)
allonq	0:fac0542384d7	3243	/** Array initializer of MCG peripheral base pointers */
allonq	0:fac0542384d7	3244	#define MCG_BASES { MCG }
allonq	0:fac0542384d7	3245
allonq	0:fac0542384d7	3246	/*!
allonq	0:fac0542384d7	3247	* @}
allonq	0:fac0542384d7	3248	/ / end of group MCG_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3249
allonq	0:fac0542384d7	3250
allonq	0:fac0542384d7	3251	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3252	-- MCM Peripheral Access Layer
allonq	0:fac0542384d7	3253	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3254
allonq	0:fac0542384d7	3255	/*!
allonq	0:fac0542384d7	3256	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
allonq	0:fac0542384d7	3257	* @{
allonq	0:fac0542384d7	3258	*/
allonq	0:fac0542384d7	3259
allonq	0:fac0542384d7	3260	/** MCM - Register Layout Typedef */
allonq	0:fac0542384d7	3261	typedef struct {
allonq	0:fac0542384d7	3262	uint8_t RESERVED_0[8];
allonq	0:fac0542384d7	3263	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
allonq	0:fac0542384d7	3264	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
allonq	0:fac0542384d7	3265	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
allonq	0:fac0542384d7	3266	uint8_t RESERVED_1[48];
allonq	0:fac0542384d7	3267	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
allonq	0:fac0542384d7	3268	} MCM_Type;
allonq	0:fac0542384d7	3269
allonq	0:fac0542384d7	3270	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3271	-- MCM Register Masks
allonq	0:fac0542384d7	3272	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3273
allonq	0:fac0542384d7	3274	/*!
allonq	0:fac0542384d7	3275	* @addtogroup MCM_Register_Masks MCM Register Masks
allonq	0:fac0542384d7	3276	* @{
allonq	0:fac0542384d7	3277	*/
allonq	0:fac0542384d7	3278
allonq	0:fac0542384d7	3279	/* PLASC Bit Fields */
allonq	0:fac0542384d7	3280	#define MCM_PLASC_ASC_MASK 0xFFu
allonq	0:fac0542384d7	3281	#define MCM_PLASC_ASC_SHIFT 0
allonq	0:fac0542384d7	3282	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
allonq	0:fac0542384d7	3283	/* PLAMC Bit Fields */
allonq	0:fac0542384d7	3284	#define MCM_PLAMC_AMC_MASK 0xFFu
allonq	0:fac0542384d7	3285	#define MCM_PLAMC_AMC_SHIFT 0
allonq	0:fac0542384d7	3286	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
allonq	0:fac0542384d7	3287	/* PLACR Bit Fields */
allonq	0:fac0542384d7	3288	#define MCM_PLACR_ARB_MASK 0x200u
allonq	0:fac0542384d7	3289	#define MCM_PLACR_ARB_SHIFT 9
allonq	0:fac0542384d7	3290	#define MCM_PLACR_CFCC_MASK 0x400u
allonq	0:fac0542384d7	3291	#define MCM_PLACR_CFCC_SHIFT 10
allonq	0:fac0542384d7	3292	#define MCM_PLACR_DFCDA_MASK 0x800u
allonq	0:fac0542384d7	3293	#define MCM_PLACR_DFCDA_SHIFT 11
allonq	0:fac0542384d7	3294	#define MCM_PLACR_DFCIC_MASK 0x1000u
allonq	0:fac0542384d7	3295	#define MCM_PLACR_DFCIC_SHIFT 12
allonq	0:fac0542384d7	3296	#define MCM_PLACR_DFCC_MASK 0x2000u
allonq	0:fac0542384d7	3297	#define MCM_PLACR_DFCC_SHIFT 13
allonq	0:fac0542384d7	3298	#define MCM_PLACR_EFDS_MASK 0x4000u
allonq	0:fac0542384d7	3299	#define MCM_PLACR_EFDS_SHIFT 14
allonq	0:fac0542384d7	3300	#define MCM_PLACR_DFCS_MASK 0x8000u
allonq	0:fac0542384d7	3301	#define MCM_PLACR_DFCS_SHIFT 15
allonq	0:fac0542384d7	3302	#define MCM_PLACR_ESFC_MASK 0x10000u
allonq	0:fac0542384d7	3303	#define MCM_PLACR_ESFC_SHIFT 16
allonq	0:fac0542384d7	3304	/* CPO Bit Fields */
allonq	0:fac0542384d7	3305	#define MCM_CPO_CPOREQ_MASK 0x1u
allonq	0:fac0542384d7	3306	#define MCM_CPO_CPOREQ_SHIFT 0
allonq	0:fac0542384d7	3307	#define MCM_CPO_CPOACK_MASK 0x2u
allonq	0:fac0542384d7	3308	#define MCM_CPO_CPOACK_SHIFT 1
allonq	0:fac0542384d7	3309	#define MCM_CPO_CPOWOI_MASK 0x4u
allonq	0:fac0542384d7	3310	#define MCM_CPO_CPOWOI_SHIFT 2
allonq	0:fac0542384d7	3311
allonq	0:fac0542384d7	3312	/*!
allonq	0:fac0542384d7	3313	* @}
allonq	0:fac0542384d7	3314	/ / end of group MCM_Register_Masks */
allonq	0:fac0542384d7	3315
allonq	0:fac0542384d7	3316
allonq	0:fac0542384d7	3317	/* MCM - Peripheral instance base addresses */
allonq	0:fac0542384d7	3318	/** Peripheral MCM base address */
allonq	0:fac0542384d7	3319	#define MCM_BASE (0xF0003000u)
allonq	0:fac0542384d7	3320	/** Peripheral MCM base pointer */
allonq	0:fac0542384d7	3321	#define MCM ((MCM_Type *)MCM_BASE)
allonq	0:fac0542384d7	3322	/** Array initializer of MCM peripheral base pointers */
allonq	0:fac0542384d7	3323	#define MCM_BASES { MCM }
allonq	0:fac0542384d7	3324
allonq	0:fac0542384d7	3325	/*!
allonq	0:fac0542384d7	3326	* @}
allonq	0:fac0542384d7	3327	/ / end of group MCM_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3328
allonq	0:fac0542384d7	3329
allonq	0:fac0542384d7	3330	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3331	-- MTB Peripheral Access Layer
allonq	0:fac0542384d7	3332	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3333
allonq	0:fac0542384d7	3334	/*!
allonq	0:fac0542384d7	3335	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
allonq	0:fac0542384d7	3336	* @{
allonq	0:fac0542384d7	3337	*/
allonq	0:fac0542384d7	3338
allonq	0:fac0542384d7	3339	/** MTB - Register Layout Typedef */
allonq	0:fac0542384d7	3340	typedef struct {
allonq	0:fac0542384d7	3341	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
allonq	0:fac0542384d7	3342	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
allonq	0:fac0542384d7	3343	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
allonq	0:fac0542384d7	3344	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
allonq	0:fac0542384d7	3345	uint8_t RESERVED_0[3824];
allonq	0:fac0542384d7	3346	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
allonq	0:fac0542384d7	3347	uint8_t RESERVED_1[156];
allonq	0:fac0542384d7	3348	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
allonq	0:fac0542384d7	3349	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
allonq	0:fac0542384d7	3350	uint8_t RESERVED_2[8];
allonq	0:fac0542384d7	3351	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
allonq	0:fac0542384d7	3352	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
allonq	0:fac0542384d7	3353	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
allonq	0:fac0542384d7	3354	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
allonq	0:fac0542384d7	3355	uint8_t RESERVED_3[8];
allonq	0:fac0542384d7	3356	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
allonq	0:fac0542384d7	3357	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
allonq	0:fac0542384d7	3358	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
allonq	0:fac0542384d7	3359	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
allonq	0:fac0542384d7	3360	} MTB_Type;
allonq	0:fac0542384d7	3361
allonq	0:fac0542384d7	3362	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3363	-- MTB Register Masks
allonq	0:fac0542384d7	3364	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3365
allonq	0:fac0542384d7	3366	/*!
allonq	0:fac0542384d7	3367	* @addtogroup MTB_Register_Masks MTB Register Masks
allonq	0:fac0542384d7	3368	* @{
allonq	0:fac0542384d7	3369	*/
allonq	0:fac0542384d7	3370
allonq	0:fac0542384d7	3371	/* POSITION Bit Fields */
allonq	0:fac0542384d7	3372	#define MTB_POSITION_WRAP_MASK 0x4u
allonq	0:fac0542384d7	3373	#define MTB_POSITION_WRAP_SHIFT 2
allonq	0:fac0542384d7	3374	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
allonq	0:fac0542384d7	3375	#define MTB_POSITION_POINTER_SHIFT 3
allonq	0:fac0542384d7	3376	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
allonq	0:fac0542384d7	3377	/* MASTER Bit Fields */
allonq	0:fac0542384d7	3378	#define MTB_MASTER_MASK_MASK 0x1Fu
allonq	0:fac0542384d7	3379	#define MTB_MASTER_MASK_SHIFT 0
allonq	0:fac0542384d7	3380	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
allonq	0:fac0542384d7	3381	#define MTB_MASTER_TSTARTEN_MASK 0x20u
allonq	0:fac0542384d7	3382	#define MTB_MASTER_TSTARTEN_SHIFT 5
allonq	0:fac0542384d7	3383	#define MTB_MASTER_TSTOPEN_MASK 0x40u
allonq	0:fac0542384d7	3384	#define MTB_MASTER_TSTOPEN_SHIFT 6
allonq	0:fac0542384d7	3385	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
allonq	0:fac0542384d7	3386	#define MTB_MASTER_SFRWPRIV_SHIFT 7
allonq	0:fac0542384d7	3387	#define MTB_MASTER_RAMPRIV_MASK 0x100u
allonq	0:fac0542384d7	3388	#define MTB_MASTER_RAMPRIV_SHIFT 8
allonq	0:fac0542384d7	3389	#define MTB_MASTER_HALTREQ_MASK 0x200u
allonq	0:fac0542384d7	3390	#define MTB_MASTER_HALTREQ_SHIFT 9
allonq	0:fac0542384d7	3391	#define MTB_MASTER_EN_MASK 0x80000000u
allonq	0:fac0542384d7	3392	#define MTB_MASTER_EN_SHIFT 31
allonq	0:fac0542384d7	3393	/* FLOW Bit Fields */
allonq	0:fac0542384d7	3394	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
allonq	0:fac0542384d7	3395	#define MTB_FLOW_AUTOSTOP_SHIFT 0
allonq	0:fac0542384d7	3396	#define MTB_FLOW_AUTOHALT_MASK 0x2u
allonq	0:fac0542384d7	3397	#define MTB_FLOW_AUTOHALT_SHIFT 1
allonq	0:fac0542384d7	3398	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
allonq	0:fac0542384d7	3399	#define MTB_FLOW_WATERMARK_SHIFT 3
allonq	0:fac0542384d7	3400	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
allonq	0:fac0542384d7	3401	/* BASE Bit Fields */
allonq	0:fac0542384d7	3402	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3403	#define MTB_BASE_BASEADDR_SHIFT 0
allonq	0:fac0542384d7	3404	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
allonq	0:fac0542384d7	3405	/* MODECTRL Bit Fields */
allonq	0:fac0542384d7	3406	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3407	#define MTB_MODECTRL_MODECTRL_SHIFT 0
allonq	0:fac0542384d7	3408	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
allonq	0:fac0542384d7	3409	/* TAGSET Bit Fields */
allonq	0:fac0542384d7	3410	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3411	#define MTB_TAGSET_TAGSET_SHIFT 0
allonq	0:fac0542384d7	3412	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
allonq	0:fac0542384d7	3413	/* TAGCLEAR Bit Fields */
allonq	0:fac0542384d7	3414	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3415	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
allonq	0:fac0542384d7	3416	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
allonq	0:fac0542384d7	3417	/* LOCKACCESS Bit Fields */
allonq	0:fac0542384d7	3418	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3419	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
allonq	0:fac0542384d7	3420	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
allonq	0:fac0542384d7	3421	/* LOCKSTAT Bit Fields */
allonq	0:fac0542384d7	3422	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3423	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
allonq	0:fac0542384d7	3424	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
allonq	0:fac0542384d7	3425	/* AUTHSTAT Bit Fields */
allonq	0:fac0542384d7	3426	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
allonq	0:fac0542384d7	3427	#define MTB_AUTHSTAT_BIT0_SHIFT 0
allonq	0:fac0542384d7	3428	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
allonq	0:fac0542384d7	3429	#define MTB_AUTHSTAT_BIT1_SHIFT 1
allonq	0:fac0542384d7	3430	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
allonq	0:fac0542384d7	3431	#define MTB_AUTHSTAT_BIT2_SHIFT 2
allonq	0:fac0542384d7	3432	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
allonq	0:fac0542384d7	3433	#define MTB_AUTHSTAT_BIT3_SHIFT 3
allonq	0:fac0542384d7	3434	/* DEVICEARCH Bit Fields */
allonq	0:fac0542384d7	3435	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3436	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
allonq	0:fac0542384d7	3437	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
allonq	0:fac0542384d7	3438	/* DEVICECFG Bit Fields */
allonq	0:fac0542384d7	3439	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3440	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
allonq	0:fac0542384d7	3441	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
allonq	0:fac0542384d7	3442	/* DEVICETYPID Bit Fields */
allonq	0:fac0542384d7	3443	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3444	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
allonq	0:fac0542384d7	3445	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
allonq	0:fac0542384d7	3446	/* PERIPHID Bit Fields */
allonq	0:fac0542384d7	3447	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3448	#define MTB_PERIPHID_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	3449	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
allonq	0:fac0542384d7	3450	/* COMPID Bit Fields */
allonq	0:fac0542384d7	3451	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3452	#define MTB_COMPID_COMPID_SHIFT 0
allonq	0:fac0542384d7	3453	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
allonq	0:fac0542384d7	3454
allonq	0:fac0542384d7	3455	/*!
allonq	0:fac0542384d7	3456	* @}
allonq	0:fac0542384d7	3457	/ / end of group MTB_Register_Masks */
allonq	0:fac0542384d7	3458
allonq	0:fac0542384d7	3459
allonq	0:fac0542384d7	3460	/* MTB - Peripheral instance base addresses */
allonq	0:fac0542384d7	3461	/** Peripheral MTB base address */
allonq	0:fac0542384d7	3462	#define MTB_BASE (0xF0000000u)
allonq	0:fac0542384d7	3463	/** Peripheral MTB base pointer */
allonq	0:fac0542384d7	3464	#define MTB ((MTB_Type *)MTB_BASE)
allonq	0:fac0542384d7	3465	/** Array initializer of MTB peripheral base pointers */
allonq	0:fac0542384d7	3466	#define MTB_BASES { MTB }
allonq	0:fac0542384d7	3467
allonq	0:fac0542384d7	3468	/*!
allonq	0:fac0542384d7	3469	* @}
allonq	0:fac0542384d7	3470	/ / end of group MTB_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3471
allonq	0:fac0542384d7	3472
allonq	0:fac0542384d7	3473	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3474	-- MTBDWT Peripheral Access Layer
allonq	0:fac0542384d7	3475	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3476
allonq	0:fac0542384d7	3477	/*!
allonq	0:fac0542384d7	3478	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
allonq	0:fac0542384d7	3479	* @{
allonq	0:fac0542384d7	3480	*/
allonq	0:fac0542384d7	3481
allonq	0:fac0542384d7	3482	/** MTBDWT - Register Layout Typedef */
allonq	0:fac0542384d7	3483	typedef struct {
allonq	0:fac0542384d7	3484	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
allonq	0:fac0542384d7	3485	uint8_t RESERVED_0[28];
allonq	0:fac0542384d7	3486	struct { /* offset: 0x20, array step: 0x10 */
allonq	0:fac0542384d7	3487	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
allonq	0:fac0542384d7	3488	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
allonq	0:fac0542384d7	3489	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
allonq	0:fac0542384d7	3490	uint8_t RESERVED_0[4];
allonq	0:fac0542384d7	3491	} COMPARATOR[2];
allonq	0:fac0542384d7	3492	uint8_t RESERVED_1[448];
allonq	0:fac0542384d7	3493	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
allonq	0:fac0542384d7	3494	uint8_t RESERVED_2[3524];
allonq	0:fac0542384d7	3495	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
allonq	0:fac0542384d7	3496	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
allonq	0:fac0542384d7	3497	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
allonq	0:fac0542384d7	3498	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
allonq	0:fac0542384d7	3499	} MTBDWT_Type;
allonq	0:fac0542384d7	3500
allonq	0:fac0542384d7	3501	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3502	-- MTBDWT Register Masks
allonq	0:fac0542384d7	3503	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3504
allonq	0:fac0542384d7	3505	/*!
allonq	0:fac0542384d7	3506	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
allonq	0:fac0542384d7	3507	* @{
allonq	0:fac0542384d7	3508	*/
allonq	0:fac0542384d7	3509
allonq	0:fac0542384d7	3510	/* CTRL Bit Fields */
allonq	0:fac0542384d7	3511	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
allonq	0:fac0542384d7	3512	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
allonq	0:fac0542384d7	3513	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
allonq	0:fac0542384d7	3514	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
allonq	0:fac0542384d7	3515	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
allonq	0:fac0542384d7	3516	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
allonq	0:fac0542384d7	3517	/* COMP Bit Fields */
allonq	0:fac0542384d7	3518	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3519	#define MTBDWT_COMP_COMP_SHIFT 0
allonq	0:fac0542384d7	3520	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
allonq	0:fac0542384d7	3521	/* MASK Bit Fields */
allonq	0:fac0542384d7	3522	#define MTBDWT_MASK_MASK_MASK 0x1Fu
allonq	0:fac0542384d7	3523	#define MTBDWT_MASK_MASK_SHIFT 0
allonq	0:fac0542384d7	3524	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
allonq	0:fac0542384d7	3525	/* FCT Bit Fields */
allonq	0:fac0542384d7	3526	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
allonq	0:fac0542384d7	3527	#define MTBDWT_FCT_FUNCTION_SHIFT 0
allonq	0:fac0542384d7	3528	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
allonq	0:fac0542384d7	3529	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
allonq	0:fac0542384d7	3530	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
allonq	0:fac0542384d7	3531	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
allonq	0:fac0542384d7	3532	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
allonq	0:fac0542384d7	3533	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
allonq	0:fac0542384d7	3534	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
allonq	0:fac0542384d7	3535	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
allonq	0:fac0542384d7	3536	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
allonq	0:fac0542384d7	3537	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
allonq	0:fac0542384d7	3538	#define MTBDWT_FCT_MATCHED_SHIFT 24
allonq	0:fac0542384d7	3539	/* TBCTRL Bit Fields */
allonq	0:fac0542384d7	3540	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
allonq	0:fac0542384d7	3541	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
allonq	0:fac0542384d7	3542	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
allonq	0:fac0542384d7	3543	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
allonq	0:fac0542384d7	3544	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
allonq	0:fac0542384d7	3545	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
allonq	0:fac0542384d7	3546	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
allonq	0:fac0542384d7	3547	/* DEVICECFG Bit Fields */
allonq	0:fac0542384d7	3548	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3549	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
allonq	0:fac0542384d7	3550	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
allonq	0:fac0542384d7	3551	/* DEVICETYPID Bit Fields */
allonq	0:fac0542384d7	3552	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3553	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
allonq	0:fac0542384d7	3554	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
allonq	0:fac0542384d7	3555	/* PERIPHID Bit Fields */
allonq	0:fac0542384d7	3556	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3557	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	3558	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
allonq	0:fac0542384d7	3559	/* COMPID Bit Fields */
allonq	0:fac0542384d7	3560	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3561	#define MTBDWT_COMPID_COMPID_SHIFT 0
allonq	0:fac0542384d7	3562	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
allonq	0:fac0542384d7	3563
allonq	0:fac0542384d7	3564	/*!
allonq	0:fac0542384d7	3565	* @}
allonq	0:fac0542384d7	3566	/ / end of group MTBDWT_Register_Masks */
allonq	0:fac0542384d7	3567
allonq	0:fac0542384d7	3568
allonq	0:fac0542384d7	3569	/* MTBDWT - Peripheral instance base addresses */
allonq	0:fac0542384d7	3570	/** Peripheral MTBDWT base address */
allonq	0:fac0542384d7	3571	#define MTBDWT_BASE (0xF0001000u)
allonq	0:fac0542384d7	3572	/** Peripheral MTBDWT base pointer */
allonq	0:fac0542384d7	3573	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
allonq	0:fac0542384d7	3574	/** Array initializer of MTBDWT peripheral base pointers */
allonq	0:fac0542384d7	3575	#define MTBDWT_BASES { MTBDWT }
allonq	0:fac0542384d7	3576
allonq	0:fac0542384d7	3577	/*!
allonq	0:fac0542384d7	3578	* @}
allonq	0:fac0542384d7	3579	/ / end of group MTBDWT_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3580
allonq	0:fac0542384d7	3581
allonq	0:fac0542384d7	3582	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3583	-- NV Peripheral Access Layer
allonq	0:fac0542384d7	3584	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3585
allonq	0:fac0542384d7	3586	/*!
allonq	0:fac0542384d7	3587	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
allonq	0:fac0542384d7	3588	* @{
allonq	0:fac0542384d7	3589	*/
allonq	0:fac0542384d7	3590
allonq	0:fac0542384d7	3591	/** NV - Register Layout Typedef */
allonq	0:fac0542384d7	3592	typedef struct {
allonq	0:fac0542384d7	3593	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
allonq	0:fac0542384d7	3594	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
allonq	0:fac0542384d7	3595	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
allonq	0:fac0542384d7	3596	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
allonq	0:fac0542384d7	3597	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
allonq	0:fac0542384d7	3598	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
allonq	0:fac0542384d7	3599	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
allonq	0:fac0542384d7	3600	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
allonq	0:fac0542384d7	3601	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
allonq	0:fac0542384d7	3602	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
allonq	0:fac0542384d7	3603	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
allonq	0:fac0542384d7	3604	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
allonq	0:fac0542384d7	3605	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
allonq	0:fac0542384d7	3606	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
allonq	0:fac0542384d7	3607	} NV_Type;
allonq	0:fac0542384d7	3608
allonq	0:fac0542384d7	3609	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3610	-- NV Register Masks
allonq	0:fac0542384d7	3611	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3612
allonq	0:fac0542384d7	3613	/*!
allonq	0:fac0542384d7	3614	* @addtogroup NV_Register_Masks NV Register Masks
allonq	0:fac0542384d7	3615	* @{
allonq	0:fac0542384d7	3616	*/
allonq	0:fac0542384d7	3617
allonq	0:fac0542384d7	3618	/* BACKKEY3 Bit Fields */
allonq	0:fac0542384d7	3619	#define NV_BACKKEY3_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3620	#define NV_BACKKEY3_KEY_SHIFT 0
allonq	0:fac0542384d7	3621	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
allonq	0:fac0542384d7	3622	/* BACKKEY2 Bit Fields */
allonq	0:fac0542384d7	3623	#define NV_BACKKEY2_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3624	#define NV_BACKKEY2_KEY_SHIFT 0
allonq	0:fac0542384d7	3625	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
allonq	0:fac0542384d7	3626	/* BACKKEY1 Bit Fields */
allonq	0:fac0542384d7	3627	#define NV_BACKKEY1_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3628	#define NV_BACKKEY1_KEY_SHIFT 0
allonq	0:fac0542384d7	3629	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
allonq	0:fac0542384d7	3630	/* BACKKEY0 Bit Fields */
allonq	0:fac0542384d7	3631	#define NV_BACKKEY0_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3632	#define NV_BACKKEY0_KEY_SHIFT 0
allonq	0:fac0542384d7	3633	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
allonq	0:fac0542384d7	3634	/* BACKKEY7 Bit Fields */
allonq	0:fac0542384d7	3635	#define NV_BACKKEY7_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3636	#define NV_BACKKEY7_KEY_SHIFT 0
allonq	0:fac0542384d7	3637	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
allonq	0:fac0542384d7	3638	/* BACKKEY6 Bit Fields */
allonq	0:fac0542384d7	3639	#define NV_BACKKEY6_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3640	#define NV_BACKKEY6_KEY_SHIFT 0
allonq	0:fac0542384d7	3641	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
allonq	0:fac0542384d7	3642	/* BACKKEY5 Bit Fields */
allonq	0:fac0542384d7	3643	#define NV_BACKKEY5_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3644	#define NV_BACKKEY5_KEY_SHIFT 0
allonq	0:fac0542384d7	3645	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
allonq	0:fac0542384d7	3646	/* BACKKEY4 Bit Fields */
allonq	0:fac0542384d7	3647	#define NV_BACKKEY4_KEY_MASK 0xFFu
allonq	0:fac0542384d7	3648	#define NV_BACKKEY4_KEY_SHIFT 0
allonq	0:fac0542384d7	3649	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
allonq	0:fac0542384d7	3650	/* FPROT3 Bit Fields */
allonq	0:fac0542384d7	3651	#define NV_FPROT3_PROT_MASK 0xFFu
allonq	0:fac0542384d7	3652	#define NV_FPROT3_PROT_SHIFT 0
allonq	0:fac0542384d7	3653	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
allonq	0:fac0542384d7	3654	/* FPROT2 Bit Fields */
allonq	0:fac0542384d7	3655	#define NV_FPROT2_PROT_MASK 0xFFu
allonq	0:fac0542384d7	3656	#define NV_FPROT2_PROT_SHIFT 0
allonq	0:fac0542384d7	3657	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
allonq	0:fac0542384d7	3658	/* FPROT1 Bit Fields */
allonq	0:fac0542384d7	3659	#define NV_FPROT1_PROT_MASK 0xFFu
allonq	0:fac0542384d7	3660	#define NV_FPROT1_PROT_SHIFT 0
allonq	0:fac0542384d7	3661	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
allonq	0:fac0542384d7	3662	/* FPROT0 Bit Fields */
allonq	0:fac0542384d7	3663	#define NV_FPROT0_PROT_MASK 0xFFu
allonq	0:fac0542384d7	3664	#define NV_FPROT0_PROT_SHIFT 0
allonq	0:fac0542384d7	3665	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
allonq	0:fac0542384d7	3666	/* FSEC Bit Fields */
allonq	0:fac0542384d7	3667	#define NV_FSEC_SEC_MASK 0x3u
allonq	0:fac0542384d7	3668	#define NV_FSEC_SEC_SHIFT 0
allonq	0:fac0542384d7	3669	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
allonq	0:fac0542384d7	3670	#define NV_FSEC_FSLACC_MASK 0xCu
allonq	0:fac0542384d7	3671	#define NV_FSEC_FSLACC_SHIFT 2
allonq	0:fac0542384d7	3672	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
allonq	0:fac0542384d7	3673	#define NV_FSEC_MEEN_MASK 0x30u
allonq	0:fac0542384d7	3674	#define NV_FSEC_MEEN_SHIFT 4
allonq	0:fac0542384d7	3675	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
allonq	0:fac0542384d7	3676	#define NV_FSEC_KEYEN_MASK 0xC0u
allonq	0:fac0542384d7	3677	#define NV_FSEC_KEYEN_SHIFT 6
allonq	0:fac0542384d7	3678	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
allonq	0:fac0542384d7	3679	/* FOPT Bit Fields */
allonq	0:fac0542384d7	3680	#define NV_FOPT_LPBOOT0_MASK 0x1u
allonq	0:fac0542384d7	3681	#define NV_FOPT_LPBOOT0_SHIFT 0
allonq	0:fac0542384d7	3682	#define NV_FOPT_NMI_DIS_MASK 0x4u
allonq	0:fac0542384d7	3683	#define NV_FOPT_NMI_DIS_SHIFT 2
allonq	0:fac0542384d7	3684	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
allonq	0:fac0542384d7	3685	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
allonq	0:fac0542384d7	3686	#define NV_FOPT_LPBOOT1_MASK 0x10u
allonq	0:fac0542384d7	3687	#define NV_FOPT_LPBOOT1_SHIFT 4
allonq	0:fac0542384d7	3688	#define NV_FOPT_FAST_INIT_MASK 0x20u
allonq	0:fac0542384d7	3689	#define NV_FOPT_FAST_INIT_SHIFT 5
allonq	0:fac0542384d7	3690
allonq	0:fac0542384d7	3691	/*!
allonq	0:fac0542384d7	3692	* @}
allonq	0:fac0542384d7	3693	/ / end of group NV_Register_Masks */
allonq	0:fac0542384d7	3694
allonq	0:fac0542384d7	3695
allonq	0:fac0542384d7	3696	/* NV - Peripheral instance base addresses */
allonq	0:fac0542384d7	3697	/** Peripheral FTFA_FlashConfig base address */
allonq	0:fac0542384d7	3698	#define FTFA_FlashConfig_BASE (0x400u)
allonq	0:fac0542384d7	3699	/** Peripheral FTFA_FlashConfig base pointer */
allonq	0:fac0542384d7	3700	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
allonq	0:fac0542384d7	3701	/** Array initializer of NV peripheral base pointers */
allonq	0:fac0542384d7	3702	#define NV_BASES { FTFA_FlashConfig }
allonq	0:fac0542384d7	3703
allonq	0:fac0542384d7	3704	/*!
allonq	0:fac0542384d7	3705	* @}
allonq	0:fac0542384d7	3706	/ / end of group NV_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3707
allonq	0:fac0542384d7	3708
allonq	0:fac0542384d7	3709	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3710	-- OSC Peripheral Access Layer
allonq	0:fac0542384d7	3711	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3712
allonq	0:fac0542384d7	3713	/*!
allonq	0:fac0542384d7	3714	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
allonq	0:fac0542384d7	3715	* @{
allonq	0:fac0542384d7	3716	*/
allonq	0:fac0542384d7	3717
allonq	0:fac0542384d7	3718	/** OSC - Register Layout Typedef */
allonq	0:fac0542384d7	3719	typedef struct {
allonq	0:fac0542384d7	3720	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
allonq	0:fac0542384d7	3721	} OSC_Type;
allonq	0:fac0542384d7	3722
allonq	0:fac0542384d7	3723	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3724	-- OSC Register Masks
allonq	0:fac0542384d7	3725	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3726
allonq	0:fac0542384d7	3727	/*!
allonq	0:fac0542384d7	3728	* @addtogroup OSC_Register_Masks OSC Register Masks
allonq	0:fac0542384d7	3729	* @{
allonq	0:fac0542384d7	3730	*/
allonq	0:fac0542384d7	3731
allonq	0:fac0542384d7	3732	/* CR Bit Fields */
allonq	0:fac0542384d7	3733	#define OSC_CR_SC16P_MASK 0x1u
allonq	0:fac0542384d7	3734	#define OSC_CR_SC16P_SHIFT 0
allonq	0:fac0542384d7	3735	#define OSC_CR_SC8P_MASK 0x2u
allonq	0:fac0542384d7	3736	#define OSC_CR_SC8P_SHIFT 1
allonq	0:fac0542384d7	3737	#define OSC_CR_SC4P_MASK 0x4u
allonq	0:fac0542384d7	3738	#define OSC_CR_SC4P_SHIFT 2
allonq	0:fac0542384d7	3739	#define OSC_CR_SC2P_MASK 0x8u
allonq	0:fac0542384d7	3740	#define OSC_CR_SC2P_SHIFT 3
allonq	0:fac0542384d7	3741	#define OSC_CR_EREFSTEN_MASK 0x20u
allonq	0:fac0542384d7	3742	#define OSC_CR_EREFSTEN_SHIFT 5
allonq	0:fac0542384d7	3743	#define OSC_CR_ERCLKEN_MASK 0x80u
allonq	0:fac0542384d7	3744	#define OSC_CR_ERCLKEN_SHIFT 7
allonq	0:fac0542384d7	3745
allonq	0:fac0542384d7	3746	/*!
allonq	0:fac0542384d7	3747	* @}
allonq	0:fac0542384d7	3748	/ / end of group OSC_Register_Masks */
allonq	0:fac0542384d7	3749
allonq	0:fac0542384d7	3750
allonq	0:fac0542384d7	3751	/* OSC - Peripheral instance base addresses */
allonq	0:fac0542384d7	3752	/** Peripheral OSC0 base address */
allonq	0:fac0542384d7	3753	#define OSC0_BASE (0x40065000u)
allonq	0:fac0542384d7	3754	/** Peripheral OSC0 base pointer */
allonq	0:fac0542384d7	3755	#define OSC0 ((OSC_Type *)OSC0_BASE)
allonq	0:fac0542384d7	3756	/** Array initializer of OSC peripheral base pointers */
allonq	0:fac0542384d7	3757	#define OSC_BASES { OSC0 }
allonq	0:fac0542384d7	3758
allonq	0:fac0542384d7	3759	/*!
allonq	0:fac0542384d7	3760	* @}
allonq	0:fac0542384d7	3761	/ / end of group OSC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3762
allonq	0:fac0542384d7	3763
allonq	0:fac0542384d7	3764	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3765	-- PIT Peripheral Access Layer
allonq	0:fac0542384d7	3766	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3767
allonq	0:fac0542384d7	3768	/*!
allonq	0:fac0542384d7	3769	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
allonq	0:fac0542384d7	3770	* @{
allonq	0:fac0542384d7	3771	*/
allonq	0:fac0542384d7	3772
allonq	0:fac0542384d7	3773	/** PIT - Register Layout Typedef */
allonq	0:fac0542384d7	3774	typedef struct {
allonq	0:fac0542384d7	3775	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
allonq	0:fac0542384d7	3776	uint8_t RESERVED_0[220];
allonq	0:fac0542384d7	3777	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
allonq	0:fac0542384d7	3778	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
allonq	0:fac0542384d7	3779	uint8_t RESERVED_1[24];
allonq	0:fac0542384d7	3780	struct { /* offset: 0x100, array step: 0x10 */
allonq	0:fac0542384d7	3781	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
allonq	0:fac0542384d7	3782	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
allonq	0:fac0542384d7	3783	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
allonq	0:fac0542384d7	3784	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
allonq	0:fac0542384d7	3785	} CHANNEL[2];
allonq	0:fac0542384d7	3786	} PIT_Type;
allonq	0:fac0542384d7	3787
allonq	0:fac0542384d7	3788	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3789	-- PIT Register Masks
allonq	0:fac0542384d7	3790	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3791
allonq	0:fac0542384d7	3792	/*!
allonq	0:fac0542384d7	3793	* @addtogroup PIT_Register_Masks PIT Register Masks
allonq	0:fac0542384d7	3794	* @{
allonq	0:fac0542384d7	3795	*/
allonq	0:fac0542384d7	3796
allonq	0:fac0542384d7	3797	/* MCR Bit Fields */
allonq	0:fac0542384d7	3798	#define PIT_MCR_FRZ_MASK 0x1u
allonq	0:fac0542384d7	3799	#define PIT_MCR_FRZ_SHIFT 0
allonq	0:fac0542384d7	3800	#define PIT_MCR_MDIS_MASK 0x2u
allonq	0:fac0542384d7	3801	#define PIT_MCR_MDIS_SHIFT 1
allonq	0:fac0542384d7	3802	/* LTMR64H Bit Fields */
allonq	0:fac0542384d7	3803	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3804	#define PIT_LTMR64H_LTH_SHIFT 0
allonq	0:fac0542384d7	3805	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
allonq	0:fac0542384d7	3806	/* LTMR64L Bit Fields */
allonq	0:fac0542384d7	3807	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3808	#define PIT_LTMR64L_LTL_SHIFT 0
allonq	0:fac0542384d7	3809	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
allonq	0:fac0542384d7	3810	/* LDVAL Bit Fields */
allonq	0:fac0542384d7	3811	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3812	#define PIT_LDVAL_TSV_SHIFT 0
allonq	0:fac0542384d7	3813	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
allonq	0:fac0542384d7	3814	/* CVAL Bit Fields */
allonq	0:fac0542384d7	3815	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3816	#define PIT_CVAL_TVL_SHIFT 0
allonq	0:fac0542384d7	3817	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
allonq	0:fac0542384d7	3818	/* TCTRL Bit Fields */
allonq	0:fac0542384d7	3819	#define PIT_TCTRL_TEN_MASK 0x1u
allonq	0:fac0542384d7	3820	#define PIT_TCTRL_TEN_SHIFT 0
allonq	0:fac0542384d7	3821	#define PIT_TCTRL_TIE_MASK 0x2u
allonq	0:fac0542384d7	3822	#define PIT_TCTRL_TIE_SHIFT 1
allonq	0:fac0542384d7	3823	#define PIT_TCTRL_CHN_MASK 0x4u
allonq	0:fac0542384d7	3824	#define PIT_TCTRL_CHN_SHIFT 2
allonq	0:fac0542384d7	3825	/* TFLG Bit Fields */
allonq	0:fac0542384d7	3826	#define PIT_TFLG_TIF_MASK 0x1u
allonq	0:fac0542384d7	3827	#define PIT_TFLG_TIF_SHIFT 0
allonq	0:fac0542384d7	3828
allonq	0:fac0542384d7	3829	/*!
allonq	0:fac0542384d7	3830	* @}
allonq	0:fac0542384d7	3831	/ / end of group PIT_Register_Masks */
allonq	0:fac0542384d7	3832
allonq	0:fac0542384d7	3833
allonq	0:fac0542384d7	3834	/* PIT - Peripheral instance base addresses */
allonq	0:fac0542384d7	3835	/** Peripheral PIT base address */
allonq	0:fac0542384d7	3836	#define PIT_BASE (0x40037000u)
allonq	0:fac0542384d7	3837	/** Peripheral PIT base pointer */
allonq	0:fac0542384d7	3838	#define PIT ((PIT_Type *)PIT_BASE)
allonq	0:fac0542384d7	3839	/** Array initializer of PIT peripheral base pointers */
allonq	0:fac0542384d7	3840	#define PIT_BASES { PIT }
allonq	0:fac0542384d7	3841
allonq	0:fac0542384d7	3842	/*!
allonq	0:fac0542384d7	3843	* @}
allonq	0:fac0542384d7	3844	/ / end of group PIT_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3845
allonq	0:fac0542384d7	3846
allonq	0:fac0542384d7	3847	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3848	-- PMC Peripheral Access Layer
allonq	0:fac0542384d7	3849	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3850
allonq	0:fac0542384d7	3851	/*!
allonq	0:fac0542384d7	3852	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
allonq	0:fac0542384d7	3853	* @{
allonq	0:fac0542384d7	3854	*/
allonq	0:fac0542384d7	3855
allonq	0:fac0542384d7	3856	/** PMC - Register Layout Typedef */
allonq	0:fac0542384d7	3857	typedef struct {
allonq	0:fac0542384d7	3858	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
allonq	0:fac0542384d7	3859	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
allonq	0:fac0542384d7	3860	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
allonq	0:fac0542384d7	3861	} PMC_Type;
allonq	0:fac0542384d7	3862
allonq	0:fac0542384d7	3863	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3864	-- PMC Register Masks
allonq	0:fac0542384d7	3865	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3866
allonq	0:fac0542384d7	3867	/*!
allonq	0:fac0542384d7	3868	* @addtogroup PMC_Register_Masks PMC Register Masks
allonq	0:fac0542384d7	3869	* @{
allonq	0:fac0542384d7	3870	*/
allonq	0:fac0542384d7	3871
allonq	0:fac0542384d7	3872	/* LVDSC1 Bit Fields */
allonq	0:fac0542384d7	3873	#define PMC_LVDSC1_LVDV_MASK 0x3u
allonq	0:fac0542384d7	3874	#define PMC_LVDSC1_LVDV_SHIFT 0
allonq	0:fac0542384d7	3875	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
allonq	0:fac0542384d7	3876	#define PMC_LVDSC1_LVDRE_MASK 0x10u
allonq	0:fac0542384d7	3877	#define PMC_LVDSC1_LVDRE_SHIFT 4
allonq	0:fac0542384d7	3878	#define PMC_LVDSC1_LVDIE_MASK 0x20u
allonq	0:fac0542384d7	3879	#define PMC_LVDSC1_LVDIE_SHIFT 5
allonq	0:fac0542384d7	3880	#define PMC_LVDSC1_LVDACK_MASK 0x40u
allonq	0:fac0542384d7	3881	#define PMC_LVDSC1_LVDACK_SHIFT 6
allonq	0:fac0542384d7	3882	#define PMC_LVDSC1_LVDF_MASK 0x80u
allonq	0:fac0542384d7	3883	#define PMC_LVDSC1_LVDF_SHIFT 7
allonq	0:fac0542384d7	3884	/* LVDSC2 Bit Fields */
allonq	0:fac0542384d7	3885	#define PMC_LVDSC2_LVWV_MASK 0x3u
allonq	0:fac0542384d7	3886	#define PMC_LVDSC2_LVWV_SHIFT 0
allonq	0:fac0542384d7	3887	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
allonq	0:fac0542384d7	3888	#define PMC_LVDSC2_LVWIE_MASK 0x20u
allonq	0:fac0542384d7	3889	#define PMC_LVDSC2_LVWIE_SHIFT 5
allonq	0:fac0542384d7	3890	#define PMC_LVDSC2_LVWACK_MASK 0x40u
allonq	0:fac0542384d7	3891	#define PMC_LVDSC2_LVWACK_SHIFT 6
allonq	0:fac0542384d7	3892	#define PMC_LVDSC2_LVWF_MASK 0x80u
allonq	0:fac0542384d7	3893	#define PMC_LVDSC2_LVWF_SHIFT 7
allonq	0:fac0542384d7	3894	/* REGSC Bit Fields */
allonq	0:fac0542384d7	3895	#define PMC_REGSC_BGBE_MASK 0x1u
allonq	0:fac0542384d7	3896	#define PMC_REGSC_BGBE_SHIFT 0
allonq	0:fac0542384d7	3897	#define PMC_REGSC_REGONS_MASK 0x4u
allonq	0:fac0542384d7	3898	#define PMC_REGSC_REGONS_SHIFT 2
allonq	0:fac0542384d7	3899	#define PMC_REGSC_ACKISO_MASK 0x8u
allonq	0:fac0542384d7	3900	#define PMC_REGSC_ACKISO_SHIFT 3
allonq	0:fac0542384d7	3901	#define PMC_REGSC_BGEN_MASK 0x10u
allonq	0:fac0542384d7	3902	#define PMC_REGSC_BGEN_SHIFT 4
allonq	0:fac0542384d7	3903
allonq	0:fac0542384d7	3904	/*!
allonq	0:fac0542384d7	3905	* @}
allonq	0:fac0542384d7	3906	/ / end of group PMC_Register_Masks */
allonq	0:fac0542384d7	3907
allonq	0:fac0542384d7	3908
allonq	0:fac0542384d7	3909	/* PMC - Peripheral instance base addresses */
allonq	0:fac0542384d7	3910	/** Peripheral PMC base address */
allonq	0:fac0542384d7	3911	#define PMC_BASE (0x4007D000u)
allonq	0:fac0542384d7	3912	/** Peripheral PMC base pointer */
allonq	0:fac0542384d7	3913	#define PMC ((PMC_Type *)PMC_BASE)
allonq	0:fac0542384d7	3914	/** Array initializer of PMC peripheral base pointers */
allonq	0:fac0542384d7	3915	#define PMC_BASES { PMC }
allonq	0:fac0542384d7	3916
allonq	0:fac0542384d7	3917	/*!
allonq	0:fac0542384d7	3918	* @}
allonq	0:fac0542384d7	3919	/ / end of group PMC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	3920
allonq	0:fac0542384d7	3921
allonq	0:fac0542384d7	3922	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3923	-- PORT Peripheral Access Layer
allonq	0:fac0542384d7	3924	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3925
allonq	0:fac0542384d7	3926	/*!
allonq	0:fac0542384d7	3927	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
allonq	0:fac0542384d7	3928	* @{
allonq	0:fac0542384d7	3929	*/
allonq	0:fac0542384d7	3930
allonq	0:fac0542384d7	3931	/** PORT - Register Layout Typedef */
allonq	0:fac0542384d7	3932	typedef struct {
allonq	0:fac0542384d7	3933	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
allonq	0:fac0542384d7	3934	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
allonq	0:fac0542384d7	3935	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
allonq	0:fac0542384d7	3936	uint8_t RESERVED_0[24];
allonq	0:fac0542384d7	3937	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
allonq	0:fac0542384d7	3938	} PORT_Type;
allonq	0:fac0542384d7	3939
allonq	0:fac0542384d7	3940	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	3941	-- PORT Register Masks
allonq	0:fac0542384d7	3942	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	3943
allonq	0:fac0542384d7	3944	/*!
allonq	0:fac0542384d7	3945	* @addtogroup PORT_Register_Masks PORT Register Masks
allonq	0:fac0542384d7	3946	* @{
allonq	0:fac0542384d7	3947	*/
allonq	0:fac0542384d7	3948
allonq	0:fac0542384d7	3949	/* PCR Bit Fields */
allonq	0:fac0542384d7	3950	#define PORT_PCR_PS_MASK 0x1u
allonq	0:fac0542384d7	3951	#define PORT_PCR_PS_SHIFT 0
allonq	0:fac0542384d7	3952	#define PORT_PCR_PE_MASK 0x2u
allonq	0:fac0542384d7	3953	#define PORT_PCR_PE_SHIFT 1
allonq	0:fac0542384d7	3954	#define PORT_PCR_SRE_MASK 0x4u
allonq	0:fac0542384d7	3955	#define PORT_PCR_SRE_SHIFT 2
allonq	0:fac0542384d7	3956	#define PORT_PCR_PFE_MASK 0x10u
allonq	0:fac0542384d7	3957	#define PORT_PCR_PFE_SHIFT 4
allonq	0:fac0542384d7	3958	#define PORT_PCR_DSE_MASK 0x40u
allonq	0:fac0542384d7	3959	#define PORT_PCR_DSE_SHIFT 6
allonq	0:fac0542384d7	3960	#define PORT_PCR_MUX_MASK 0x700u
allonq	0:fac0542384d7	3961	#define PORT_PCR_MUX_SHIFT 8
allonq	0:fac0542384d7	3962	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
allonq	0:fac0542384d7	3963	#define PORT_PCR_IRQC_MASK 0xF0000u
allonq	0:fac0542384d7	3964	#define PORT_PCR_IRQC_SHIFT 16
allonq	0:fac0542384d7	3965	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
allonq	0:fac0542384d7	3966	#define PORT_PCR_ISF_MASK 0x1000000u
allonq	0:fac0542384d7	3967	#define PORT_PCR_ISF_SHIFT 24
allonq	0:fac0542384d7	3968	/* GPCLR Bit Fields */
allonq	0:fac0542384d7	3969	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
allonq	0:fac0542384d7	3970	#define PORT_GPCLR_GPWD_SHIFT 0
allonq	0:fac0542384d7	3971	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
allonq	0:fac0542384d7	3972	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
allonq	0:fac0542384d7	3973	#define PORT_GPCLR_GPWE_SHIFT 16
allonq	0:fac0542384d7	3974	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
allonq	0:fac0542384d7	3975	/* GPCHR Bit Fields */
allonq	0:fac0542384d7	3976	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
allonq	0:fac0542384d7	3977	#define PORT_GPCHR_GPWD_SHIFT 0
allonq	0:fac0542384d7	3978	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
allonq	0:fac0542384d7	3979	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
allonq	0:fac0542384d7	3980	#define PORT_GPCHR_GPWE_SHIFT 16
allonq	0:fac0542384d7	3981	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
allonq	0:fac0542384d7	3982	/* ISFR Bit Fields */
allonq	0:fac0542384d7	3983	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	3984	#define PORT_ISFR_ISF_SHIFT 0
allonq	0:fac0542384d7	3985	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
allonq	0:fac0542384d7	3986
allonq	0:fac0542384d7	3987	/*!
allonq	0:fac0542384d7	3988	* @}
allonq	0:fac0542384d7	3989	/ / end of group PORT_Register_Masks */
allonq	0:fac0542384d7	3990
allonq	0:fac0542384d7	3991
allonq	0:fac0542384d7	3992	/* PORT - Peripheral instance base addresses */
allonq	0:fac0542384d7	3993	/** Peripheral PORTA base address */
allonq	0:fac0542384d7	3994	#define PORTA_BASE (0x40049000u)
allonq	0:fac0542384d7	3995	/** Peripheral PORTA base pointer */
allonq	0:fac0542384d7	3996	#define PORTA ((PORT_Type *)PORTA_BASE)
allonq	0:fac0542384d7	3997	/** Peripheral PORTB base address */
allonq	0:fac0542384d7	3998	#define PORTB_BASE (0x4004A000u)
allonq	0:fac0542384d7	3999	/** Peripheral PORTB base pointer */
allonq	0:fac0542384d7	4000	#define PORTB ((PORT_Type *)PORTB_BASE)
allonq	0:fac0542384d7	4001	/** Peripheral PORTC base address */
allonq	0:fac0542384d7	4002	#define PORTC_BASE (0x4004B000u)
allonq	0:fac0542384d7	4003	/** Peripheral PORTC base pointer */
allonq	0:fac0542384d7	4004	#define PORTC ((PORT_Type *)PORTC_BASE)
allonq	0:fac0542384d7	4005	/** Peripheral PORTD base address */
allonq	0:fac0542384d7	4006	#define PORTD_BASE (0x4004C000u)
allonq	0:fac0542384d7	4007	/** Peripheral PORTD base pointer */
allonq	0:fac0542384d7	4008	#define PORTD ((PORT_Type *)PORTD_BASE)
allonq	0:fac0542384d7	4009	/** Peripheral PORTE base address */
allonq	0:fac0542384d7	4010	#define PORTE_BASE (0x4004D000u)
allonq	0:fac0542384d7	4011	/** Peripheral PORTE base pointer */
allonq	0:fac0542384d7	4012	#define PORTE ((PORT_Type *)PORTE_BASE)
allonq	0:fac0542384d7	4013	/** Array initializer of PORT peripheral base pointers */
allonq	0:fac0542384d7	4014	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
allonq	0:fac0542384d7	4015
allonq	0:fac0542384d7	4016	/*!
allonq	0:fac0542384d7	4017	* @}
allonq	0:fac0542384d7	4018	/ / end of group PORT_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4019
allonq	0:fac0542384d7	4020
allonq	0:fac0542384d7	4021	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4022	-- RCM Peripheral Access Layer
allonq	0:fac0542384d7	4023	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4024
allonq	0:fac0542384d7	4025	/*!
allonq	0:fac0542384d7	4026	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
allonq	0:fac0542384d7	4027	* @{
allonq	0:fac0542384d7	4028	*/
allonq	0:fac0542384d7	4029
allonq	0:fac0542384d7	4030	/** RCM - Register Layout Typedef */
allonq	0:fac0542384d7	4031	typedef struct {
allonq	0:fac0542384d7	4032	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
allonq	0:fac0542384d7	4033	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
allonq	0:fac0542384d7	4034	uint8_t RESERVED_0[2];
allonq	0:fac0542384d7	4035	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
allonq	0:fac0542384d7	4036	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
allonq	0:fac0542384d7	4037	} RCM_Type;
allonq	0:fac0542384d7	4038
allonq	0:fac0542384d7	4039	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4040	-- RCM Register Masks
allonq	0:fac0542384d7	4041	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4042
allonq	0:fac0542384d7	4043	/*!
allonq	0:fac0542384d7	4044	* @addtogroup RCM_Register_Masks RCM Register Masks
allonq	0:fac0542384d7	4045	* @{
allonq	0:fac0542384d7	4046	*/
allonq	0:fac0542384d7	4047
allonq	0:fac0542384d7	4048	/* SRS0 Bit Fields */
allonq	0:fac0542384d7	4049	#define RCM_SRS0_WAKEUP_MASK 0x1u
allonq	0:fac0542384d7	4050	#define RCM_SRS0_WAKEUP_SHIFT 0
allonq	0:fac0542384d7	4051	#define RCM_SRS0_LVD_MASK 0x2u
allonq	0:fac0542384d7	4052	#define RCM_SRS0_LVD_SHIFT 1
allonq	0:fac0542384d7	4053	#define RCM_SRS0_LOC_MASK 0x4u
allonq	0:fac0542384d7	4054	#define RCM_SRS0_LOC_SHIFT 2
allonq	0:fac0542384d7	4055	#define RCM_SRS0_LOL_MASK 0x8u
allonq	0:fac0542384d7	4056	#define RCM_SRS0_LOL_SHIFT 3
allonq	0:fac0542384d7	4057	#define RCM_SRS0_WDOG_MASK 0x20u
allonq	0:fac0542384d7	4058	#define RCM_SRS0_WDOG_SHIFT 5
allonq	0:fac0542384d7	4059	#define RCM_SRS0_PIN_MASK 0x40u
allonq	0:fac0542384d7	4060	#define RCM_SRS0_PIN_SHIFT 6
allonq	0:fac0542384d7	4061	#define RCM_SRS0_POR_MASK 0x80u
allonq	0:fac0542384d7	4062	#define RCM_SRS0_POR_SHIFT 7
allonq	0:fac0542384d7	4063	/* SRS1 Bit Fields */
allonq	0:fac0542384d7	4064	#define RCM_SRS1_LOCKUP_MASK 0x2u
allonq	0:fac0542384d7	4065	#define RCM_SRS1_LOCKUP_SHIFT 1
allonq	0:fac0542384d7	4066	#define RCM_SRS1_SW_MASK 0x4u
allonq	0:fac0542384d7	4067	#define RCM_SRS1_SW_SHIFT 2
allonq	0:fac0542384d7	4068	#define RCM_SRS1_MDM_AP_MASK 0x8u
allonq	0:fac0542384d7	4069	#define RCM_SRS1_MDM_AP_SHIFT 3
allonq	0:fac0542384d7	4070	#define RCM_SRS1_SACKERR_MASK 0x20u
allonq	0:fac0542384d7	4071	#define RCM_SRS1_SACKERR_SHIFT 5
allonq	0:fac0542384d7	4072	/* RPFC Bit Fields */
allonq	0:fac0542384d7	4073	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
allonq	0:fac0542384d7	4074	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
allonq	0:fac0542384d7	4075	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
allonq	0:fac0542384d7	4076	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
allonq	0:fac0542384d7	4077	#define RCM_RPFC_RSTFLTSS_SHIFT 2
allonq	0:fac0542384d7	4078	/* RPFW Bit Fields */
allonq	0:fac0542384d7	4079	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
allonq	0:fac0542384d7	4080	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
allonq	0:fac0542384d7	4081	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
allonq	0:fac0542384d7	4082
allonq	0:fac0542384d7	4083	/*!
allonq	0:fac0542384d7	4084	* @}
allonq	0:fac0542384d7	4085	/ / end of group RCM_Register_Masks */
allonq	0:fac0542384d7	4086
allonq	0:fac0542384d7	4087
allonq	0:fac0542384d7	4088	/* RCM - Peripheral instance base addresses */
allonq	0:fac0542384d7	4089	/** Peripheral RCM base address */
allonq	0:fac0542384d7	4090	#define RCM_BASE (0x4007F000u)
allonq	0:fac0542384d7	4091	/** Peripheral RCM base pointer */
allonq	0:fac0542384d7	4092	#define RCM ((RCM_Type *)RCM_BASE)
allonq	0:fac0542384d7	4093	/** Array initializer of RCM peripheral base pointers */
allonq	0:fac0542384d7	4094	#define RCM_BASES { RCM }
allonq	0:fac0542384d7	4095
allonq	0:fac0542384d7	4096	/*!
allonq	0:fac0542384d7	4097	* @}
allonq	0:fac0542384d7	4098	/ / end of group RCM_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4099
allonq	0:fac0542384d7	4100
allonq	0:fac0542384d7	4101	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4102	-- ROM Peripheral Access Layer
allonq	0:fac0542384d7	4103	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4104
allonq	0:fac0542384d7	4105	/*!
allonq	0:fac0542384d7	4106	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
allonq	0:fac0542384d7	4107	* @{
allonq	0:fac0542384d7	4108	*/
allonq	0:fac0542384d7	4109
allonq	0:fac0542384d7	4110	/** ROM - Register Layout Typedef */
allonq	0:fac0542384d7	4111	typedef struct {
allonq	0:fac0542384d7	4112	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
allonq	0:fac0542384d7	4113	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
allonq	0:fac0542384d7	4114	uint8_t RESERVED_0[4028];
allonq	0:fac0542384d7	4115	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
allonq	0:fac0542384d7	4116	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
allonq	0:fac0542384d7	4117	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
allonq	0:fac0542384d7	4118	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
allonq	0:fac0542384d7	4119	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
allonq	0:fac0542384d7	4120	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
allonq	0:fac0542384d7	4121	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
allonq	0:fac0542384d7	4122	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
allonq	0:fac0542384d7	4123	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
allonq	0:fac0542384d7	4124	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
allonq	0:fac0542384d7	4125	} ROM_Type;
allonq	0:fac0542384d7	4126
allonq	0:fac0542384d7	4127	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4128	-- ROM Register Masks
allonq	0:fac0542384d7	4129	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4130
allonq	0:fac0542384d7	4131	/*!
allonq	0:fac0542384d7	4132	* @addtogroup ROM_Register_Masks ROM Register Masks
allonq	0:fac0542384d7	4133	* @{
allonq	0:fac0542384d7	4134	*/
allonq	0:fac0542384d7	4135
allonq	0:fac0542384d7	4136	/* ENTRY Bit Fields */
allonq	0:fac0542384d7	4137	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4138	#define ROM_ENTRY_ENTRY_SHIFT 0
allonq	0:fac0542384d7	4139	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
allonq	0:fac0542384d7	4140	/* TABLEMARK Bit Fields */
allonq	0:fac0542384d7	4141	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4142	#define ROM_TABLEMARK_MARK_SHIFT 0
allonq	0:fac0542384d7	4143	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
allonq	0:fac0542384d7	4144	/* SYSACCESS Bit Fields */
allonq	0:fac0542384d7	4145	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4146	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
allonq	0:fac0542384d7	4147	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
allonq	0:fac0542384d7	4148	/* PERIPHID4 Bit Fields */
allonq	0:fac0542384d7	4149	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4150	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4151	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
allonq	0:fac0542384d7	4152	/* PERIPHID5 Bit Fields */
allonq	0:fac0542384d7	4153	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4154	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4155	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
allonq	0:fac0542384d7	4156	/* PERIPHID6 Bit Fields */
allonq	0:fac0542384d7	4157	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4158	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4159	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
allonq	0:fac0542384d7	4160	/* PERIPHID7 Bit Fields */
allonq	0:fac0542384d7	4161	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4162	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4163	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
allonq	0:fac0542384d7	4164	/* PERIPHID0 Bit Fields */
allonq	0:fac0542384d7	4165	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4166	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4167	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
allonq	0:fac0542384d7	4168	/* PERIPHID1 Bit Fields */
allonq	0:fac0542384d7	4169	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4170	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4171	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
allonq	0:fac0542384d7	4172	/* PERIPHID2 Bit Fields */
allonq	0:fac0542384d7	4173	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4174	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4175	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
allonq	0:fac0542384d7	4176	/* PERIPHID3 Bit Fields */
allonq	0:fac0542384d7	4177	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4178	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
allonq	0:fac0542384d7	4179	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
allonq	0:fac0542384d7	4180	/* COMPID Bit Fields */
allonq	0:fac0542384d7	4181	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4182	#define ROM_COMPID_COMPID_SHIFT 0
allonq	0:fac0542384d7	4183	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
allonq	0:fac0542384d7	4184
allonq	0:fac0542384d7	4185	/*!
allonq	0:fac0542384d7	4186	* @}
allonq	0:fac0542384d7	4187	/ / end of group ROM_Register_Masks */
allonq	0:fac0542384d7	4188
allonq	0:fac0542384d7	4189
allonq	0:fac0542384d7	4190	/* ROM - Peripheral instance base addresses */
allonq	0:fac0542384d7	4191	/** Peripheral ROM base address */
allonq	0:fac0542384d7	4192	#define ROM_BASE (0xF0002000u)
allonq	0:fac0542384d7	4193	/** Peripheral ROM base pointer */
allonq	0:fac0542384d7	4194	#define ROM ((ROM_Type *)ROM_BASE)
allonq	0:fac0542384d7	4195	/** Array initializer of ROM peripheral base pointers */
allonq	0:fac0542384d7	4196	#define ROM_BASES { ROM }
allonq	0:fac0542384d7	4197
allonq	0:fac0542384d7	4198	/*!
allonq	0:fac0542384d7	4199	* @}
allonq	0:fac0542384d7	4200	/ / end of group ROM_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4201
allonq	0:fac0542384d7	4202
allonq	0:fac0542384d7	4203	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4204	-- RTC Peripheral Access Layer
allonq	0:fac0542384d7	4205	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4206
allonq	0:fac0542384d7	4207	/*!
allonq	0:fac0542384d7	4208	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
allonq	0:fac0542384d7	4209	* @{
allonq	0:fac0542384d7	4210	*/
allonq	0:fac0542384d7	4211
allonq	0:fac0542384d7	4212	/** RTC - Register Layout Typedef */
allonq	0:fac0542384d7	4213	typedef struct {
allonq	0:fac0542384d7	4214	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
allonq	0:fac0542384d7	4215	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
allonq	0:fac0542384d7	4216	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
allonq	0:fac0542384d7	4217	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
allonq	0:fac0542384d7	4218	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
allonq	0:fac0542384d7	4219	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
allonq	0:fac0542384d7	4220	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
allonq	0:fac0542384d7	4221	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
allonq	0:fac0542384d7	4222	} RTC_Type;
allonq	0:fac0542384d7	4223
allonq	0:fac0542384d7	4224	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4225	-- RTC Register Masks
allonq	0:fac0542384d7	4226	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4227
allonq	0:fac0542384d7	4228	/*!
allonq	0:fac0542384d7	4229	* @addtogroup RTC_Register_Masks RTC Register Masks
allonq	0:fac0542384d7	4230	* @{
allonq	0:fac0542384d7	4231	*/
allonq	0:fac0542384d7	4232
allonq	0:fac0542384d7	4233	/* TSR Bit Fields */
allonq	0:fac0542384d7	4234	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4235	#define RTC_TSR_TSR_SHIFT 0
allonq	0:fac0542384d7	4236	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
allonq	0:fac0542384d7	4237	/* TPR Bit Fields */
allonq	0:fac0542384d7	4238	#define RTC_TPR_TPR_MASK 0xFFFFu
allonq	0:fac0542384d7	4239	#define RTC_TPR_TPR_SHIFT 0
allonq	0:fac0542384d7	4240	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
allonq	0:fac0542384d7	4241	/* TAR Bit Fields */
allonq	0:fac0542384d7	4242	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4243	#define RTC_TAR_TAR_SHIFT 0
allonq	0:fac0542384d7	4244	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
allonq	0:fac0542384d7	4245	/* TCR Bit Fields */
allonq	0:fac0542384d7	4246	#define RTC_TCR_TCR_MASK 0xFFu
allonq	0:fac0542384d7	4247	#define RTC_TCR_TCR_SHIFT 0
allonq	0:fac0542384d7	4248	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
allonq	0:fac0542384d7	4249	#define RTC_TCR_CIR_MASK 0xFF00u
allonq	0:fac0542384d7	4250	#define RTC_TCR_CIR_SHIFT 8
allonq	0:fac0542384d7	4251	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
allonq	0:fac0542384d7	4252	#define RTC_TCR_TCV_MASK 0xFF0000u
allonq	0:fac0542384d7	4253	#define RTC_TCR_TCV_SHIFT 16
allonq	0:fac0542384d7	4254	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
allonq	0:fac0542384d7	4255	#define RTC_TCR_CIC_MASK 0xFF000000u
allonq	0:fac0542384d7	4256	#define RTC_TCR_CIC_SHIFT 24
allonq	0:fac0542384d7	4257	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
allonq	0:fac0542384d7	4258	/* CR Bit Fields */
allonq	0:fac0542384d7	4259	#define RTC_CR_SWR_MASK 0x1u
allonq	0:fac0542384d7	4260	#define RTC_CR_SWR_SHIFT 0
allonq	0:fac0542384d7	4261	#define RTC_CR_WPE_MASK 0x2u
allonq	0:fac0542384d7	4262	#define RTC_CR_WPE_SHIFT 1
allonq	0:fac0542384d7	4263	#define RTC_CR_SUP_MASK 0x4u
allonq	0:fac0542384d7	4264	#define RTC_CR_SUP_SHIFT 2
allonq	0:fac0542384d7	4265	#define RTC_CR_UM_MASK 0x8u
allonq	0:fac0542384d7	4266	#define RTC_CR_UM_SHIFT 3
allonq	0:fac0542384d7	4267	#define RTC_CR_OSCE_MASK 0x100u
allonq	0:fac0542384d7	4268	#define RTC_CR_OSCE_SHIFT 8
allonq	0:fac0542384d7	4269	#define RTC_CR_CLKO_MASK 0x200u
allonq	0:fac0542384d7	4270	#define RTC_CR_CLKO_SHIFT 9
allonq	0:fac0542384d7	4271	#define RTC_CR_SC16P_MASK 0x400u
allonq	0:fac0542384d7	4272	#define RTC_CR_SC16P_SHIFT 10
allonq	0:fac0542384d7	4273	#define RTC_CR_SC8P_MASK 0x800u
allonq	0:fac0542384d7	4274	#define RTC_CR_SC8P_SHIFT 11
allonq	0:fac0542384d7	4275	#define RTC_CR_SC4P_MASK 0x1000u
allonq	0:fac0542384d7	4276	#define RTC_CR_SC4P_SHIFT 12
allonq	0:fac0542384d7	4277	#define RTC_CR_SC2P_MASK 0x2000u
allonq	0:fac0542384d7	4278	#define RTC_CR_SC2P_SHIFT 13
allonq	0:fac0542384d7	4279	/* SR Bit Fields */
allonq	0:fac0542384d7	4280	#define RTC_SR_TIF_MASK 0x1u
allonq	0:fac0542384d7	4281	#define RTC_SR_TIF_SHIFT 0
allonq	0:fac0542384d7	4282	#define RTC_SR_TOF_MASK 0x2u
allonq	0:fac0542384d7	4283	#define RTC_SR_TOF_SHIFT 1
allonq	0:fac0542384d7	4284	#define RTC_SR_TAF_MASK 0x4u
allonq	0:fac0542384d7	4285	#define RTC_SR_TAF_SHIFT 2
allonq	0:fac0542384d7	4286	#define RTC_SR_TCE_MASK 0x10u
allonq	0:fac0542384d7	4287	#define RTC_SR_TCE_SHIFT 4
allonq	0:fac0542384d7	4288	/* LR Bit Fields */
allonq	0:fac0542384d7	4289	#define RTC_LR_TCL_MASK 0x8u
allonq	0:fac0542384d7	4290	#define RTC_LR_TCL_SHIFT 3
allonq	0:fac0542384d7	4291	#define RTC_LR_CRL_MASK 0x10u
allonq	0:fac0542384d7	4292	#define RTC_LR_CRL_SHIFT 4
allonq	0:fac0542384d7	4293	#define RTC_LR_SRL_MASK 0x20u
allonq	0:fac0542384d7	4294	#define RTC_LR_SRL_SHIFT 5
allonq	0:fac0542384d7	4295	#define RTC_LR_LRL_MASK 0x40u
allonq	0:fac0542384d7	4296	#define RTC_LR_LRL_SHIFT 6
allonq	0:fac0542384d7	4297	/* IER Bit Fields */
allonq	0:fac0542384d7	4298	#define RTC_IER_TIIE_MASK 0x1u
allonq	0:fac0542384d7	4299	#define RTC_IER_TIIE_SHIFT 0
allonq	0:fac0542384d7	4300	#define RTC_IER_TOIE_MASK 0x2u
allonq	0:fac0542384d7	4301	#define RTC_IER_TOIE_SHIFT 1
allonq	0:fac0542384d7	4302	#define RTC_IER_TAIE_MASK 0x4u
allonq	0:fac0542384d7	4303	#define RTC_IER_TAIE_SHIFT 2
allonq	0:fac0542384d7	4304	#define RTC_IER_TSIE_MASK 0x10u
allonq	0:fac0542384d7	4305	#define RTC_IER_TSIE_SHIFT 4
allonq	0:fac0542384d7	4306	#define RTC_IER_WPON_MASK 0x80u
allonq	0:fac0542384d7	4307	#define RTC_IER_WPON_SHIFT 7
allonq	0:fac0542384d7	4308
allonq	0:fac0542384d7	4309	/*!
allonq	0:fac0542384d7	4310	* @}
allonq	0:fac0542384d7	4311	/ / end of group RTC_Register_Masks */
allonq	0:fac0542384d7	4312
allonq	0:fac0542384d7	4313
allonq	0:fac0542384d7	4314	/* RTC - Peripheral instance base addresses */
allonq	0:fac0542384d7	4315	/** Peripheral RTC base address */
allonq	0:fac0542384d7	4316	#define RTC_BASE (0x4003D000u)
allonq	0:fac0542384d7	4317	/** Peripheral RTC base pointer */
allonq	0:fac0542384d7	4318	#define RTC ((RTC_Type *)RTC_BASE)
allonq	0:fac0542384d7	4319	/** Array initializer of RTC peripheral base pointers */
allonq	0:fac0542384d7	4320	#define RTC_BASES { RTC }
allonq	0:fac0542384d7	4321
allonq	0:fac0542384d7	4322	/*!
allonq	0:fac0542384d7	4323	* @}
allonq	0:fac0542384d7	4324	/ / end of group RTC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4325
allonq	0:fac0542384d7	4326
allonq	0:fac0542384d7	4327	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4328	-- SIM Peripheral Access Layer
allonq	0:fac0542384d7	4329	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4330
allonq	0:fac0542384d7	4331	/*!
allonq	0:fac0542384d7	4332	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
allonq	0:fac0542384d7	4333	* @{
allonq	0:fac0542384d7	4334	*/
allonq	0:fac0542384d7	4335
allonq	0:fac0542384d7	4336	/** SIM - Register Layout Typedef */
allonq	0:fac0542384d7	4337	typedef struct {
allonq	0:fac0542384d7	4338	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
allonq	0:fac0542384d7	4339	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
allonq	0:fac0542384d7	4340	uint8_t RESERVED_0[4092];
allonq	0:fac0542384d7	4341	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
allonq	0:fac0542384d7	4342	uint8_t RESERVED_1[4];
allonq	0:fac0542384d7	4343	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
allonq	0:fac0542384d7	4344	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
allonq	0:fac0542384d7	4345	uint8_t RESERVED_2[4];
allonq	0:fac0542384d7	4346	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
allonq	0:fac0542384d7	4347	uint8_t RESERVED_3[8];
allonq	0:fac0542384d7	4348	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
allonq	0:fac0542384d7	4349	uint8_t RESERVED_4[12];
allonq	0:fac0542384d7	4350	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
allonq	0:fac0542384d7	4351	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
allonq	0:fac0542384d7	4352	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
allonq	0:fac0542384d7	4353	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
allonq	0:fac0542384d7	4354	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
allonq	0:fac0542384d7	4355	uint8_t RESERVED_5[4];
allonq	0:fac0542384d7	4356	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
allonq	0:fac0542384d7	4357	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
allonq	0:fac0542384d7	4358	uint8_t RESERVED_6[4];
allonq	0:fac0542384d7	4359	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
allonq	0:fac0542384d7	4360	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
allonq	0:fac0542384d7	4361	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
allonq	0:fac0542384d7	4362	uint8_t RESERVED_7[156];
allonq	0:fac0542384d7	4363	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
allonq	0:fac0542384d7	4364	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
allonq	0:fac0542384d7	4365	} SIM_Type;
allonq	0:fac0542384d7	4366
allonq	0:fac0542384d7	4367	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4368	-- SIM Register Masks
allonq	0:fac0542384d7	4369	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4370
allonq	0:fac0542384d7	4371	/*!
allonq	0:fac0542384d7	4372	* @addtogroup SIM_Register_Masks SIM Register Masks
allonq	0:fac0542384d7	4373	* @{
allonq	0:fac0542384d7	4374	*/
allonq	0:fac0542384d7	4375
allonq	0:fac0542384d7	4376	/* SOPT1 Bit Fields */
allonq	0:fac0542384d7	4377	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
allonq	0:fac0542384d7	4378	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
allonq	0:fac0542384d7	4379	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
allonq	0:fac0542384d7	4380	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
allonq	0:fac0542384d7	4381	#define SIM_SOPT1_USBVSTBY_SHIFT 29
allonq	0:fac0542384d7	4382	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
allonq	0:fac0542384d7	4383	#define SIM_SOPT1_USBSSTBY_SHIFT 30
allonq	0:fac0542384d7	4384	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
allonq	0:fac0542384d7	4385	#define SIM_SOPT1_USBREGEN_SHIFT 31
allonq	0:fac0542384d7	4386	/* SOPT1CFG Bit Fields */
allonq	0:fac0542384d7	4387	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
allonq	0:fac0542384d7	4388	#define SIM_SOPT1CFG_URWE_SHIFT 24
allonq	0:fac0542384d7	4389	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
allonq	0:fac0542384d7	4390	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
allonq	0:fac0542384d7	4391	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
allonq	0:fac0542384d7	4392	#define SIM_SOPT1CFG_USSWE_SHIFT 26
allonq	0:fac0542384d7	4393	/* SOPT2 Bit Fields */
allonq	0:fac0542384d7	4394	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
allonq	0:fac0542384d7	4395	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
allonq	0:fac0542384d7	4396	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
allonq	0:fac0542384d7	4397	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
allonq	0:fac0542384d7	4398	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
allonq	0:fac0542384d7	4399	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
allonq	0:fac0542384d7	4400	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
allonq	0:fac0542384d7	4401	#define SIM_SOPT2_USBSRC_MASK 0x40000u
allonq	0:fac0542384d7	4402	#define SIM_SOPT2_USBSRC_SHIFT 18
allonq	0:fac0542384d7	4403	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
allonq	0:fac0542384d7	4404	#define SIM_SOPT2_TPMSRC_SHIFT 24
allonq	0:fac0542384d7	4405	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
allonq	0:fac0542384d7	4406	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
allonq	0:fac0542384d7	4407	#define SIM_SOPT2_UART0SRC_SHIFT 26
allonq	0:fac0542384d7	4408	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
allonq	0:fac0542384d7	4409	/* SOPT4 Bit Fields */
allonq	0:fac0542384d7	4410	#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
allonq	0:fac0542384d7	4411	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
allonq	0:fac0542384d7	4412	#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
allonq	0:fac0542384d7	4413	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
allonq	0:fac0542384d7	4414	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
allonq	0:fac0542384d7	4415	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
allonq	0:fac0542384d7	4416	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
allonq	0:fac0542384d7	4417	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
allonq	0:fac0542384d7	4418	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
allonq	0:fac0542384d7	4419	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
allonq	0:fac0542384d7	4420	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
allonq	0:fac0542384d7	4421	/* SOPT5 Bit Fields */
allonq	0:fac0542384d7	4422	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
allonq	0:fac0542384d7	4423	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
allonq	0:fac0542384d7	4424	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
allonq	0:fac0542384d7	4425	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
allonq	0:fac0542384d7	4426	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
allonq	0:fac0542384d7	4427	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
allonq	0:fac0542384d7	4428	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
allonq	0:fac0542384d7	4429	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
allonq	0:fac0542384d7	4430	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
allonq	0:fac0542384d7	4431	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
allonq	0:fac0542384d7	4432	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
allonq	0:fac0542384d7	4433	#define SIM_SOPT5_UART0ODE_SHIFT 16
allonq	0:fac0542384d7	4434	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
allonq	0:fac0542384d7	4435	#define SIM_SOPT5_UART1ODE_SHIFT 17
allonq	0:fac0542384d7	4436	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
allonq	0:fac0542384d7	4437	#define SIM_SOPT5_UART2ODE_SHIFT 18
allonq	0:fac0542384d7	4438	/* SOPT7 Bit Fields */
allonq	0:fac0542384d7	4439	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
allonq	0:fac0542384d7	4440	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
allonq	0:fac0542384d7	4441	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
allonq	0:fac0542384d7	4442	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
allonq	0:fac0542384d7	4443	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
allonq	0:fac0542384d7	4444	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
allonq	0:fac0542384d7	4445	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
allonq	0:fac0542384d7	4446	/* SDID Bit Fields */
allonq	0:fac0542384d7	4447	#define SIM_SDID_PINID_MASK 0xFu
allonq	0:fac0542384d7	4448	#define SIM_SDID_PINID_SHIFT 0
allonq	0:fac0542384d7	4449	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
allonq	0:fac0542384d7	4450	#define SIM_SDID_DIEID_MASK 0xF80u
allonq	0:fac0542384d7	4451	#define SIM_SDID_DIEID_SHIFT 7
allonq	0:fac0542384d7	4452	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
allonq	0:fac0542384d7	4453	#define SIM_SDID_REVID_MASK 0xF000u
allonq	0:fac0542384d7	4454	#define SIM_SDID_REVID_SHIFT 12
allonq	0:fac0542384d7	4455	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
allonq	0:fac0542384d7	4456	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
allonq	0:fac0542384d7	4457	#define SIM_SDID_SRAMSIZE_SHIFT 16
allonq	0:fac0542384d7	4458	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
allonq	0:fac0542384d7	4459	#define SIM_SDID_SERIESID_MASK 0xF00000u
allonq	0:fac0542384d7	4460	#define SIM_SDID_SERIESID_SHIFT 20
allonq	0:fac0542384d7	4461	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
allonq	0:fac0542384d7	4462	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
allonq	0:fac0542384d7	4463	#define SIM_SDID_SUBFAMID_SHIFT 24
allonq	0:fac0542384d7	4464	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
allonq	0:fac0542384d7	4465	#define SIM_SDID_FAMID_MASK 0xF0000000u
allonq	0:fac0542384d7	4466	#define SIM_SDID_FAMID_SHIFT 28
allonq	0:fac0542384d7	4467	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
allonq	0:fac0542384d7	4468	/* SCGC4 Bit Fields */
allonq	0:fac0542384d7	4469	#define SIM_SCGC4_I2C0_MASK 0x40u
allonq	0:fac0542384d7	4470	#define SIM_SCGC4_I2C0_SHIFT 6
allonq	0:fac0542384d7	4471	#define SIM_SCGC4_I2C1_MASK 0x80u
allonq	0:fac0542384d7	4472	#define SIM_SCGC4_I2C1_SHIFT 7
allonq	0:fac0542384d7	4473	#define SIM_SCGC4_UART0_MASK 0x400u
allonq	0:fac0542384d7	4474	#define SIM_SCGC4_UART0_SHIFT 10
allonq	0:fac0542384d7	4475	#define SIM_SCGC4_UART1_MASK 0x800u
allonq	0:fac0542384d7	4476	#define SIM_SCGC4_UART1_SHIFT 11
allonq	0:fac0542384d7	4477	#define SIM_SCGC4_UART2_MASK 0x1000u
allonq	0:fac0542384d7	4478	#define SIM_SCGC4_UART2_SHIFT 12
allonq	0:fac0542384d7	4479	#define SIM_SCGC4_USBOTG_MASK 0x40000u
allonq	0:fac0542384d7	4480	#define SIM_SCGC4_USBOTG_SHIFT 18
allonq	0:fac0542384d7	4481	#define SIM_SCGC4_CMP_MASK 0x80000u
allonq	0:fac0542384d7	4482	#define SIM_SCGC4_CMP_SHIFT 19
allonq	0:fac0542384d7	4483	#define SIM_SCGC4_SPI0_MASK 0x400000u
allonq	0:fac0542384d7	4484	#define SIM_SCGC4_SPI0_SHIFT 22
allonq	0:fac0542384d7	4485	#define SIM_SCGC4_SPI1_MASK 0x800000u
allonq	0:fac0542384d7	4486	#define SIM_SCGC4_SPI1_SHIFT 23
allonq	0:fac0542384d7	4487	/* SCGC5 Bit Fields */
allonq	0:fac0542384d7	4488	#define SIM_SCGC5_LPTMR_MASK 0x1u
allonq	0:fac0542384d7	4489	#define SIM_SCGC5_LPTMR_SHIFT 0
allonq	0:fac0542384d7	4490	#define SIM_SCGC5_TSI_MASK 0x20u
allonq	0:fac0542384d7	4491	#define SIM_SCGC5_TSI_SHIFT 5
allonq	0:fac0542384d7	4492	#define SIM_SCGC5_PORTA_MASK 0x200u
allonq	0:fac0542384d7	4493	#define SIM_SCGC5_PORTA_SHIFT 9
allonq	0:fac0542384d7	4494	#define SIM_SCGC5_PORTB_MASK 0x400u
allonq	0:fac0542384d7	4495	#define SIM_SCGC5_PORTB_SHIFT 10
allonq	0:fac0542384d7	4496	#define SIM_SCGC5_PORTC_MASK 0x800u
allonq	0:fac0542384d7	4497	#define SIM_SCGC5_PORTC_SHIFT 11
allonq	0:fac0542384d7	4498	#define SIM_SCGC5_PORTD_MASK 0x1000u
allonq	0:fac0542384d7	4499	#define SIM_SCGC5_PORTD_SHIFT 12
allonq	0:fac0542384d7	4500	#define SIM_SCGC5_PORTE_MASK 0x2000u
allonq	0:fac0542384d7	4501	#define SIM_SCGC5_PORTE_SHIFT 13
allonq	0:fac0542384d7	4502	#define SIM_SCGC5_SLCD_MASK 0x80000u
allonq	0:fac0542384d7	4503	#define SIM_SCGC5_SLCD_SHIFT 19
allonq	0:fac0542384d7	4504	/* SCGC6 Bit Fields */
allonq	0:fac0542384d7	4505	#define SIM_SCGC6_FTF_MASK 0x1u
allonq	0:fac0542384d7	4506	#define SIM_SCGC6_FTF_SHIFT 0
allonq	0:fac0542384d7	4507	#define SIM_SCGC6_DMAMUX_MASK 0x2u
allonq	0:fac0542384d7	4508	#define SIM_SCGC6_DMAMUX_SHIFT 1
allonq	0:fac0542384d7	4509	#define SIM_SCGC6_I2S_MASK 0x8000u
allonq	0:fac0542384d7	4510	#define SIM_SCGC6_I2S_SHIFT 15
allonq	0:fac0542384d7	4511	#define SIM_SCGC6_PIT_MASK 0x800000u
allonq	0:fac0542384d7	4512	#define SIM_SCGC6_PIT_SHIFT 23
allonq	0:fac0542384d7	4513	#define SIM_SCGC6_TPM0_MASK 0x1000000u
allonq	0:fac0542384d7	4514	#define SIM_SCGC6_TPM0_SHIFT 24
allonq	0:fac0542384d7	4515	#define SIM_SCGC6_TPM1_MASK 0x2000000u
allonq	0:fac0542384d7	4516	#define SIM_SCGC6_TPM1_SHIFT 25
allonq	0:fac0542384d7	4517	#define SIM_SCGC6_TPM2_MASK 0x4000000u
allonq	0:fac0542384d7	4518	#define SIM_SCGC6_TPM2_SHIFT 26
allonq	0:fac0542384d7	4519	#define SIM_SCGC6_ADC0_MASK 0x8000000u
allonq	0:fac0542384d7	4520	#define SIM_SCGC6_ADC0_SHIFT 27
allonq	0:fac0542384d7	4521	#define SIM_SCGC6_RTC_MASK 0x20000000u
allonq	0:fac0542384d7	4522	#define SIM_SCGC6_RTC_SHIFT 29
allonq	0:fac0542384d7	4523	#define SIM_SCGC6_DAC0_MASK 0x80000000u
allonq	0:fac0542384d7	4524	#define SIM_SCGC6_DAC0_SHIFT 31
allonq	0:fac0542384d7	4525	/* SCGC7 Bit Fields */
allonq	0:fac0542384d7	4526	#define SIM_SCGC7_DMA_MASK 0x100u
allonq	0:fac0542384d7	4527	#define SIM_SCGC7_DMA_SHIFT 8
allonq	0:fac0542384d7	4528	/* CLKDIV1 Bit Fields */
allonq	0:fac0542384d7	4529	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
allonq	0:fac0542384d7	4530	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
allonq	0:fac0542384d7	4531	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
allonq	0:fac0542384d7	4532	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
allonq	0:fac0542384d7	4533	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
allonq	0:fac0542384d7	4534	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
allonq	0:fac0542384d7	4535	/* FCFG1 Bit Fields */
allonq	0:fac0542384d7	4536	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
allonq	0:fac0542384d7	4537	#define SIM_FCFG1_FLASHDIS_SHIFT 0
allonq	0:fac0542384d7	4538	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
allonq	0:fac0542384d7	4539	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
allonq	0:fac0542384d7	4540	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
allonq	0:fac0542384d7	4541	#define SIM_FCFG1_PFSIZE_SHIFT 24
allonq	0:fac0542384d7	4542	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
allonq	0:fac0542384d7	4543	/* FCFG2 Bit Fields */
allonq	0:fac0542384d7	4544	#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
allonq	0:fac0542384d7	4545	#define SIM_FCFG2_MAXADDR1_SHIFT 16
allonq	0:fac0542384d7	4546	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
allonq	0:fac0542384d7	4547	#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
allonq	0:fac0542384d7	4548	#define SIM_FCFG2_MAXADDR0_SHIFT 24
allonq	0:fac0542384d7	4549	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
allonq	0:fac0542384d7	4550	/* UIDMH Bit Fields */
allonq	0:fac0542384d7	4551	#define SIM_UIDMH_UID_MASK 0xFFFFu
allonq	0:fac0542384d7	4552	#define SIM_UIDMH_UID_SHIFT 0
allonq	0:fac0542384d7	4553	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
allonq	0:fac0542384d7	4554	/* UIDML Bit Fields */
allonq	0:fac0542384d7	4555	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4556	#define SIM_UIDML_UID_SHIFT 0
allonq	0:fac0542384d7	4557	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
allonq	0:fac0542384d7	4558	/* UIDL Bit Fields */
allonq	0:fac0542384d7	4559	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
allonq	0:fac0542384d7	4560	#define SIM_UIDL_UID_SHIFT 0
allonq	0:fac0542384d7	4561	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
allonq	0:fac0542384d7	4562	/* COPC Bit Fields */
allonq	0:fac0542384d7	4563	#define SIM_COPC_COPW_MASK 0x1u
allonq	0:fac0542384d7	4564	#define SIM_COPC_COPW_SHIFT 0
allonq	0:fac0542384d7	4565	#define SIM_COPC_COPCLKS_MASK 0x2u
allonq	0:fac0542384d7	4566	#define SIM_COPC_COPCLKS_SHIFT 1
allonq	0:fac0542384d7	4567	#define SIM_COPC_COPT_MASK 0xCu
allonq	0:fac0542384d7	4568	#define SIM_COPC_COPT_SHIFT 2
allonq	0:fac0542384d7	4569	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
allonq	0:fac0542384d7	4570	/* SRVCOP Bit Fields */
allonq	0:fac0542384d7	4571	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
allonq	0:fac0542384d7	4572	#define SIM_SRVCOP_SRVCOP_SHIFT 0
allonq	0:fac0542384d7	4573	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
allonq	0:fac0542384d7	4574
allonq	0:fac0542384d7	4575	/*!
allonq	0:fac0542384d7	4576	* @}
allonq	0:fac0542384d7	4577	/ / end of group SIM_Register_Masks */
allonq	0:fac0542384d7	4578
allonq	0:fac0542384d7	4579
allonq	0:fac0542384d7	4580	/* SIM - Peripheral instance base addresses */
allonq	0:fac0542384d7	4581	/** Peripheral SIM base address */
allonq	0:fac0542384d7	4582	#define SIM_BASE (0x40047000u)
allonq	0:fac0542384d7	4583	/** Peripheral SIM base pointer */
allonq	0:fac0542384d7	4584	#define SIM ((SIM_Type *)SIM_BASE)
allonq	0:fac0542384d7	4585	/** Array initializer of SIM peripheral base pointers */
allonq	0:fac0542384d7	4586	#define SIM_BASES { SIM }
allonq	0:fac0542384d7	4587
allonq	0:fac0542384d7	4588	/*!
allonq	0:fac0542384d7	4589	* @}
allonq	0:fac0542384d7	4590	/ / end of group SIM_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4591
allonq	0:fac0542384d7	4592
allonq	0:fac0542384d7	4593	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4594	-- SMC Peripheral Access Layer
allonq	0:fac0542384d7	4595	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4596
allonq	0:fac0542384d7	4597	/*!
allonq	0:fac0542384d7	4598	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
allonq	0:fac0542384d7	4599	* @{
allonq	0:fac0542384d7	4600	*/
allonq	0:fac0542384d7	4601
allonq	0:fac0542384d7	4602	/** SMC - Register Layout Typedef */
allonq	0:fac0542384d7	4603	typedef struct {
allonq	0:fac0542384d7	4604	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
allonq	0:fac0542384d7	4605	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
allonq	0:fac0542384d7	4606	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
allonq	0:fac0542384d7	4607	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
allonq	0:fac0542384d7	4608	} SMC_Type;
allonq	0:fac0542384d7	4609
allonq	0:fac0542384d7	4610	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4611	-- SMC Register Masks
allonq	0:fac0542384d7	4612	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4613
allonq	0:fac0542384d7	4614	/*!
allonq	0:fac0542384d7	4615	* @addtogroup SMC_Register_Masks SMC Register Masks
allonq	0:fac0542384d7	4616	* @{
allonq	0:fac0542384d7	4617	*/
allonq	0:fac0542384d7	4618
allonq	0:fac0542384d7	4619	/* PMPROT Bit Fields */
allonq	0:fac0542384d7	4620	#define SMC_PMPROT_AVLLS_MASK 0x2u
allonq	0:fac0542384d7	4621	#define SMC_PMPROT_AVLLS_SHIFT 1
allonq	0:fac0542384d7	4622	#define SMC_PMPROT_ALLS_MASK 0x8u
allonq	0:fac0542384d7	4623	#define SMC_PMPROT_ALLS_SHIFT 3
allonq	0:fac0542384d7	4624	#define SMC_PMPROT_AVLP_MASK 0x20u
allonq	0:fac0542384d7	4625	#define SMC_PMPROT_AVLP_SHIFT 5
allonq	0:fac0542384d7	4626	/* PMCTRL Bit Fields */
allonq	0:fac0542384d7	4627	#define SMC_PMCTRL_STOPM_MASK 0x7u
allonq	0:fac0542384d7	4628	#define SMC_PMCTRL_STOPM_SHIFT 0
allonq	0:fac0542384d7	4629	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
allonq	0:fac0542384d7	4630	#define SMC_PMCTRL_STOPA_MASK 0x8u
allonq	0:fac0542384d7	4631	#define SMC_PMCTRL_STOPA_SHIFT 3
allonq	0:fac0542384d7	4632	#define SMC_PMCTRL_RUNM_MASK 0x60u
allonq	0:fac0542384d7	4633	#define SMC_PMCTRL_RUNM_SHIFT 5
allonq	0:fac0542384d7	4634	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
allonq	0:fac0542384d7	4635	/* STOPCTRL Bit Fields */
allonq	0:fac0542384d7	4636	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
allonq	0:fac0542384d7	4637	#define SMC_STOPCTRL_VLLSM_SHIFT 0
allonq	0:fac0542384d7	4638	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
allonq	0:fac0542384d7	4639	#define SMC_STOPCTRL_PORPO_MASK 0x20u
allonq	0:fac0542384d7	4640	#define SMC_STOPCTRL_PORPO_SHIFT 5
allonq	0:fac0542384d7	4641	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
allonq	0:fac0542384d7	4642	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
allonq	0:fac0542384d7	4643	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
allonq	0:fac0542384d7	4644	/* PMSTAT Bit Fields */
allonq	0:fac0542384d7	4645	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
allonq	0:fac0542384d7	4646	#define SMC_PMSTAT_PMSTAT_SHIFT 0
allonq	0:fac0542384d7	4647	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
allonq	0:fac0542384d7	4648
allonq	0:fac0542384d7	4649	/*!
allonq	0:fac0542384d7	4650	* @}
allonq	0:fac0542384d7	4651	/ / end of group SMC_Register_Masks */
allonq	0:fac0542384d7	4652
allonq	0:fac0542384d7	4653
allonq	0:fac0542384d7	4654	/* SMC - Peripheral instance base addresses */
allonq	0:fac0542384d7	4655	/** Peripheral SMC base address */
allonq	0:fac0542384d7	4656	#define SMC_BASE (0x4007E000u)
allonq	0:fac0542384d7	4657	/** Peripheral SMC base pointer */
allonq	0:fac0542384d7	4658	#define SMC ((SMC_Type *)SMC_BASE)
allonq	0:fac0542384d7	4659	/** Array initializer of SMC peripheral base pointers */
allonq	0:fac0542384d7	4660	#define SMC_BASES { SMC }
allonq	0:fac0542384d7	4661
allonq	0:fac0542384d7	4662	/*!
allonq	0:fac0542384d7	4663	* @}
allonq	0:fac0542384d7	4664	/ / end of group SMC_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4665
allonq	0:fac0542384d7	4666
allonq	0:fac0542384d7	4667	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4668	-- SPI Peripheral Access Layer
allonq	0:fac0542384d7	4669	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4670
allonq	0:fac0542384d7	4671	/*!
allonq	0:fac0542384d7	4672	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
allonq	0:fac0542384d7	4673	* @{
allonq	0:fac0542384d7	4674	*/
allonq	0:fac0542384d7	4675
allonq	0:fac0542384d7	4676	/** SPI - Register Layout Typedef */
allonq	0:fac0542384d7	4677	typedef struct {
allonq	0:fac0542384d7	4678	__I uint8_t S; /*< SPI status register, offset: 0x0 /
allonq	0:fac0542384d7	4679	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x1 /
allonq	0:fac0542384d7	4680	__IO uint8_t C2; /*< SPI control register 2, offset: 0x2 /
allonq	0:fac0542384d7	4681	__IO uint8_t C1; /*< SPI control register 1, offset: 0x3 /
allonq	0:fac0542384d7	4682	__IO uint8_t ML; /*< SPI match register low, offset: 0x4 /
allonq	0:fac0542384d7	4683	__IO uint8_t MH; /*< SPI match register high, offset: 0x5 /
allonq	0:fac0542384d7	4684	__IO uint8_t DL; /*< SPI data register low, offset: 0x6 /
allonq	0:fac0542384d7	4685	__IO uint8_t DH; /*< SPI data register high, offset: 0x7 /
allonq	0:fac0542384d7	4686	uint8_t RESERVED_0[2];
allonq	0:fac0542384d7	4687	__IO uint8_t CI; /*< SPI clear interrupt register, offset: 0xA /
allonq	0:fac0542384d7	4688	__IO uint8_t C3; /*< SPI control register 3, offset: 0xB /
allonq	0:fac0542384d7	4689	} SPI_Type;
allonq	0:fac0542384d7	4690
allonq	0:fac0542384d7	4691	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4692	-- SPI Register Masks
allonq	0:fac0542384d7	4693	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4694
allonq	0:fac0542384d7	4695	/*!
allonq	0:fac0542384d7	4696	* @addtogroup SPI_Register_Masks SPI Register Masks
allonq	0:fac0542384d7	4697	* @{
allonq	0:fac0542384d7	4698	*/
allonq	0:fac0542384d7	4699
allonq	0:fac0542384d7	4700	/* S Bit Fields */
allonq	0:fac0542384d7	4701	#define SPI_S_RFIFOEF_MASK 0x1u
allonq	0:fac0542384d7	4702	#define SPI_S_RFIFOEF_SHIFT 0
allonq	0:fac0542384d7	4703	#define SPI_S_TXFULLF_MASK 0x2u
allonq	0:fac0542384d7	4704	#define SPI_S_TXFULLF_SHIFT 1
allonq	0:fac0542384d7	4705	#define SPI_S_TNEAREF_MASK 0x4u
allonq	0:fac0542384d7	4706	#define SPI_S_TNEAREF_SHIFT 2
allonq	0:fac0542384d7	4707	#define SPI_S_RNFULLF_MASK 0x8u
allonq	0:fac0542384d7	4708	#define SPI_S_RNFULLF_SHIFT 3
allonq	0:fac0542384d7	4709	#define SPI_S_MODF_MASK 0x10u
allonq	0:fac0542384d7	4710	#define SPI_S_MODF_SHIFT 4
allonq	0:fac0542384d7	4711	#define SPI_S_SPTEF_MASK 0x20u
allonq	0:fac0542384d7	4712	#define SPI_S_SPTEF_SHIFT 5
allonq	0:fac0542384d7	4713	#define SPI_S_SPMF_MASK 0x40u
allonq	0:fac0542384d7	4714	#define SPI_S_SPMF_SHIFT 6
allonq	0:fac0542384d7	4715	#define SPI_S_SPRF_MASK 0x80u
allonq	0:fac0542384d7	4716	#define SPI_S_SPRF_SHIFT 7
allonq	0:fac0542384d7	4717	/* BR Bit Fields */
allonq	0:fac0542384d7	4718	#define SPI_BR_SPR_MASK 0xFu
allonq	0:fac0542384d7	4719	#define SPI_BR_SPR_SHIFT 0
allonq	0:fac0542384d7	4720	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
allonq	0:fac0542384d7	4721	#define SPI_BR_SPPR_MASK 0x70u
allonq	0:fac0542384d7	4722	#define SPI_BR_SPPR_SHIFT 4
allonq	0:fac0542384d7	4723	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
allonq	0:fac0542384d7	4724	/* C2 Bit Fields */
allonq	0:fac0542384d7	4725	#define SPI_C2_SPC0_MASK 0x1u
allonq	0:fac0542384d7	4726	#define SPI_C2_SPC0_SHIFT 0
allonq	0:fac0542384d7	4727	#define SPI_C2_SPISWAI_MASK 0x2u
allonq	0:fac0542384d7	4728	#define SPI_C2_SPISWAI_SHIFT 1
allonq	0:fac0542384d7	4729	#define SPI_C2_RXDMAE_MASK 0x4u
allonq	0:fac0542384d7	4730	#define SPI_C2_RXDMAE_SHIFT 2
allonq	0:fac0542384d7	4731	#define SPI_C2_BIDIROE_MASK 0x8u
allonq	0:fac0542384d7	4732	#define SPI_C2_BIDIROE_SHIFT 3
allonq	0:fac0542384d7	4733	#define SPI_C2_MODFEN_MASK 0x10u
allonq	0:fac0542384d7	4734	#define SPI_C2_MODFEN_SHIFT 4
allonq	0:fac0542384d7	4735	#define SPI_C2_TXDMAE_MASK 0x20u
allonq	0:fac0542384d7	4736	#define SPI_C2_TXDMAE_SHIFT 5
allonq	0:fac0542384d7	4737	#define SPI_C2_SPIMODE_MASK 0x40u
allonq	0:fac0542384d7	4738	#define SPI_C2_SPIMODE_SHIFT 6
allonq	0:fac0542384d7	4739	#define SPI_C2_SPMIE_MASK 0x80u
allonq	0:fac0542384d7	4740	#define SPI_C2_SPMIE_SHIFT 7
allonq	0:fac0542384d7	4741	/* C1 Bit Fields */
allonq	0:fac0542384d7	4742	#define SPI_C1_LSBFE_MASK 0x1u
allonq	0:fac0542384d7	4743	#define SPI_C1_LSBFE_SHIFT 0
allonq	0:fac0542384d7	4744	#define SPI_C1_SSOE_MASK 0x2u
allonq	0:fac0542384d7	4745	#define SPI_C1_SSOE_SHIFT 1
allonq	0:fac0542384d7	4746	#define SPI_C1_CPHA_MASK 0x4u
allonq	0:fac0542384d7	4747	#define SPI_C1_CPHA_SHIFT 2
allonq	0:fac0542384d7	4748	#define SPI_C1_CPOL_MASK 0x8u
allonq	0:fac0542384d7	4749	#define SPI_C1_CPOL_SHIFT 3
allonq	0:fac0542384d7	4750	#define SPI_C1_MSTR_MASK 0x10u
allonq	0:fac0542384d7	4751	#define SPI_C1_MSTR_SHIFT 4
allonq	0:fac0542384d7	4752	#define SPI_C1_SPTIE_MASK 0x20u
allonq	0:fac0542384d7	4753	#define SPI_C1_SPTIE_SHIFT 5
allonq	0:fac0542384d7	4754	#define SPI_C1_SPE_MASK 0x40u
allonq	0:fac0542384d7	4755	#define SPI_C1_SPE_SHIFT 6
allonq	0:fac0542384d7	4756	#define SPI_C1_SPIE_MASK 0x80u
allonq	0:fac0542384d7	4757	#define SPI_C1_SPIE_SHIFT 7
allonq	0:fac0542384d7	4758	/* ML Bit Fields */
allonq	0:fac0542384d7	4759	#define SPI_ML_Bits_MASK 0xFFu
allonq	0:fac0542384d7	4760	#define SPI_ML_Bits_SHIFT 0
allonq	0:fac0542384d7	4761	#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
allonq	0:fac0542384d7	4762	/* MH Bit Fields */
allonq	0:fac0542384d7	4763	#define SPI_MH_Bits_MASK 0xFFu
allonq	0:fac0542384d7	4764	#define SPI_MH_Bits_SHIFT 0
allonq	0:fac0542384d7	4765	#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
allonq	0:fac0542384d7	4766	/* DL Bit Fields */
allonq	0:fac0542384d7	4767	#define SPI_DL_Bits_MASK 0xFFu
allonq	0:fac0542384d7	4768	#define SPI_DL_Bits_SHIFT 0
allonq	0:fac0542384d7	4769	#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
allonq	0:fac0542384d7	4770	/* DH Bit Fields */
allonq	0:fac0542384d7	4771	#define SPI_DH_Bits_MASK 0xFFu
allonq	0:fac0542384d7	4772	#define SPI_DH_Bits_SHIFT 0
allonq	0:fac0542384d7	4773	#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
allonq	0:fac0542384d7	4774	/* CI Bit Fields */
allonq	0:fac0542384d7	4775	#define SPI_CI_SPRFCI_MASK 0x1u
allonq	0:fac0542384d7	4776	#define SPI_CI_SPRFCI_SHIFT 0
allonq	0:fac0542384d7	4777	#define SPI_CI_SPTEFCI_MASK 0x2u
allonq	0:fac0542384d7	4778	#define SPI_CI_SPTEFCI_SHIFT 1
allonq	0:fac0542384d7	4779	#define SPI_CI_RNFULLFCI_MASK 0x4u
allonq	0:fac0542384d7	4780	#define SPI_CI_RNFULLFCI_SHIFT 2
allonq	0:fac0542384d7	4781	#define SPI_CI_TNEAREFCI_MASK 0x8u
allonq	0:fac0542384d7	4782	#define SPI_CI_TNEAREFCI_SHIFT 3
allonq	0:fac0542384d7	4783	#define SPI_CI_RXFOF_MASK 0x10u
allonq	0:fac0542384d7	4784	#define SPI_CI_RXFOF_SHIFT 4
allonq	0:fac0542384d7	4785	#define SPI_CI_TXFOF_MASK 0x20u
allonq	0:fac0542384d7	4786	#define SPI_CI_TXFOF_SHIFT 5
allonq	0:fac0542384d7	4787	#define SPI_CI_RXFERR_MASK 0x40u
allonq	0:fac0542384d7	4788	#define SPI_CI_RXFERR_SHIFT 6
allonq	0:fac0542384d7	4789	#define SPI_CI_TXFERR_MASK 0x80u
allonq	0:fac0542384d7	4790	#define SPI_CI_TXFERR_SHIFT 7
allonq	0:fac0542384d7	4791	/* C3 Bit Fields */
allonq	0:fac0542384d7	4792	#define SPI_C3_FIFOMODE_MASK 0x1u
allonq	0:fac0542384d7	4793	#define SPI_C3_FIFOMODE_SHIFT 0
allonq	0:fac0542384d7	4794	#define SPI_C3_RNFULLIEN_MASK 0x2u
allonq	0:fac0542384d7	4795	#define SPI_C3_RNFULLIEN_SHIFT 1
allonq	0:fac0542384d7	4796	#define SPI_C3_TNEARIEN_MASK 0x4u
allonq	0:fac0542384d7	4797	#define SPI_C3_TNEARIEN_SHIFT 2
allonq	0:fac0542384d7	4798	#define SPI_C3_INTCLR_MASK 0x8u
allonq	0:fac0542384d7	4799	#define SPI_C3_INTCLR_SHIFT 3
allonq	0:fac0542384d7	4800	#define SPI_C3_RNFULLF_MARK_MASK 0x10u
allonq	0:fac0542384d7	4801	#define SPI_C3_RNFULLF_MARK_SHIFT 4
allonq	0:fac0542384d7	4802	#define SPI_C3_TNEAREF_MARK_MASK 0x20u
allonq	0:fac0542384d7	4803	#define SPI_C3_TNEAREF_MARK_SHIFT 5
allonq	0:fac0542384d7	4804
allonq	0:fac0542384d7	4805	/*!
allonq	0:fac0542384d7	4806	* @}
allonq	0:fac0542384d7	4807	/ / end of group SPI_Register_Masks */
allonq	0:fac0542384d7	4808
allonq	0:fac0542384d7	4809
allonq	0:fac0542384d7	4810	/* SPI - Peripheral instance base addresses */
allonq	0:fac0542384d7	4811	/** Peripheral SPI0 base address */
allonq	0:fac0542384d7	4812	#define SPI0_BASE (0x40076000u)
allonq	0:fac0542384d7	4813	/** Peripheral SPI0 base pointer */
allonq	0:fac0542384d7	4814	#define SPI0 ((SPI_Type *)SPI0_BASE)
allonq	0:fac0542384d7	4815	/** Peripheral SPI1 base address */
allonq	0:fac0542384d7	4816	#define SPI1_BASE (0x40077000u)
allonq	0:fac0542384d7	4817	/** Peripheral SPI1 base pointer */
allonq	0:fac0542384d7	4818	#define SPI1 ((SPI_Type *)SPI1_BASE)
allonq	0:fac0542384d7	4819	/** Array initializer of SPI peripheral base pointers */
allonq	0:fac0542384d7	4820	#define SPI_BASES { SPI0, SPI1 }
allonq	0:fac0542384d7	4821
allonq	0:fac0542384d7	4822	/*!
allonq	0:fac0542384d7	4823	* @}
allonq	0:fac0542384d7	4824	/ / end of group SPI_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4825
allonq	0:fac0542384d7	4826
allonq	0:fac0542384d7	4827	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4828	-- TPM Peripheral Access Layer
allonq	0:fac0542384d7	4829	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4830
allonq	0:fac0542384d7	4831	/*!
allonq	0:fac0542384d7	4832	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
allonq	0:fac0542384d7	4833	* @{
allonq	0:fac0542384d7	4834	*/
allonq	0:fac0542384d7	4835
allonq	0:fac0542384d7	4836	/** TPM - Register Layout Typedef */
allonq	0:fac0542384d7	4837	typedef struct {
allonq	0:fac0542384d7	4838	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
allonq	0:fac0542384d7	4839	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
allonq	0:fac0542384d7	4840	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
allonq	0:fac0542384d7	4841	struct { /* offset: 0xC, array step: 0x8 */
allonq	0:fac0542384d7	4842	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
allonq	0:fac0542384d7	4843	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
allonq	0:fac0542384d7	4844	} CONTROLS[6];
allonq	0:fac0542384d7	4845	uint8_t RESERVED_0[20];
allonq	0:fac0542384d7	4846	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
allonq	0:fac0542384d7	4847	uint8_t RESERVED_1[48];
allonq	0:fac0542384d7	4848	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
allonq	0:fac0542384d7	4849	} TPM_Type;
allonq	0:fac0542384d7	4850
allonq	0:fac0542384d7	4851	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4852	-- TPM Register Masks
allonq	0:fac0542384d7	4853	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4854
allonq	0:fac0542384d7	4855	/*!
allonq	0:fac0542384d7	4856	* @addtogroup TPM_Register_Masks TPM Register Masks
allonq	0:fac0542384d7	4857	* @{
allonq	0:fac0542384d7	4858	*/
allonq	0:fac0542384d7	4859
allonq	0:fac0542384d7	4860	/* SC Bit Fields */
allonq	0:fac0542384d7	4861	#define TPM_SC_PS_MASK 0x7u
allonq	0:fac0542384d7	4862	#define TPM_SC_PS_SHIFT 0
allonq	0:fac0542384d7	4863	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
allonq	0:fac0542384d7	4864	#define TPM_SC_CMOD_MASK 0x18u
allonq	0:fac0542384d7	4865	#define TPM_SC_CMOD_SHIFT 3
allonq	0:fac0542384d7	4866	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
allonq	0:fac0542384d7	4867	#define TPM_SC_CPWMS_MASK 0x20u
allonq	0:fac0542384d7	4868	#define TPM_SC_CPWMS_SHIFT 5
allonq	0:fac0542384d7	4869	#define TPM_SC_TOIE_MASK 0x40u
allonq	0:fac0542384d7	4870	#define TPM_SC_TOIE_SHIFT 6
allonq	0:fac0542384d7	4871	#define TPM_SC_TOF_MASK 0x80u
allonq	0:fac0542384d7	4872	#define TPM_SC_TOF_SHIFT 7
allonq	0:fac0542384d7	4873	#define TPM_SC_DMA_MASK 0x100u
allonq	0:fac0542384d7	4874	#define TPM_SC_DMA_SHIFT 8
allonq	0:fac0542384d7	4875	/* CNT Bit Fields */
allonq	0:fac0542384d7	4876	#define TPM_CNT_COUNT_MASK 0xFFFFu
allonq	0:fac0542384d7	4877	#define TPM_CNT_COUNT_SHIFT 0
allonq	0:fac0542384d7	4878	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
allonq	0:fac0542384d7	4879	/* MOD Bit Fields */
allonq	0:fac0542384d7	4880	#define TPM_MOD_MOD_MASK 0xFFFFu
allonq	0:fac0542384d7	4881	#define TPM_MOD_MOD_SHIFT 0
allonq	0:fac0542384d7	4882	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
allonq	0:fac0542384d7	4883	/* CnSC Bit Fields */
allonq	0:fac0542384d7	4884	#define TPM_CnSC_DMA_MASK 0x1u
allonq	0:fac0542384d7	4885	#define TPM_CnSC_DMA_SHIFT 0
allonq	0:fac0542384d7	4886	#define TPM_CnSC_ELSA_MASK 0x4u
allonq	0:fac0542384d7	4887	#define TPM_CnSC_ELSA_SHIFT 2
allonq	0:fac0542384d7	4888	#define TPM_CnSC_ELSB_MASK 0x8u
allonq	0:fac0542384d7	4889	#define TPM_CnSC_ELSB_SHIFT 3
allonq	0:fac0542384d7	4890	#define TPM_CnSC_MSA_MASK 0x10u
allonq	0:fac0542384d7	4891	#define TPM_CnSC_MSA_SHIFT 4
allonq	0:fac0542384d7	4892	#define TPM_CnSC_MSB_MASK 0x20u
allonq	0:fac0542384d7	4893	#define TPM_CnSC_MSB_SHIFT 5
allonq	0:fac0542384d7	4894	#define TPM_CnSC_CHIE_MASK 0x40u
allonq	0:fac0542384d7	4895	#define TPM_CnSC_CHIE_SHIFT 6
allonq	0:fac0542384d7	4896	#define TPM_CnSC_CHF_MASK 0x80u
allonq	0:fac0542384d7	4897	#define TPM_CnSC_CHF_SHIFT 7
allonq	0:fac0542384d7	4898	/* CnV Bit Fields */
allonq	0:fac0542384d7	4899	#define TPM_CnV_VAL_MASK 0xFFFFu
allonq	0:fac0542384d7	4900	#define TPM_CnV_VAL_SHIFT 0
allonq	0:fac0542384d7	4901	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
allonq	0:fac0542384d7	4902	/* STATUS Bit Fields */
allonq	0:fac0542384d7	4903	#define TPM_STATUS_CH0F_MASK 0x1u
allonq	0:fac0542384d7	4904	#define TPM_STATUS_CH0F_SHIFT 0
allonq	0:fac0542384d7	4905	#define TPM_STATUS_CH1F_MASK 0x2u
allonq	0:fac0542384d7	4906	#define TPM_STATUS_CH1F_SHIFT 1
allonq	0:fac0542384d7	4907	#define TPM_STATUS_CH2F_MASK 0x4u
allonq	0:fac0542384d7	4908	#define TPM_STATUS_CH2F_SHIFT 2
allonq	0:fac0542384d7	4909	#define TPM_STATUS_CH3F_MASK 0x8u
allonq	0:fac0542384d7	4910	#define TPM_STATUS_CH3F_SHIFT 3
allonq	0:fac0542384d7	4911	#define TPM_STATUS_CH4F_MASK 0x10u
allonq	0:fac0542384d7	4912	#define TPM_STATUS_CH4F_SHIFT 4
allonq	0:fac0542384d7	4913	#define TPM_STATUS_CH5F_MASK 0x20u
allonq	0:fac0542384d7	4914	#define TPM_STATUS_CH5F_SHIFT 5
allonq	0:fac0542384d7	4915	#define TPM_STATUS_TOF_MASK 0x100u
allonq	0:fac0542384d7	4916	#define TPM_STATUS_TOF_SHIFT 8
allonq	0:fac0542384d7	4917	/* CONF Bit Fields */
allonq	0:fac0542384d7	4918	#define TPM_CONF_DOZEEN_MASK 0x20u
allonq	0:fac0542384d7	4919	#define TPM_CONF_DOZEEN_SHIFT 5
allonq	0:fac0542384d7	4920	#define TPM_CONF_DBGMODE_MASK 0xC0u
allonq	0:fac0542384d7	4921	#define TPM_CONF_DBGMODE_SHIFT 6
allonq	0:fac0542384d7	4922	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
allonq	0:fac0542384d7	4923	#define TPM_CONF_GTBEEN_MASK 0x200u
allonq	0:fac0542384d7	4924	#define TPM_CONF_GTBEEN_SHIFT 9
allonq	0:fac0542384d7	4925	#define TPM_CONF_CSOT_MASK 0x10000u
allonq	0:fac0542384d7	4926	#define TPM_CONF_CSOT_SHIFT 16
allonq	0:fac0542384d7	4927	#define TPM_CONF_CSOO_MASK 0x20000u
allonq	0:fac0542384d7	4928	#define TPM_CONF_CSOO_SHIFT 17
allonq	0:fac0542384d7	4929	#define TPM_CONF_CROT_MASK 0x40000u
allonq	0:fac0542384d7	4930	#define TPM_CONF_CROT_SHIFT 18
allonq	0:fac0542384d7	4931	#define TPM_CONF_TRGSEL_MASK 0xF000000u
allonq	0:fac0542384d7	4932	#define TPM_CONF_TRGSEL_SHIFT 24
allonq	0:fac0542384d7	4933	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
allonq	0:fac0542384d7	4934
allonq	0:fac0542384d7	4935	/*!
allonq	0:fac0542384d7	4936	* @}
allonq	0:fac0542384d7	4937	/ / end of group TPM_Register_Masks */
allonq	0:fac0542384d7	4938
allonq	0:fac0542384d7	4939
allonq	0:fac0542384d7	4940	/* TPM - Peripheral instance base addresses */
allonq	0:fac0542384d7	4941	/** Peripheral TPM0 base address */
allonq	0:fac0542384d7	4942	#define TPM0_BASE (0x40038000u)
allonq	0:fac0542384d7	4943	/** Peripheral TPM0 base pointer */
allonq	0:fac0542384d7	4944	#define TPM0 ((TPM_Type *)TPM0_BASE)
allonq	0:fac0542384d7	4945	/** Peripheral TPM1 base address */
allonq	0:fac0542384d7	4946	#define TPM1_BASE (0x40039000u)
allonq	0:fac0542384d7	4947	/** Peripheral TPM1 base pointer */
allonq	0:fac0542384d7	4948	#define TPM1 ((TPM_Type *)TPM1_BASE)
allonq	0:fac0542384d7	4949	/** Peripheral TPM2 base address */
allonq	0:fac0542384d7	4950	#define TPM2_BASE (0x4003A000u)
allonq	0:fac0542384d7	4951	/** Peripheral TPM2 base pointer */
allonq	0:fac0542384d7	4952	#define TPM2 ((TPM_Type *)TPM2_BASE)
allonq	0:fac0542384d7	4953	/** Array initializer of TPM peripheral base pointers */
allonq	0:fac0542384d7	4954	#define TPM_BASES { TPM0, TPM1, TPM2 }
allonq	0:fac0542384d7	4955
allonq	0:fac0542384d7	4956	/*!
allonq	0:fac0542384d7	4957	* @}
allonq	0:fac0542384d7	4958	/ / end of group TPM_Peripheral_Access_Layer */
allonq	0:fac0542384d7	4959
allonq	0:fac0542384d7	4960
allonq	0:fac0542384d7	4961	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4962	-- TSI Peripheral Access Layer
allonq	0:fac0542384d7	4963	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4964
allonq	0:fac0542384d7	4965	/*!
allonq	0:fac0542384d7	4966	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
allonq	0:fac0542384d7	4967	* @{
allonq	0:fac0542384d7	4968	*/
allonq	0:fac0542384d7	4969
allonq	0:fac0542384d7	4970	/** TSI - Register Layout Typedef */
allonq	0:fac0542384d7	4971	typedef struct {
allonq	0:fac0542384d7	4972	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
allonq	0:fac0542384d7	4973	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
allonq	0:fac0542384d7	4974	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
allonq	0:fac0542384d7	4975	} TSI_Type;
allonq	0:fac0542384d7	4976
allonq	0:fac0542384d7	4977	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	4978	-- TSI Register Masks
allonq	0:fac0542384d7	4979	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	4980
allonq	0:fac0542384d7	4981	/*!
allonq	0:fac0542384d7	4982	* @addtogroup TSI_Register_Masks TSI Register Masks
allonq	0:fac0542384d7	4983	* @{
allonq	0:fac0542384d7	4984	*/
allonq	0:fac0542384d7	4985
allonq	0:fac0542384d7	4986	/* GENCS Bit Fields */
allonq	0:fac0542384d7	4987	#define TSI_GENCS_CURSW_MASK 0x2u
allonq	0:fac0542384d7	4988	#define TSI_GENCS_CURSW_SHIFT 1
allonq	0:fac0542384d7	4989	#define TSI_GENCS_EOSF_MASK 0x4u
allonq	0:fac0542384d7	4990	#define TSI_GENCS_EOSF_SHIFT 2
allonq	0:fac0542384d7	4991	#define TSI_GENCS_SCNIP_MASK 0x8u
allonq	0:fac0542384d7	4992	#define TSI_GENCS_SCNIP_SHIFT 3
allonq	0:fac0542384d7	4993	#define TSI_GENCS_STM_MASK 0x10u
allonq	0:fac0542384d7	4994	#define TSI_GENCS_STM_SHIFT 4
allonq	0:fac0542384d7	4995	#define TSI_GENCS_STPE_MASK 0x20u
allonq	0:fac0542384d7	4996	#define TSI_GENCS_STPE_SHIFT 5
allonq	0:fac0542384d7	4997	#define TSI_GENCS_TSIIEN_MASK 0x40u
allonq	0:fac0542384d7	4998	#define TSI_GENCS_TSIIEN_SHIFT 6
allonq	0:fac0542384d7	4999	#define TSI_GENCS_TSIEN_MASK 0x80u
allonq	0:fac0542384d7	5000	#define TSI_GENCS_TSIEN_SHIFT 7
allonq	0:fac0542384d7	5001	#define TSI_GENCS_NSCN_MASK 0x1F00u
allonq	0:fac0542384d7	5002	#define TSI_GENCS_NSCN_SHIFT 8
allonq	0:fac0542384d7	5003	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
allonq	0:fac0542384d7	5004	#define TSI_GENCS_PS_MASK 0xE000u
allonq	0:fac0542384d7	5005	#define TSI_GENCS_PS_SHIFT 13
allonq	0:fac0542384d7	5006	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
allonq	0:fac0542384d7	5007	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
allonq	0:fac0542384d7	5008	#define TSI_GENCS_EXTCHRG_SHIFT 16
allonq	0:fac0542384d7	5009	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
allonq	0:fac0542384d7	5010	#define TSI_GENCS_DVOLT_MASK 0x180000u
allonq	0:fac0542384d7	5011	#define TSI_GENCS_DVOLT_SHIFT 19
allonq	0:fac0542384d7	5012	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
allonq	0:fac0542384d7	5013	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
allonq	0:fac0542384d7	5014	#define TSI_GENCS_REFCHRG_SHIFT 21
allonq	0:fac0542384d7	5015	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
allonq	0:fac0542384d7	5016	#define TSI_GENCS_MODE_MASK 0xF000000u
allonq	0:fac0542384d7	5017	#define TSI_GENCS_MODE_SHIFT 24
allonq	0:fac0542384d7	5018	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
allonq	0:fac0542384d7	5019	#define TSI_GENCS_ESOR_MASK 0x10000000u
allonq	0:fac0542384d7	5020	#define TSI_GENCS_ESOR_SHIFT 28
allonq	0:fac0542384d7	5021	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
allonq	0:fac0542384d7	5022	#define TSI_GENCS_OUTRGF_SHIFT 31
allonq	0:fac0542384d7	5023	/* DATA Bit Fields */
allonq	0:fac0542384d7	5024	#define TSI_DATA_TSICNT_MASK 0xFFFFu
allonq	0:fac0542384d7	5025	#define TSI_DATA_TSICNT_SHIFT 0
allonq	0:fac0542384d7	5026	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
allonq	0:fac0542384d7	5027	#define TSI_DATA_SWTS_MASK 0x400000u
allonq	0:fac0542384d7	5028	#define TSI_DATA_SWTS_SHIFT 22
allonq	0:fac0542384d7	5029	#define TSI_DATA_DMAEN_MASK 0x800000u
allonq	0:fac0542384d7	5030	#define TSI_DATA_DMAEN_SHIFT 23
allonq	0:fac0542384d7	5031	#define TSI_DATA_TSICH_MASK 0xF0000000u
allonq	0:fac0542384d7	5032	#define TSI_DATA_TSICH_SHIFT 28
allonq	0:fac0542384d7	5033	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
allonq	0:fac0542384d7	5034	/* TSHD Bit Fields */
allonq	0:fac0542384d7	5035	#define TSI_TSHD_THRESL_MASK 0xFFFFu
allonq	0:fac0542384d7	5036	#define TSI_TSHD_THRESL_SHIFT 0
allonq	0:fac0542384d7	5037	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
allonq	0:fac0542384d7	5038	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
allonq	0:fac0542384d7	5039	#define TSI_TSHD_THRESH_SHIFT 16
allonq	0:fac0542384d7	5040	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
allonq	0:fac0542384d7	5041
allonq	0:fac0542384d7	5042	/*!
allonq	0:fac0542384d7	5043	* @}
allonq	0:fac0542384d7	5044	/ / end of group TSI_Register_Masks */
allonq	0:fac0542384d7	5045
allonq	0:fac0542384d7	5046
allonq	0:fac0542384d7	5047	/* TSI - Peripheral instance base addresses */
allonq	0:fac0542384d7	5048	/** Peripheral TSI0 base address */
allonq	0:fac0542384d7	5049	#define TSI0_BASE (0x40045000u)
allonq	0:fac0542384d7	5050	/** Peripheral TSI0 base pointer */
allonq	0:fac0542384d7	5051	#define TSI0 ((TSI_Type *)TSI0_BASE)
allonq	0:fac0542384d7	5052	/** Array initializer of TSI peripheral base pointers */
allonq	0:fac0542384d7	5053	#define TSI_BASES { TSI0 }
allonq	0:fac0542384d7	5054
allonq	0:fac0542384d7	5055	/*!
allonq	0:fac0542384d7	5056	* @}
allonq	0:fac0542384d7	5057	/ / end of group TSI_Peripheral_Access_Layer */
allonq	0:fac0542384d7	5058
allonq	0:fac0542384d7	5059
allonq	0:fac0542384d7	5060	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5061	-- UART Peripheral Access Layer
allonq	0:fac0542384d7	5062	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5063
allonq	0:fac0542384d7	5064	/*!
allonq	0:fac0542384d7	5065	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
allonq	0:fac0542384d7	5066	* @{
allonq	0:fac0542384d7	5067	*/
allonq	0:fac0542384d7	5068
allonq	0:fac0542384d7	5069	/** UART - Register Layout Typedef */
allonq	0:fac0542384d7	5070	typedef struct {
allonq	0:fac0542384d7	5071	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
allonq	0:fac0542384d7	5072	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
allonq	0:fac0542384d7	5073	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
allonq	0:fac0542384d7	5074	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
allonq	0:fac0542384d7	5075	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
allonq	0:fac0542384d7	5076	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
allonq	0:fac0542384d7	5077	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
allonq	0:fac0542384d7	5078	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
allonq	0:fac0542384d7	5079	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
allonq	0:fac0542384d7	5080	} UART_Type;
allonq	0:fac0542384d7	5081
allonq	0:fac0542384d7	5082	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5083	-- UART Register Masks
allonq	0:fac0542384d7	5084	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5085
allonq	0:fac0542384d7	5086	/*!
allonq	0:fac0542384d7	5087	* @addtogroup UART_Register_Masks UART Register Masks
allonq	0:fac0542384d7	5088	* @{
allonq	0:fac0542384d7	5089	*/
allonq	0:fac0542384d7	5090
allonq	0:fac0542384d7	5091	/* BDH Bit Fields */
allonq	0:fac0542384d7	5092	#define UART_BDH_SBR_MASK 0x1Fu
allonq	0:fac0542384d7	5093	#define UART_BDH_SBR_SHIFT 0
allonq	0:fac0542384d7	5094	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
allonq	0:fac0542384d7	5095	#define UART_BDH_SBNS_MASK 0x20u
allonq	0:fac0542384d7	5096	#define UART_BDH_SBNS_SHIFT 5
allonq	0:fac0542384d7	5097	#define UART_BDH_RXEDGIE_MASK 0x40u
allonq	0:fac0542384d7	5098	#define UART_BDH_RXEDGIE_SHIFT 6
allonq	0:fac0542384d7	5099	#define UART_BDH_LBKDIE_MASK 0x80u
allonq	0:fac0542384d7	5100	#define UART_BDH_LBKDIE_SHIFT 7
allonq	0:fac0542384d7	5101	/* BDL Bit Fields */
allonq	0:fac0542384d7	5102	#define UART_BDL_SBR_MASK 0xFFu
allonq	0:fac0542384d7	5103	#define UART_BDL_SBR_SHIFT 0
allonq	0:fac0542384d7	5104	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
allonq	0:fac0542384d7	5105	/* C1 Bit Fields */
allonq	0:fac0542384d7	5106	#define UART_C1_PT_MASK 0x1u
allonq	0:fac0542384d7	5107	#define UART_C1_PT_SHIFT 0
allonq	0:fac0542384d7	5108	#define UART_C1_PE_MASK 0x2u
allonq	0:fac0542384d7	5109	#define UART_C1_PE_SHIFT 1
allonq	0:fac0542384d7	5110	#define UART_C1_ILT_MASK 0x4u
allonq	0:fac0542384d7	5111	#define UART_C1_ILT_SHIFT 2
allonq	0:fac0542384d7	5112	#define UART_C1_WAKE_MASK 0x8u
allonq	0:fac0542384d7	5113	#define UART_C1_WAKE_SHIFT 3
allonq	0:fac0542384d7	5114	#define UART_C1_M_MASK 0x10u
allonq	0:fac0542384d7	5115	#define UART_C1_M_SHIFT 4
allonq	0:fac0542384d7	5116	#define UART_C1_RSRC_MASK 0x20u
allonq	0:fac0542384d7	5117	#define UART_C1_RSRC_SHIFT 5
allonq	0:fac0542384d7	5118	#define UART_C1_UARTSWAI_MASK 0x40u
allonq	0:fac0542384d7	5119	#define UART_C1_UARTSWAI_SHIFT 6
allonq	0:fac0542384d7	5120	#define UART_C1_LOOPS_MASK 0x80u
allonq	0:fac0542384d7	5121	#define UART_C1_LOOPS_SHIFT 7
allonq	0:fac0542384d7	5122	/* C2 Bit Fields */
allonq	0:fac0542384d7	5123	#define UART_C2_SBK_MASK 0x1u
allonq	0:fac0542384d7	5124	#define UART_C2_SBK_SHIFT 0
allonq	0:fac0542384d7	5125	#define UART_C2_RWU_MASK 0x2u
allonq	0:fac0542384d7	5126	#define UART_C2_RWU_SHIFT 1
allonq	0:fac0542384d7	5127	#define UART_C2_RE_MASK 0x4u
allonq	0:fac0542384d7	5128	#define UART_C2_RE_SHIFT 2
allonq	0:fac0542384d7	5129	#define UART_C2_TE_MASK 0x8u
allonq	0:fac0542384d7	5130	#define UART_C2_TE_SHIFT 3
allonq	0:fac0542384d7	5131	#define UART_C2_ILIE_MASK 0x10u
allonq	0:fac0542384d7	5132	#define UART_C2_ILIE_SHIFT 4
allonq	0:fac0542384d7	5133	#define UART_C2_RIE_MASK 0x20u
allonq	0:fac0542384d7	5134	#define UART_C2_RIE_SHIFT 5
allonq	0:fac0542384d7	5135	#define UART_C2_TCIE_MASK 0x40u
allonq	0:fac0542384d7	5136	#define UART_C2_TCIE_SHIFT 6
allonq	0:fac0542384d7	5137	#define UART_C2_TIE_MASK 0x80u
allonq	0:fac0542384d7	5138	#define UART_C2_TIE_SHIFT 7
allonq	0:fac0542384d7	5139	/* S1 Bit Fields */
allonq	0:fac0542384d7	5140	#define UART_S1_PF_MASK 0x1u
allonq	0:fac0542384d7	5141	#define UART_S1_PF_SHIFT 0
allonq	0:fac0542384d7	5142	#define UART_S1_FE_MASK 0x2u
allonq	0:fac0542384d7	5143	#define UART_S1_FE_SHIFT 1
allonq	0:fac0542384d7	5144	#define UART_S1_NF_MASK 0x4u
allonq	0:fac0542384d7	5145	#define UART_S1_NF_SHIFT 2
allonq	0:fac0542384d7	5146	#define UART_S1_OR_MASK 0x8u
allonq	0:fac0542384d7	5147	#define UART_S1_OR_SHIFT 3
allonq	0:fac0542384d7	5148	#define UART_S1_IDLE_MASK 0x10u
allonq	0:fac0542384d7	5149	#define UART_S1_IDLE_SHIFT 4
allonq	0:fac0542384d7	5150	#define UART_S1_RDRF_MASK 0x20u
allonq	0:fac0542384d7	5151	#define UART_S1_RDRF_SHIFT 5
allonq	0:fac0542384d7	5152	#define UART_S1_TC_MASK 0x40u
allonq	0:fac0542384d7	5153	#define UART_S1_TC_SHIFT 6
allonq	0:fac0542384d7	5154	#define UART_S1_TDRE_MASK 0x80u
allonq	0:fac0542384d7	5155	#define UART_S1_TDRE_SHIFT 7
allonq	0:fac0542384d7	5156	/* S2 Bit Fields */
allonq	0:fac0542384d7	5157	#define UART_S2_RAF_MASK 0x1u
allonq	0:fac0542384d7	5158	#define UART_S2_RAF_SHIFT 0
allonq	0:fac0542384d7	5159	#define UART_S2_LBKDE_MASK 0x2u
allonq	0:fac0542384d7	5160	#define UART_S2_LBKDE_SHIFT 1
allonq	0:fac0542384d7	5161	#define UART_S2_BRK13_MASK 0x4u
allonq	0:fac0542384d7	5162	#define UART_S2_BRK13_SHIFT 2
allonq	0:fac0542384d7	5163	#define UART_S2_RWUID_MASK 0x8u
allonq	0:fac0542384d7	5164	#define UART_S2_RWUID_SHIFT 3
allonq	0:fac0542384d7	5165	#define UART_S2_RXINV_MASK 0x10u
allonq	0:fac0542384d7	5166	#define UART_S2_RXINV_SHIFT 4
allonq	0:fac0542384d7	5167	#define UART_S2_RXEDGIF_MASK 0x40u
allonq	0:fac0542384d7	5168	#define UART_S2_RXEDGIF_SHIFT 6
allonq	0:fac0542384d7	5169	#define UART_S2_LBKDIF_MASK 0x80u
allonq	0:fac0542384d7	5170	#define UART_S2_LBKDIF_SHIFT 7
allonq	0:fac0542384d7	5171	/* C3 Bit Fields */
allonq	0:fac0542384d7	5172	#define UART_C3_PEIE_MASK 0x1u
allonq	0:fac0542384d7	5173	#define UART_C3_PEIE_SHIFT 0
allonq	0:fac0542384d7	5174	#define UART_C3_FEIE_MASK 0x2u
allonq	0:fac0542384d7	5175	#define UART_C3_FEIE_SHIFT 1
allonq	0:fac0542384d7	5176	#define UART_C3_NEIE_MASK 0x4u
allonq	0:fac0542384d7	5177	#define UART_C3_NEIE_SHIFT 2
allonq	0:fac0542384d7	5178	#define UART_C3_ORIE_MASK 0x8u
allonq	0:fac0542384d7	5179	#define UART_C3_ORIE_SHIFT 3
allonq	0:fac0542384d7	5180	#define UART_C3_TXINV_MASK 0x10u
allonq	0:fac0542384d7	5181	#define UART_C3_TXINV_SHIFT 4
allonq	0:fac0542384d7	5182	#define UART_C3_TXDIR_MASK 0x20u
allonq	0:fac0542384d7	5183	#define UART_C3_TXDIR_SHIFT 5
allonq	0:fac0542384d7	5184	#define UART_C3_T8_MASK 0x40u
allonq	0:fac0542384d7	5185	#define UART_C3_T8_SHIFT 6
allonq	0:fac0542384d7	5186	#define UART_C3_R8_MASK 0x80u
allonq	0:fac0542384d7	5187	#define UART_C3_R8_SHIFT 7
allonq	0:fac0542384d7	5188	/* D Bit Fields */
allonq	0:fac0542384d7	5189	#define UART_D_R0T0_MASK 0x1u
allonq	0:fac0542384d7	5190	#define UART_D_R0T0_SHIFT 0
allonq	0:fac0542384d7	5191	#define UART_D_R1T1_MASK 0x2u
allonq	0:fac0542384d7	5192	#define UART_D_R1T1_SHIFT 1
allonq	0:fac0542384d7	5193	#define UART_D_R2T2_MASK 0x4u
allonq	0:fac0542384d7	5194	#define UART_D_R2T2_SHIFT 2
allonq	0:fac0542384d7	5195	#define UART_D_R3T3_MASK 0x8u
allonq	0:fac0542384d7	5196	#define UART_D_R3T3_SHIFT 3
allonq	0:fac0542384d7	5197	#define UART_D_R4T4_MASK 0x10u
allonq	0:fac0542384d7	5198	#define UART_D_R4T4_SHIFT 4
allonq	0:fac0542384d7	5199	#define UART_D_R5T5_MASK 0x20u
allonq	0:fac0542384d7	5200	#define UART_D_R5T5_SHIFT 5
allonq	0:fac0542384d7	5201	#define UART_D_R6T6_MASK 0x40u
allonq	0:fac0542384d7	5202	#define UART_D_R6T6_SHIFT 6
allonq	0:fac0542384d7	5203	#define UART_D_R7T7_MASK 0x80u
allonq	0:fac0542384d7	5204	#define UART_D_R7T7_SHIFT 7
allonq	0:fac0542384d7	5205	/* C4 Bit Fields */
allonq	0:fac0542384d7	5206	#define UART_C4_RDMAS_MASK 0x20u
allonq	0:fac0542384d7	5207	#define UART_C4_RDMAS_SHIFT 5
allonq	0:fac0542384d7	5208	#define UART_C4_TDMAS_MASK 0x80u
allonq	0:fac0542384d7	5209	#define UART_C4_TDMAS_SHIFT 7
allonq	0:fac0542384d7	5210
allonq	0:fac0542384d7	5211	/*!
allonq	0:fac0542384d7	5212	* @}
allonq	0:fac0542384d7	5213	/ / end of group UART_Register_Masks */
allonq	0:fac0542384d7	5214
allonq	0:fac0542384d7	5215
allonq	0:fac0542384d7	5216	/* UART - Peripheral instance base addresses */
allonq	0:fac0542384d7	5217	/** Peripheral UART1 base address */
allonq	0:fac0542384d7	5218	#define UART1_BASE (0x4006B000u)
allonq	0:fac0542384d7	5219	/** Peripheral UART1 base pointer */
allonq	0:fac0542384d7	5220	#define UART1 ((UART_Type *)UART1_BASE)
allonq	0:fac0542384d7	5221	/** Peripheral UART2 base address */
allonq	0:fac0542384d7	5222	#define UART2_BASE (0x4006C000u)
allonq	0:fac0542384d7	5223	/** Peripheral UART2 base pointer */
allonq	0:fac0542384d7	5224	#define UART2 ((UART_Type *)UART2_BASE)
allonq	0:fac0542384d7	5225	/** Array initializer of UART peripheral base pointers */
allonq	0:fac0542384d7	5226	#define UART_BASES { UART1, UART2 }
allonq	0:fac0542384d7	5227
allonq	0:fac0542384d7	5228	/*!
allonq	0:fac0542384d7	5229	* @}
allonq	0:fac0542384d7	5230	/ / end of group UART_Peripheral_Access_Layer */
allonq	0:fac0542384d7	5231
allonq	0:fac0542384d7	5232
allonq	0:fac0542384d7	5233	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5234	-- UART0 Peripheral Access Layer
allonq	0:fac0542384d7	5235	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5236
allonq	0:fac0542384d7	5237	/*!
allonq	0:fac0542384d7	5238	* @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
allonq	0:fac0542384d7	5239	* @{
allonq	0:fac0542384d7	5240	*/
allonq	0:fac0542384d7	5241
allonq	0:fac0542384d7	5242	/** UART0 - Register Layout Typedef */
allonq	0:fac0542384d7	5243	typedef struct {
allonq	0:fac0542384d7	5244	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
allonq	0:fac0542384d7	5245	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
allonq	0:fac0542384d7	5246	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
allonq	0:fac0542384d7	5247	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
allonq	0:fac0542384d7	5248	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
allonq	0:fac0542384d7	5249	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
allonq	0:fac0542384d7	5250	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
allonq	0:fac0542384d7	5251	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
allonq	0:fac0542384d7	5252	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
allonq	0:fac0542384d7	5253	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
allonq	0:fac0542384d7	5254	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
allonq	0:fac0542384d7	5255	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
allonq	0:fac0542384d7	5256	} UART0_Type;
allonq	0:fac0542384d7	5257
allonq	0:fac0542384d7	5258	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5259	-- UART0 Register Masks
allonq	0:fac0542384d7	5260	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5261
allonq	0:fac0542384d7	5262	/*!
allonq	0:fac0542384d7	5263	* @addtogroup UART0_Register_Masks UART0 Register Masks
allonq	0:fac0542384d7	5264	* @{
allonq	0:fac0542384d7	5265	*/
allonq	0:fac0542384d7	5266
allonq	0:fac0542384d7	5267	/* BDH Bit Fields */
allonq	0:fac0542384d7	5268	#define UART0_BDH_SBR_MASK 0x1Fu
allonq	0:fac0542384d7	5269	#define UART0_BDH_SBR_SHIFT 0
allonq	0:fac0542384d7	5270	#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
allonq	0:fac0542384d7	5271	#define UART0_BDH_SBNS_MASK 0x20u
allonq	0:fac0542384d7	5272	#define UART0_BDH_SBNS_SHIFT 5
allonq	0:fac0542384d7	5273	#define UART0_BDH_RXEDGIE_MASK 0x40u
allonq	0:fac0542384d7	5274	#define UART0_BDH_RXEDGIE_SHIFT 6
allonq	0:fac0542384d7	5275	#define UART0_BDH_LBKDIE_MASK 0x80u
allonq	0:fac0542384d7	5276	#define UART0_BDH_LBKDIE_SHIFT 7
allonq	0:fac0542384d7	5277	/* BDL Bit Fields */
allonq	0:fac0542384d7	5278	#define UART0_BDL_SBR_MASK 0xFFu
allonq	0:fac0542384d7	5279	#define UART0_BDL_SBR_SHIFT 0
allonq	0:fac0542384d7	5280	#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
allonq	0:fac0542384d7	5281	/* C1 Bit Fields */
allonq	0:fac0542384d7	5282	#define UART0_C1_PT_MASK 0x1u
allonq	0:fac0542384d7	5283	#define UART0_C1_PT_SHIFT 0
allonq	0:fac0542384d7	5284	#define UART0_C1_PE_MASK 0x2u
allonq	0:fac0542384d7	5285	#define UART0_C1_PE_SHIFT 1
allonq	0:fac0542384d7	5286	#define UART0_C1_ILT_MASK 0x4u
allonq	0:fac0542384d7	5287	#define UART0_C1_ILT_SHIFT 2
allonq	0:fac0542384d7	5288	#define UART0_C1_WAKE_MASK 0x8u
allonq	0:fac0542384d7	5289	#define UART0_C1_WAKE_SHIFT 3
allonq	0:fac0542384d7	5290	#define UART0_C1_M_MASK 0x10u
allonq	0:fac0542384d7	5291	#define UART0_C1_M_SHIFT 4
allonq	0:fac0542384d7	5292	#define UART0_C1_RSRC_MASK 0x20u
allonq	0:fac0542384d7	5293	#define UART0_C1_RSRC_SHIFT 5
allonq	0:fac0542384d7	5294	#define UART0_C1_DOZEEN_MASK 0x40u
allonq	0:fac0542384d7	5295	#define UART0_C1_DOZEEN_SHIFT 6
allonq	0:fac0542384d7	5296	#define UART0_C1_LOOPS_MASK 0x80u
allonq	0:fac0542384d7	5297	#define UART0_C1_LOOPS_SHIFT 7
allonq	0:fac0542384d7	5298	/* C2 Bit Fields */
allonq	0:fac0542384d7	5299	#define UART0_C2_SBK_MASK 0x1u
allonq	0:fac0542384d7	5300	#define UART0_C2_SBK_SHIFT 0
allonq	0:fac0542384d7	5301	#define UART0_C2_RWU_MASK 0x2u
allonq	0:fac0542384d7	5302	#define UART0_C2_RWU_SHIFT 1
allonq	0:fac0542384d7	5303	#define UART0_C2_RE_MASK 0x4u
allonq	0:fac0542384d7	5304	#define UART0_C2_RE_SHIFT 2
allonq	0:fac0542384d7	5305	#define UART0_C2_TE_MASK 0x8u
allonq	0:fac0542384d7	5306	#define UART0_C2_TE_SHIFT 3
allonq	0:fac0542384d7	5307	#define UART0_C2_ILIE_MASK 0x10u
allonq	0:fac0542384d7	5308	#define UART0_C2_ILIE_SHIFT 4
allonq	0:fac0542384d7	5309	#define UART0_C2_RIE_MASK 0x20u
allonq	0:fac0542384d7	5310	#define UART0_C2_RIE_SHIFT 5
allonq	0:fac0542384d7	5311	#define UART0_C2_TCIE_MASK 0x40u
allonq	0:fac0542384d7	5312	#define UART0_C2_TCIE_SHIFT 6
allonq	0:fac0542384d7	5313	#define UART0_C2_TIE_MASK 0x80u
allonq	0:fac0542384d7	5314	#define UART0_C2_TIE_SHIFT 7
allonq	0:fac0542384d7	5315	/* S1 Bit Fields */
allonq	0:fac0542384d7	5316	#define UART0_S1_PF_MASK 0x1u
allonq	0:fac0542384d7	5317	#define UART0_S1_PF_SHIFT 0
allonq	0:fac0542384d7	5318	#define UART0_S1_FE_MASK 0x2u
allonq	0:fac0542384d7	5319	#define UART0_S1_FE_SHIFT 1
allonq	0:fac0542384d7	5320	#define UART0_S1_NF_MASK 0x4u
allonq	0:fac0542384d7	5321	#define UART0_S1_NF_SHIFT 2
allonq	0:fac0542384d7	5322	#define UART0_S1_OR_MASK 0x8u
allonq	0:fac0542384d7	5323	#define UART0_S1_OR_SHIFT 3
allonq	0:fac0542384d7	5324	#define UART0_S1_IDLE_MASK 0x10u
allonq	0:fac0542384d7	5325	#define UART0_S1_IDLE_SHIFT 4
allonq	0:fac0542384d7	5326	#define UART0_S1_RDRF_MASK 0x20u
allonq	0:fac0542384d7	5327	#define UART0_S1_RDRF_SHIFT 5
allonq	0:fac0542384d7	5328	#define UART0_S1_TC_MASK 0x40u
allonq	0:fac0542384d7	5329	#define UART0_S1_TC_SHIFT 6
allonq	0:fac0542384d7	5330	#define UART0_S1_TDRE_MASK 0x80u
allonq	0:fac0542384d7	5331	#define UART0_S1_TDRE_SHIFT 7
allonq	0:fac0542384d7	5332	/* S2 Bit Fields */
allonq	0:fac0542384d7	5333	#define UART0_S2_RAF_MASK 0x1u
allonq	0:fac0542384d7	5334	#define UART0_S2_RAF_SHIFT 0
allonq	0:fac0542384d7	5335	#define UART0_S2_LBKDE_MASK 0x2u
allonq	0:fac0542384d7	5336	#define UART0_S2_LBKDE_SHIFT 1
allonq	0:fac0542384d7	5337	#define UART0_S2_BRK13_MASK 0x4u
allonq	0:fac0542384d7	5338	#define UART0_S2_BRK13_SHIFT 2
allonq	0:fac0542384d7	5339	#define UART0_S2_RWUID_MASK 0x8u
allonq	0:fac0542384d7	5340	#define UART0_S2_RWUID_SHIFT 3
allonq	0:fac0542384d7	5341	#define UART0_S2_RXINV_MASK 0x10u
allonq	0:fac0542384d7	5342	#define UART0_S2_RXINV_SHIFT 4
allonq	0:fac0542384d7	5343	#define UART0_S2_MSBF_MASK 0x20u
allonq	0:fac0542384d7	5344	#define UART0_S2_MSBF_SHIFT 5
allonq	0:fac0542384d7	5345	#define UART0_S2_RXEDGIF_MASK 0x40u
allonq	0:fac0542384d7	5346	#define UART0_S2_RXEDGIF_SHIFT 6
allonq	0:fac0542384d7	5347	#define UART0_S2_LBKDIF_MASK 0x80u
allonq	0:fac0542384d7	5348	#define UART0_S2_LBKDIF_SHIFT 7
allonq	0:fac0542384d7	5349	/* C3 Bit Fields */
allonq	0:fac0542384d7	5350	#define UART0_C3_PEIE_MASK 0x1u
allonq	0:fac0542384d7	5351	#define UART0_C3_PEIE_SHIFT 0
allonq	0:fac0542384d7	5352	#define UART0_C3_FEIE_MASK 0x2u
allonq	0:fac0542384d7	5353	#define UART0_C3_FEIE_SHIFT 1
allonq	0:fac0542384d7	5354	#define UART0_C3_NEIE_MASK 0x4u
allonq	0:fac0542384d7	5355	#define UART0_C3_NEIE_SHIFT 2
allonq	0:fac0542384d7	5356	#define UART0_C3_ORIE_MASK 0x8u
allonq	0:fac0542384d7	5357	#define UART0_C3_ORIE_SHIFT 3
allonq	0:fac0542384d7	5358	#define UART0_C3_TXINV_MASK 0x10u
allonq	0:fac0542384d7	5359	#define UART0_C3_TXINV_SHIFT 4
allonq	0:fac0542384d7	5360	#define UART0_C3_TXDIR_MASK 0x20u
allonq	0:fac0542384d7	5361	#define UART0_C3_TXDIR_SHIFT 5
allonq	0:fac0542384d7	5362	#define UART0_C3_R9T8_MASK 0x40u
allonq	0:fac0542384d7	5363	#define UART0_C3_R9T8_SHIFT 6
allonq	0:fac0542384d7	5364	#define UART0_C3_R8T9_MASK 0x80u
allonq	0:fac0542384d7	5365	#define UART0_C3_R8T9_SHIFT 7
allonq	0:fac0542384d7	5366	/* D Bit Fields */
allonq	0:fac0542384d7	5367	#define UART0_D_R0T0_MASK 0x1u
allonq	0:fac0542384d7	5368	#define UART0_D_R0T0_SHIFT 0
allonq	0:fac0542384d7	5369	#define UART0_D_R1T1_MASK 0x2u
allonq	0:fac0542384d7	5370	#define UART0_D_R1T1_SHIFT 1
allonq	0:fac0542384d7	5371	#define UART0_D_R2T2_MASK 0x4u
allonq	0:fac0542384d7	5372	#define UART0_D_R2T2_SHIFT 2
allonq	0:fac0542384d7	5373	#define UART0_D_R3T3_MASK 0x8u
allonq	0:fac0542384d7	5374	#define UART0_D_R3T3_SHIFT 3
allonq	0:fac0542384d7	5375	#define UART0_D_R4T4_MASK 0x10u
allonq	0:fac0542384d7	5376	#define UART0_D_R4T4_SHIFT 4
allonq	0:fac0542384d7	5377	#define UART0_D_R5T5_MASK 0x20u
allonq	0:fac0542384d7	5378	#define UART0_D_R5T5_SHIFT 5
allonq	0:fac0542384d7	5379	#define UART0_D_R6T6_MASK 0x40u
allonq	0:fac0542384d7	5380	#define UART0_D_R6T6_SHIFT 6
allonq	0:fac0542384d7	5381	#define UART0_D_R7T7_MASK 0x80u
allonq	0:fac0542384d7	5382	#define UART0_D_R7T7_SHIFT 7
allonq	0:fac0542384d7	5383	/* MA1 Bit Fields */
allonq	0:fac0542384d7	5384	#define UART0_MA1_MA_MASK 0xFFu
allonq	0:fac0542384d7	5385	#define UART0_MA1_MA_SHIFT 0
allonq	0:fac0542384d7	5386	#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
allonq	0:fac0542384d7	5387	/* MA2 Bit Fields */
allonq	0:fac0542384d7	5388	#define UART0_MA2_MA_MASK 0xFFu
allonq	0:fac0542384d7	5389	#define UART0_MA2_MA_SHIFT 0
allonq	0:fac0542384d7	5390	#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
allonq	0:fac0542384d7	5391	/* C4 Bit Fields */
allonq	0:fac0542384d7	5392	#define UART0_C4_OSR_MASK 0x1Fu
allonq	0:fac0542384d7	5393	#define UART0_C4_OSR_SHIFT 0
allonq	0:fac0542384d7	5394	#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
allonq	0:fac0542384d7	5395	#define UART0_C4_M10_MASK 0x20u
allonq	0:fac0542384d7	5396	#define UART0_C4_M10_SHIFT 5
allonq	0:fac0542384d7	5397	#define UART0_C4_MAEN2_MASK 0x40u
allonq	0:fac0542384d7	5398	#define UART0_C4_MAEN2_SHIFT 6
allonq	0:fac0542384d7	5399	#define UART0_C4_MAEN1_MASK 0x80u
allonq	0:fac0542384d7	5400	#define UART0_C4_MAEN1_SHIFT 7
allonq	0:fac0542384d7	5401	/* C5 Bit Fields */
allonq	0:fac0542384d7	5402	#define UART0_C5_RESYNCDIS_MASK 0x1u
allonq	0:fac0542384d7	5403	#define UART0_C5_RESYNCDIS_SHIFT 0
allonq	0:fac0542384d7	5404	#define UART0_C5_BOTHEDGE_MASK 0x2u
allonq	0:fac0542384d7	5405	#define UART0_C5_BOTHEDGE_SHIFT 1
allonq	0:fac0542384d7	5406	#define UART0_C5_RDMAE_MASK 0x20u
allonq	0:fac0542384d7	5407	#define UART0_C5_RDMAE_SHIFT 5
allonq	0:fac0542384d7	5408	#define UART0_C5_TDMAE_MASK 0x80u
allonq	0:fac0542384d7	5409	#define UART0_C5_TDMAE_SHIFT 7
allonq	0:fac0542384d7	5410
allonq	0:fac0542384d7	5411	/*!
allonq	0:fac0542384d7	5412	* @}
allonq	0:fac0542384d7	5413	/ / end of group UART0_Register_Masks */
allonq	0:fac0542384d7	5414
allonq	0:fac0542384d7	5415
allonq	0:fac0542384d7	5416	/* UART0 - Peripheral instance base addresses */
allonq	0:fac0542384d7	5417	/** Peripheral UART0 base address */
allonq	0:fac0542384d7	5418	#define UART0_BASE (0x4006A000u)
allonq	0:fac0542384d7	5419	/** Peripheral UART0 base pointer */
allonq	0:fac0542384d7	5420	#define UART0 ((UART0_Type *)UART0_BASE)
allonq	0:fac0542384d7	5421	/** Array initializer of UART0 peripheral base pointers */
allonq	0:fac0542384d7	5422	#define UART0_BASES { UART0 }
allonq	0:fac0542384d7	5423
allonq	0:fac0542384d7	5424	/*!
allonq	0:fac0542384d7	5425	* @}
allonq	0:fac0542384d7	5426	/ / end of group UART0_Peripheral_Access_Layer */
allonq	0:fac0542384d7	5427
allonq	0:fac0542384d7	5428
allonq	0:fac0542384d7	5429	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5430	-- USB Peripheral Access Layer
allonq	0:fac0542384d7	5431	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5432
allonq	0:fac0542384d7	5433	/*!
allonq	0:fac0542384d7	5434	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
allonq	0:fac0542384d7	5435	* @{
allonq	0:fac0542384d7	5436	*/
allonq	0:fac0542384d7	5437
allonq	0:fac0542384d7	5438	/** USB - Register Layout Typedef */
allonq	0:fac0542384d7	5439	typedef struct {
allonq	0:fac0542384d7	5440	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
allonq	0:fac0542384d7	5441	uint8_t RESERVED_0[3];
allonq	0:fac0542384d7	5442	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
allonq	0:fac0542384d7	5443	uint8_t RESERVED_1[3];
allonq	0:fac0542384d7	5444	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
allonq	0:fac0542384d7	5445	uint8_t RESERVED_2[3];
allonq	0:fac0542384d7	5446	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
allonq	0:fac0542384d7	5447	uint8_t RESERVED_3[3];
allonq	0:fac0542384d7	5448	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
allonq	0:fac0542384d7	5449	uint8_t RESERVED_4[3];
allonq	0:fac0542384d7	5450	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
allonq	0:fac0542384d7	5451	uint8_t RESERVED_5[3];
allonq	0:fac0542384d7	5452	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
allonq	0:fac0542384d7	5453	uint8_t RESERVED_6[3];
allonq	0:fac0542384d7	5454	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
allonq	0:fac0542384d7	5455	uint8_t RESERVED_7[99];
allonq	0:fac0542384d7	5456	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
allonq	0:fac0542384d7	5457	uint8_t RESERVED_8[3];
allonq	0:fac0542384d7	5458	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
allonq	0:fac0542384d7	5459	uint8_t RESERVED_9[3];
allonq	0:fac0542384d7	5460	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
allonq	0:fac0542384d7	5461	uint8_t RESERVED_10[3];
allonq	0:fac0542384d7	5462	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
allonq	0:fac0542384d7	5463	uint8_t RESERVED_11[3];
allonq	0:fac0542384d7	5464	__I uint8_t STAT; /*< Status register, offset: 0x90 /
allonq	0:fac0542384d7	5465	uint8_t RESERVED_12[3];
allonq	0:fac0542384d7	5466	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
allonq	0:fac0542384d7	5467	uint8_t RESERVED_13[3];
allonq	0:fac0542384d7	5468	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
allonq	0:fac0542384d7	5469	uint8_t RESERVED_14[3];
allonq	0:fac0542384d7	5470	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
allonq	0:fac0542384d7	5471	uint8_t RESERVED_15[3];
allonq	0:fac0542384d7	5472	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
allonq	0:fac0542384d7	5473	uint8_t RESERVED_16[3];
allonq	0:fac0542384d7	5474	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
allonq	0:fac0542384d7	5475	uint8_t RESERVED_17[3];
allonq	0:fac0542384d7	5476	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
allonq	0:fac0542384d7	5477	uint8_t RESERVED_18[3];
allonq	0:fac0542384d7	5478	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
allonq	0:fac0542384d7	5479	uint8_t RESERVED_19[3];
allonq	0:fac0542384d7	5480	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
allonq	0:fac0542384d7	5481	uint8_t RESERVED_20[3];
allonq	0:fac0542384d7	5482	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
allonq	0:fac0542384d7	5483	uint8_t RESERVED_21[11];
allonq	0:fac0542384d7	5484	struct { /* offset: 0xC0, array step: 0x4 */
allonq	0:fac0542384d7	5485	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
allonq	0:fac0542384d7	5486	uint8_t RESERVED_0[3];
allonq	0:fac0542384d7	5487	} ENDPOINT[16];
allonq	0:fac0542384d7	5488	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
allonq	0:fac0542384d7	5489	uint8_t RESERVED_22[3];
allonq	0:fac0542384d7	5490	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
allonq	0:fac0542384d7	5491	uint8_t RESERVED_23[3];
allonq	0:fac0542384d7	5492	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
allonq	0:fac0542384d7	5493	uint8_t RESERVED_24[3];
allonq	0:fac0542384d7	5494	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
allonq	0:fac0542384d7	5495	uint8_t RESERVED_25[7];
allonq	0:fac0542384d7	5496	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
allonq	0:fac0542384d7	5497	} USB_Type;
allonq	0:fac0542384d7	5498
allonq	0:fac0542384d7	5499	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5500	-- USB Register Masks
allonq	0:fac0542384d7	5501	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5502
allonq	0:fac0542384d7	5503	/*!
allonq	0:fac0542384d7	5504	* @addtogroup USB_Register_Masks USB Register Masks
allonq	0:fac0542384d7	5505	* @{
allonq	0:fac0542384d7	5506	*/
allonq	0:fac0542384d7	5507
allonq	0:fac0542384d7	5508	/* PERID Bit Fields */
allonq	0:fac0542384d7	5509	#define USB_PERID_ID_MASK 0x3Fu
allonq	0:fac0542384d7	5510	#define USB_PERID_ID_SHIFT 0
allonq	0:fac0542384d7	5511	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
allonq	0:fac0542384d7	5512	/* IDCOMP Bit Fields */
allonq	0:fac0542384d7	5513	#define USB_IDCOMP_NID_MASK 0x3Fu
allonq	0:fac0542384d7	5514	#define USB_IDCOMP_NID_SHIFT 0
allonq	0:fac0542384d7	5515	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
allonq	0:fac0542384d7	5516	/* REV Bit Fields */
allonq	0:fac0542384d7	5517	#define USB_REV_REV_MASK 0xFFu
allonq	0:fac0542384d7	5518	#define USB_REV_REV_SHIFT 0
allonq	0:fac0542384d7	5519	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
allonq	0:fac0542384d7	5520	/* ADDINFO Bit Fields */
allonq	0:fac0542384d7	5521	#define USB_ADDINFO_IEHOST_MASK 0x1u
allonq	0:fac0542384d7	5522	#define USB_ADDINFO_IEHOST_SHIFT 0
allonq	0:fac0542384d7	5523	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
allonq	0:fac0542384d7	5524	#define USB_ADDINFO_IRQNUM_SHIFT 3
allonq	0:fac0542384d7	5525	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
allonq	0:fac0542384d7	5526	/* OTGISTAT Bit Fields */
allonq	0:fac0542384d7	5527	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
allonq	0:fac0542384d7	5528	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
allonq	0:fac0542384d7	5529	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
allonq	0:fac0542384d7	5530	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
allonq	0:fac0542384d7	5531	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
allonq	0:fac0542384d7	5532	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
allonq	0:fac0542384d7	5533	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
allonq	0:fac0542384d7	5534	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
allonq	0:fac0542384d7	5535	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
allonq	0:fac0542384d7	5536	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
allonq	0:fac0542384d7	5537	#define USB_OTGISTAT_IDCHG_MASK 0x80u
allonq	0:fac0542384d7	5538	#define USB_OTGISTAT_IDCHG_SHIFT 7
allonq	0:fac0542384d7	5539	/* OTGICR Bit Fields */
allonq	0:fac0542384d7	5540	#define USB_OTGICR_AVBUSEN_MASK 0x1u
allonq	0:fac0542384d7	5541	#define USB_OTGICR_AVBUSEN_SHIFT 0
allonq	0:fac0542384d7	5542	#define USB_OTGICR_BSESSEN_MASK 0x4u
allonq	0:fac0542384d7	5543	#define USB_OTGICR_BSESSEN_SHIFT 2
allonq	0:fac0542384d7	5544	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
allonq	0:fac0542384d7	5545	#define USB_OTGICR_SESSVLDEN_SHIFT 3
allonq	0:fac0542384d7	5546	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
allonq	0:fac0542384d7	5547	#define USB_OTGICR_LINESTATEEN_SHIFT 5
allonq	0:fac0542384d7	5548	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
allonq	0:fac0542384d7	5549	#define USB_OTGICR_ONEMSECEN_SHIFT 6
allonq	0:fac0542384d7	5550	#define USB_OTGICR_IDEN_MASK 0x80u
allonq	0:fac0542384d7	5551	#define USB_OTGICR_IDEN_SHIFT 7
allonq	0:fac0542384d7	5552	/* OTGSTAT Bit Fields */
allonq	0:fac0542384d7	5553	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
allonq	0:fac0542384d7	5554	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
allonq	0:fac0542384d7	5555	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
allonq	0:fac0542384d7	5556	#define USB_OTGSTAT_BSESSEND_SHIFT 2
allonq	0:fac0542384d7	5557	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
allonq	0:fac0542384d7	5558	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
allonq	0:fac0542384d7	5559	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
allonq	0:fac0542384d7	5560	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
allonq	0:fac0542384d7	5561	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
allonq	0:fac0542384d7	5562	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
allonq	0:fac0542384d7	5563	#define USB_OTGSTAT_ID_MASK 0x80u
allonq	0:fac0542384d7	5564	#define USB_OTGSTAT_ID_SHIFT 7
allonq	0:fac0542384d7	5565	/* OTGCTL Bit Fields */
allonq	0:fac0542384d7	5566	#define USB_OTGCTL_OTGEN_MASK 0x4u
allonq	0:fac0542384d7	5567	#define USB_OTGCTL_OTGEN_SHIFT 2
allonq	0:fac0542384d7	5568	#define USB_OTGCTL_DMLOW_MASK 0x10u
allonq	0:fac0542384d7	5569	#define USB_OTGCTL_DMLOW_SHIFT 4
allonq	0:fac0542384d7	5570	#define USB_OTGCTL_DPLOW_MASK 0x20u
allonq	0:fac0542384d7	5571	#define USB_OTGCTL_DPLOW_SHIFT 5
allonq	0:fac0542384d7	5572	#define USB_OTGCTL_DPHIGH_MASK 0x80u
allonq	0:fac0542384d7	5573	#define USB_OTGCTL_DPHIGH_SHIFT 7
allonq	0:fac0542384d7	5574	/* ISTAT Bit Fields */
allonq	0:fac0542384d7	5575	#define USB_ISTAT_USBRST_MASK 0x1u
allonq	0:fac0542384d7	5576	#define USB_ISTAT_USBRST_SHIFT 0
allonq	0:fac0542384d7	5577	#define USB_ISTAT_ERROR_MASK 0x2u
allonq	0:fac0542384d7	5578	#define USB_ISTAT_ERROR_SHIFT 1
allonq	0:fac0542384d7	5579	#define USB_ISTAT_SOFTOK_MASK 0x4u
allonq	0:fac0542384d7	5580	#define USB_ISTAT_SOFTOK_SHIFT 2
allonq	0:fac0542384d7	5581	#define USB_ISTAT_TOKDNE_MASK 0x8u
allonq	0:fac0542384d7	5582	#define USB_ISTAT_TOKDNE_SHIFT 3
allonq	0:fac0542384d7	5583	#define USB_ISTAT_SLEEP_MASK 0x10u
allonq	0:fac0542384d7	5584	#define USB_ISTAT_SLEEP_SHIFT 4
allonq	0:fac0542384d7	5585	#define USB_ISTAT_RESUME_MASK 0x20u
allonq	0:fac0542384d7	5586	#define USB_ISTAT_RESUME_SHIFT 5
allonq	0:fac0542384d7	5587	#define USB_ISTAT_ATTACH_MASK 0x40u
allonq	0:fac0542384d7	5588	#define USB_ISTAT_ATTACH_SHIFT 6
allonq	0:fac0542384d7	5589	#define USB_ISTAT_STALL_MASK 0x80u
allonq	0:fac0542384d7	5590	#define USB_ISTAT_STALL_SHIFT 7
allonq	0:fac0542384d7	5591	/* INTEN Bit Fields */
allonq	0:fac0542384d7	5592	#define USB_INTEN_USBRSTEN_MASK 0x1u
allonq	0:fac0542384d7	5593	#define USB_INTEN_USBRSTEN_SHIFT 0
allonq	0:fac0542384d7	5594	#define USB_INTEN_ERROREN_MASK 0x2u
allonq	0:fac0542384d7	5595	#define USB_INTEN_ERROREN_SHIFT 1
allonq	0:fac0542384d7	5596	#define USB_INTEN_SOFTOKEN_MASK 0x4u
allonq	0:fac0542384d7	5597	#define USB_INTEN_SOFTOKEN_SHIFT 2
allonq	0:fac0542384d7	5598	#define USB_INTEN_TOKDNEEN_MASK 0x8u
allonq	0:fac0542384d7	5599	#define USB_INTEN_TOKDNEEN_SHIFT 3
allonq	0:fac0542384d7	5600	#define USB_INTEN_SLEEPEN_MASK 0x10u
allonq	0:fac0542384d7	5601	#define USB_INTEN_SLEEPEN_SHIFT 4
allonq	0:fac0542384d7	5602	#define USB_INTEN_RESUMEEN_MASK 0x20u
allonq	0:fac0542384d7	5603	#define USB_INTEN_RESUMEEN_SHIFT 5
allonq	0:fac0542384d7	5604	#define USB_INTEN_ATTACHEN_MASK 0x40u
allonq	0:fac0542384d7	5605	#define USB_INTEN_ATTACHEN_SHIFT 6
allonq	0:fac0542384d7	5606	#define USB_INTEN_STALLEN_MASK 0x80u
allonq	0:fac0542384d7	5607	#define USB_INTEN_STALLEN_SHIFT 7
allonq	0:fac0542384d7	5608	/* ERRSTAT Bit Fields */
allonq	0:fac0542384d7	5609	#define USB_ERRSTAT_PIDERR_MASK 0x1u
allonq	0:fac0542384d7	5610	#define USB_ERRSTAT_PIDERR_SHIFT 0
allonq	0:fac0542384d7	5611	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
allonq	0:fac0542384d7	5612	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
allonq	0:fac0542384d7	5613	#define USB_ERRSTAT_CRC16_MASK 0x4u
allonq	0:fac0542384d7	5614	#define USB_ERRSTAT_CRC16_SHIFT 2
allonq	0:fac0542384d7	5615	#define USB_ERRSTAT_DFN8_MASK 0x8u
allonq	0:fac0542384d7	5616	#define USB_ERRSTAT_DFN8_SHIFT 3
allonq	0:fac0542384d7	5617	#define USB_ERRSTAT_BTOERR_MASK 0x10u
allonq	0:fac0542384d7	5618	#define USB_ERRSTAT_BTOERR_SHIFT 4
allonq	0:fac0542384d7	5619	#define USB_ERRSTAT_DMAERR_MASK 0x20u
allonq	0:fac0542384d7	5620	#define USB_ERRSTAT_DMAERR_SHIFT 5
allonq	0:fac0542384d7	5621	#define USB_ERRSTAT_BTSERR_MASK 0x80u
allonq	0:fac0542384d7	5622	#define USB_ERRSTAT_BTSERR_SHIFT 7
allonq	0:fac0542384d7	5623	/* ERREN Bit Fields */
allonq	0:fac0542384d7	5624	#define USB_ERREN_PIDERREN_MASK 0x1u
allonq	0:fac0542384d7	5625	#define USB_ERREN_PIDERREN_SHIFT 0
allonq	0:fac0542384d7	5626	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
allonq	0:fac0542384d7	5627	#define USB_ERREN_CRC5EOFEN_SHIFT 1
allonq	0:fac0542384d7	5628	#define USB_ERREN_CRC16EN_MASK 0x4u
allonq	0:fac0542384d7	5629	#define USB_ERREN_CRC16EN_SHIFT 2
allonq	0:fac0542384d7	5630	#define USB_ERREN_DFN8EN_MASK 0x8u
allonq	0:fac0542384d7	5631	#define USB_ERREN_DFN8EN_SHIFT 3
allonq	0:fac0542384d7	5632	#define USB_ERREN_BTOERREN_MASK 0x10u
allonq	0:fac0542384d7	5633	#define USB_ERREN_BTOERREN_SHIFT 4
allonq	0:fac0542384d7	5634	#define USB_ERREN_DMAERREN_MASK 0x20u
allonq	0:fac0542384d7	5635	#define USB_ERREN_DMAERREN_SHIFT 5
allonq	0:fac0542384d7	5636	#define USB_ERREN_BTSERREN_MASK 0x80u
allonq	0:fac0542384d7	5637	#define USB_ERREN_BTSERREN_SHIFT 7
allonq	0:fac0542384d7	5638	/* STAT Bit Fields */
allonq	0:fac0542384d7	5639	#define USB_STAT_ODD_MASK 0x4u
allonq	0:fac0542384d7	5640	#define USB_STAT_ODD_SHIFT 2
allonq	0:fac0542384d7	5641	#define USB_STAT_TX_MASK 0x8u
allonq	0:fac0542384d7	5642	#define USB_STAT_TX_SHIFT 3
allonq	0:fac0542384d7	5643	#define USB_STAT_ENDP_MASK 0xF0u
allonq	0:fac0542384d7	5644	#define USB_STAT_ENDP_SHIFT 4
allonq	0:fac0542384d7	5645	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
allonq	0:fac0542384d7	5646	/* CTL Bit Fields */
allonq	0:fac0542384d7	5647	#define USB_CTL_USBENSOFEN_MASK 0x1u
allonq	0:fac0542384d7	5648	#define USB_CTL_USBENSOFEN_SHIFT 0
allonq	0:fac0542384d7	5649	#define USB_CTL_ODDRST_MASK 0x2u
allonq	0:fac0542384d7	5650	#define USB_CTL_ODDRST_SHIFT 1
allonq	0:fac0542384d7	5651	#define USB_CTL_RESUME_MASK 0x4u
allonq	0:fac0542384d7	5652	#define USB_CTL_RESUME_SHIFT 2
allonq	0:fac0542384d7	5653	#define USB_CTL_HOSTMODEEN_MASK 0x8u
allonq	0:fac0542384d7	5654	#define USB_CTL_HOSTMODEEN_SHIFT 3
allonq	0:fac0542384d7	5655	#define USB_CTL_RESET_MASK 0x10u
allonq	0:fac0542384d7	5656	#define USB_CTL_RESET_SHIFT 4
allonq	0:fac0542384d7	5657	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
allonq	0:fac0542384d7	5658	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
allonq	0:fac0542384d7	5659	#define USB_CTL_SE0_MASK 0x40u
allonq	0:fac0542384d7	5660	#define USB_CTL_SE0_SHIFT 6
allonq	0:fac0542384d7	5661	#define USB_CTL_JSTATE_MASK 0x80u
allonq	0:fac0542384d7	5662	#define USB_CTL_JSTATE_SHIFT 7
allonq	0:fac0542384d7	5663	/* ADDR Bit Fields */
allonq	0:fac0542384d7	5664	#define USB_ADDR_ADDR_MASK 0x7Fu
allonq	0:fac0542384d7	5665	#define USB_ADDR_ADDR_SHIFT 0
allonq	0:fac0542384d7	5666	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
allonq	0:fac0542384d7	5667	#define USB_ADDR_LSEN_MASK 0x80u
allonq	0:fac0542384d7	5668	#define USB_ADDR_LSEN_SHIFT 7
allonq	0:fac0542384d7	5669	/* BDTPAGE1 Bit Fields */
allonq	0:fac0542384d7	5670	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
allonq	0:fac0542384d7	5671	#define USB_BDTPAGE1_BDTBA_SHIFT 1
allonq	0:fac0542384d7	5672	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
allonq	0:fac0542384d7	5673	/* FRMNUML Bit Fields */
allonq	0:fac0542384d7	5674	#define USB_FRMNUML_FRM_MASK 0xFFu
allonq	0:fac0542384d7	5675	#define USB_FRMNUML_FRM_SHIFT 0
allonq	0:fac0542384d7	5676	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
allonq	0:fac0542384d7	5677	/* FRMNUMH Bit Fields */
allonq	0:fac0542384d7	5678	#define USB_FRMNUMH_FRM_MASK 0x7u
allonq	0:fac0542384d7	5679	#define USB_FRMNUMH_FRM_SHIFT 0
allonq	0:fac0542384d7	5680	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
allonq	0:fac0542384d7	5681	/* TOKEN Bit Fields */
allonq	0:fac0542384d7	5682	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
allonq	0:fac0542384d7	5683	#define USB_TOKEN_TOKENENDPT_SHIFT 0
allonq	0:fac0542384d7	5684	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
allonq	0:fac0542384d7	5685	#define USB_TOKEN_TOKENPID_MASK 0xF0u
allonq	0:fac0542384d7	5686	#define USB_TOKEN_TOKENPID_SHIFT 4
allonq	0:fac0542384d7	5687	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
allonq	0:fac0542384d7	5688	/* SOFTHLD Bit Fields */
allonq	0:fac0542384d7	5689	#define USB_SOFTHLD_CNT_MASK 0xFFu
allonq	0:fac0542384d7	5690	#define USB_SOFTHLD_CNT_SHIFT 0
allonq	0:fac0542384d7	5691	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
allonq	0:fac0542384d7	5692	/* BDTPAGE2 Bit Fields */
allonq	0:fac0542384d7	5693	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
allonq	0:fac0542384d7	5694	#define USB_BDTPAGE2_BDTBA_SHIFT 0
allonq	0:fac0542384d7	5695	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
allonq	0:fac0542384d7	5696	/* BDTPAGE3 Bit Fields */
allonq	0:fac0542384d7	5697	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
allonq	0:fac0542384d7	5698	#define USB_BDTPAGE3_BDTBA_SHIFT 0
allonq	0:fac0542384d7	5699	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
allonq	0:fac0542384d7	5700	/* ENDPT Bit Fields */
allonq	0:fac0542384d7	5701	#define USB_ENDPT_EPHSHK_MASK 0x1u
allonq	0:fac0542384d7	5702	#define USB_ENDPT_EPHSHK_SHIFT 0
allonq	0:fac0542384d7	5703	#define USB_ENDPT_EPSTALL_MASK 0x2u
allonq	0:fac0542384d7	5704	#define USB_ENDPT_EPSTALL_SHIFT 1
allonq	0:fac0542384d7	5705	#define USB_ENDPT_EPTXEN_MASK 0x4u
allonq	0:fac0542384d7	5706	#define USB_ENDPT_EPTXEN_SHIFT 2
allonq	0:fac0542384d7	5707	#define USB_ENDPT_EPRXEN_MASK 0x8u
allonq	0:fac0542384d7	5708	#define USB_ENDPT_EPRXEN_SHIFT 3
allonq	0:fac0542384d7	5709	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
allonq	0:fac0542384d7	5710	#define USB_ENDPT_EPCTLDIS_SHIFT 4
allonq	0:fac0542384d7	5711	#define USB_ENDPT_RETRYDIS_MASK 0x40u
allonq	0:fac0542384d7	5712	#define USB_ENDPT_RETRYDIS_SHIFT 6
allonq	0:fac0542384d7	5713	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
allonq	0:fac0542384d7	5714	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
allonq	0:fac0542384d7	5715	/* USBCTRL Bit Fields */
allonq	0:fac0542384d7	5716	#define USB_USBCTRL_PDE_MASK 0x40u
allonq	0:fac0542384d7	5717	#define USB_USBCTRL_PDE_SHIFT 6
allonq	0:fac0542384d7	5718	#define USB_USBCTRL_SUSP_MASK 0x80u
allonq	0:fac0542384d7	5719	#define USB_USBCTRL_SUSP_SHIFT 7
allonq	0:fac0542384d7	5720	/* OBSERVE Bit Fields */
allonq	0:fac0542384d7	5721	#define USB_OBSERVE_DMPD_MASK 0x10u
allonq	0:fac0542384d7	5722	#define USB_OBSERVE_DMPD_SHIFT 4
allonq	0:fac0542384d7	5723	#define USB_OBSERVE_DPPD_MASK 0x40u
allonq	0:fac0542384d7	5724	#define USB_OBSERVE_DPPD_SHIFT 6
allonq	0:fac0542384d7	5725	#define USB_OBSERVE_DPPU_MASK 0x80u
allonq	0:fac0542384d7	5726	#define USB_OBSERVE_DPPU_SHIFT 7
allonq	0:fac0542384d7	5727	/* CONTROL Bit Fields */
allonq	0:fac0542384d7	5728	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
allonq	0:fac0542384d7	5729	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
allonq	0:fac0542384d7	5730	/* USBTRC0 Bit Fields */
allonq	0:fac0542384d7	5731	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
allonq	0:fac0542384d7	5732	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
allonq	0:fac0542384d7	5733	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
allonq	0:fac0542384d7	5734	#define USB_USBTRC0_SYNC_DET_SHIFT 1
allonq	0:fac0542384d7	5735	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
allonq	0:fac0542384d7	5736	#define USB_USBTRC0_USBRESMEN_SHIFT 5
allonq	0:fac0542384d7	5737	#define USB_USBTRC0_USBRESET_MASK 0x80u
allonq	0:fac0542384d7	5738	#define USB_USBTRC0_USBRESET_SHIFT 7
allonq	0:fac0542384d7	5739	/* USBFRMADJUST Bit Fields */
allonq	0:fac0542384d7	5740	#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
allonq	0:fac0542384d7	5741	#define USB_USBFRMADJUST_ADJ_SHIFT 0
allonq	0:fac0542384d7	5742	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
allonq	0:fac0542384d7	5743
allonq	0:fac0542384d7	5744	/*!
allonq	0:fac0542384d7	5745	* @}
allonq	0:fac0542384d7	5746	/ / end of group USB_Register_Masks */
allonq	0:fac0542384d7	5747
allonq	0:fac0542384d7	5748
allonq	0:fac0542384d7	5749	/* USB - Peripheral instance base addresses */
allonq	0:fac0542384d7	5750	/** Peripheral USB0 base address */
allonq	0:fac0542384d7	5751	#define USB0_BASE (0x40072000u)
allonq	0:fac0542384d7	5752	/** Peripheral USB0 base pointer */
allonq	0:fac0542384d7	5753	#define USB0 ((USB_Type *)USB0_BASE)
allonq	0:fac0542384d7	5754	/** Array initializer of USB peripheral base pointers */
allonq	0:fac0542384d7	5755	#define USB_BASES { USB0 }
allonq	0:fac0542384d7	5756
allonq	0:fac0542384d7	5757	/*!
allonq	0:fac0542384d7	5758	* @}
allonq	0:fac0542384d7	5759	/ / end of group USB_Peripheral_Access_Layer */
allonq	0:fac0542384d7	5760
allonq	0:fac0542384d7	5761
allonq	0:fac0542384d7	5762	/*
allonq	0:fac0542384d7	5763	** End of section using anonymous unions
allonq	0:fac0542384d7	5764	*/
allonq	0:fac0542384d7	5765
allonq	0:fac0542384d7	5766	#if defined(__ARMCC_VERSION)
allonq	0:fac0542384d7	5767	#pragma pop
allonq	0:fac0542384d7	5768	#elif defined(__CWCC__)
allonq	0:fac0542384d7	5769	#pragma pop
allonq	0:fac0542384d7	5770	#elif defined(__GNUC__)
allonq	0:fac0542384d7	5771	/* leave anonymous unions enabled */
allonq	0:fac0542384d7	5772	#elif defined(__IAR_SYSTEMS_ICC__)
allonq	0:fac0542384d7	5773	#pragma language=default
allonq	0:fac0542384d7	5774	#else
allonq	0:fac0542384d7	5775	#error Not supported compiler type
allonq	0:fac0542384d7	5776	#endif
allonq	0:fac0542384d7	5777
allonq	0:fac0542384d7	5778	/*!
allonq	0:fac0542384d7	5779	* @}
allonq	0:fac0542384d7	5780	/ / end of group Peripheral_access_layer */
allonq	0:fac0542384d7	5781
allonq	0:fac0542384d7	5782
allonq	0:fac0542384d7	5783	/* ----------------------------------------------------------------------------
allonq	0:fac0542384d7	5784	-- Backward Compatibility
allonq	0:fac0542384d7	5785	---------------------------------------------------------------------------- */
allonq	0:fac0542384d7	5786
allonq	0:fac0542384d7	5787	/*!
allonq	0:fac0542384d7	5788	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
allonq	0:fac0542384d7	5789	* @{
allonq	0:fac0542384d7	5790	*/
allonq	0:fac0542384d7	5791
allonq	0:fac0542384d7	5792	/* No backward compatibility issues. */
allonq	0:fac0542384d7	5793
allonq	0:fac0542384d7	5794	/*!
allonq	0:fac0542384d7	5795	* @}
allonq	0:fac0542384d7	5796	/ / end of group Backward_Compatibility_Symbols */
allonq	0:fac0542384d7	5797
allonq	0:fac0542384d7	5798
allonq	0:fac0542384d7	5799	#endif /* #if !defined(MKL46Z4_H_) */
allonq	0:fac0542384d7	5800
allonq	0:fac0542384d7	5801	/* MKL46Z4.h, eof. */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	16 Mar 2014
Imports:	0
Forks:	0
Commits:	4
Dependents:	0
Dependencies:	1
Followers:	1

MKL46Z4.h@0:fac0542384d7, 2014-03-13 (annotated)

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