Kai Liu / Mbed 2 deprecated CC1101_Transceiver

Codebase from CC1101_Transceiver, ported to LPC1114/LPC824/STM32F103 and other micros, will be merged with panStamp project to replace AVR/MSP.

Dependencies:   mbed

Fork of CC1101_Transceiver_LPC1114 by Kai Liu

CC1101.cpp@2:0e79d58be0f6, 2017-08-24 (annotated)

Committer:
allankliu
Date:
Thu Aug 24 10:37:31 2017 +0000
Revision:
2:0e79d58be0f6
Parent:
0:9df942ea84f4 
Init version, integrated CC1101_Transceiver with STM32F103RB/LPC824, publish to public for further debugging. Current SPI access 0x30 to 0x3D registers are not stable.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmav123 0:9df942ea84f4 1
tmav123 0:9df942ea84f4 2 #include "CC1101.h"
tmav123 0:9df942ea84f4 3
tmav123 0:9df942ea84f4 4 #define RF_0db
tmav123 0:9df942ea84f4 5 //#define RF_10db
tmav123 0:9df942ea84f4 6 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 7 CC1101::CC1101(PinName mosi, PinName miso, PinName clk, PinName csn, PinName RDmiso):
tmav123 0:9df942ea84f4 8 _spi(mosi, miso, clk), _csn(csn), _RDmiso(RDmiso)
tmav123 0:9df942ea84f4 9 {
tmav123 0:9df942ea84f4 10 _csn = 1;
tmav123 0:9df942ea84f4 11
tmav123 0:9df942ea84f4 12 // Setup the spi for 8 bit data, high steady state clock,
tmav123 0:9df942ea84f4 13 // second edge capture, with a 1MHz clock rate
tmav123 0:9df942ea84f4 14 _spi.format(8,0);
tmav123 0:9df942ea84f4 15 _spi.frequency(1000000);
tmav123 0:9df942ea84f4 16
tmav123 0:9df942ea84f4 17 POWER_UP_RESET_CCxxx0();
tmav123 0:9df942ea84f4 18 Strobe(CCxxx0_SRX);
tmav123 0:9df942ea84f4 19 }
tmav123 0:9df942ea84f4 20 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 21 RF_SETTINGS rfSettings = // 433Mhz, 9600Bauds
tmav123 0:9df942ea84f4 22 {
tmav123 0:9df942ea84f4 23 0x06, // FSCTRL1 Frequency Synthesizer Control - IF:152.343Khz
tmav123 0:9df942ea84f4 24 0x07, // IOCFG0 GDO0 Output Pin Configuration - Packet received and CRC OK
tmav123 0:9df942ea84f4 25 0x00, // FSCTRL0 Frequency Synthesizer Control - Freq offset
tmav123 0:9df942ea84f4 26 0x10, // FREQ2 Frequency Control Word, High Byte - 433.999 Mhz
tmav123 0:9df942ea84f4 27 0xB1, // FREQ1 Frequency Control Word, Middle Byte
tmav123 0:9df942ea84f4 28 0x3B, // FREQ0 Frequency Control Word, Low Byte
tmav123 0:9df942ea84f4 29 0xF8, // MDMCFG4 Modem Configuration - BW: 58.035Khz
tmav123 0:9df942ea84f4 30 0x83, // MDMCFG3 Modem Configuration - 9595 Baud
tmav123 0:9df942ea84f4 31 0x13, // MDMCFG2 Modem Configuration - 30/32 sync word bits - Manchester disable - GFSK - Digital DC filter enable
tmav123 0:9df942ea84f4 32 0x22, // MDMCFG1 Modem Configuration - num of preamble bytes:4 - FEC disable
tmav123 0:9df942ea84f4 33 0xF8, // MDMCFG0 Modem Configuration - Channel spacing: 199.951Khz
tmav123 0:9df942ea84f4 34 0x00, // CHANNR Channel Number
tmav123 0:9df942ea84f4 35 0x15, // DEVIATN Modem Deviation Setting - 5.157Khz
tmav123 0:9df942ea84f4 36 0x56, // FREND1 Front End RX Configuration
tmav123 0:9df942ea84f4 37 0x10, // FREND0 Front End TX Configuration
tmav123 0:9df942ea84f4 38 0x18, // MCSM0 Main Radio Control State Machine Configuration - PO timeout: 64(149-155us) - Auto calibrate from idle to rx/tx
tmav123 0:9df942ea84f4 39 0x16, // FOCCFG Frequency Offset Compensation Configuration
tmav123 0:9df942ea84f4 40 0x6C, // BSCFG Bit Synchronization Configuration
tmav123 0:9df942ea84f4 41 0x03, // AGCCTRL2 AGC Control - target amplitude: 33dB - Maximum possible LNA + LNA 2 gain - All gain settings can be used
tmav123 0:9df942ea84f4 42 0x40, // AGCCTRL1 AGC Control - LNA gain decreased first
tmav123 0:9df942ea84f4 43 0x91, // AGCCTRL0 AGC Control - Medium hysterisis - Filter Samples: 16 - Normal AGC operation
tmav123 0:9df942ea84f4 44 0xE9, // FSCAL3 Frequency Synthesizer Calibration
tmav123 0:9df942ea84f4 45 0x2A, // FSCAL2 Frequency Synthesizer Calibration
tmav123 0:9df942ea84f4 46 0x00, // FSCAL1 Frequency Synthesizer Calibration
tmav123 0:9df942ea84f4 47 0x1F, // FSCAL0 Frequency Synthesizer Calibration
tmav123 0:9df942ea84f4 48 0x59, // FSTEST Frequency Synthesizer Calibration Control
tmav123 0:9df942ea84f4 49 0x88, // TEST2 Various Test Settings
tmav123 0:9df942ea84f4 50 0x31, // TEST1 Various Test Settings
tmav123 0:9df942ea84f4 51 0x09, // TEST0 Various Test Settings
tmav123 0:9df942ea84f4 52 0x07, // FIFOTHR RX FIFO and TX FIFO Thresholds - Bytes in TX FIFO:33 - Bytes in RX FIFO:32
tmav123 0:9df942ea84f4 53 0x06, // IOCFG2 GDO2 Output Pin Configuration - Sync word received/sent - end of packet
tmav123 0:9df942ea84f4 54 0x04, // PKTCTRL1 Packet Automation Control - No address check - Automatic flush of RX FIFO is disable - sync word is always accepted
tmav123 0:9df942ea84f4 55 0x05, // PKTCTRL0 Packet Automation Control - whitening is off - RX/TX data normal mode - CRC calculation in TX and CRC check in RX - Variable packet length
tmav123 0:9df942ea84f4 56 0x00, // ADDR Device Address
tmav123 0:9df942ea84f4 57 0xFF, // PKTLEN Packet Length
tmav123 0:9df942ea84f4 58 0x3F, // MCSM1 Main Radio Control State Machine Configuration
tmav123 0:9df942ea84f4 59 };
tmav123 0:9df942ea84f4 60 #ifdef RF_0db
tmav123 0:9df942ea84f4 61 // PATABLE (0 dBm output power)
tmav123 0:9df942ea84f4 62 char paTable[] = {0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
tmav123 0:9df942ea84f4 63 #endif
tmav123 0:9df942ea84f4 64 #ifdef RF_10db
tmav123 0:9df942ea84f4 65 // PATABLE (10 dBm output power)
tmav123 0:9df942ea84f4 66 char paTable[] = {0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
tmav123 0:9df942ea84f4 67 #endif
tmav123 0:9df942ea84f4 68 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 69 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 70 // Macro to reset the CCxxx0 and wait for it to be ready
tmav123 0:9df942ea84f4 71 void CC1101::RESET_CCxxx0(void)
tmav123 0:9df942ea84f4 72 {
tmav123 0:9df942ea84f4 73 // while (_RDmiso);
tmav123 0:9df942ea84f4 74 _csn = 0;
tmav123 0:9df942ea84f4 75 wait(0.000002);
tmav123 0:9df942ea84f4 76 while (_RDmiso);
tmav123 0:9df942ea84f4 77 _spi.write(CCxxx0_SRES);
tmav123 0:9df942ea84f4 78 wait(0.000002);
tmav123 0:9df942ea84f4 79 _csn = 1;
tmav123 0:9df942ea84f4 80 }
tmav123 0:9df942ea84f4 81 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 82 // Macro to reset the CCxxx0 after power_on and wait for it to be ready
tmav123 0:9df942ea84f4 83 // IMPORTANT NOTICE:
tmav123 0:9df942ea84f4 84 // The file Wait.c must be included if this macro shall be used
tmav123 0:9df942ea84f4 85 // The file is located under: ..\Lib\Chipcon\Hal\CCxx00
tmav123 0:9df942ea84f4 86 //
tmav123 0:9df942ea84f4 87 // min 40 us
tmav123 0:9df942ea84f4 88 // <----------------------->
tmav123 0:9df942ea84f4 89 // CSn |--| |--------------------| |-----------
tmav123 0:9df942ea84f4 90 // | | | | |
tmav123 0:9df942ea84f4 91 // -- ----------
tmav123 0:9df942ea84f4 92 //
tmav123 0:9df942ea84f4 93 // MISO |---------------
tmav123 0:9df942ea84f4 94 // - - - - - - - - - - - - - - - -| |
tmav123 0:9df942ea84f4 95 // --
tmav123 0:9df942ea84f4 96 // Unknown / don't care
tmav123 0:9df942ea84f4 97 //
tmav123 0:9df942ea84f4 98 // MOSI - - - - - - - - - - - - - - - ---------- - - - - -
tmav123 0:9df942ea84f4 99 // | SRES |
tmav123 0:9df942ea84f4 100 // - - - - - - - - - - - - - - - ---------- - - - - -
tmav123 0:9df942ea84f4 101 //
tmav123 0:9df942ea84f4 102 void CC1101::POWER_UP_RESET_CCxxx0(void)
tmav123 0:9df942ea84f4 103 {
tmav123 0:9df942ea84f4 104 _csn = 1;
tmav123 0:9df942ea84f4 105 wait(1e-6);
tmav123 0:9df942ea84f4 106 _csn = 0;
tmav123 0:9df942ea84f4 107 wait(1e-6);
tmav123 0:9df942ea84f4 108 _csn = 1;
tmav123 0:9df942ea84f4 109 wait(41e-6);
tmav123 0:9df942ea84f4 110 RESET_CCxxx0();
tmav123 0:9df942ea84f4 111 }
tmav123 0:9df942ea84f4 112 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 113 // void Strobe(unsigned char strobe)
tmav123 0:9df942ea84f4 114 //
tmav123 0:9df942ea84f4 115 // DESCRIPTION:
tmav123 0:9df942ea84f4 116 // Function for writing a strobe command to the CCxxx0
tmav123 0:9df942ea84f4 117 //
tmav123 0:9df942ea84f4 118 // ARGUMENTS:
tmav123 0:9df942ea84f4 119 // unsigned char strobe
tmav123 0:9df942ea84f4 120 // Strobe command
tmav123 0:9df942ea84f4 121 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 122 unsigned char CC1101::Strobe(unsigned char strobe)
tmav123 0:9df942ea84f4 123 {
tmav123 0:9df942ea84f4 124 unsigned char x;
tmav123 0:9df942ea84f4 125 wait(0.000005);
tmav123 0:9df942ea84f4 126 _csn = 0;
tmav123 0:9df942ea84f4 127 wait(0.000002);
tmav123 0:9df942ea84f4 128 while (_RDmiso);
tmav123 0:9df942ea84f4 129 x = _spi.write(strobe);
tmav123 0:9df942ea84f4 130 wait(0.000002);
tmav123 0:9df942ea84f4 131 _csn = 1;
tmav123 0:9df942ea84f4 132 return x;
tmav123 0:9df942ea84f4 133 }// Strobe
tmav123 0:9df942ea84f4 134 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 135 // unsigned char ReadStatus(unsigned char addr)
tmav123 0:9df942ea84f4 136 //
tmav123 0:9df942ea84f4 137 // DESCRIPTION:
tmav123 0:9df942ea84f4 138 // This function reads a CCxxx0 status register.
tmav123 0:9df942ea84f4 139 //
tmav123 0:9df942ea84f4 140 // ARGUMENTS:
tmav123 0:9df942ea84f4 141 // unsigned char addr
tmav123 0:9df942ea84f4 142 // Address of the CCxxx0 status register to be accessed.
tmav123 0:9df942ea84f4 143 //
tmav123 0:9df942ea84f4 144 // RETURN VALUE:
tmav123 0:9df942ea84f4 145 // unsigned char
tmav123 0:9df942ea84f4 146 // Value of the accessed CCxxx0 status register.
tmav123 0:9df942ea84f4 147 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 148 unsigned char CC1101::ReadStatus(unsigned char addr)
tmav123 0:9df942ea84f4 149 {
tmav123 0:9df942ea84f4 150 unsigned char x;
tmav123 0:9df942ea84f4 151 wait(0.000005);
tmav123 0:9df942ea84f4 152 _csn = 0;
tmav123 0:9df942ea84f4 153 wait(0.000002);
tmav123 0:9df942ea84f4 154 while (_RDmiso);
tmav123 0:9df942ea84f4 155 _spi.write(addr | READ_BURST);
tmav123 0:9df942ea84f4 156 x = _spi.write(0);
tmav123 0:9df942ea84f4 157 wait(0.000002);
tmav123 0:9df942ea84f4 158 _csn = 1;
tmav123 0:9df942ea84f4 159 return x;
tmav123 0:9df942ea84f4 160 }// ReadStatus
tmav123 0:9df942ea84f4 161 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 162 // void WriteRfSettings(RF_SETTINGS *pRfSettings)
tmav123 0:9df942ea84f4 163 //
tmav123 0:9df942ea84f4 164 // DESCRIPTION:
tmav123 0:9df942ea84f4 165 // This function is used to configure the CCxxx0 based on a given rf setting
tmav123 0:9df942ea84f4 166 //
tmav123 0:9df942ea84f4 167 // ARGUMENTS:
tmav123 0:9df942ea84f4 168 // RF_SETTINGS *pRfSettings
tmav123 0:9df942ea84f4 169 // Pointer to a struct containing rf register settings
tmav123 0:9df942ea84f4 170 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 171 void CC1101::WriteRfSettings(RF_SETTINGS *pRfSettings)
tmav123 0:9df942ea84f4 172 {
tmav123 0:9df942ea84f4 173 // Write register settings
tmav123 0:9df942ea84f4 174 WriteReg(CCxxx0_FSCTRL1, pRfSettings->FSCTRL1);
tmav123 0:9df942ea84f4 175 WriteReg(CCxxx0_FSCTRL0, pRfSettings->FSCTRL0);
tmav123 0:9df942ea84f4 176 WriteReg(CCxxx0_FREQ2, pRfSettings->FREQ2);
tmav123 0:9df942ea84f4 177 WriteReg(CCxxx0_FREQ1, pRfSettings->FREQ1);
tmav123 0:9df942ea84f4 178 WriteReg(CCxxx0_FREQ0, pRfSettings->FREQ0);
tmav123 0:9df942ea84f4 179 WriteReg(CCxxx0_MDMCFG4, pRfSettings->MDMCFG4);
tmav123 0:9df942ea84f4 180 WriteReg(CCxxx0_MDMCFG3, pRfSettings->MDMCFG3);
tmav123 0:9df942ea84f4 181 WriteReg(CCxxx0_MDMCFG2, pRfSettings->MDMCFG2);
tmav123 0:9df942ea84f4 182 WriteReg(CCxxx0_MDMCFG1, pRfSettings->MDMCFG1);
tmav123 0:9df942ea84f4 183 WriteReg(CCxxx0_MDMCFG0, pRfSettings->MDMCFG0);
tmav123 0:9df942ea84f4 184 WriteReg(CCxxx0_CHANNR, pRfSettings->CHANNR);
tmav123 0:9df942ea84f4 185 WriteReg(CCxxx0_DEVIATN, pRfSettings->DEVIATN);
tmav123 0:9df942ea84f4 186 WriteReg(CCxxx0_FREND1, pRfSettings->FREND1);
tmav123 0:9df942ea84f4 187 WriteReg(CCxxx0_FREND0, pRfSettings->FREND0);
tmav123 0:9df942ea84f4 188 WriteReg(CCxxx0_MCSM0 , pRfSettings->MCSM0 );
tmav123 0:9df942ea84f4 189 WriteReg(CCxxx0_FOCCFG, pRfSettings->FOCCFG);
tmav123 0:9df942ea84f4 190 WriteReg(CCxxx0_BSCFG, pRfSettings->BSCFG);
tmav123 0:9df942ea84f4 191 WriteReg(CCxxx0_AGCCTRL2, pRfSettings->AGCCTRL2);
tmav123 0:9df942ea84f4 192 WriteReg(CCxxx0_AGCCTRL1, pRfSettings->AGCCTRL1);
tmav123 0:9df942ea84f4 193 WriteReg(CCxxx0_AGCCTRL0, pRfSettings->AGCCTRL0);
tmav123 0:9df942ea84f4 194 WriteReg(CCxxx0_FSCAL3, pRfSettings->FSCAL3);
tmav123 0:9df942ea84f4 195 WriteReg(CCxxx0_FSCAL2, pRfSettings->FSCAL2);
tmav123 0:9df942ea84f4 196 WriteReg(CCxxx0_FSCAL1, pRfSettings->FSCAL1);
tmav123 0:9df942ea84f4 197 WriteReg(CCxxx0_FSCAL0, pRfSettings->FSCAL0);
tmav123 0:9df942ea84f4 198 WriteReg(CCxxx0_FSTEST, pRfSettings->FSTEST);
tmav123 0:9df942ea84f4 199 WriteReg(CCxxx0_TEST2, pRfSettings->TEST2);
tmav123 0:9df942ea84f4 200 WriteReg(CCxxx0_TEST1, pRfSettings->TEST1);
tmav123 0:9df942ea84f4 201 WriteReg(CCxxx0_TEST0, pRfSettings->TEST0);
tmav123 0:9df942ea84f4 202 WriteReg(CCxxx0_FIFOTHR, pRfSettings->FIFOTHR);
tmav123 0:9df942ea84f4 203 WriteReg(CCxxx0_IOCFG2, pRfSettings->IOCFG2);
tmav123 0:9df942ea84f4 204 WriteReg(CCxxx0_IOCFG0, pRfSettings->IOCFG0);
tmav123 0:9df942ea84f4 205 WriteReg(CCxxx0_PKTCTRL1, pRfSettings->PKTCTRL1);
tmav123 0:9df942ea84f4 206 WriteReg(CCxxx0_PKTCTRL0, pRfSettings->PKTCTRL0);
tmav123 0:9df942ea84f4 207 WriteReg(CCxxx0_ADDR, pRfSettings->ADDR);
tmav123 0:9df942ea84f4 208 WriteReg(CCxxx0_PKTLEN, pRfSettings->PKTLEN);
tmav123 0:9df942ea84f4 209 WriteReg(CCxxx0_MCSM1 , pRfSettings->MCSM1 );
tmav123 0:9df942ea84f4 210 RXMode();
tmav123 0:9df942ea84f4 211
tmav123 0:9df942ea84f4 212 }// WriteRfSettings
tmav123 0:9df942ea84f4 213 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 214 void CC1101::init(void)
tmav123 0:9df942ea84f4 215 {
tmav123 0:9df942ea84f4 216 WriteRfSettings(&rfSettings);
tmav123 0:9df942ea84f4 217 WriteReg(CCxxx0_PATABLE, paTable[0]);
tmav123 0:9df942ea84f4 218 }
tmav123 0:9df942ea84f4 219 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 220 // unsigned char ReadReg(unsigned char addr)
tmav123 0:9df942ea84f4 221 //
tmav123 0:9df942ea84f4 222 // DESCRIPTION:
tmav123 0:9df942ea84f4 223 // This function gets the value of a single specified CCxxx0 register.
tmav123 0:9df942ea84f4 224 //
tmav123 0:9df942ea84f4 225 // ARGUMENTS:
tmav123 0:9df942ea84f4 226 // unsigned char addr
tmav123 0:9df942ea84f4 227 // Address of the CCxxx0 register to be accessed.
tmav123 0:9df942ea84f4 228 //
tmav123 0:9df942ea84f4 229 // RETURN VALUE:
tmav123 0:9df942ea84f4 230 // unsigned char
tmav123 0:9df942ea84f4 231 // Value of the accessed CCxxx0 register.
tmav123 0:9df942ea84f4 232 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 233 unsigned char CC1101::ReadReg(unsigned char addr)
tmav123 0:9df942ea84f4 234 {
tmav123 0:9df942ea84f4 235 unsigned char x;
tmav123 0:9df942ea84f4 236 wait(0.000005);
tmav123 0:9df942ea84f4 237 _csn = 0;
tmav123 0:9df942ea84f4 238 wait(0.000002);
tmav123 0:9df942ea84f4 239 while (_RDmiso);
tmav123 0:9df942ea84f4 240 _spi.write(addr | READ_SINGLE);
tmav123 0:9df942ea84f4 241 x = _spi.write(0);
tmav123 0:9df942ea84f4 242 wait(0.000002);
tmav123 0:9df942ea84f4 243 _csn = 1;
tmav123 0:9df942ea84f4 244 return x;
tmav123 0:9df942ea84f4 245 }// ReadReg
tmav123 0:9df942ea84f4 246 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 247 // void ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
tmav123 0:9df942ea84f4 248 //
tmav123 0:9df942ea84f4 249 // DESCRIPTION:
tmav123 0:9df942ea84f4 250 // This function reads multiple CCxxx0 register, using SPI burst access.
tmav123 0:9df942ea84f4 251 //
tmav123 0:9df942ea84f4 252 // ARGUMENTS:
tmav123 0:9df942ea84f4 253 // unsigned char addr
tmav123 0:9df942ea84f4 254 // Address of the first CCxxx0 register to be accessed.
tmav123 0:9df942ea84f4 255 // unsigned char *buffer
tmav123 0:9df942ea84f4 256 // Pointer to a byte array which stores the values read from a
tmav123 0:9df942ea84f4 257 // corresponding range of CCxxx0 registers.
tmav123 0:9df942ea84f4 258 // unsigned char count
tmav123 0:9df942ea84f4 259 // Number of bytes to be read from the subsequent CCxxx0 registers.
tmav123 0:9df942ea84f4 260 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 261 void CC1101::ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
tmav123 0:9df942ea84f4 262 {
tmav123 0:9df942ea84f4 263 unsigned char i;
tmav123 0:9df942ea84f4 264 wait(0.000005);
tmav123 0:9df942ea84f4 265 _csn = 0;
tmav123 0:9df942ea84f4 266 wait(0.000002);
tmav123 0:9df942ea84f4 267 while (_RDmiso);
tmav123 0:9df942ea84f4 268 _spi.write(addr | READ_BURST);
tmav123 0:9df942ea84f4 269 for (i = 0; i < count; i++)
tmav123 0:9df942ea84f4 270 {
tmav123 0:9df942ea84f4 271 buffer[i] = _spi.write(0);
tmav123 0:9df942ea84f4 272 }
tmav123 0:9df942ea84f4 273 wait(0.000002);
tmav123 0:9df942ea84f4 274 _csn = 1;
tmav123 0:9df942ea84f4 275 }// ReadBurstReg
tmav123 0:9df942ea84f4 276 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 277 // void WriteReg(unsigned char addr, unsigned char value)
tmav123 0:9df942ea84f4 278 //
tmav123 0:9df942ea84f4 279 // DESCRIPTION:
tmav123 0:9df942ea84f4 280 // Function for writing to a single CCxxx0 register
tmav123 0:9df942ea84f4 281 //
tmav123 0:9df942ea84f4 282 // ARGUMENTS:
tmav123 0:9df942ea84f4 283 // unsigned char addr
tmav123 0:9df942ea84f4 284 // Address of a specific CCxxx0 register to accessed.
tmav123 0:9df942ea84f4 285 // unsigned char value
tmav123 0:9df942ea84f4 286 // Value to be written to the specified CCxxx0 register.
tmav123 0:9df942ea84f4 287 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 288 void CC1101::WriteReg(unsigned char addr, unsigned char value)
tmav123 0:9df942ea84f4 289 {
tmav123 0:9df942ea84f4 290 wait(0.000005);
tmav123 0:9df942ea84f4 291 _csn = 0;
tmav123 0:9df942ea84f4 292 wait(0.000002);
tmav123 0:9df942ea84f4 293 while (_RDmiso);
tmav123 0:9df942ea84f4 294 _spi.write(addr);
tmav123 0:9df942ea84f4 295 _spi.write(value);
tmav123 0:9df942ea84f4 296 wait(0.000002);
tmav123 0:9df942ea84f4 297 _csn = 1;
tmav123 0:9df942ea84f4 298 }// WriteReg
tmav123 0:9df942ea84f4 299 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 300 // void WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
tmav123 0:9df942ea84f4 301 //
tmav123 0:9df942ea84f4 302 // DESCRIPTION:
tmav123 0:9df942ea84f4 303 // This function writes to multiple CCxxx0 register, using SPI burst access.
tmav123 0:9df942ea84f4 304 //
tmav123 0:9df942ea84f4 305 // ARGUMENTS:
tmav123 0:9df942ea84f4 306 // unsigned char addr
tmav123 0:9df942ea84f4 307 // Address of the first CCxxx0 register to be accessed.
tmav123 0:9df942ea84f4 308 // unsigned char *buffer
tmav123 0:9df942ea84f4 309 // Array of bytes to be written into a corresponding range of
tmav123 0:9df942ea84f4 310 // CCxx00 registers, starting by the address specified in _addr_.
tmav123 0:9df942ea84f4 311 // unsigned char count
tmav123 0:9df942ea84f4 312 // Number of bytes to be written to the subsequent CCxxx0 registers.
tmav123 0:9df942ea84f4 313 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 314 void CC1101::WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count)
tmav123 0:9df942ea84f4 315 {
tmav123 0:9df942ea84f4 316 unsigned char i;
tmav123 0:9df942ea84f4 317 wait(0.000005);
tmav123 0:9df942ea84f4 318 _csn = 0;
tmav123 0:9df942ea84f4 319 wait(0.000002);
tmav123 0:9df942ea84f4 320 while (_RDmiso);
tmav123 0:9df942ea84f4 321 _spi.write(addr | WRITE_BURST);
tmav123 0:9df942ea84f4 322 for (i = 0; i < count; i++)
tmav123 0:9df942ea84f4 323 {
tmav123 0:9df942ea84f4 324 _spi.write(buffer[i]);
tmav123 0:9df942ea84f4 325 }
tmav123 0:9df942ea84f4 326 wait(0.000002);
tmav123 0:9df942ea84f4 327 _csn = 1;
tmav123 0:9df942ea84f4 328 }// WriteBurstReg
tmav123 0:9df942ea84f4 329 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 330 unsigned char CC1101::RdRSSI(void)
tmav123 0:9df942ea84f4 331 {
tmav123 0:9df942ea84f4 332 unsigned char crssi;
tmav123 0:9df942ea84f4 333
tmav123 0:9df942ea84f4 334
tmav123 0:9df942ea84f4 335 if (rssi >= 128)
tmav123 0:9df942ea84f4 336 {
tmav123 0:9df942ea84f4 337 crssi = 255 - rssi;
tmav123 0:9df942ea84f4 338 crssi /= 2;
tmav123 0:9df942ea84f4 339 crssi += 74;
tmav123 0:9df942ea84f4 340 }
tmav123 0:9df942ea84f4 341 else
tmav123 0:9df942ea84f4 342 {
tmav123 0:9df942ea84f4 343 crssi = rssi/2;
tmav123 0:9df942ea84f4 344 crssi += 74;
tmav123 0:9df942ea84f4 345 }
tmav123 0:9df942ea84f4 346 return crssi;
tmav123 0:9df942ea84f4 347 }
tmav123 0:9df942ea84f4 348 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 349 unsigned char CC1101::RdLQI(void)
tmav123 0:9df942ea84f4 350 {
tmav123 0:9df942ea84f4 351 unsigned char clqi;
tmav123 0:9df942ea84f4 352 clqi = 0x3F - (lqi & 0x3F);
tmav123 0:9df942ea84f4 353
tmav123 0:9df942ea84f4 354 return clqi;
tmav123 0:9df942ea84f4 355 }
tmav123 0:9df942ea84f4 356 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 357 unsigned char CC1101::RxFifoEmpty(void)
tmav123 0:9df942ea84f4 358 {
tmav123 0:9df942ea84f4 359 unsigned char RxFifoStatus;
tmav123 0:9df942ea84f4 360
tmav123 0:9df942ea84f4 361 Strobe(CCxxx0_SRX);
tmav123 0:9df942ea84f4 362 RxFifoStatus = ReadStatus(CCxxx0_RXBYTES);
tmav123 0:9df942ea84f4 363
tmav123 0:9df942ea84f4 364 if (RxFifoStatus & 0x80) // check for RXFIFO overflow
tmav123 0:9df942ea84f4 365 {
tmav123 0:9df942ea84f4 366 // Make sure that the radio is in IDLE state before flushing the FIFO
tmav123 0:9df942ea84f4 367 // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
tmav123 0:9df942ea84f4 368 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 369
tmav123 0:9df942ea84f4 370 // Flush RX FIFO
tmav123 0:9df942ea84f4 371 Strobe(CCxxx0_SFRX);
tmav123 0:9df942ea84f4 372 }
tmav123 0:9df942ea84f4 373 if (RxFifoStatus & ~0x80)
tmav123 0:9df942ea84f4 374 {
tmav123 0:9df942ea84f4 375 return 0;
tmav123 0:9df942ea84f4 376 }
tmav123 0:9df942ea84f4 377 else
tmav123 0:9df942ea84f4 378 return 1;
tmav123 0:9df942ea84f4 379 }
tmav123 0:9df942ea84f4 380 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 381 //-------------------------------------------------------------------------------------------------------
tmav123 0:9df942ea84f4 382 // BOOL ReceivePacket(unsigned char *rxBuffer, unsigned char *length)
tmav123 0:9df942ea84f4 383 //
tmav123 0:9df942ea84f4 384 // DESCRIPTION:
tmav123 0:9df942ea84f4 385 // This function can be used to receive a packet of variable packet length (first byte in the packet
tmav123 0:9df942ea84f4 386 // must be the length byte). The packet length should not exceed the RX FIFO size.
tmav123 0:9df942ea84f4 387 //
tmav123 0:9df942ea84f4 388 // ARGUMENTS:
tmav123 0:9df942ea84f4 389 // unsigned char *rxBuffer
tmav123 0:9df942ea84f4 390 // Pointer to the buffer where the incoming data should be stored
tmav123 0:9df942ea84f4 391 // unsigned char *length
tmav123 0:9df942ea84f4 392 // Pointer to a variable containing the size of the buffer where the incoming data should be
tmav123 0:9df942ea84f4 393 // stored. After this function returns, that variable holds the packet length.
tmav123 0:9df942ea84f4 394 //
tmav123 0:9df942ea84f4 395 // RETURN VALUE:
tmav123 0:9df942ea84f4 396 // BOOL
tmav123 0:9df942ea84f4 397 // 1: CRC OK
tmav123 0:9df942ea84f4 398 // 0: CRC NOT OK (or no packet was put in the RX FIFO due to filtering)
tmav123 0:9df942ea84f4 399 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 400
tmav123 0:9df942ea84f4 401 int CC1101::ReceivePacket(unsigned char *rxBuffer, unsigned char *length)
tmav123 0:9df942ea84f4 402 {
tmav123 0:9df942ea84f4 403 unsigned char status[2];
tmav123 0:9df942ea84f4 404 unsigned char packetLength;
tmav123 0:9df942ea84f4 405
tmav123 0:9df942ea84f4 406 packetLength = ReadStatus(CCxxx0_RXBYTES);
tmav123 0:9df942ea84f4 407 if (packetLength & BYTES_IN_RXFIFO)
tmav123 0:9df942ea84f4 408 {
tmav123 0:9df942ea84f4 409 // Read length byte
tmav123 0:9df942ea84f4 410 packetLength = ReadReg(CCxxx0_RXFIFO);
tmav123 0:9df942ea84f4 411
tmav123 0:9df942ea84f4 412 // Read data from RX FIFO and store in rxBuffer
tmav123 0:9df942ea84f4 413 if (packetLength <= *length)
tmav123 0:9df942ea84f4 414 {
tmav123 0:9df942ea84f4 415 ReadBurstReg(CCxxx0_RXFIFO, rxBuffer, packetLength);
tmav123 0:9df942ea84f4 416 *length = packetLength;
tmav123 0:9df942ea84f4 417
tmav123 0:9df942ea84f4 418 // Read the 2 appended status bytes (status[0] = RSSI, status[1] = LQI)
tmav123 0:9df942ea84f4 419 ReadBurstReg(CCxxx0_RXFIFO, status, 2);
tmav123 0:9df942ea84f4 420
tmav123 0:9df942ea84f4 421 rssi = status[RSSI];
tmav123 0:9df942ea84f4 422 lqi = status[LQI];
tmav123 0:9df942ea84f4 423 // MSB of LQI is the CRC_OK bit
tmav123 0:9df942ea84f4 424 // return (status[LQI] & CRC_OK);
tmav123 0:9df942ea84f4 425 if(status[LQI] & CRC_OK)
tmav123 0:9df942ea84f4 426 {
tmav123 0:9df942ea84f4 427 return 1;
tmav123 0:9df942ea84f4 428 }
tmav123 0:9df942ea84f4 429 }
tmav123 0:9df942ea84f4 430 else
tmav123 0:9df942ea84f4 431 {
tmav123 0:9df942ea84f4 432 *length = packetLength;
tmav123 0:9df942ea84f4 433
tmav123 0:9df942ea84f4 434 // Make sure that the radio is in IDLE state before flushing the FIFO
tmav123 0:9df942ea84f4 435 // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
tmav123 0:9df942ea84f4 436 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 437
tmav123 0:9df942ea84f4 438 // Flush RX FIFO
tmav123 0:9df942ea84f4 439 Strobe(CCxxx0_SFRX);
tmav123 0:9df942ea84f4 440 return 0;
tmav123 0:9df942ea84f4 441 }
tmav123 0:9df942ea84f4 442 } else
tmav123 0:9df942ea84f4 443 return 0;
tmav123 0:9df942ea84f4 444 return 0;
tmav123 0:9df942ea84f4 445 }// halRfReceivePacket
tmav123 0:9df942ea84f4 446 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 447 unsigned char CC1101::TxFifoEmpty(void)
tmav123 0:9df942ea84f4 448 {
tmav123 0:9df942ea84f4 449 unsigned char TxFifoStatus;
tmav123 0:9df942ea84f4 450
tmav123 0:9df942ea84f4 451 Strobe(CCxxx0_STX);
tmav123 0:9df942ea84f4 452 TxFifoStatus = ReadStatus(CCxxx0_TXBYTES);
tmav123 0:9df942ea84f4 453
tmav123 0:9df942ea84f4 454 if (TxFifoStatus & 0x80) // check for TXFIFO underflow
tmav123 0:9df942ea84f4 455 {
tmav123 0:9df942ea84f4 456 // Make sure that the radio is in IDLE state before flushing the FIFO
tmav123 0:9df942ea84f4 457 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 458
tmav123 0:9df942ea84f4 459 // Flush TX FIFO
tmav123 0:9df942ea84f4 460 Strobe(CCxxx0_SFTX);
tmav123 0:9df942ea84f4 461 }
tmav123 0:9df942ea84f4 462 if (TxFifoStatus & ~0x80)
tmav123 0:9df942ea84f4 463 {
tmav123 0:9df942ea84f4 464 return 0;
tmav123 0:9df942ea84f4 465 }
tmav123 0:9df942ea84f4 466 else
tmav123 0:9df942ea84f4 467 return 1;
tmav123 0:9df942ea84f4 468 }
tmav123 0:9df942ea84f4 469 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 470 // void halRfSendPacket(unsigned char *txBuffer, unsigned char size)
tmav123 0:9df942ea84f4 471 //
tmav123 0:9df942ea84f4 472 // DESCRIPTION:
tmav123 0:9df942ea84f4 473 // This function can be used to transmit a packet with packet length up to 63 bytes.
tmav123 0:9df942ea84f4 474 //
tmav123 0:9df942ea84f4 475 // ARGUMENTS:
tmav123 0:9df942ea84f4 476 // unsigned char *txBuffer
tmav123 0:9df942ea84f4 477 // Pointer to a buffer containing the data that are going to be transmitted
tmav123 0:9df942ea84f4 478 //
tmav123 0:9df942ea84f4 479 // unsigned char size
tmav123 0:9df942ea84f4 480 // The size of the txBuffer
tmav123 0:9df942ea84f4 481 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 482 void CC1101::SendPacket(unsigned char *txBuffer, unsigned char size)
tmav123 0:9df942ea84f4 483 {
tmav123 0:9df942ea84f4 484 unsigned char i;
tmav123 0:9df942ea84f4 485
tmav123 0:9df942ea84f4 486 for (i = size; i > 0; i--)
tmav123 0:9df942ea84f4 487 txBuffer[i] = txBuffer[i-1];
tmav123 0:9df942ea84f4 488 txBuffer[0] = size;
tmav123 0:9df942ea84f4 489
tmav123 0:9df942ea84f4 490 WriteBurstReg(CCxxx0_TXFIFO, txBuffer, size+1);
tmav123 0:9df942ea84f4 491 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 492 Strobe(CCxxx0_STX);
tmav123 0:9df942ea84f4 493 }// halRfSendPacket
tmav123 0:9df942ea84f4 494 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 495 unsigned char CC1101::ReadChipStatusTX(void)
tmav123 0:9df942ea84f4 496 {
tmav123 0:9df942ea84f4 497 unsigned char x;
tmav123 0:9df942ea84f4 498
tmav123 0:9df942ea84f4 499 x = Strobe(CCxxx0_SNOP);
tmav123 0:9df942ea84f4 500 return x;
tmav123 0:9df942ea84f4 501 }
tmav123 0:9df942ea84f4 502 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 503 unsigned char CC1101::ReadChipStatusRX(void)
tmav123 0:9df942ea84f4 504 {
tmav123 0:9df942ea84f4 505 unsigned char x;
tmav123 0:9df942ea84f4 506 wait(0.000005);
tmav123 0:9df942ea84f4 507 _csn = 0;
tmav123 0:9df942ea84f4 508 wait(0.000002);
tmav123 0:9df942ea84f4 509 while (_RDmiso);
tmav123 0:9df942ea84f4 510 x = _spi.write(CCxxx0_PARTNUM | READ_BURST);
tmav123 0:9df942ea84f4 511 wait(0.000002);
tmav123 0:9df942ea84f4 512 _csn = 1;
tmav123 0:9df942ea84f4 513 return x;
tmav123 0:9df942ea84f4 514 }
tmav123 0:9df942ea84f4 515 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 516 void CC1101::FlushRX(void)
tmav123 0:9df942ea84f4 517 {
tmav123 0:9df942ea84f4 518 // Make sure that the radio is in IDLE state before flushing the FIFO
tmav123 0:9df942ea84f4 519 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 520
tmav123 0:9df942ea84f4 521 // Flush RX FIFO
tmav123 0:9df942ea84f4 522 Strobe(CCxxx0_SFRX);
tmav123 0:9df942ea84f4 523 }
tmav123 0:9df942ea84f4 524 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 525 void CC1101::FlushTX(void)
tmav123 0:9df942ea84f4 526 {
tmav123 0:9df942ea84f4 527 // Make sure that the radio is in IDLE state before flushing the FIFO
tmav123 0:9df942ea84f4 528 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 529
tmav123 0:9df942ea84f4 530 // Flush TX FIFO
tmav123 0:9df942ea84f4 531 Strobe(CCxxx0_SFTX);
tmav123 0:9df942ea84f4 532 }
tmav123 0:9df942ea84f4 533 ///////////////////////////////////////////////////////////////////////////////////////
tmav123 0:9df942ea84f4 534 void CC1101::RXMode(void)
tmav123 0:9df942ea84f4 535 {
tmav123 0:9df942ea84f4 536 Strobe(CCxxx0_SIDLE);
tmav123 0:9df942ea84f4 537 Strobe(CCxxx0_SRX);
tmav123 0:9df942ea84f4 538 }
tmav123 0:9df942ea84f4 539 ///////////////////////////////////////////////////////////////////////////////////////