Alan Ffrench / Mbed 2 deprecated Experiment_2_5

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Dependencies:   mbed

mbed-rtos/rtx/rt_HAL_CM.h@0:52468b19aa21, 2020-07-29 (annotated)

Committer:
alanffrench
Date:
Wed Jul 29 18:51:38 2020 +0000
Revision:
0:52468b19aa21
Threads

Who changed what in which revision?

UserRevisionLine numberNew contents of line
alanffrench 0:52468b19aa21 1 /*----------------------------------------------------------------------------
alanffrench 0:52468b19aa21 2 * RL-ARM - RTX
alanffrench 0:52468b19aa21 3 *----------------------------------------------------------------------------
alanffrench 0:52468b19aa21 4 * Name: RT_HAL_CM.H
alanffrench 0:52468b19aa21 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
alanffrench 0:52468b19aa21 6 * Rev.: V4.60
alanffrench 0:52468b19aa21 7 *----------------------------------------------------------------------------
alanffrench 0:52468b19aa21 8 *
alanffrench 0:52468b19aa21 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
alanffrench 0:52468b19aa21 10 * All rights reserved.
alanffrench 0:52468b19aa21 11 * Redistribution and use in source and binary forms, with or without
alanffrench 0:52468b19aa21 12 * modification, are permitted provided that the following conditions are met:
alanffrench 0:52468b19aa21 13 * - Redistributions of source code must retain the above copyright
alanffrench 0:52468b19aa21 14 * notice, this list of conditions and the following disclaimer.
alanffrench 0:52468b19aa21 15 * - Redistributions in binary form must reproduce the above copyright
alanffrench 0:52468b19aa21 16 * notice, this list of conditions and the following disclaimer in the
alanffrench 0:52468b19aa21 17 * documentation and/or other materials provided with the distribution.
alanffrench 0:52468b19aa21 18 * - Neither the name of ARM nor the names of its contributors may be used
alanffrench 0:52468b19aa21 19 * to endorse or promote products derived from this software without
alanffrench 0:52468b19aa21 20 * specific prior written permission.
alanffrench 0:52468b19aa21 21 *
alanffrench 0:52468b19aa21 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
alanffrench 0:52468b19aa21 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
alanffrench 0:52468b19aa21 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
alanffrench 0:52468b19aa21 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
alanffrench 0:52468b19aa21 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
alanffrench 0:52468b19aa21 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
alanffrench 0:52468b19aa21 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
alanffrench 0:52468b19aa21 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
alanffrench 0:52468b19aa21 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
alanffrench 0:52468b19aa21 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
alanffrench 0:52468b19aa21 32 * POSSIBILITY OF SUCH DAMAGE.
alanffrench 0:52468b19aa21 33 *---------------------------------------------------------------------------*/
alanffrench 0:52468b19aa21 34
alanffrench 0:52468b19aa21 35 /* Definitions */
alanffrench 0:52468b19aa21 36 #define INITIAL_xPSR 0x01000000
alanffrench 0:52468b19aa21 37 #define DEMCR_TRCENA 0x01000000
alanffrench 0:52468b19aa21 38 #define ITM_ITMENA 0x00000001
alanffrench 0:52468b19aa21 39 #define MAGIC_WORD 0xE25A2EA5
alanffrench 0:52468b19aa21 40
alanffrench 0:52468b19aa21 41 #if defined (__CC_ARM) /* ARM Compiler */
alanffrench 0:52468b19aa21 42
alanffrench 0:52468b19aa21 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
alanffrench 0:52468b19aa21 44 #define __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 45 #else
alanffrench 0:52468b19aa21 46 #undef __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 47 #endif
alanffrench 0:52468b19aa21 48
alanffrench 0:52468b19aa21 49 #elif defined (__GNUC__) /* GNU Compiler */
alanffrench 0:52468b19aa21 50
alanffrench 0:52468b19aa21 51 #undef __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 52
alanffrench 0:52468b19aa21 53 #if defined (__CORTEX_M0)
alanffrench 0:52468b19aa21 54 #define __TARGET_ARCH_6S_M 1
alanffrench 0:52468b19aa21 55 #else
alanffrench 0:52468b19aa21 56 #define __TARGET_ARCH_6S_M 0
alanffrench 0:52468b19aa21 57 #endif
alanffrench 0:52468b19aa21 58
alanffrench 0:52468b19aa21 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
alanffrench 0:52468b19aa21 60 #define __TARGET_FPU_VFP 1
alanffrench 0:52468b19aa21 61 #else
alanffrench 0:52468b19aa21 62 #define __TARGET_FPU_VFP 0
alanffrench 0:52468b19aa21 63 #endif
alanffrench 0:52468b19aa21 64
alanffrench 0:52468b19aa21 65 #define __inline inline
alanffrench 0:52468b19aa21 66 #define __weak __attribute__((weak))
alanffrench 0:52468b19aa21 67
alanffrench 0:52468b19aa21 68 #ifndef __CMSIS_GENERIC
alanffrench 0:52468b19aa21 69
alanffrench 0:52468b19aa21 70 __attribute__((always_inline)) static inline void __enable_irq(void)
alanffrench 0:52468b19aa21 71 {
alanffrench 0:52468b19aa21 72 __asm volatile ("cpsie i");
alanffrench 0:52468b19aa21 73 }
alanffrench 0:52468b19aa21 74
alanffrench 0:52468b19aa21 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
alanffrench 0:52468b19aa21 76 {
alanffrench 0:52468b19aa21 77 U32 result;
alanffrench 0:52468b19aa21 78
alanffrench 0:52468b19aa21 79 __asm volatile ("mrs %0, primask" : "=r" (result));
alanffrench 0:52468b19aa21 80 __asm volatile ("cpsid i");
alanffrench 0:52468b19aa21 81 return(result & 1);
alanffrench 0:52468b19aa21 82 }
alanffrench 0:52468b19aa21 83
alanffrench 0:52468b19aa21 84 #endif
alanffrench 0:52468b19aa21 85
alanffrench 0:52468b19aa21 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
alanffrench 0:52468b19aa21 87 {
alanffrench 0:52468b19aa21 88 U8 result;
alanffrench 0:52468b19aa21 89
alanffrench 0:52468b19aa21 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
alanffrench 0:52468b19aa21 91 return(result);
alanffrench 0:52468b19aa21 92 }
alanffrench 0:52468b19aa21 93
alanffrench 0:52468b19aa21 94 #elif defined (__ICCARM__) /* IAR Compiler */
alanffrench 0:52468b19aa21 95
alanffrench 0:52468b19aa21 96 #undef __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 97
alanffrench 0:52468b19aa21 98 #if (__CORE__ == __ARM6M__)
alanffrench 0:52468b19aa21 99 #define __TARGET_ARCH_6S_M 1
alanffrench 0:52468b19aa21 100 #else
alanffrench 0:52468b19aa21 101 #define __TARGET_ARCH_6S_M 0
alanffrench 0:52468b19aa21 102 #endif
alanffrench 0:52468b19aa21 103
alanffrench 0:52468b19aa21 104 #if defined __ARMVFP__
alanffrench 0:52468b19aa21 105 #define __TARGET_FPU_VFP 1
alanffrench 0:52468b19aa21 106 #else
alanffrench 0:52468b19aa21 107 #define __TARGET_FPU_VFP 0
alanffrench 0:52468b19aa21 108 #endif
alanffrench 0:52468b19aa21 109
alanffrench 0:52468b19aa21 110 #define __inline inline
alanffrench 0:52468b19aa21 111
alanffrench 0:52468b19aa21 112 #ifndef __CMSIS_GENERIC
alanffrench 0:52468b19aa21 113
alanffrench 0:52468b19aa21 114 static inline void __enable_irq(void)
alanffrench 0:52468b19aa21 115 {
alanffrench 0:52468b19aa21 116 __asm volatile ("cpsie i");
alanffrench 0:52468b19aa21 117 }
alanffrench 0:52468b19aa21 118
alanffrench 0:52468b19aa21 119 static inline U32 __disable_irq(void)
alanffrench 0:52468b19aa21 120 {
alanffrench 0:52468b19aa21 121 U32 result;
alanffrench 0:52468b19aa21 122
alanffrench 0:52468b19aa21 123 __asm volatile ("mrs %0, primask" : "=r" (result));
alanffrench 0:52468b19aa21 124 __asm volatile ("cpsid i");
alanffrench 0:52468b19aa21 125 return(result & 1);
alanffrench 0:52468b19aa21 126 }
alanffrench 0:52468b19aa21 127
alanffrench 0:52468b19aa21 128 #endif
alanffrench 0:52468b19aa21 129
alanffrench 0:52468b19aa21 130 static inline U8 __clz(U32 value)
alanffrench 0:52468b19aa21 131 {
alanffrench 0:52468b19aa21 132 U8 result;
alanffrench 0:52468b19aa21 133
alanffrench 0:52468b19aa21 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
alanffrench 0:52468b19aa21 135 return(result);
alanffrench 0:52468b19aa21 136 }
alanffrench 0:52468b19aa21 137
alanffrench 0:52468b19aa21 138 #endif
alanffrench 0:52468b19aa21 139
alanffrench 0:52468b19aa21 140 /* NVIC registers */
alanffrench 0:52468b19aa21 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
alanffrench 0:52468b19aa21 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
alanffrench 0:52468b19aa21 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
alanffrench 0:52468b19aa21 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
alanffrench 0:52468b19aa21 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
alanffrench 0:52468b19aa21 146 #if (__TARGET_ARCH_6S_M)
alanffrench 0:52468b19aa21 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
alanffrench 0:52468b19aa21 148 #else
alanffrench 0:52468b19aa21 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
alanffrench 0:52468b19aa21 150 #endif
alanffrench 0:52468b19aa21 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
alanffrench 0:52468b19aa21 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
alanffrench 0:52468b19aa21 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
alanffrench 0:52468b19aa21 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
alanffrench 0:52468b19aa21 155
alanffrench 0:52468b19aa21 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
alanffrench 0:52468b19aa21 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
alanffrench 0:52468b19aa21 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
alanffrench 0:52468b19aa21 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
alanffrench 0:52468b19aa21 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
alanffrench 0:52468b19aa21 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
alanffrench 0:52468b19aa21 162
alanffrench 0:52468b19aa21 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
alanffrench 0:52468b19aa21 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
alanffrench 0:52468b19aa21 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
alanffrench 0:52468b19aa21 166 #if (__TARGET_ARCH_6S_M)
alanffrench 0:52468b19aa21 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
alanffrench 0:52468b19aa21 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
alanffrench 0:52468b19aa21 169 #else
alanffrench 0:52468b19aa21 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
alanffrench 0:52468b19aa21 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
alanffrench 0:52468b19aa21 172 #endif
alanffrench 0:52468b19aa21 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
alanffrench 0:52468b19aa21 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
alanffrench 0:52468b19aa21 175
alanffrench 0:52468b19aa21 176 /* Core Debug registers */
alanffrench 0:52468b19aa21 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
alanffrench 0:52468b19aa21 178
alanffrench 0:52468b19aa21 179 /* ITM registers */
alanffrench 0:52468b19aa21 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
alanffrench 0:52468b19aa21 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
alanffrench 0:52468b19aa21 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
alanffrench 0:52468b19aa21 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
alanffrench 0:52468b19aa21 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
alanffrench 0:52468b19aa21 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
alanffrench 0:52468b19aa21 186
alanffrench 0:52468b19aa21 187 /* Variables */
alanffrench 0:52468b19aa21 188 extern BIT dbg_msg;
alanffrench 0:52468b19aa21 189
alanffrench 0:52468b19aa21 190 /* Functions */
alanffrench 0:52468b19aa21 191 #ifdef __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
alanffrench 0:52468b19aa21 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
alanffrench 0:52468b19aa21 194 #else
alanffrench 0:52468b19aa21 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
alanffrench 0:52468b19aa21 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
alanffrench 0:52468b19aa21 197 #endif
alanffrench 0:52468b19aa21 198
alanffrench 0:52468b19aa21 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
alanffrench 0:52468b19aa21 200 U32 cnt,c2;
alanffrench 0:52468b19aa21 201 #ifdef __USE_EXCLUSIVE_ACCESS
alanffrench 0:52468b19aa21 202 do {
alanffrench 0:52468b19aa21 203 if ((cnt = __ldrex(count)) == size) {
alanffrench 0:52468b19aa21 204 __clrex();
alanffrench 0:52468b19aa21 205 return (cnt); }
alanffrench 0:52468b19aa21 206 } while (__strex(cnt+1, count));
alanffrench 0:52468b19aa21 207 do {
alanffrench 0:52468b19aa21 208 c2 = (cnt = __ldrex(first)) + 1;
alanffrench 0:52468b19aa21 209 if (c2 == size) c2 = 0;
alanffrench 0:52468b19aa21 210 } while (__strex(c2, first));
alanffrench 0:52468b19aa21 211 #else
alanffrench 0:52468b19aa21 212 __disable_irq();
alanffrench 0:52468b19aa21 213 if ((cnt = *count) < size) {
alanffrench 0:52468b19aa21 214 *count = cnt+1;
alanffrench 0:52468b19aa21 215 c2 = (cnt = *first) + 1;
alanffrench 0:52468b19aa21 216 if (c2 == size) c2 = 0;
alanffrench 0:52468b19aa21 217 *first = c2;
alanffrench 0:52468b19aa21 218 }
alanffrench 0:52468b19aa21 219 __enable_irq ();
alanffrench 0:52468b19aa21 220 #endif
alanffrench 0:52468b19aa21 221 return (cnt);
alanffrench 0:52468b19aa21 222 }
alanffrench 0:52468b19aa21 223
alanffrench 0:52468b19aa21 224 __inline static void rt_systick_init (void) {
alanffrench 0:52468b19aa21 225 NVIC_ST_RELOAD = os_trv;
alanffrench 0:52468b19aa21 226 NVIC_ST_CURRENT = 0;
alanffrench 0:52468b19aa21 227 NVIC_ST_CTRL = 0x0007;
alanffrench 0:52468b19aa21 228 NVIC_SYS_PRI3 |= 0xFF000000;
alanffrench 0:52468b19aa21 229 }
alanffrench 0:52468b19aa21 230
alanffrench 0:52468b19aa21 231 __inline static void rt_svc_init (void) {
alanffrench 0:52468b19aa21 232 #if !(__TARGET_ARCH_6S_M)
alanffrench 0:52468b19aa21 233 int sh,prigroup;
alanffrench 0:52468b19aa21 234 #endif
alanffrench 0:52468b19aa21 235 NVIC_SYS_PRI3 |= 0x00FF0000;
alanffrench 0:52468b19aa21 236 #if (__TARGET_ARCH_6S_M)
alanffrench 0:52468b19aa21 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
alanffrench 0:52468b19aa21 238 #else
alanffrench 0:52468b19aa21 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
alanffrench 0:52468b19aa21 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
alanffrench 0:52468b19aa21 241 if (prigroup >= sh) {
alanffrench 0:52468b19aa21 242 sh = prigroup + 1;
alanffrench 0:52468b19aa21 243 }
alanffrench 0:52468b19aa21 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
alanffrench 0:52468b19aa21 245 #endif
alanffrench 0:52468b19aa21 246 }
alanffrench 0:52468b19aa21 247
alanffrench 0:52468b19aa21 248 extern void rt_set_PSP (U32 stack);
alanffrench 0:52468b19aa21 249 extern U32 rt_get_PSP (void);
alanffrench 0:52468b19aa21 250 extern void os_set_env (void);
alanffrench 0:52468b19aa21 251 extern void *_alloc_box (void *box_mem);
alanffrench 0:52468b19aa21 252 extern int _free_box (void *box_mem, void *box);
alanffrench 0:52468b19aa21 253
alanffrench 0:52468b19aa21 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
alanffrench 0:52468b19aa21 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
alanffrench 0:52468b19aa21 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
alanffrench 0:52468b19aa21 257
alanffrench 0:52468b19aa21 258 extern void dbg_init (void);
alanffrench 0:52468b19aa21 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
alanffrench 0:52468b19aa21 260 extern void dbg_task_switch (U32 task_id);
alanffrench 0:52468b19aa21 261
alanffrench 0:52468b19aa21 262 #ifdef DBG_MSG
alanffrench 0:52468b19aa21 263 #define DBG_INIT() dbg_init()
alanffrench 0:52468b19aa21 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
alanffrench 0:52468b19aa21 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
alanffrench 0:52468b19aa21 266 dbg_task_switch(task_id)
alanffrench 0:52468b19aa21 267 #else
alanffrench 0:52468b19aa21 268 #define DBG_INIT()
alanffrench 0:52468b19aa21 269 #define DBG_TASK_NOTIFY(p_tcb,create)
alanffrench 0:52468b19aa21 270 #define DBG_TASK_SWITCH(task_id)
alanffrench 0:52468b19aa21 271 #endif
alanffrench 0:52468b19aa21 272
alanffrench 0:52468b19aa21 273 /*----------------------------------------------------------------------------
alanffrench 0:52468b19aa21 274 * end of file
alanffrench 0:52468b19aa21 275 *---------------------------------------------------------------------------*/
alanffrench 0:52468b19aa21 276