Samira Afzal / pulga-lorawan-drv

testing hex for lorawan communication

SX1272/registers/sx1272Regs-LoRa.h@3:9e7d20163e7a, 2020-12-04 (annotated)

Committer:
afzalsamira
Date:
Fri Dec 04 18:33:07 2020 +0000
Revision:
3:9e7d20163e7a
Parent:
0:561d07a737bc 
testing hex;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
brunnobbco 0:561d07a737bc 1 /**
brunnobbco 0:561d07a737bc 2 / _____) _ | |
brunnobbco 0:561d07a737bc 3 ( (____ _____ ____ _| |_ _____ ____| |__
brunnobbco 0:561d07a737bc 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
brunnobbco 0:561d07a737bc 5 _____) ) ____| | | || |_| ____( (___| | | |
brunnobbco 0:561d07a737bc 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
brunnobbco 0:561d07a737bc 7 (C) 2015 Semtech
brunnobbco 0:561d07a737bc 8
brunnobbco 0:561d07a737bc 9 Description: SX1272 LoRa modem registers and bits definitions
brunnobbco 0:561d07a737bc 10
brunnobbco 0:561d07a737bc 11 License: Revised BSD License, see LICENSE.TXT file include in the project
brunnobbco 0:561d07a737bc 12
brunnobbco 0:561d07a737bc 13 Maintainer: Miguel Luis and Gregory Cristian
brunnobbco 0:561d07a737bc 14
brunnobbco 0:561d07a737bc 15 Copyright (c) 2017, Arm Limited and affiliates.
brunnobbco 0:561d07a737bc 16
brunnobbco 0:561d07a737bc 17 SPDX-License-Identifier: BSD-3-Clause
brunnobbco 0:561d07a737bc 18 */
brunnobbco 0:561d07a737bc 19 #ifndef __SX1272_REGS_LORA_H__
brunnobbco 0:561d07a737bc 20 #define __SX1272_REGS_LORA_H__
brunnobbco 0:561d07a737bc 21
brunnobbco 0:561d07a737bc 22 /*!
brunnobbco 0:561d07a737bc 23 * ============================================================================
brunnobbco 0:561d07a737bc 24 * SX1272 Internal registers Address
brunnobbco 0:561d07a737bc 25 * ============================================================================
brunnobbco 0:561d07a737bc 26 */
brunnobbco 0:561d07a737bc 27 #define REG_LR_FIFO 0x00
brunnobbco 0:561d07a737bc 28 // Common settings
brunnobbco 0:561d07a737bc 29 #define REG_LR_OPMODE 0x01
brunnobbco 0:561d07a737bc 30 #define REG_LR_FRFMSB 0x06
brunnobbco 0:561d07a737bc 31 #define REG_LR_FRFMID 0x07
brunnobbco 0:561d07a737bc 32 #define REG_LR_FRFLSB 0x08
brunnobbco 0:561d07a737bc 33 // Tx settings
brunnobbco 0:561d07a737bc 34 #define REG_LR_PACONFIG 0x09
brunnobbco 0:561d07a737bc 35 #define REG_LR_PARAMP 0x0A
brunnobbco 0:561d07a737bc 36 #define REG_LR_OCP 0x0B
brunnobbco 0:561d07a737bc 37 // Rx settings
brunnobbco 0:561d07a737bc 38 #define REG_LR_LNA 0x0C
brunnobbco 0:561d07a737bc 39 // LoRa registers
brunnobbco 0:561d07a737bc 40 #define REG_LR_FIFOADDRPTR 0x0D
brunnobbco 0:561d07a737bc 41 #define REG_LR_FIFOTXBASEADDR 0x0E
brunnobbco 0:561d07a737bc 42 #define REG_LR_FIFORXBASEADDR 0x0F
brunnobbco 0:561d07a737bc 43 #define REG_LR_FIFORXCURRENTADDR 0x10
brunnobbco 0:561d07a737bc 44 #define REG_LR_IRQFLAGSMASK 0x11
brunnobbco 0:561d07a737bc 45 #define REG_LR_IRQFLAGS 0x12
brunnobbco 0:561d07a737bc 46 #define REG_LR_RXNBBYTES 0x13
brunnobbco 0:561d07a737bc 47 #define REG_LR_RXHEADERCNTVALUEMSB 0x14
brunnobbco 0:561d07a737bc 48 #define REG_LR_RXHEADERCNTVALUELSB 0x15
brunnobbco 0:561d07a737bc 49 #define REG_LR_RXPACKETCNTVALUEMSB 0x16
brunnobbco 0:561d07a737bc 50 #define REG_LR_RXPACKETCNTVALUELSB 0x17
brunnobbco 0:561d07a737bc 51 #define REG_LR_MODEMSTAT 0x18
brunnobbco 0:561d07a737bc 52 #define REG_LR_PKTSNRVALUE 0x19
brunnobbco 0:561d07a737bc 53 #define REG_LR_PKTRSSIVALUE 0x1A
brunnobbco 0:561d07a737bc 54 #define REG_LR_RSSIVALUE 0x1B
brunnobbco 0:561d07a737bc 55 #define REG_LR_HOPCHANNEL 0x1C
brunnobbco 0:561d07a737bc 56 #define REG_LR_MODEMCONFIG1 0x1D
brunnobbco 0:561d07a737bc 57 #define REG_LR_MODEMCONFIG2 0x1E
brunnobbco 0:561d07a737bc 58 #define REG_LR_SYMBTIMEOUTLSB 0x1F
brunnobbco 0:561d07a737bc 59 #define REG_LR_PREAMBLEMSB 0x20
brunnobbco 0:561d07a737bc 60 #define REG_LR_PREAMBLELSB 0x21
brunnobbco 0:561d07a737bc 61 #define REG_LR_PAYLOADLENGTH 0x22
brunnobbco 0:561d07a737bc 62 #define REG_LR_PAYLOADMAXLENGTH 0x23
brunnobbco 0:561d07a737bc 63 #define REG_LR_HOPPERIOD 0x24
brunnobbco 0:561d07a737bc 64 #define REG_LR_FIFORXBYTEADDR 0x25
brunnobbco 0:561d07a737bc 65 #define REG_LR_FEIMSB 0x28
brunnobbco 0:561d07a737bc 66 #define REG_LR_FEIMID 0x29
brunnobbco 0:561d07a737bc 67 #define REG_LR_FEILSB 0x2A
brunnobbco 0:561d07a737bc 68 #define REG_LR_RSSIWIDEBAND 0x2C
brunnobbco 0:561d07a737bc 69 #define REG_LR_DETECTOPTIMIZE 0x31
brunnobbco 0:561d07a737bc 70 #define REG_LR_INVERTIQ 0x33
brunnobbco 0:561d07a737bc 71 #define REG_LR_DETECTIONTHRESHOLD 0x37
brunnobbco 0:561d07a737bc 72 #define REG_LR_SYNCWORD 0x39
brunnobbco 0:561d07a737bc 73 #define REG_LR_INVERTIQ2 0x3B
brunnobbco 0:561d07a737bc 74
brunnobbco 0:561d07a737bc 75 // end of documented register in datasheet
brunnobbco 0:561d07a737bc 76 // I/O settings
brunnobbco 0:561d07a737bc 77 #define REG_LR_DIOMAPPING1 0x40
brunnobbco 0:561d07a737bc 78 #define REG_LR_DIOMAPPING2 0x41
brunnobbco 0:561d07a737bc 79 // Version
brunnobbco 0:561d07a737bc 80 #define REG_LR_VERSION 0x42
brunnobbco 0:561d07a737bc 81 // Additional settings
brunnobbco 0:561d07a737bc 82 #define REG_LR_AGCREF 0x43
brunnobbco 0:561d07a737bc 83 #define REG_LR_AGCTHRESH1 0x44
brunnobbco 0:561d07a737bc 84 #define REG_LR_AGCTHRESH2 0x45
brunnobbco 0:561d07a737bc 85 #define REG_LR_AGCTHRESH3 0x46
brunnobbco 0:561d07a737bc 86 #define REG_LR_PLLHOP 0x4B
brunnobbco 0:561d07a737bc 87 #define REG_LR_TCXO 0x58
brunnobbco 0:561d07a737bc 88 #define REG_LR_PADAC 0x5A
brunnobbco 0:561d07a737bc 89 #define REG_LR_PLL 0x5C
brunnobbco 0:561d07a737bc 90 #define REG_LR_PLLLOWPN 0x5E
brunnobbco 0:561d07a737bc 91 #define REG_LR_FORMERTEMP 0x6C
brunnobbco 0:561d07a737bc 92
brunnobbco 0:561d07a737bc 93 /*!
brunnobbco 0:561d07a737bc 94 * ============================================================================
brunnobbco 0:561d07a737bc 95 * SX1272 LoRa bits control definition
brunnobbco 0:561d07a737bc 96 * ============================================================================
brunnobbco 0:561d07a737bc 97 */
brunnobbco 0:561d07a737bc 98
brunnobbco 0:561d07a737bc 99 /*!
brunnobbco 0:561d07a737bc 100 * RegFifo
brunnobbco 0:561d07a737bc 101 */
brunnobbco 0:561d07a737bc 102
brunnobbco 0:561d07a737bc 103 /*!
brunnobbco 0:561d07a737bc 104 * RegOpMode
brunnobbco 0:561d07a737bc 105 */
brunnobbco 0:561d07a737bc 106 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
brunnobbco 0:561d07a737bc 107 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 108 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
brunnobbco 0:561d07a737bc 109
brunnobbco 0:561d07a737bc 110 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
brunnobbco 0:561d07a737bc 111 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
brunnobbco 0:561d07a737bc 112 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
brunnobbco 0:561d07a737bc 113
brunnobbco 0:561d07a737bc 114 #define RFLR_OPMODE_MASK 0xF8
brunnobbco 0:561d07a737bc 115 #define RFLR_OPMODE_SLEEP 0x00
brunnobbco 0:561d07a737bc 116 #define RFLR_OPMODE_STANDBY 0x01 // Default
brunnobbco 0:561d07a737bc 117 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02
brunnobbco 0:561d07a737bc 118 #define RFLR_OPMODE_TRANSMITTER 0x03
brunnobbco 0:561d07a737bc 119 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04
brunnobbco 0:561d07a737bc 120 #define RFLR_OPMODE_RECEIVER 0x05
brunnobbco 0:561d07a737bc 121 // LoRa specific modes
brunnobbco 0:561d07a737bc 122 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06
brunnobbco 0:561d07a737bc 123 #define RFLR_OPMODE_CAD 0x07
brunnobbco 0:561d07a737bc 124
brunnobbco 0:561d07a737bc 125 /*!
brunnobbco 0:561d07a737bc 126 * RegFrf (MHz)
brunnobbco 0:561d07a737bc 127 */
brunnobbco 0:561d07a737bc 128 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default
brunnobbco 0:561d07a737bc 129 #define RFLR_FRFMID_915_MHZ 0xC0 // Default
brunnobbco 0:561d07a737bc 130 #define RFLR_FRFLSB_915_MHZ 0x00 // Default
brunnobbco 0:561d07a737bc 131
brunnobbco 0:561d07a737bc 132 /*!
brunnobbco 0:561d07a737bc 133 * RegPaConfig
brunnobbco 0:561d07a737bc 134 */
brunnobbco 0:561d07a737bc 135 #define RFLR_PACONFIG_PASELECT_MASK 0x7F
brunnobbco 0:561d07a737bc 136 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80
brunnobbco 0:561d07a737bc 137 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
brunnobbco 0:561d07a737bc 138
brunnobbco 0:561d07a737bc 139 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
brunnobbco 0:561d07a737bc 140
brunnobbco 0:561d07a737bc 141 /*!
brunnobbco 0:561d07a737bc 142 * RegPaRamp
brunnobbco 0:561d07a737bc 143 */
brunnobbco 0:561d07a737bc 144 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0
brunnobbco 0:561d07a737bc 145 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
brunnobbco 0:561d07a737bc 146 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00
brunnobbco 0:561d07a737bc 147
brunnobbco 0:561d07a737bc 148 #define RFLR_PARAMP_MASK 0xF0
brunnobbco 0:561d07a737bc 149 #define RFLR_PARAMP_3400_US 0x00
brunnobbco 0:561d07a737bc 150 #define RFLR_PARAMP_2000_US 0x01
brunnobbco 0:561d07a737bc 151 #define RFLR_PARAMP_1000_US 0x02
brunnobbco 0:561d07a737bc 152 #define RFLR_PARAMP_0500_US 0x03
brunnobbco 0:561d07a737bc 153 #define RFLR_PARAMP_0250_US 0x04
brunnobbco 0:561d07a737bc 154 #define RFLR_PARAMP_0125_US 0x05
brunnobbco 0:561d07a737bc 155 #define RFLR_PARAMP_0100_US 0x06
brunnobbco 0:561d07a737bc 156 #define RFLR_PARAMP_0062_US 0x07
brunnobbco 0:561d07a737bc 157 #define RFLR_PARAMP_0050_US 0x08
brunnobbco 0:561d07a737bc 158 #define RFLR_PARAMP_0040_US 0x09 // Default
brunnobbco 0:561d07a737bc 159 #define RFLR_PARAMP_0031_US 0x0A
brunnobbco 0:561d07a737bc 160 #define RFLR_PARAMP_0025_US 0x0B
brunnobbco 0:561d07a737bc 161 #define RFLR_PARAMP_0020_US 0x0C
brunnobbco 0:561d07a737bc 162 #define RFLR_PARAMP_0015_US 0x0D
brunnobbco 0:561d07a737bc 163 #define RFLR_PARAMP_0012_US 0x0E
brunnobbco 0:561d07a737bc 164 #define RFLR_PARAMP_0010_US 0x0F
brunnobbco 0:561d07a737bc 165
brunnobbco 0:561d07a737bc 166 /*!
brunnobbco 0:561d07a737bc 167 * RegOcp
brunnobbco 0:561d07a737bc 168 */
brunnobbco 0:561d07a737bc 169 #define RFLR_OCP_MASK 0xDF
brunnobbco 0:561d07a737bc 170 #define RFLR_OCP_ON 0x20 // Default
brunnobbco 0:561d07a737bc 171 #define RFLR_OCP_OFF 0x00
brunnobbco 0:561d07a737bc 172
brunnobbco 0:561d07a737bc 173 #define RFLR_OCP_TRIM_MASK 0xE0
brunnobbco 0:561d07a737bc 174 #define RFLR_OCP_TRIM_045_MA 0x00
brunnobbco 0:561d07a737bc 175 #define RFLR_OCP_TRIM_050_MA 0x01
brunnobbco 0:561d07a737bc 176 #define RFLR_OCP_TRIM_055_MA 0x02
brunnobbco 0:561d07a737bc 177 #define RFLR_OCP_TRIM_060_MA 0x03
brunnobbco 0:561d07a737bc 178 #define RFLR_OCP_TRIM_065_MA 0x04
brunnobbco 0:561d07a737bc 179 #define RFLR_OCP_TRIM_070_MA 0x05
brunnobbco 0:561d07a737bc 180 #define RFLR_OCP_TRIM_075_MA 0x06
brunnobbco 0:561d07a737bc 181 #define RFLR_OCP_TRIM_080_MA 0x07
brunnobbco 0:561d07a737bc 182 #define RFLR_OCP_TRIM_085_MA 0x08
brunnobbco 0:561d07a737bc 183 #define RFLR_OCP_TRIM_090_MA 0x09
brunnobbco 0:561d07a737bc 184 #define RFLR_OCP_TRIM_095_MA 0x0A
brunnobbco 0:561d07a737bc 185 #define RFLR_OCP_TRIM_100_MA 0x0B // Default
brunnobbco 0:561d07a737bc 186 #define RFLR_OCP_TRIM_105_MA 0x0C
brunnobbco 0:561d07a737bc 187 #define RFLR_OCP_TRIM_110_MA 0x0D
brunnobbco 0:561d07a737bc 188 #define RFLR_OCP_TRIM_115_MA 0x0E
brunnobbco 0:561d07a737bc 189 #define RFLR_OCP_TRIM_120_MA 0x0F
brunnobbco 0:561d07a737bc 190 #define RFLR_OCP_TRIM_130_MA 0x10
brunnobbco 0:561d07a737bc 191 #define RFLR_OCP_TRIM_140_MA 0x11
brunnobbco 0:561d07a737bc 192 #define RFLR_OCP_TRIM_150_MA 0x12
brunnobbco 0:561d07a737bc 193 #define RFLR_OCP_TRIM_160_MA 0x13
brunnobbco 0:561d07a737bc 194 #define RFLR_OCP_TRIM_170_MA 0x14
brunnobbco 0:561d07a737bc 195 #define RFLR_OCP_TRIM_180_MA 0x15
brunnobbco 0:561d07a737bc 196 #define RFLR_OCP_TRIM_190_MA 0x16
brunnobbco 0:561d07a737bc 197 #define RFLR_OCP_TRIM_200_MA 0x17
brunnobbco 0:561d07a737bc 198 #define RFLR_OCP_TRIM_210_MA 0x18
brunnobbco 0:561d07a737bc 199 #define RFLR_OCP_TRIM_220_MA 0x19
brunnobbco 0:561d07a737bc 200 #define RFLR_OCP_TRIM_230_MA 0x1A
brunnobbco 0:561d07a737bc 201 #define RFLR_OCP_TRIM_240_MA 0x1B
brunnobbco 0:561d07a737bc 202
brunnobbco 0:561d07a737bc 203 /*!
brunnobbco 0:561d07a737bc 204 * RegLna
brunnobbco 0:561d07a737bc 205 */
brunnobbco 0:561d07a737bc 206 #define RFLR_LNA_GAIN_MASK 0x1F
brunnobbco 0:561d07a737bc 207 #define RFLR_LNA_GAIN_G1 0x20 // Default
brunnobbco 0:561d07a737bc 208 #define RFLR_LNA_GAIN_G2 0x40
brunnobbco 0:561d07a737bc 209 #define RFLR_LNA_GAIN_G3 0x60
brunnobbco 0:561d07a737bc 210 #define RFLR_LNA_GAIN_G4 0x80
brunnobbco 0:561d07a737bc 211 #define RFLR_LNA_GAIN_G5 0xA0
brunnobbco 0:561d07a737bc 212 #define RFLR_LNA_GAIN_G6 0xC0
brunnobbco 0:561d07a737bc 213
brunnobbco 0:561d07a737bc 214 #define RFLR_LNA_BOOST_MASK 0xFC
brunnobbco 0:561d07a737bc 215 #define RFLR_LNA_BOOST_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 216 #define RFLR_LNA_BOOST_ON 0x03
brunnobbco 0:561d07a737bc 217
brunnobbco 0:561d07a737bc 218 /*!
brunnobbco 0:561d07a737bc 219 * RegFifoAddrPtr
brunnobbco 0:561d07a737bc 220 */
brunnobbco 0:561d07a737bc 221 #define RFLR_FIFOADDRPTR 0x00 // Default
brunnobbco 0:561d07a737bc 222
brunnobbco 0:561d07a737bc 223 /*!
brunnobbco 0:561d07a737bc 224 * RegFifoTxBaseAddr
brunnobbco 0:561d07a737bc 225 */
brunnobbco 0:561d07a737bc 226 #define RFLR_FIFOTXBASEADDR 0x80 // Default
brunnobbco 0:561d07a737bc 227
brunnobbco 0:561d07a737bc 228 /*!
brunnobbco 0:561d07a737bc 229 * RegFifoTxBaseAddr
brunnobbco 0:561d07a737bc 230 */
brunnobbco 0:561d07a737bc 231 #define RFLR_FIFORXBASEADDR 0x00 // Default
brunnobbco 0:561d07a737bc 232
brunnobbco 0:561d07a737bc 233 /*!
brunnobbco 0:561d07a737bc 234 * RegFifoRxCurrentAddr (Read Only)
brunnobbco 0:561d07a737bc 235 */
brunnobbco 0:561d07a737bc 236
brunnobbco 0:561d07a737bc 237 /*!
brunnobbco 0:561d07a737bc 238 * RegIrqFlagsMask
brunnobbco 0:561d07a737bc 239 */
brunnobbco 0:561d07a737bc 240 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
brunnobbco 0:561d07a737bc 241 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40
brunnobbco 0:561d07a737bc 242 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
brunnobbco 0:561d07a737bc 243 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
brunnobbco 0:561d07a737bc 244 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08
brunnobbco 0:561d07a737bc 245 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04
brunnobbco 0:561d07a737bc 246 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
brunnobbco 0:561d07a737bc 247 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
brunnobbco 0:561d07a737bc 248
brunnobbco 0:561d07a737bc 249 /*!
brunnobbco 0:561d07a737bc 250 * RegIrqFlags
brunnobbco 0:561d07a737bc 251 */
brunnobbco 0:561d07a737bc 252 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80
brunnobbco 0:561d07a737bc 253 #define RFLR_IRQFLAGS_RXDONE 0x40
brunnobbco 0:561d07a737bc 254 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
brunnobbco 0:561d07a737bc 255 #define RFLR_IRQFLAGS_VALIDHEADER 0x10
brunnobbco 0:561d07a737bc 256 #define RFLR_IRQFLAGS_TXDONE 0x08
brunnobbco 0:561d07a737bc 257 #define RFLR_IRQFLAGS_CADDONE 0x04
brunnobbco 0:561d07a737bc 258 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
brunnobbco 0:561d07a737bc 259 #define RFLR_IRQFLAGS_CADDETECTED 0x01
brunnobbco 0:561d07a737bc 260
brunnobbco 0:561d07a737bc 261 /*!
brunnobbco 0:561d07a737bc 262 * RegFifoRxNbBytes (Read Only)
brunnobbco 0:561d07a737bc 263 */
brunnobbco 0:561d07a737bc 264
brunnobbco 0:561d07a737bc 265 /*!
brunnobbco 0:561d07a737bc 266 * RegRxHeaderCntValueMsb (Read Only)
brunnobbco 0:561d07a737bc 267 */
brunnobbco 0:561d07a737bc 268
brunnobbco 0:561d07a737bc 269 /*!
brunnobbco 0:561d07a737bc 270 * RegRxHeaderCntValueLsb (Read Only)
brunnobbco 0:561d07a737bc 271 */
brunnobbco 0:561d07a737bc 272
brunnobbco 0:561d07a737bc 273 /*!
brunnobbco 0:561d07a737bc 274 * RegRxPacketCntValueMsb (Read Only)
brunnobbco 0:561d07a737bc 275 */
brunnobbco 0:561d07a737bc 276
brunnobbco 0:561d07a737bc 277 /*!
brunnobbco 0:561d07a737bc 278 * RegRxPacketCntValueLsb (Read Only)
brunnobbco 0:561d07a737bc 279 */
brunnobbco 0:561d07a737bc 280
brunnobbco 0:561d07a737bc 281 /*!
brunnobbco 0:561d07a737bc 282 * RegModemStat (Read Only)
brunnobbco 0:561d07a737bc 283 */
brunnobbco 0:561d07a737bc 284 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
brunnobbco 0:561d07a737bc 285 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
brunnobbco 0:561d07a737bc 286
brunnobbco 0:561d07a737bc 287 /*!
brunnobbco 0:561d07a737bc 288 * RegPktSnrValue (Read Only)
brunnobbco 0:561d07a737bc 289 */
brunnobbco 0:561d07a737bc 290
brunnobbco 0:561d07a737bc 291 /*!
brunnobbco 0:561d07a737bc 292 * RegPktRssiValue (Read Only)
brunnobbco 0:561d07a737bc 293 */
brunnobbco 0:561d07a737bc 294
brunnobbco 0:561d07a737bc 295 /*!
brunnobbco 0:561d07a737bc 296 * RegRssiValue (Read Only)
brunnobbco 0:561d07a737bc 297 */
brunnobbco 0:561d07a737bc 298
brunnobbco 0:561d07a737bc 299 /*!
brunnobbco 0:561d07a737bc 300 * RegHopChannel (Read Only)
brunnobbco 0:561d07a737bc 301 */
brunnobbco 0:561d07a737bc 302 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
brunnobbco 0:561d07a737bc 303 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
brunnobbco 0:561d07a737bc 304 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
brunnobbco 0:561d07a737bc 305
brunnobbco 0:561d07a737bc 306 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
brunnobbco 0:561d07a737bc 307 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
brunnobbco 0:561d07a737bc 308 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 309
brunnobbco 0:561d07a737bc 310 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
brunnobbco 0:561d07a737bc 311
brunnobbco 0:561d07a737bc 312 /*!
brunnobbco 0:561d07a737bc 313 * RegModemConfig1
brunnobbco 0:561d07a737bc 314 */
brunnobbco 0:561d07a737bc 315 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F
brunnobbco 0:561d07a737bc 316 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default
brunnobbco 0:561d07a737bc 317 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40
brunnobbco 0:561d07a737bc 318 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80
brunnobbco 0:561d07a737bc 319
brunnobbco 0:561d07a737bc 320 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7
brunnobbco 0:561d07a737bc 321 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08
brunnobbco 0:561d07a737bc 322 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default
brunnobbco 0:561d07a737bc 323 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18
brunnobbco 0:561d07a737bc 324 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20
brunnobbco 0:561d07a737bc 325
brunnobbco 0:561d07a737bc 326 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB
brunnobbco 0:561d07a737bc 327 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04
brunnobbco 0:561d07a737bc 328 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 329
brunnobbco 0:561d07a737bc 330 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD
brunnobbco 0:561d07a737bc 331 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02
brunnobbco 0:561d07a737bc 332 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 333
brunnobbco 0:561d07a737bc 334 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE
brunnobbco 0:561d07a737bc 335 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01
brunnobbco 0:561d07a737bc 336 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 337
brunnobbco 0:561d07a737bc 338 /*!
brunnobbco 0:561d07a737bc 339 * RegModemConfig2
brunnobbco 0:561d07a737bc 340 */
brunnobbco 0:561d07a737bc 341 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F
brunnobbco 0:561d07a737bc 342 #define RFLR_MODEMCONFIG2_SF_6 0x60
brunnobbco 0:561d07a737bc 343 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
brunnobbco 0:561d07a737bc 344 #define RFLR_MODEMCONFIG2_SF_8 0x80
brunnobbco 0:561d07a737bc 345 #define RFLR_MODEMCONFIG2_SF_9 0x90
brunnobbco 0:561d07a737bc 346 #define RFLR_MODEMCONFIG2_SF_10 0xA0
brunnobbco 0:561d07a737bc 347 #define RFLR_MODEMCONFIG2_SF_11 0xB0
brunnobbco 0:561d07a737bc 348 #define RFLR_MODEMCONFIG2_SF_12 0xC0
brunnobbco 0:561d07a737bc 349
brunnobbco 0:561d07a737bc 350 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
brunnobbco 0:561d07a737bc 351 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
brunnobbco 0:561d07a737bc 352 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
brunnobbco 0:561d07a737bc 353
brunnobbco 0:561d07a737bc 354 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB
brunnobbco 0:561d07a737bc 355 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default
brunnobbco 0:561d07a737bc 356 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00
brunnobbco 0:561d07a737bc 357
brunnobbco 0:561d07a737bc 358 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
brunnobbco 0:561d07a737bc 359 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
brunnobbco 0:561d07a737bc 360
brunnobbco 0:561d07a737bc 361 /*!
brunnobbco 0:561d07a737bc 362 * RegSymbTimeoutLsb
brunnobbco 0:561d07a737bc 363 */
brunnobbco 0:561d07a737bc 364 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
brunnobbco 0:561d07a737bc 365
brunnobbco 0:561d07a737bc 366 /*!
brunnobbco 0:561d07a737bc 367 * RegPreambleLengthMsb
brunnobbco 0:561d07a737bc 368 */
brunnobbco 0:561d07a737bc 369 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default
brunnobbco 0:561d07a737bc 370
brunnobbco 0:561d07a737bc 371 /*!
brunnobbco 0:561d07a737bc 372 * RegPreambleLengthLsb
brunnobbco 0:561d07a737bc 373 */
brunnobbco 0:561d07a737bc 374 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default
brunnobbco 0:561d07a737bc 375
brunnobbco 0:561d07a737bc 376 /*!
brunnobbco 0:561d07a737bc 377 * RegPayloadLength
brunnobbco 0:561d07a737bc 378 */
brunnobbco 0:561d07a737bc 379 #define RFLR_PAYLOADLENGTH 0x0E // Default
brunnobbco 0:561d07a737bc 380
brunnobbco 0:561d07a737bc 381 /*!
brunnobbco 0:561d07a737bc 382 * RegPayloadMaxLength
brunnobbco 0:561d07a737bc 383 */
brunnobbco 0:561d07a737bc 384 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default
brunnobbco 0:561d07a737bc 385
brunnobbco 0:561d07a737bc 386 /*!
brunnobbco 0:561d07a737bc 387 * RegHopPeriod
brunnobbco 0:561d07a737bc 388 */
brunnobbco 0:561d07a737bc 389 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
brunnobbco 0:561d07a737bc 390
brunnobbco 0:561d07a737bc 391 /*!
brunnobbco 0:561d07a737bc 392 * RegFifoRxByteAddr (Read Only)
brunnobbco 0:561d07a737bc 393 */
brunnobbco 0:561d07a737bc 394
brunnobbco 0:561d07a737bc 395 /*!
brunnobbco 0:561d07a737bc 396 * RegFeiMsb (Read Only)
brunnobbco 0:561d07a737bc 397 */
brunnobbco 0:561d07a737bc 398
brunnobbco 0:561d07a737bc 399 /*!
brunnobbco 0:561d07a737bc 400 * RegFeiMid (Read Only)
brunnobbco 0:561d07a737bc 401 */
brunnobbco 0:561d07a737bc 402
brunnobbco 0:561d07a737bc 403 /*!
brunnobbco 0:561d07a737bc 404 * RegFeiLsb (Read Only)
brunnobbco 0:561d07a737bc 405 */
brunnobbco 0:561d07a737bc 406
brunnobbco 0:561d07a737bc 407 /*!
brunnobbco 0:561d07a737bc 408 * RegRssiWideband (Read Only)
brunnobbco 0:561d07a737bc 409 */
brunnobbco 0:561d07a737bc 410
brunnobbco 0:561d07a737bc 411 /*!
brunnobbco 0:561d07a737bc 412 * RegDetectOptimize
brunnobbco 0:561d07a737bc 413 */
brunnobbco 0:561d07a737bc 414 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
brunnobbco 0:561d07a737bc 415 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
brunnobbco 0:561d07a737bc 416 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05
brunnobbco 0:561d07a737bc 417
brunnobbco 0:561d07a737bc 418 /*!
brunnobbco 0:561d07a737bc 419 * RegInvertIQ
brunnobbco 0:561d07a737bc 420 */
brunnobbco 0:561d07a737bc 421 #define RFLR_INVERTIQ_RX_MASK 0xBF
brunnobbco 0:561d07a737bc 422 #define RFLR_INVERTIQ_RX_OFF 0x00
brunnobbco 0:561d07a737bc 423 #define RFLR_INVERTIQ_RX_ON 0x40
brunnobbco 0:561d07a737bc 424 #define RFLR_INVERTIQ_TX_MASK 0xFE
brunnobbco 0:561d07a737bc 425 #define RFLR_INVERTIQ_TX_OFF 0x01
brunnobbco 0:561d07a737bc 426 #define RFLR_INVERTIQ_TX_ON 0x00
brunnobbco 0:561d07a737bc 427
brunnobbco 0:561d07a737bc 428 /*!
brunnobbco 0:561d07a737bc 429 * RegDetectionThreshold
brunnobbco 0:561d07a737bc 430 */
brunnobbco 0:561d07a737bc 431 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
brunnobbco 0:561d07a737bc 432 #define RFLR_DETECTIONTHRESH_SF6 0x0C
brunnobbco 0:561d07a737bc 433
brunnobbco 0:561d07a737bc 434 /*!
brunnobbco 0:561d07a737bc 435 * RegInvertIQ2
brunnobbco 0:561d07a737bc 436 */
brunnobbco 0:561d07a737bc 437 #define RFLR_INVERTIQ2_ON 0x19
brunnobbco 0:561d07a737bc 438 #define RFLR_INVERTIQ2_OFF 0x1D
brunnobbco 0:561d07a737bc 439
brunnobbco 0:561d07a737bc 440 /*!
brunnobbco 0:561d07a737bc 441 * RegDioMapping1
brunnobbco 0:561d07a737bc 442 */
brunnobbco 0:561d07a737bc 443 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
brunnobbco 0:561d07a737bc 444 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
brunnobbco 0:561d07a737bc 445 #define RFLR_DIOMAPPING1_DIO0_01 0x40
brunnobbco 0:561d07a737bc 446 #define RFLR_DIOMAPPING1_DIO0_10 0x80
brunnobbco 0:561d07a737bc 447 #define RFLR_DIOMAPPING1_DIO0_11 0xC0
brunnobbco 0:561d07a737bc 448
brunnobbco 0:561d07a737bc 449 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
brunnobbco 0:561d07a737bc 450 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
brunnobbco 0:561d07a737bc 451 #define RFLR_DIOMAPPING1_DIO1_01 0x10
brunnobbco 0:561d07a737bc 452 #define RFLR_DIOMAPPING1_DIO1_10 0x20
brunnobbco 0:561d07a737bc 453 #define RFLR_DIOMAPPING1_DIO1_11 0x30
brunnobbco 0:561d07a737bc 454
brunnobbco 0:561d07a737bc 455 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
brunnobbco 0:561d07a737bc 456 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
brunnobbco 0:561d07a737bc 457 #define RFLR_DIOMAPPING1_DIO2_01 0x04
brunnobbco 0:561d07a737bc 458 #define RFLR_DIOMAPPING1_DIO2_10 0x08
brunnobbco 0:561d07a737bc 459 #define RFLR_DIOMAPPING1_DIO2_11 0x0C
brunnobbco 0:561d07a737bc 460
brunnobbco 0:561d07a737bc 461 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
brunnobbco 0:561d07a737bc 462 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
brunnobbco 0:561d07a737bc 463 #define RFLR_DIOMAPPING1_DIO3_01 0x01
brunnobbco 0:561d07a737bc 464 #define RFLR_DIOMAPPING1_DIO3_10 0x02
brunnobbco 0:561d07a737bc 465 #define RFLR_DIOMAPPING1_DIO3_11 0x03
brunnobbco 0:561d07a737bc 466
brunnobbco 0:561d07a737bc 467 /*!
brunnobbco 0:561d07a737bc 468 * RegDioMapping2
brunnobbco 0:561d07a737bc 469 */
brunnobbco 0:561d07a737bc 470 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
brunnobbco 0:561d07a737bc 471 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
brunnobbco 0:561d07a737bc 472 #define RFLR_DIOMAPPING2_DIO4_01 0x40
brunnobbco 0:561d07a737bc 473 #define RFLR_DIOMAPPING2_DIO4_10 0x80
brunnobbco 0:561d07a737bc 474 #define RFLR_DIOMAPPING2_DIO4_11 0xC0
brunnobbco 0:561d07a737bc 475
brunnobbco 0:561d07a737bc 476 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
brunnobbco 0:561d07a737bc 477 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
brunnobbco 0:561d07a737bc 478 #define RFLR_DIOMAPPING2_DIO5_01 0x10
brunnobbco 0:561d07a737bc 479 #define RFLR_DIOMAPPING2_DIO5_10 0x20
brunnobbco 0:561d07a737bc 480 #define RFLR_DIOMAPPING2_DIO5_11 0x30
brunnobbco 0:561d07a737bc 481
brunnobbco 0:561d07a737bc 482 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE
brunnobbco 0:561d07a737bc 483 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
brunnobbco 0:561d07a737bc 484 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
brunnobbco 0:561d07a737bc 485
brunnobbco 0:561d07a737bc 486 /*!
brunnobbco 0:561d07a737bc 487 * RegVersion (Read Only)
brunnobbco 0:561d07a737bc 488 */
brunnobbco 0:561d07a737bc 489
brunnobbco 0:561d07a737bc 490 /*!
brunnobbco 0:561d07a737bc 491 * RegAgcRef
brunnobbco 0:561d07a737bc 492 */
brunnobbco 0:561d07a737bc 493
brunnobbco 0:561d07a737bc 494 /*!
brunnobbco 0:561d07a737bc 495 * RegAgcThresh1
brunnobbco 0:561d07a737bc 496 */
brunnobbco 0:561d07a737bc 497
brunnobbco 0:561d07a737bc 498 /*!
brunnobbco 0:561d07a737bc 499 * RegAgcThresh2
brunnobbco 0:561d07a737bc 500 */
brunnobbco 0:561d07a737bc 501
brunnobbco 0:561d07a737bc 502 /*!
brunnobbco 0:561d07a737bc 503 * RegAgcThresh3
brunnobbco 0:561d07a737bc 504 */
brunnobbco 0:561d07a737bc 505
brunnobbco 0:561d07a737bc 506 /*!
brunnobbco 0:561d07a737bc 507 * RegPllHop
brunnobbco 0:561d07a737bc 508 */
brunnobbco 0:561d07a737bc 509 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F
brunnobbco 0:561d07a737bc 510 #define RFLR_PLLHOP_FASTHOP_ON 0x80
brunnobbco 0:561d07a737bc 511 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 512
brunnobbco 0:561d07a737bc 513 /*!
brunnobbco 0:561d07a737bc 514 * RegTcxo
brunnobbco 0:561d07a737bc 515 */
brunnobbco 0:561d07a737bc 516 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF
brunnobbco 0:561d07a737bc 517 #define RFLR_TCXO_TCXOINPUT_ON 0x10
brunnobbco 0:561d07a737bc 518 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
brunnobbco 0:561d07a737bc 519
brunnobbco 0:561d07a737bc 520 /*!
brunnobbco 0:561d07a737bc 521 * RegPaDac
brunnobbco 0:561d07a737bc 522 */
brunnobbco 0:561d07a737bc 523 #define RFLR_PADAC_20DBM_MASK 0xF8
brunnobbco 0:561d07a737bc 524 #define RFLR_PADAC_20DBM_ON 0x07
brunnobbco 0:561d07a737bc 525 #define RFLR_PADAC_20DBM_OFF 0x04 // Default
brunnobbco 0:561d07a737bc 526
brunnobbco 0:561d07a737bc 527 /*!
brunnobbco 0:561d07a737bc 528 * RegPll
brunnobbco 0:561d07a737bc 529 */
brunnobbco 0:561d07a737bc 530 #define RFLR_PLL_BANDWIDTH_MASK 0x3F
brunnobbco 0:561d07a737bc 531 #define RFLR_PLL_BANDWIDTH_75 0x00
brunnobbco 0:561d07a737bc 532 #define RFLR_PLL_BANDWIDTH_150 0x40
brunnobbco 0:561d07a737bc 533 #define RFLR_PLL_BANDWIDTH_225 0x80
brunnobbco 0:561d07a737bc 534 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
brunnobbco 0:561d07a737bc 535
brunnobbco 0:561d07a737bc 536 /*!
brunnobbco 0:561d07a737bc 537 * RegPllLowPn
brunnobbco 0:561d07a737bc 538 */
brunnobbco 0:561d07a737bc 539 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
brunnobbco 0:561d07a737bc 540 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
brunnobbco 0:561d07a737bc 541 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
brunnobbco 0:561d07a737bc 542 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
brunnobbco 0:561d07a737bc 543 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
brunnobbco 0:561d07a737bc 544
brunnobbco 0:561d07a737bc 545 /*!
brunnobbco 0:561d07a737bc 546 * RegFormerTemp
brunnobbco 0:561d07a737bc 547 */
brunnobbco 0:561d07a737bc 548
brunnobbco 0:561d07a737bc 549 #endif // __SX1272_REGS_LORA_H__