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Diff: TARGET_DISCO_L072CZ_LRWAN1/radio_typeABZ.cpp
- Revision:
- 0:9c052ff8dd6a
- Child:
- 5:ab124d3842a8
diff -r 000000000000 -r 9c052ff8dd6a TARGET_DISCO_L072CZ_LRWAN1/radio_typeABZ.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/TARGET_DISCO_L072CZ_LRWAN1/radio_typeABZ.cpp Thu Jul 05 17:31:54 2018 -0700 @@ -0,0 +1,83 @@ +#include "radio.h" + +#define SSA_BOARD 1 + +SPI spi(PA_7, PA_6, PB_3); // mosi, miso, sclk +// dio0, dio1, nss, spi, rst +SX127x Radio::radio(PB_4, PB_1, PA_15, spi, PC_0); // sx1276 arduino shield +SX127x_lora Radio::lora(radio); +SX127x_fsk Radio::fsk(radio); + +InterruptIn Radio::dio0(PB_4); +InterruptIn Radio::dio1(PB_1); + +#define CRF1 PA_1 +#define CRF2 PC_2 +#define CRF3 PC_1 +DigitalOut Vctl1(CRF1); +DigitalOut Vctl2(CRF2); +DigitalOut Vctl3(CRF3); + +void Radio::rfsw_callback() +{ + if (radio.RegOpMode.bits.Mode == RF_OPMODE_TRANSMITTER) { + Vctl1 = 0; + if (radio.RegPaConfig.bits.PaSelect) { + Vctl2 = 0; + Vctl3 = 1; + } else { + Vctl2 = 1; + Vctl3 = 0; + } + } else { + if (radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER || radio.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER_SINGLE) + Vctl1 = 1; + else + Vctl1 = 0; + + Vctl2 = 0; + Vctl3 = 0; + } +} + +void +Radio::set_tx_dbm(int8_t dbm) +{ + RegPdsTrim1_t pds_trim; + pds_trim.octet = radio.read_reg(REG_PDSTRIM1_SX1276); + + if (dbm > 13) { + radio.RegPaConfig.bits.PaSelect = 1; + if (dbm > 17) { + pds_trim.bits.prog_txdac = 7; + dbm -= 3; + ocp(150); + } else { + pds_trim.bits.prog_txdac = 4; + ocp(120); + } + + radio.RegPaConfig.bits.OutputPower = dbm - 2; + } else { + pds_trim.bits.prog_txdac = 4; + radio.RegPaConfig.bits.PaSelect = 0; + radio.RegPaConfig.bits.OutputPower = dbm + 1; + ocp(80); + } + + radio.write_reg(REG_PACONFIG, radio.RegPaConfig.octet); + radio.write_reg(REG_PDSTRIM1_SX1276, pds_trim.octet); +} + +#ifdef SSA_BOARD +DigitalOut pa12(PA_12); // tcxo enable +DigitalOut pa11(PA_11); // sw9v enable -> sw3v3 +#endif +void Radio::boardInit() +{ +#ifdef SSA_BOARD + pa12 = 1; // tcxo + pa11 = 1; // sw9v -> sw3v3 +#endif +} +