Diff: utility/enc28j60.h

Revision:

11:647d53d146f1

Parent:

9:a156d3de5647

Child:

15:53715cc81c63

--- a/utility/enc28j60.h	Tue Aug 27 22:08:54 2019 +0000
+++ b/utility/enc28j60.h	Fri Aug 30 08:11:40 2019 +0000
@@ -222,35 +222,36 @@
 #define PHCON2_HDLDIS    0x0100
 
 // ENC28J60 Packet Control Byte Bit Definitions
-#define PKTCTRL_PHUGEEN  0x08
-#define PKTCTRL_PPADEN   0x04
-#define PKTCTRL_PCRCEN   0x02
-#define PKTCTRL_POVERRIDE 0x01
+#define PKTCTRL_PHUGEEN         0x08
+#define PKTCTRL_PPADEN          0x04
+#define PKTCTRL_PCRCEN          0x02
+#define PKTCTRL_POVERRIDE       0x01
 
 // SPI operation codes
-#define ENC28J60_READ_CTRL_REG       0x00
-#define ENC28J60_READ_BUF_MEM        0x3A
-#define ENC28J60_WRITE_CTRL_REG      0x40
-#define ENC28J60_WRITE_BUF_MEM       0x7A
-#define ENC28J60_BIT_FIELD_SET       0x80
-#define ENC28J60_BIT_FIELD_CLR       0xA0
-#define ENC28J60_SOFT_RESET          0xFF
+#define ENC28J60_READ_CTRL_REG  0x00
+#define ENC28J60_READ_BUF_MEM   0x3A
+#define ENC28J60_WRITE_CTRL_REG 0x40
+#define ENC28J60_WRITE_BUF_MEM  0x7A
+#define ENC28J60_BIT_FIELD_SET  0x80
+#define ENC28J60_BIT_FIELD_CLR  0xA0
+#define ENC28J60_SOFT_RESET     0xFF
 
 
-// The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
-// buffer boundaries applied to internal 8K ram
-// the entire available packet buffer space is allocated
+// The RXSTART_INIT should be zero. See Silicon Errata:
+// Sometimes, when ERXST or ERXND is written to, the exact value, 0000h, is stored in the Internal
+// Receive Write Pointer instead of the ERXST address.
+// Work around
+// Use the lower segment of the buffer memory for the receive buffer, starting at address 0000h.
+// For example, use the range (0000h to n) for the receive buffer, and ((n + 1) to 8191) for the transmit buffer.
+#define RXSTART_INIT    0x0
+// Receive buffer end. Make sure this is an odd value (See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)')
+#define RXEND_INIT      0x11CB      // = (3 * 1518) + 1
+// Start TX buffer RXEND_INIT + 1
+#define TXSTART_INIT    RXEND_INIT + 1
+// end TX buffer at end of mem
+#define TXEND_INIT      0x1FFF
 //
-// start with recbuf at 0/
-#define RXSTART_INIT     0x0
-// receive buffer end. make sure this is an odd value (See Rev. B1,B4,B5,B7 Silicon Errata 'Memory (Ethernet Buffer)')
-#define RXSTOP_INIT      (0x1FFF-0x1800)
-// start TX buffer RXSTOP_INIT+1
-#define TXSTART_INIT     (0x1FFF-0x1800+1)
-// stp TX buffer at end of mem
-#define TXSTOP_INIT      0x1FFF
-//
-// max frame length which the conroller will accept:
-#define        MAX_FRAMELEN        1500        // (note: maximum ethernet frame length would be 1518)
+// Max frame length which the conroller will accept:
+#define MAX_FRAMELEN    1518        // (note: maximum ethernet frame length is 1518)
 
 #endif