123
sx127x_lora.cpp@19:1ee6ef1ab73f, 2015-06-02 (annotated)
- Committer:
- dudmuck
- Date:
- Tue Jun 02 17:09:19 2015 +0000
- Revision:
- 19:1ee6ef1ab73f
- Parent:
- 18:0ecb6adb7c0b
- Child:
- 23:1df3dddcb43e
improve frequency error tolerance of sx1276 at 500KHz BW.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dudmuck | 2:fdae76e1215e | 1 | #include "sx127x_lora.h" |
dudmuck | 2:fdae76e1215e | 2 | |
dudmuck | 2:fdae76e1215e | 3 | /* SX127x driver |
dudmuck | 2:fdae76e1215e | 4 | * Copyright (c) 2013 Semtech |
dudmuck | 2:fdae76e1215e | 5 | * |
dudmuck | 2:fdae76e1215e | 6 | * Licensed under the Apache License, Version 2.0 (the "License"); |
dudmuck | 2:fdae76e1215e | 7 | * you may not use this file except in compliance with the License. |
dudmuck | 2:fdae76e1215e | 8 | * You may obtain a copy of the License at |
dudmuck | 2:fdae76e1215e | 9 | * |
dudmuck | 2:fdae76e1215e | 10 | * http://www.apache.org/licenses/LICENSE-2.0 |
dudmuck | 2:fdae76e1215e | 11 | * |
dudmuck | 2:fdae76e1215e | 12 | * Unless required by applicable law or agreed to in writing, software |
dudmuck | 2:fdae76e1215e | 13 | * distributed under the License is distributed on an "AS IS" BASIS, |
dudmuck | 2:fdae76e1215e | 14 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
dudmuck | 2:fdae76e1215e | 15 | * See the License for the specific language governing permissions and |
dudmuck | 2:fdae76e1215e | 16 | * limitations under the License. |
dudmuck | 2:fdae76e1215e | 17 | */ |
dudmuck | 2:fdae76e1215e | 18 | |
dudmuck | 3:3bf2515b1eed | 19 | SX127x_lora::SX127x_lora(SX127x& r) : m_xcvr(r) |
dudmuck | 2:fdae76e1215e | 20 | { |
dudmuck | 19:1ee6ef1ab73f | 21 | if (!m_xcvr.RegOpMode.bits.LongRangeMode) |
dudmuck | 19:1ee6ef1ab73f | 22 | enable(); |
dudmuck | 19:1ee6ef1ab73f | 23 | |
dudmuck | 2:fdae76e1215e | 24 | RegModemConfig.octet = m_xcvr.read_reg(REG_LR_MODEMCONFIG); |
dudmuck | 2:fdae76e1215e | 25 | RegModemConfig2.octet = m_xcvr.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 2:fdae76e1215e | 26 | RegTest31.octet = m_xcvr.read_reg(REG_LR_TEST31); |
dudmuck | 17:59279bc8cdab | 27 | RegTest33.octet = m_xcvr.read_reg(REG_LR_TEST33); // invert_i_q |
dudmuck | 17:59279bc8cdab | 28 | RegDriftInvert.octet = m_xcvr.read_reg(REG_LR_DRIFT_INVERT); |
dudmuck | 19:1ee6ef1ab73f | 29 | RegGainDrift.octet = m_xcvr.read_reg(REG_LR_GAIN_DRIFT); |
dudmuck | 19:1ee6ef1ab73f | 30 | |
dudmuck | 19:1ee6ef1ab73f | 31 | if (m_xcvr.type == SX1276) { |
dudmuck | 19:1ee6ef1ab73f | 32 | RegAutoDrift.octet = m_xcvr.read_reg(REG_LR_SX1276_AUTO_DRIFT); |
dudmuck | 19:1ee6ef1ab73f | 33 | } |
dudmuck | 2:fdae76e1215e | 34 | |
dudmuck | 2:fdae76e1215e | 35 | // CRC for TX is disabled by default |
dudmuck | 2:fdae76e1215e | 36 | setRxPayloadCrcOn(true); |
dudmuck | 2:fdae76e1215e | 37 | } |
dudmuck | 2:fdae76e1215e | 38 | |
dudmuck | 2:fdae76e1215e | 39 | SX127x_lora::~SX127x_lora() |
dudmuck | 2:fdae76e1215e | 40 | { |
dudmuck | 2:fdae76e1215e | 41 | } |
dudmuck | 2:fdae76e1215e | 42 | |
dudmuck | 2:fdae76e1215e | 43 | void SX127x_lora::write_fifo(uint8_t len) |
dudmuck | 2:fdae76e1215e | 44 | { |
dudmuck | 2:fdae76e1215e | 45 | int i; |
dudmuck | 2:fdae76e1215e | 46 | |
dudmuck | 2:fdae76e1215e | 47 | m_xcvr.m_cs = 0; |
dudmuck | 2:fdae76e1215e | 48 | m_xcvr.m_spi.write(REG_FIFO | 0x80); // bit7 is high for writing to radio |
dudmuck | 2:fdae76e1215e | 49 | |
dudmuck | 2:fdae76e1215e | 50 | for (i = 0; i < len; i++) { |
dudmuck | 2:fdae76e1215e | 51 | m_xcvr.m_spi.write(m_xcvr.tx_buf[i]); |
dudmuck | 2:fdae76e1215e | 52 | } |
dudmuck | 2:fdae76e1215e | 53 | m_xcvr.m_cs = 1; |
dudmuck | 2:fdae76e1215e | 54 | } |
dudmuck | 2:fdae76e1215e | 55 | |
dudmuck | 2:fdae76e1215e | 56 | void SX127x_lora::read_fifo(uint8_t len) |
dudmuck | 2:fdae76e1215e | 57 | { |
dudmuck | 2:fdae76e1215e | 58 | int i; |
dudmuck | 2:fdae76e1215e | 59 | |
dudmuck | 2:fdae76e1215e | 60 | m_xcvr.m_cs = 0; |
dudmuck | 2:fdae76e1215e | 61 | m_xcvr.m_spi.write(REG_FIFO); // bit7 is low for reading from radio |
dudmuck | 2:fdae76e1215e | 62 | for (i = 0; i < len; i++) { |
dudmuck | 2:fdae76e1215e | 63 | m_xcvr.rx_buf[i] = m_xcvr.m_spi.write(0); |
dudmuck | 2:fdae76e1215e | 64 | } |
dudmuck | 2:fdae76e1215e | 65 | m_xcvr.m_cs = 1; |
dudmuck | 2:fdae76e1215e | 66 | } |
dudmuck | 2:fdae76e1215e | 67 | |
dudmuck | 2:fdae76e1215e | 68 | void SX127x_lora::enable() |
dudmuck | 2:fdae76e1215e | 69 | { |
dudmuck | 2:fdae76e1215e | 70 | m_xcvr.set_opmode(RF_OPMODE_SLEEP); |
dudmuck | 2:fdae76e1215e | 71 | |
dudmuck | 2:fdae76e1215e | 72 | m_xcvr.RegOpMode.bits.LongRangeMode = 1; |
dudmuck | 2:fdae76e1215e | 73 | m_xcvr.write_reg(REG_OPMODE, m_xcvr.RegOpMode.octet); |
dudmuck | 2:fdae76e1215e | 74 | |
dudmuck | 2:fdae76e1215e | 75 | m_xcvr.RegDioMapping1.bits.Dio0Mapping = 0; // DIO0 to RxDone |
dudmuck | 2:fdae76e1215e | 76 | m_xcvr.RegDioMapping1.bits.Dio1Mapping = 0; |
dudmuck | 2:fdae76e1215e | 77 | m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet); |
dudmuck | 2:fdae76e1215e | 78 | |
dudmuck | 2:fdae76e1215e | 79 | m_xcvr.set_opmode(RF_OPMODE_STANDBY); |
dudmuck | 2:fdae76e1215e | 80 | } |
dudmuck | 2:fdae76e1215e | 81 | |
dudmuck | 2:fdae76e1215e | 82 | uint8_t SX127x_lora::getCodingRate(bool from_rx) |
dudmuck | 2:fdae76e1215e | 83 | { |
dudmuck | 2:fdae76e1215e | 84 | if (from_rx) { |
dudmuck | 2:fdae76e1215e | 85 | // expected RegModemStatus was read on RxDone interrupt |
dudmuck | 2:fdae76e1215e | 86 | return RegModemStatus.bits.RxCodingRate; |
dudmuck | 2:fdae76e1215e | 87 | } else { // transmitted coding rate... |
dudmuck | 2:fdae76e1215e | 88 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 89 | return RegModemConfig.sx1276bits.CodingRate; |
dudmuck | 2:fdae76e1215e | 90 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 91 | return RegModemConfig.sx1272bits.CodingRate; |
dudmuck | 2:fdae76e1215e | 92 | else |
dudmuck | 2:fdae76e1215e | 93 | return 0; |
dudmuck | 2:fdae76e1215e | 94 | } |
dudmuck | 2:fdae76e1215e | 95 | } |
dudmuck | 2:fdae76e1215e | 96 | |
dudmuck | 2:fdae76e1215e | 97 | |
dudmuck | 2:fdae76e1215e | 98 | |
dudmuck | 2:fdae76e1215e | 99 | void SX127x_lora::setCodingRate(uint8_t cr) |
dudmuck | 2:fdae76e1215e | 100 | { |
dudmuck | 2:fdae76e1215e | 101 | if (!m_xcvr.RegOpMode.bits.LongRangeMode) |
dudmuck | 2:fdae76e1215e | 102 | return; |
dudmuck | 2:fdae76e1215e | 103 | |
dudmuck | 2:fdae76e1215e | 104 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 105 | RegModemConfig.sx1276bits.CodingRate = cr; |
dudmuck | 2:fdae76e1215e | 106 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 107 | RegModemConfig.sx1272bits.CodingRate = cr; |
dudmuck | 2:fdae76e1215e | 108 | else |
dudmuck | 2:fdae76e1215e | 109 | return; |
dudmuck | 2:fdae76e1215e | 110 | |
dudmuck | 2:fdae76e1215e | 111 | m_xcvr.write_reg(REG_LR_MODEMCONFIG, RegModemConfig.octet); |
dudmuck | 2:fdae76e1215e | 112 | } |
dudmuck | 2:fdae76e1215e | 113 | |
dudmuck | 2:fdae76e1215e | 114 | |
dudmuck | 2:fdae76e1215e | 115 | |
dudmuck | 2:fdae76e1215e | 116 | bool SX127x_lora::getHeaderMode(void) |
dudmuck | 2:fdae76e1215e | 117 | { |
dudmuck | 2:fdae76e1215e | 118 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 119 | return RegModemConfig.sx1276bits.ImplicitHeaderModeOn; |
dudmuck | 2:fdae76e1215e | 120 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 121 | return RegModemConfig.sx1272bits.ImplicitHeaderModeOn; |
dudmuck | 2:fdae76e1215e | 122 | else |
dudmuck | 2:fdae76e1215e | 123 | return false; |
dudmuck | 2:fdae76e1215e | 124 | } |
dudmuck | 2:fdae76e1215e | 125 | |
dudmuck | 2:fdae76e1215e | 126 | void SX127x_lora::setHeaderMode(bool hm) |
dudmuck | 2:fdae76e1215e | 127 | { |
dudmuck | 2:fdae76e1215e | 128 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 129 | RegModemConfig.sx1276bits.ImplicitHeaderModeOn = hm; |
dudmuck | 2:fdae76e1215e | 130 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 131 | RegModemConfig.sx1272bits.ImplicitHeaderModeOn = hm; |
dudmuck | 2:fdae76e1215e | 132 | else |
dudmuck | 2:fdae76e1215e | 133 | return; |
dudmuck | 2:fdae76e1215e | 134 | |
dudmuck | 2:fdae76e1215e | 135 | m_xcvr.write_reg(REG_LR_MODEMCONFIG, RegModemConfig.octet); |
dudmuck | 2:fdae76e1215e | 136 | } |
dudmuck | 2:fdae76e1215e | 137 | |
dudmuck | 2:fdae76e1215e | 138 | |
dudmuck | 2:fdae76e1215e | 139 | uint8_t SX127x_lora::getBw(void) |
dudmuck | 2:fdae76e1215e | 140 | { |
dudmuck | 2:fdae76e1215e | 141 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 142 | return RegModemConfig.sx1276bits.Bw; |
dudmuck | 2:fdae76e1215e | 143 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 144 | return RegModemConfig.sx1272bits.Bw; |
dudmuck | 2:fdae76e1215e | 145 | else |
dudmuck | 2:fdae76e1215e | 146 | return 0; |
dudmuck | 2:fdae76e1215e | 147 | } |
dudmuck | 15:3f3fc6792f97 | 148 | |
dudmuck | 15:3f3fc6792f97 | 149 | int SX127x_lora::get_freq_error_Hz() |
dudmuck | 15:3f3fc6792f97 | 150 | { |
dudmuck | 15:3f3fc6792f97 | 151 | int freq_error; |
dudmuck | 15:3f3fc6792f97 | 152 | float f, khz = 0; |
dudmuck | 15:3f3fc6792f97 | 153 | freq_error = m_xcvr.read_reg(REG_LR_TEST28); |
dudmuck | 15:3f3fc6792f97 | 154 | freq_error <<= 8; |
dudmuck | 15:3f3fc6792f97 | 155 | freq_error += m_xcvr.read_reg(REG_LR_TEST29); |
dudmuck | 15:3f3fc6792f97 | 156 | freq_error <<= 8; |
dudmuck | 15:3f3fc6792f97 | 157 | freq_error += m_xcvr.read_reg(REG_LR_TEST2A); |
dudmuck | 15:3f3fc6792f97 | 158 | if (freq_error & 0x80000) { // 20bit value is negative |
dudmuck | 15:3f3fc6792f97 | 159 | //signed 20bit to 32bit |
dudmuck | 15:3f3fc6792f97 | 160 | freq_error |= 0xfff00000; |
dudmuck | 15:3f3fc6792f97 | 161 | } |
dudmuck | 15:3f3fc6792f97 | 162 | f = freq_error / (float)XTAL_FREQ; |
dudmuck | 15:3f3fc6792f97 | 163 | f *= (float)0x1000000; // 2^24 |
dudmuck | 15:3f3fc6792f97 | 164 | if (m_xcvr.type == SX1272) { |
dudmuck | 15:3f3fc6792f97 | 165 | switch (RegModemConfig.sx1272bits.Bw) { |
dudmuck | 15:3f3fc6792f97 | 166 | case 0: khz = 125; break; |
dudmuck | 15:3f3fc6792f97 | 167 | case 1: khz = 250; break; |
dudmuck | 15:3f3fc6792f97 | 168 | case 2: khz = 500; break; |
dudmuck | 15:3f3fc6792f97 | 169 | } |
dudmuck | 15:3f3fc6792f97 | 170 | } else if (m_xcvr.type == SX1276) { |
dudmuck | 15:3f3fc6792f97 | 171 | switch (RegModemConfig.sx1276bits.Bw) { |
dudmuck | 15:3f3fc6792f97 | 172 | case 0: khz = 7.8; break; |
dudmuck | 15:3f3fc6792f97 | 173 | case 1: khz = 10.4; break; |
dudmuck | 15:3f3fc6792f97 | 174 | case 2: khz = 15.6; break; |
dudmuck | 15:3f3fc6792f97 | 175 | case 3: khz = 20.8; break; |
dudmuck | 15:3f3fc6792f97 | 176 | case 4: khz = 31.25; break; |
dudmuck | 15:3f3fc6792f97 | 177 | case 5: khz = 41.7; break; |
dudmuck | 15:3f3fc6792f97 | 178 | case 6: khz = 62.5; break; |
dudmuck | 15:3f3fc6792f97 | 179 | case 7: khz = 125; break; |
dudmuck | 15:3f3fc6792f97 | 180 | case 8: khz = 250; break; |
dudmuck | 15:3f3fc6792f97 | 181 | case 9: khz = 500; break; |
dudmuck | 15:3f3fc6792f97 | 182 | } |
dudmuck | 15:3f3fc6792f97 | 183 | } |
dudmuck | 15:3f3fc6792f97 | 184 | f *= khz / 500; |
dudmuck | 15:3f3fc6792f97 | 185 | return (int)f; |
dudmuck | 15:3f3fc6792f97 | 186 | } |
dudmuck | 15:3f3fc6792f97 | 187 | |
dudmuck | 10:7382c260c4b1 | 188 | float SX127x_lora::get_symbol_period() |
dudmuck | 10:7382c260c4b1 | 189 | { |
dudmuck | 10:7382c260c4b1 | 190 | float khz = 0; |
dudmuck | 10:7382c260c4b1 | 191 | |
dudmuck | 10:7382c260c4b1 | 192 | if (m_xcvr.type == SX1276) { |
dudmuck | 10:7382c260c4b1 | 193 | switch (RegModemConfig.sx1276bits.Bw) { |
dudmuck | 10:7382c260c4b1 | 194 | case 0: khz = 7.8; break; |
dudmuck | 10:7382c260c4b1 | 195 | case 1: khz = 10.4; break; |
dudmuck | 10:7382c260c4b1 | 196 | case 2: khz = 15.6; break; |
dudmuck | 10:7382c260c4b1 | 197 | case 3: khz = 20.8; break; |
dudmuck | 10:7382c260c4b1 | 198 | case 4: khz = 31.25; break; |
dudmuck | 10:7382c260c4b1 | 199 | case 5: khz = 41.7; break; |
dudmuck | 10:7382c260c4b1 | 200 | case 6: khz = 62.5; break; |
dudmuck | 10:7382c260c4b1 | 201 | case 7: khz = 125; break; |
dudmuck | 10:7382c260c4b1 | 202 | case 8: khz = 250; break; |
dudmuck | 10:7382c260c4b1 | 203 | case 9: khz = 500; break; |
dudmuck | 10:7382c260c4b1 | 204 | } |
dudmuck | 10:7382c260c4b1 | 205 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 10:7382c260c4b1 | 206 | switch (RegModemConfig.sx1272bits.Bw) { |
dudmuck | 10:7382c260c4b1 | 207 | case 0: khz = 125; break; |
dudmuck | 10:7382c260c4b1 | 208 | case 1: khz = 250; break; |
dudmuck | 10:7382c260c4b1 | 209 | case 2: khz = 500; break; |
dudmuck | 10:7382c260c4b1 | 210 | } |
dudmuck | 10:7382c260c4b1 | 211 | } |
dudmuck | 10:7382c260c4b1 | 212 | |
dudmuck | 10:7382c260c4b1 | 213 | // return symbol duration in milliseconds |
dudmuck | 10:7382c260c4b1 | 214 | return (1 << RegModemConfig2.sx1276bits.SpreadingFactor) / khz; |
dudmuck | 10:7382c260c4b1 | 215 | } |
dudmuck | 2:fdae76e1215e | 216 | |
dudmuck | 16:3de8e1c465eb | 217 | void SX127x_lora::setBw_KHz(int khz) |
dudmuck | 16:3de8e1c465eb | 218 | { |
dudmuck | 16:3de8e1c465eb | 219 | uint8_t bw = 0; |
dudmuck | 16:3de8e1c465eb | 220 | |
dudmuck | 16:3de8e1c465eb | 221 | if (m_xcvr.type == SX1276) { |
dudmuck | 16:3de8e1c465eb | 222 | if (khz <= 8) bw = 0; |
dudmuck | 16:3de8e1c465eb | 223 | else if (khz <= 11) bw = 1; |
dudmuck | 16:3de8e1c465eb | 224 | else if (khz <= 16) bw = 2; |
dudmuck | 16:3de8e1c465eb | 225 | else if (khz <= 21) bw = 3; |
dudmuck | 16:3de8e1c465eb | 226 | else if (khz <= 32) bw = 4; |
dudmuck | 16:3de8e1c465eb | 227 | else if (khz <= 42) bw = 5; |
dudmuck | 16:3de8e1c465eb | 228 | else if (khz <= 63) bw = 6; |
dudmuck | 16:3de8e1c465eb | 229 | else if (khz <= 125) bw = 7; |
dudmuck | 16:3de8e1c465eb | 230 | else if (khz <= 250) bw = 8; |
dudmuck | 16:3de8e1c465eb | 231 | else if (khz <= 500) bw = 9; |
dudmuck | 16:3de8e1c465eb | 232 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 16:3de8e1c465eb | 233 | if (khz <= 125) bw = 0; |
dudmuck | 16:3de8e1c465eb | 234 | else if (khz <= 250) bw = 1; |
dudmuck | 16:3de8e1c465eb | 235 | else if (khz <= 500) bw = 2; |
dudmuck | 16:3de8e1c465eb | 236 | } |
dudmuck | 16:3de8e1c465eb | 237 | |
dudmuck | 16:3de8e1c465eb | 238 | setBw(bw); |
dudmuck | 16:3de8e1c465eb | 239 | } |
dudmuck | 16:3de8e1c465eb | 240 | |
dudmuck | 2:fdae76e1215e | 241 | void SX127x_lora::setBw(uint8_t bw) |
dudmuck | 2:fdae76e1215e | 242 | { |
dudmuck | 2:fdae76e1215e | 243 | if (!m_xcvr.RegOpMode.bits.LongRangeMode) |
dudmuck | 2:fdae76e1215e | 244 | return; |
dudmuck | 2:fdae76e1215e | 245 | |
dudmuck | 19:1ee6ef1ab73f | 246 | if (m_xcvr.type == SX1276) { |
dudmuck | 2:fdae76e1215e | 247 | RegModemConfig.sx1276bits.Bw = bw; |
dudmuck | 10:7382c260c4b1 | 248 | if (get_symbol_period() > 16) |
dudmuck | 10:7382c260c4b1 | 249 | RegModemConfig3.sx1276bits.LowDataRateOptimize = 1; |
dudmuck | 10:7382c260c4b1 | 250 | else |
dudmuck | 10:7382c260c4b1 | 251 | RegModemConfig3.sx1276bits.LowDataRateOptimize = 0; |
dudmuck | 19:1ee6ef1ab73f | 252 | m_xcvr.write_reg(REG_LR_MODEMCONFIG3, RegModemConfig3.octet); |
dudmuck | 10:7382c260c4b1 | 253 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 2:fdae76e1215e | 254 | RegModemConfig.sx1272bits.Bw = bw; |
dudmuck | 10:7382c260c4b1 | 255 | if (get_symbol_period() > 16) |
dudmuck | 2:fdae76e1215e | 256 | RegModemConfig.sx1272bits.LowDataRateOptimize = 1; |
dudmuck | 2:fdae76e1215e | 257 | else |
dudmuck | 2:fdae76e1215e | 258 | RegModemConfig.sx1272bits.LowDataRateOptimize = 0; |
dudmuck | 2:fdae76e1215e | 259 | } else |
dudmuck | 2:fdae76e1215e | 260 | return; |
dudmuck | 2:fdae76e1215e | 261 | |
dudmuck | 2:fdae76e1215e | 262 | m_xcvr.write_reg(REG_LR_MODEMCONFIG, RegModemConfig.octet); |
dudmuck | 2:fdae76e1215e | 263 | } |
dudmuck | 2:fdae76e1215e | 264 | |
dudmuck | 2:fdae76e1215e | 265 | |
dudmuck | 2:fdae76e1215e | 266 | |
dudmuck | 2:fdae76e1215e | 267 | uint8_t SX127x_lora::getSf(void) |
dudmuck | 2:fdae76e1215e | 268 | { |
dudmuck | 2:fdae76e1215e | 269 | // spreading factor same between sx127[26] |
dudmuck | 2:fdae76e1215e | 270 | return RegModemConfig2.sx1276bits.SpreadingFactor; |
dudmuck | 2:fdae76e1215e | 271 | } |
dudmuck | 2:fdae76e1215e | 272 | |
dudmuck | 2:fdae76e1215e | 273 | void SX127x_lora::set_nb_trig_peaks(int n) |
dudmuck | 2:fdae76e1215e | 274 | { |
dudmuck | 13:1953e70522aa | 275 | /* TODO: different requirements for RX_CONTINUOUS vs RX_SINGLE */ |
dudmuck | 2:fdae76e1215e | 276 | RegTest31.bits.detect_trig_same_peaks_nb = n; |
dudmuck | 2:fdae76e1215e | 277 | m_xcvr.write_reg(REG_LR_TEST31, RegTest31.octet); |
dudmuck | 2:fdae76e1215e | 278 | } |
dudmuck | 2:fdae76e1215e | 279 | |
dudmuck | 2:fdae76e1215e | 280 | |
dudmuck | 2:fdae76e1215e | 281 | void SX127x_lora::setSf(uint8_t sf) |
dudmuck | 2:fdae76e1215e | 282 | { |
dudmuck | 2:fdae76e1215e | 283 | if (!m_xcvr.RegOpMode.bits.LongRangeMode) |
dudmuck | 19:1ee6ef1ab73f | 284 | return; |
dudmuck | 19:1ee6ef1ab73f | 285 | |
dudmuck | 2:fdae76e1215e | 286 | // write register at 0x37 with value 0xc if at SF6 |
dudmuck | 2:fdae76e1215e | 287 | if (sf < 7) |
dudmuck | 2:fdae76e1215e | 288 | m_xcvr.write_reg(REG_LR_DETECTION_THRESHOLD, 0x0c); |
dudmuck | 2:fdae76e1215e | 289 | else |
dudmuck | 2:fdae76e1215e | 290 | m_xcvr.write_reg(REG_LR_DETECTION_THRESHOLD, 0x0a); |
dudmuck | 2:fdae76e1215e | 291 | |
dudmuck | 2:fdae76e1215e | 292 | RegModemConfig2.sx1276bits.SpreadingFactor = sf; // spreading factor same between sx127[26] |
dudmuck | 2:fdae76e1215e | 293 | m_xcvr.write_reg(REG_LR_MODEMCONFIG2, RegModemConfig2.octet); |
dudmuck | 2:fdae76e1215e | 294 | |
dudmuck | 2:fdae76e1215e | 295 | if (m_xcvr.type == SX1272) { |
dudmuck | 10:7382c260c4b1 | 296 | if (get_symbol_period() > 16) |
dudmuck | 2:fdae76e1215e | 297 | RegModemConfig.sx1272bits.LowDataRateOptimize = 1; |
dudmuck | 2:fdae76e1215e | 298 | else |
dudmuck | 2:fdae76e1215e | 299 | RegModemConfig.sx1272bits.LowDataRateOptimize = 0; |
dudmuck | 2:fdae76e1215e | 300 | m_xcvr.write_reg(REG_LR_MODEMCONFIG, RegModemConfig.octet); |
dudmuck | 2:fdae76e1215e | 301 | } else if (m_xcvr.type == SX1276) { |
dudmuck | 10:7382c260c4b1 | 302 | if (get_symbol_period() > 16) |
dudmuck | 2:fdae76e1215e | 303 | RegModemConfig3.sx1276bits.LowDataRateOptimize = 1; |
dudmuck | 2:fdae76e1215e | 304 | else |
dudmuck | 2:fdae76e1215e | 305 | RegModemConfig3.sx1276bits.LowDataRateOptimize = 0; |
dudmuck | 2:fdae76e1215e | 306 | m_xcvr.write_reg(REG_LR_MODEMCONFIG3, RegModemConfig3.octet); |
dudmuck | 2:fdae76e1215e | 307 | } |
dudmuck | 2:fdae76e1215e | 308 | } |
dudmuck | 2:fdae76e1215e | 309 | |
dudmuck | 2:fdae76e1215e | 310 | |
dudmuck | 2:fdae76e1215e | 311 | |
dudmuck | 2:fdae76e1215e | 312 | bool SX127x_lora::getRxPayloadCrcOn(void) |
dudmuck | 2:fdae76e1215e | 313 | { |
dudmuck | 2:fdae76e1215e | 314 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 315 | return RegModemConfig2.sx1276bits.RxPayloadCrcOn; |
dudmuck | 2:fdae76e1215e | 316 | else if (m_xcvr.type == SX1272) |
dudmuck | 2:fdae76e1215e | 317 | return RegModemConfig.sx1272bits.RxPayloadCrcOn; |
dudmuck | 2:fdae76e1215e | 318 | else |
dudmuck | 2:fdae76e1215e | 319 | return 0; |
dudmuck | 2:fdae76e1215e | 320 | } |
dudmuck | 2:fdae76e1215e | 321 | |
dudmuck | 2:fdae76e1215e | 322 | |
dudmuck | 2:fdae76e1215e | 323 | void SX127x_lora::setRxPayloadCrcOn(bool on) |
dudmuck | 2:fdae76e1215e | 324 | { |
dudmuck | 2:fdae76e1215e | 325 | if (m_xcvr.type == SX1276) { |
dudmuck | 2:fdae76e1215e | 326 | RegModemConfig2.sx1276bits.RxPayloadCrcOn = on; |
dudmuck | 2:fdae76e1215e | 327 | m_xcvr.write_reg(REG_LR_MODEMCONFIG2, RegModemConfig2.octet); |
dudmuck | 2:fdae76e1215e | 328 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 2:fdae76e1215e | 329 | RegModemConfig.sx1272bits.RxPayloadCrcOn = on; |
dudmuck | 2:fdae76e1215e | 330 | m_xcvr.write_reg(REG_LR_MODEMCONFIG, RegModemConfig.octet); |
dudmuck | 2:fdae76e1215e | 331 | } |
dudmuck | 2:fdae76e1215e | 332 | } |
dudmuck | 2:fdae76e1215e | 333 | |
dudmuck | 2:fdae76e1215e | 334 | |
dudmuck | 2:fdae76e1215e | 335 | |
dudmuck | 2:fdae76e1215e | 336 | bool SX127x_lora::getAgcAutoOn(void) |
dudmuck | 2:fdae76e1215e | 337 | { |
dudmuck | 2:fdae76e1215e | 338 | if (m_xcvr.type == SX1276) { |
dudmuck | 2:fdae76e1215e | 339 | RegModemConfig3.octet = m_xcvr.read_reg(REG_LR_MODEMCONFIG3); |
dudmuck | 2:fdae76e1215e | 340 | return RegModemConfig3.sx1276bits.AgcAutoOn; |
dudmuck | 2:fdae76e1215e | 341 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 2:fdae76e1215e | 342 | RegModemConfig2.octet = m_xcvr.read_reg(REG_LR_MODEMCONFIG2); |
dudmuck | 2:fdae76e1215e | 343 | return RegModemConfig2.sx1272bits.AgcAutoOn; |
dudmuck | 2:fdae76e1215e | 344 | } else |
dudmuck | 2:fdae76e1215e | 345 | return 0; |
dudmuck | 2:fdae76e1215e | 346 | } |
dudmuck | 2:fdae76e1215e | 347 | |
dudmuck | 2:fdae76e1215e | 348 | void SX127x_lora::setAgcAutoOn(bool on) |
dudmuck | 2:fdae76e1215e | 349 | { |
dudmuck | 2:fdae76e1215e | 350 | if (m_xcvr.type == SX1276) { |
dudmuck | 2:fdae76e1215e | 351 | RegModemConfig3.sx1276bits.AgcAutoOn = on; |
dudmuck | 2:fdae76e1215e | 352 | m_xcvr.write_reg(REG_LR_MODEMCONFIG3, RegModemConfig3.octet); |
dudmuck | 2:fdae76e1215e | 353 | } else if (m_xcvr.type == SX1272) { |
dudmuck | 2:fdae76e1215e | 354 | RegModemConfig2.sx1272bits.AgcAutoOn = on; |
dudmuck | 2:fdae76e1215e | 355 | m_xcvr.write_reg(REG_LR_MODEMCONFIG2, RegModemConfig2.octet); |
dudmuck | 2:fdae76e1215e | 356 | } |
dudmuck | 2:fdae76e1215e | 357 | |
dudmuck | 2:fdae76e1215e | 358 | } |
dudmuck | 2:fdae76e1215e | 359 | |
dudmuck | 17:59279bc8cdab | 360 | void SX127x_lora::invert_tx(bool inv) |
dudmuck | 17:59279bc8cdab | 361 | { |
dudmuck | 17:59279bc8cdab | 362 | RegTest33.bits.chirp_invert_tx = !inv; |
dudmuck | 17:59279bc8cdab | 363 | m_xcvr.write_reg(REG_LR_TEST33, RegTest33.octet); |
dudmuck | 17:59279bc8cdab | 364 | } |
dudmuck | 17:59279bc8cdab | 365 | |
dudmuck | 17:59279bc8cdab | 366 | void SX127x_lora::invert_rx(bool inv) |
dudmuck | 17:59279bc8cdab | 367 | { |
dudmuck | 17:59279bc8cdab | 368 | RegTest33.bits.invert_i_q = inv; |
dudmuck | 17:59279bc8cdab | 369 | m_xcvr.write_reg(REG_LR_TEST33, RegTest33.octet); |
dudmuck | 17:59279bc8cdab | 370 | /**/ |
dudmuck | 17:59279bc8cdab | 371 | RegDriftInvert.bits.invert_timing_error_per_symbol = !RegTest33.bits.invert_i_q; |
dudmuck | 17:59279bc8cdab | 372 | m_xcvr.write_reg(REG_LR_DRIFT_INVERT, RegDriftInvert.octet); |
dudmuck | 17:59279bc8cdab | 373 | } |
dudmuck | 17:59279bc8cdab | 374 | |
dudmuck | 2:fdae76e1215e | 375 | void SX127x_lora::start_tx(uint8_t len) |
dudmuck | 7:927a05f84ede | 376 | { |
dudmuck | 2:fdae76e1215e | 377 | // DIO0 to TxDone |
dudmuck | 2:fdae76e1215e | 378 | if (m_xcvr.RegDioMapping1.bits.Dio0Mapping != 1) { |
dudmuck | 2:fdae76e1215e | 379 | m_xcvr.RegDioMapping1.bits.Dio0Mapping = 1; |
dudmuck | 2:fdae76e1215e | 380 | m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet); |
dudmuck | 2:fdae76e1215e | 381 | } |
dudmuck | 2:fdae76e1215e | 382 | |
dudmuck | 2:fdae76e1215e | 383 | // set FifoPtrAddr to FifoTxPtrBase |
dudmuck | 2:fdae76e1215e | 384 | m_xcvr.write_reg(REG_LR_FIFOADDRPTR, m_xcvr.read_reg(REG_LR_FIFOTXBASEADDR)); |
dudmuck | 2:fdae76e1215e | 385 | |
dudmuck | 2:fdae76e1215e | 386 | // write PayloadLength bytes to fifo |
dudmuck | 2:fdae76e1215e | 387 | write_fifo(len); |
dudmuck | 7:927a05f84ede | 388 | |
dudmuck | 2:fdae76e1215e | 389 | m_xcvr.set_opmode(RF_OPMODE_TRANSMITTER); |
dudmuck | 2:fdae76e1215e | 390 | } |
dudmuck | 2:fdae76e1215e | 391 | |
dudmuck | 2:fdae76e1215e | 392 | void SX127x_lora::start_rx() |
dudmuck | 2:fdae76e1215e | 393 | { |
dudmuck | 2:fdae76e1215e | 394 | if (!m_xcvr.RegOpMode.bits.LongRangeMode) |
dudmuck | 12:bda42457c34a | 395 | return; // fsk mode |
dudmuck | 12:bda42457c34a | 396 | if (m_xcvr.RegOpMode.sx1276LORAbits.AccessSharedReg) |
dudmuck | 12:bda42457c34a | 397 | return; // fsk page |
dudmuck | 13:1953e70522aa | 398 | |
dudmuck | 19:1ee6ef1ab73f | 399 | if (m_xcvr.type == SX1276) { |
dudmuck | 19:1ee6ef1ab73f | 400 | if (RegModemConfig.sx1276bits.Bw == 9) { // if 500KHz bw: improved tolerance of reference frequency error |
dudmuck | 19:1ee6ef1ab73f | 401 | if (RegAutoDrift.bits.freq_to_time_drift_auto) { |
dudmuck | 19:1ee6ef1ab73f | 402 | RegAutoDrift.bits.freq_to_time_drift_auto = 0; |
dudmuck | 19:1ee6ef1ab73f | 403 | m_xcvr.write_reg(REG_LR_SX1276_AUTO_DRIFT, RegAutoDrift.octet); |
dudmuck | 19:1ee6ef1ab73f | 404 | } |
dudmuck | 19:1ee6ef1ab73f | 405 | if (m_xcvr.HF) { |
dudmuck | 19:1ee6ef1ab73f | 406 | // > 525MHz |
dudmuck | 19:1ee6ef1ab73f | 407 | if (RegGainDrift.bits.freq_to_time_drift != 0x24) { |
dudmuck | 19:1ee6ef1ab73f | 408 | RegGainDrift.bits.freq_to_time_drift = 0x24; |
dudmuck | 19:1ee6ef1ab73f | 409 | m_xcvr.write_reg(REG_LR_GAIN_DRIFT, RegGainDrift.octet); |
dudmuck | 19:1ee6ef1ab73f | 410 | } |
dudmuck | 19:1ee6ef1ab73f | 411 | } else { |
dudmuck | 19:1ee6ef1ab73f | 412 | // < 525MHz |
dudmuck | 19:1ee6ef1ab73f | 413 | if (RegGainDrift.bits.freq_to_time_drift != 0x3f) { |
dudmuck | 19:1ee6ef1ab73f | 414 | RegGainDrift.bits.freq_to_time_drift = 0x3f; |
dudmuck | 19:1ee6ef1ab73f | 415 | m_xcvr.write_reg(REG_LR_GAIN_DRIFT, RegGainDrift.octet); |
dudmuck | 19:1ee6ef1ab73f | 416 | } |
dudmuck | 19:1ee6ef1ab73f | 417 | } |
dudmuck | 19:1ee6ef1ab73f | 418 | |
dudmuck | 19:1ee6ef1ab73f | 419 | } else { |
dudmuck | 19:1ee6ef1ab73f | 420 | if (!RegAutoDrift.bits.freq_to_time_drift_auto) { |
dudmuck | 19:1ee6ef1ab73f | 421 | RegAutoDrift.bits.freq_to_time_drift_auto = 1; |
dudmuck | 19:1ee6ef1ab73f | 422 | m_xcvr.write_reg(REG_LR_SX1276_AUTO_DRIFT, RegAutoDrift.octet); |
dudmuck | 19:1ee6ef1ab73f | 423 | } |
dudmuck | 19:1ee6ef1ab73f | 424 | } |
dudmuck | 19:1ee6ef1ab73f | 425 | } // ... if (m_xcvr.type == SX1276) |
dudmuck | 19:1ee6ef1ab73f | 426 | |
dudmuck | 19:1ee6ef1ab73f | 427 | // RX_CONTINUOUS: false detections vs missed detections tradeoff |
dudmuck | 19:1ee6ef1ab73f | 428 | switch (RegModemConfig2.sx1276bits.SpreadingFactor) { |
dudmuck | 19:1ee6ef1ab73f | 429 | case 6: |
dudmuck | 19:1ee6ef1ab73f | 430 | set_nb_trig_peaks(3); |
dudmuck | 19:1ee6ef1ab73f | 431 | break; |
dudmuck | 19:1ee6ef1ab73f | 432 | case 7: |
dudmuck | 19:1ee6ef1ab73f | 433 | set_nb_trig_peaks(4); |
dudmuck | 19:1ee6ef1ab73f | 434 | break; |
dudmuck | 19:1ee6ef1ab73f | 435 | default: |
dudmuck | 19:1ee6ef1ab73f | 436 | set_nb_trig_peaks(5); |
dudmuck | 19:1ee6ef1ab73f | 437 | break; |
dudmuck | 19:1ee6ef1ab73f | 438 | } |
dudmuck | 19:1ee6ef1ab73f | 439 | |
dudmuck | 13:1953e70522aa | 440 | m_xcvr.set_opmode(RF_OPMODE_RECEIVER); |
dudmuck | 2:fdae76e1215e | 441 | |
dudmuck | 2:fdae76e1215e | 442 | if (m_xcvr.RegDioMapping1.bits.Dio0Mapping != 0) { |
dudmuck | 2:fdae76e1215e | 443 | m_xcvr.RegDioMapping1.bits.Dio0Mapping = 0; // DIO0 to RxDone |
dudmuck | 2:fdae76e1215e | 444 | m_xcvr.write_reg(REG_DIOMAPPING1, m_xcvr.RegDioMapping1.octet); |
dudmuck | 2:fdae76e1215e | 445 | } |
dudmuck | 2:fdae76e1215e | 446 | |
dudmuck | 2:fdae76e1215e | 447 | m_xcvr.write_reg(REG_LR_FIFOADDRPTR, m_xcvr.read_reg(REG_LR_FIFORXBASEADDR)); |
dudmuck | 2:fdae76e1215e | 448 | } |
dudmuck | 2:fdae76e1215e | 449 | |
dudmuck | 2:fdae76e1215e | 450 | float SX127x_lora::get_pkt_rssi() |
dudmuck | 2:fdae76e1215e | 451 | { |
dudmuck | 2:fdae76e1215e | 452 | /* TODO: calculating with pktSNR to give meaningful result below noise floor */ |
dudmuck | 2:fdae76e1215e | 453 | if (m_xcvr.type == SX1276) |
dudmuck | 2:fdae76e1215e | 454 | return RegPktRssiValue - 137; |
dudmuck | 2:fdae76e1215e | 455 | else |
dudmuck | 2:fdae76e1215e | 456 | return RegPktRssiValue - 125; |
dudmuck | 2:fdae76e1215e | 457 | } |
dudmuck | 2:fdae76e1215e | 458 | |
dudmuck | 2:fdae76e1215e | 459 | service_action_e SX127x_lora::service() |
dudmuck | 2:fdae76e1215e | 460 | { |
dudmuck | 2:fdae76e1215e | 461 | if (m_xcvr.RegOpMode.bits.Mode == RF_OPMODE_RECEIVER) { |
dudmuck | 2:fdae76e1215e | 462 | if (poll_vh) { |
dudmuck | 2:fdae76e1215e | 463 | RegIrqFlags.octet = m_xcvr.read_reg(REG_LR_IRQFLAGS); |
dudmuck | 2:fdae76e1215e | 464 | if (RegIrqFlags.bits.ValidHeader) { |
dudmuck | 2:fdae76e1215e | 465 | RegIrqFlags.octet = 0; |
dudmuck | 2:fdae76e1215e | 466 | RegIrqFlags.bits.ValidHeader = 1; |
dudmuck | 2:fdae76e1215e | 467 | m_xcvr.write_reg(REG_LR_IRQFLAGS, RegIrqFlags.octet); |
dudmuck | 2:fdae76e1215e | 468 | printf("VH\r\n"); |
dudmuck | 2:fdae76e1215e | 469 | } |
dudmuck | 2:fdae76e1215e | 470 | } |
dudmuck | 2:fdae76e1215e | 471 | } |
dudmuck | 7:927a05f84ede | 472 | |
dudmuck | 2:fdae76e1215e | 473 | if (m_xcvr.dio0 == 0) |
dudmuck | 2:fdae76e1215e | 474 | return SERVICE_NONE; |
dudmuck | 2:fdae76e1215e | 475 | |
dudmuck | 2:fdae76e1215e | 476 | switch (m_xcvr.RegDioMapping1.bits.Dio0Mapping) { |
dudmuck | 2:fdae76e1215e | 477 | case 0: // RxDone |
dudmuck | 2:fdae76e1215e | 478 | /* user checks for CRC error in IrqFlags */ |
dudmuck | 2:fdae76e1215e | 479 | RegIrqFlags.octet = m_xcvr.read_reg(REG_LR_IRQFLAGS); // save flags |
dudmuck | 2:fdae76e1215e | 480 | RegHopChannel.octet = m_xcvr.read_reg(REG_LR_HOPCHANNEL); |
dudmuck | 2:fdae76e1215e | 481 | //printf("[%02x]", RegIrqFlags.octet); |
dudmuck | 2:fdae76e1215e | 482 | m_xcvr.write_reg(REG_LR_IRQFLAGS, RegIrqFlags.octet); // clear flags in radio |
dudmuck | 2:fdae76e1215e | 483 | |
dudmuck | 2:fdae76e1215e | 484 | /* any register of interest on received packet is read(saved) here */ |
dudmuck | 2:fdae76e1215e | 485 | RegModemStatus.octet = m_xcvr.read_reg(REG_LR_MODEMSTAT); |
dudmuck | 2:fdae76e1215e | 486 | RegPktSnrValue = m_xcvr.read_reg(REG_LR_PKTSNRVALUE); |
dudmuck | 2:fdae76e1215e | 487 | RegPktRssiValue = m_xcvr.read_reg(REG_LR_PKTRSSIVALUE); |
dudmuck | 2:fdae76e1215e | 488 | RegRxNbBytes = m_xcvr.read_reg(REG_LR_RXNBBYTES); |
dudmuck | 2:fdae76e1215e | 489 | |
dudmuck | 2:fdae76e1215e | 490 | m_xcvr.write_reg(REG_LR_FIFOADDRPTR, m_xcvr.read_reg(REG_LR_FIFORXCURRENTADDR)); |
dudmuck | 2:fdae76e1215e | 491 | read_fifo(RegRxNbBytes); |
dudmuck | 2:fdae76e1215e | 492 | return SERVICE_READ_FIFO; |
dudmuck | 2:fdae76e1215e | 493 | case 1: // TxDone |
dudmuck | 2:fdae76e1215e | 494 | RegIrqFlags.octet = 0; |
dudmuck | 2:fdae76e1215e | 495 | RegIrqFlags.bits.TxDone = 1; |
dudmuck | 2:fdae76e1215e | 496 | m_xcvr.write_reg(REG_LR_IRQFLAGS, RegIrqFlags.octet); |
dudmuck | 2:fdae76e1215e | 497 | return SERVICE_TX_DONE; |
dudmuck | 2:fdae76e1215e | 498 | } // ...switch (RegDioMapping1.bits.Dio0Mapping) |
dudmuck | 2:fdae76e1215e | 499 | |
dudmuck | 2:fdae76e1215e | 500 | return SERVICE_ERROR; |
dudmuck | 12:bda42457c34a | 501 | } |
dudmuck | 12:bda42457c34a | 502 |