123
sx12xx.h@37:5bc5e77d71d2, 2022-06-06 (annotated)
- Committer:
- advxolltm
- Date:
- Mon Jun 06 09:26:05 2022 +0000
- Revision:
- 37:5bc5e77d71d2
- Parent:
- 35:cd54c52c6003
123;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Wayne Roberts |
33:4b9fd8969428 | 1 | /* SX127x driver |
Wayne Roberts |
33:4b9fd8969428 | 2 | * Copyright (c) 2013 Semtech |
Wayne Roberts |
33:4b9fd8969428 | 3 | * |
Wayne Roberts |
33:4b9fd8969428 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
Wayne Roberts |
33:4b9fd8969428 | 5 | * you may not use this file except in compliance with the License. |
Wayne Roberts |
33:4b9fd8969428 | 6 | * You may obtain a copy of the License at |
Wayne Roberts |
33:4b9fd8969428 | 7 | * |
Wayne Roberts |
33:4b9fd8969428 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
Wayne Roberts |
33:4b9fd8969428 | 9 | * |
Wayne Roberts |
33:4b9fd8969428 | 10 | * Unless required by applicable law or agreed to in writing, software |
Wayne Roberts |
33:4b9fd8969428 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
Wayne Roberts |
33:4b9fd8969428 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Wayne Roberts |
33:4b9fd8969428 | 13 | * See the License for the specific language governing permissions and |
Wayne Roberts |
33:4b9fd8969428 | 14 | * limitations under the License. |
Wayne Roberts |
33:4b9fd8969428 | 15 | */ |
Wayne Roberts |
33:4b9fd8969428 | 16 | |
Wayne Roberts |
33:4b9fd8969428 | 17 | #ifndef SX127x_H |
Wayne Roberts |
33:4b9fd8969428 | 18 | #define SX127x_H |
Wayne Roberts |
33:4b9fd8969428 | 19 | |
Wayne Roberts |
33:4b9fd8969428 | 20 | #include "mbed.h" |
Wayne Roberts |
33:4b9fd8969428 | 21 | |
Wayne Roberts |
33:4b9fd8969428 | 22 | #define XTAL_FREQ 32000000 |
Wayne Roberts |
33:4b9fd8969428 | 23 | |
Wayne Roberts |
33:4b9fd8969428 | 24 | #define FREQ_STEP_MHZ 61.03515625e-6 // 32 / (2^19) |
Wayne Roberts |
33:4b9fd8969428 | 25 | #define FREQ_STEP_KHZ 61.03515625e-3 // 32e3 / (2^19) |
Wayne Roberts |
33:4b9fd8969428 | 26 | #define FREQ_STEP_HZ 61.03515625 // 32e6 / (2^19) |
Wayne Roberts |
33:4b9fd8969428 | 27 | |
Wayne Roberts |
33:4b9fd8969428 | 28 | #define MHZ_TO_FRF(m) (m / FREQ_STEP_MHZ) |
Wayne Roberts |
33:4b9fd8969428 | 29 | |
Wayne Roberts |
33:4b9fd8969428 | 30 | /******************************************************************************/ |
Wayne Roberts |
33:4b9fd8969428 | 31 | /*! |
Wayne Roberts |
33:4b9fd8969428 | 32 | * SX127x Internal registers Address |
Wayne Roberts |
33:4b9fd8969428 | 33 | */ |
Wayne Roberts |
33:4b9fd8969428 | 34 | #define REG_FIFO 0x00 |
Wayne Roberts |
33:4b9fd8969428 | 35 | #define REG_OPMODE 0x01 |
Wayne Roberts |
33:4b9fd8969428 | 36 | #define REG_FRFMSB 0x06 |
Wayne Roberts |
33:4b9fd8969428 | 37 | #define REG_FRFMID 0x07 |
Wayne Roberts |
33:4b9fd8969428 | 38 | #define REG_FRFLSB 0x08 |
Wayne Roberts |
33:4b9fd8969428 | 39 | // Tx settings |
Wayne Roberts |
33:4b9fd8969428 | 40 | #define REG_PACONFIG 0x09 |
Wayne Roberts |
33:4b9fd8969428 | 41 | #define REG_PARAMP 0x0A |
Wayne Roberts |
33:4b9fd8969428 | 42 | #define REG_OCP 0x0B |
Wayne Roberts |
33:4b9fd8969428 | 43 | // Rx settings |
Wayne Roberts |
33:4b9fd8969428 | 44 | #define REG_LNA 0x0C |
Wayne Roberts |
33:4b9fd8969428 | 45 | |
Wayne Roberts |
33:4b9fd8969428 | 46 | |
Wayne Roberts |
33:4b9fd8969428 | 47 | /***** registers above 0x40 are same as FSK/OOK page */ |
Wayne Roberts |
33:4b9fd8969428 | 48 | |
Wayne Roberts |
33:4b9fd8969428 | 49 | #define REG_DIOMAPPING1 0x40 |
Wayne Roberts |
33:4b9fd8969428 | 50 | #define REG_DIOMAPPING2 0x41 |
Wayne Roberts |
33:4b9fd8969428 | 51 | #define REG_VERSION 0x42 |
Wayne Roberts |
33:4b9fd8969428 | 52 | |
Wayne Roberts |
35:cd54c52c6003 | 53 | #define REG_PATEST_SX1276 0x44 |
Wayne Roberts |
35:cd54c52c6003 | 54 | #define REG_PATEST_SX1272 0x4b |
Wayne Roberts |
33:4b9fd8969428 | 55 | #define REG_PDSTRIM1_SX1276 0x4d |
Wayne Roberts |
33:4b9fd8969428 | 56 | #define REG_PDSTRIM1_SX1272 0x5a |
Wayne Roberts |
33:4b9fd8969428 | 57 | #define REG_PLL_SX1272 0x5c // RX PLL bandwidth |
Wayne Roberts |
33:4b9fd8969428 | 58 | #define REG_PLL_LOWPN_SX1272 0x5e |
Wayne Roberts |
33:4b9fd8969428 | 59 | #define REG_PLL_SX1276 0x70 |
Wayne Roberts |
33:4b9fd8969428 | 60 | #define REG_BSYNCTST2 0x67 |
Wayne Roberts |
33:4b9fd8969428 | 61 | /******************************************************************************/ |
Wayne Roberts |
33:4b9fd8969428 | 62 | |
Wayne Roberts |
33:4b9fd8969428 | 63 | |
Wayne Roberts |
33:4b9fd8969428 | 64 | typedef enum { |
Wayne Roberts |
33:4b9fd8969428 | 65 | RF_OPMODE_SLEEP = 0, |
Wayne Roberts |
33:4b9fd8969428 | 66 | RF_OPMODE_STANDBY, // 1 |
Wayne Roberts |
33:4b9fd8969428 | 67 | RF_OPMODE_SYNTHESIZER_TX, // 2 |
Wayne Roberts |
33:4b9fd8969428 | 68 | RF_OPMODE_TRANSMITTER, // 3 |
Wayne Roberts |
33:4b9fd8969428 | 69 | RF_OPMODE_SYNTHESIZER_RX, // 4 |
Wayne Roberts |
33:4b9fd8969428 | 70 | RF_OPMODE_RECEIVER, // 5 |
Wayne Roberts |
33:4b9fd8969428 | 71 | RF_OPMODE_RECEIVER_SINGLE, // 6 |
Wayne Roberts |
33:4b9fd8969428 | 72 | RF_OPMODE_CAD // 7 |
Wayne Roberts |
33:4b9fd8969428 | 73 | } chip_mode_e; |
Wayne Roberts |
33:4b9fd8969428 | 74 | |
Wayne Roberts |
33:4b9fd8969428 | 75 | typedef enum { |
Wayne Roberts |
33:4b9fd8969428 | 76 | SX_NONE = 0, |
Wayne Roberts |
33:4b9fd8969428 | 77 | SX1272, |
Wayne Roberts |
33:4b9fd8969428 | 78 | SX1276 |
Wayne Roberts |
33:4b9fd8969428 | 79 | } type_e; |
Wayne Roberts |
33:4b9fd8969428 | 80 | |
Wayne Roberts |
33:4b9fd8969428 | 81 | typedef enum { |
Wayne Roberts |
33:4b9fd8969428 | 82 | SERVICE_NONE = 0, |
Wayne Roberts |
33:4b9fd8969428 | 83 | SERVICE_ERROR, |
Wayne Roberts |
33:4b9fd8969428 | 84 | //! request to call read_fifo() |
Wayne Roberts |
33:4b9fd8969428 | 85 | SERVICE_READ_FIFO, |
Wayne Roberts |
33:4b9fd8969428 | 86 | //! notification to application of transmit complete |
Wayne Roberts |
33:4b9fd8969428 | 87 | SERVICE_TX_DONE |
Wayne Roberts |
33:4b9fd8969428 | 88 | } service_action_e; |
Wayne Roberts |
33:4b9fd8969428 | 89 | |
Wayne Roberts |
33:4b9fd8969428 | 90 | /******************************************************************************/ |
Wayne Roberts |
33:4b9fd8969428 | 91 | |
Wayne Roberts |
33:4b9fd8969428 | 92 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 93 | struct { // sx1272 register 0x01 |
Wayne Roberts |
33:4b9fd8969428 | 94 | uint8_t Mode : 3; // 0,1,2 |
Wayne Roberts |
33:4b9fd8969428 | 95 | uint8_t ModulationShaping : 2; // 3,4 FSK/OOK |
Wayne Roberts |
33:4b9fd8969428 | 96 | uint8_t ModulationType : 2; // 5,6 FSK/OOK |
Wayne Roberts |
33:4b9fd8969428 | 97 | uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode |
Wayne Roberts |
33:4b9fd8969428 | 98 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 99 | struct { // sx1276 register 0x01 |
Wayne Roberts |
33:4b9fd8969428 | 100 | uint8_t Mode : 3; // 0,1,2 |
Wayne Roberts |
33:4b9fd8969428 | 101 | uint8_t LowFrequencyModeOn : 1; // 3 1=access to LF test registers (0=HF regs) |
Wayne Roberts |
33:4b9fd8969428 | 102 | uint8_t reserved : 1; // 4 |
Wayne Roberts |
33:4b9fd8969428 | 103 | uint8_t ModulationType : 2; // 5,6 FSK/OOK |
Wayne Roberts |
33:4b9fd8969428 | 104 | uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode |
Wayne Roberts |
33:4b9fd8969428 | 105 | } sx1276FSKbits; |
Wayne Roberts |
33:4b9fd8969428 | 106 | struct { // sx1276 register 0x01 |
Wayne Roberts |
33:4b9fd8969428 | 107 | uint8_t Mode : 3; // 0,1,2 |
Wayne Roberts |
33:4b9fd8969428 | 108 | uint8_t LowFrequencyModeOn : 1; // 3 1=access to LF test registers (0=HF regs) |
Wayne Roberts |
33:4b9fd8969428 | 109 | uint8_t reserved : 2; // 4,5 |
Wayne Roberts |
33:4b9fd8969428 | 110 | uint8_t AccessSharedReg : 1; // 6 1=FSK registers while in LoRa mode |
Wayne Roberts |
33:4b9fd8969428 | 111 | uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode |
Wayne Roberts |
33:4b9fd8969428 | 112 | } sx1276LORAbits; |
Wayne Roberts |
33:4b9fd8969428 | 113 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 114 | } RegOpMode_t; |
Wayne Roberts |
33:4b9fd8969428 | 115 | |
Wayne Roberts |
33:4b9fd8969428 | 116 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 117 | struct { // sx12xx register 0x09 |
Wayne Roberts |
33:4b9fd8969428 | 118 | uint8_t OutputPower : 4; // 0,1,2,3 |
Wayne Roberts |
33:4b9fd8969428 | 119 | uint8_t MaxPower : 3; // 4,5,6 |
Wayne Roberts |
33:4b9fd8969428 | 120 | uint8_t PaSelect : 1; // 7 1=PA_BOOST |
Wayne Roberts |
33:4b9fd8969428 | 121 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 122 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 123 | } RegPaConfig_t; |
Wayne Roberts |
33:4b9fd8969428 | 124 | |
Wayne Roberts |
33:4b9fd8969428 | 125 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 126 | struct { // sx12xx register 0x0b |
Wayne Roberts |
33:4b9fd8969428 | 127 | uint8_t OcpTrim : 5; // 0,1,2,3,4 |
Wayne Roberts |
33:4b9fd8969428 | 128 | uint8_t OcpOn : 1; // 5 |
Wayne Roberts |
33:4b9fd8969428 | 129 | uint8_t unused : 2; // 6,7 |
Wayne Roberts |
33:4b9fd8969428 | 130 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 131 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 132 | } RegOcp_t; |
Wayne Roberts |
33:4b9fd8969428 | 133 | |
Wayne Roberts |
33:4b9fd8969428 | 134 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 135 | struct { // sx12xx register 0x0c |
Wayne Roberts |
33:4b9fd8969428 | 136 | uint8_t LnaBoostHF : 2; // 0,1 |
Wayne Roberts |
33:4b9fd8969428 | 137 | uint8_t reserved : 1; // 2 |
Wayne Roberts |
33:4b9fd8969428 | 138 | uint8_t LnaBoostLF : 2; // 3,4 |
Wayne Roberts |
33:4b9fd8969428 | 139 | uint8_t LnaGain : 3; // 5,6,7 |
Wayne Roberts |
33:4b9fd8969428 | 140 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 141 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 142 | } RegLna_t; // RXFE |
Wayne Roberts |
33:4b9fd8969428 | 143 | |
Wayne Roberts |
33:4b9fd8969428 | 144 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 145 | struct { // sx127x register 0x0a |
Wayne Roberts |
33:4b9fd8969428 | 146 | uint8_t PaRamp : 4; // 0,1,2,3 |
Wayne Roberts |
33:4b9fd8969428 | 147 | uint8_t LowPnTxPllOff : 1; // 4 sx1272 only |
Wayne Roberts |
33:4b9fd8969428 | 148 | uint8_t ModulationShaping : 2; // 5,6 sx1276 only |
Wayne Roberts |
33:4b9fd8969428 | 149 | uint8_t unused : 1; // 7 |
Wayne Roberts |
33:4b9fd8969428 | 150 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 151 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 152 | } RegPaRamp_t; // |
Wayne Roberts |
33:4b9fd8969428 | 153 | |
Wayne Roberts |
33:4b9fd8969428 | 154 | /*********************** ****************************/ |
Wayne Roberts |
33:4b9fd8969428 | 155 | |
Wayne Roberts |
33:4b9fd8969428 | 156 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 157 | struct { // sx12xx register 0x40 |
Wayne Roberts |
33:4b9fd8969428 | 158 | uint8_t Dio3Mapping : 2; // 0,1 |
Wayne Roberts |
33:4b9fd8969428 | 159 | uint8_t Dio2Mapping : 2; // 2,3 |
Wayne Roberts |
33:4b9fd8969428 | 160 | uint8_t Dio1Mapping : 2; // 4,5 |
Wayne Roberts |
33:4b9fd8969428 | 161 | uint8_t Dio0Mapping : 2; // 6,7 |
Wayne Roberts |
33:4b9fd8969428 | 162 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 163 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 164 | } RegDioMapping1_t; |
Wayne Roberts |
33:4b9fd8969428 | 165 | |
Wayne Roberts |
33:4b9fd8969428 | 166 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 167 | struct { // sx12xx register 0x41 |
Wayne Roberts |
33:4b9fd8969428 | 168 | uint8_t MapPreambleDetect : 1; // 0 //DIO4 assign: 1b=preambleDet 0b=rssiThresh |
Wayne Roberts |
33:4b9fd8969428 | 169 | uint8_t io_mode : 3; // 1,2,3 //0=normal,1=debug,2=fpga,3=pll_tx,4=pll_rx,5=analog |
Wayne Roberts |
33:4b9fd8969428 | 170 | uint8_t Dio5Mapping : 2; // 4,5 |
Wayne Roberts |
33:4b9fd8969428 | 171 | uint8_t Dio4Mapping : 2; // 6,7 |
Wayne Roberts |
33:4b9fd8969428 | 172 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 173 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 174 | } RegDioMapping2_t; |
Wayne Roberts |
33:4b9fd8969428 | 175 | |
Wayne Roberts |
33:4b9fd8969428 | 176 | /***************************************************/ |
Wayne Roberts |
33:4b9fd8969428 | 177 | |
Wayne Roberts |
33:4b9fd8969428 | 178 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 179 | struct { // sx1272 register 0x5a (sx1276 0x4d) |
Wayne Roberts |
33:4b9fd8969428 | 180 | uint8_t prog_txdac : 3; // 0,1,2 BGR ref current to PA DAC |
Wayne Roberts |
33:4b9fd8969428 | 181 | uint8_t pds_analog_test : 1; // 3 |
Wayne Roberts |
33:4b9fd8969428 | 182 | uint8_t pds_pa_test : 2; // 4,5 |
Wayne Roberts |
33:4b9fd8969428 | 183 | uint8_t pds_ptat : 2; // 6,7 leave at 2 (5uA) |
Wayne Roberts |
33:4b9fd8969428 | 184 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 185 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 186 | } RegPdsTrim1_t; |
Wayne Roberts |
33:4b9fd8969428 | 187 | |
Wayne Roberts |
33:4b9fd8969428 | 188 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 189 | struct { // sx1272 register 0x5c |
Wayne Roberts |
33:4b9fd8969428 | 190 | uint8_t reserved : 6; // 0->5 |
Wayne Roberts |
33:4b9fd8969428 | 191 | uint8_t PllBandwidth : 2; // 6,7 |
Wayne Roberts |
33:4b9fd8969428 | 192 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 193 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 194 | } RegPll_t; |
Wayne Roberts |
33:4b9fd8969428 | 195 | |
Wayne Roberts |
33:4b9fd8969428 | 196 | typedef union { |
Wayne Roberts |
33:4b9fd8969428 | 197 | struct { // sx1272 register 0x67 |
Wayne Roberts |
33:4b9fd8969428 | 198 | uint8_t bsync_mode : 3; // 0,1,2 |
Wayne Roberts |
33:4b9fd8969428 | 199 | uint8_t reserved : 1; // 3 |
Wayne Roberts |
33:4b9fd8969428 | 200 | uint8_t bsync_thresh_validity : 1; // 4 |
Wayne Roberts |
33:4b9fd8969428 | 201 | uint8_t unused : 3; // 5,6,7 |
Wayne Roberts |
33:4b9fd8969428 | 202 | } bits; |
Wayne Roberts |
33:4b9fd8969428 | 203 | uint8_t octet; |
Wayne Roberts |
33:4b9fd8969428 | 204 | } RegBsyncTest2_t; |
Wayne Roberts |
33:4b9fd8969428 | 205 | |
Wayne Roberts |
33:4b9fd8969428 | 206 | /** FSK/LoRa radio transceiver. |
Wayne Roberts |
33:4b9fd8969428 | 207 | * see http://en.wikipedia.org/wiki/Chirp_spread_spectrum |
Wayne Roberts |
33:4b9fd8969428 | 208 | */ |
Wayne Roberts |
33:4b9fd8969428 | 209 | |
Wayne Roberts |
33:4b9fd8969428 | 210 | class SX127x { |
Wayne Roberts |
33:4b9fd8969428 | 211 | public: |
Wayne Roberts |
33:4b9fd8969428 | 212 | /** Create SX127x instance |
Wayne Roberts |
33:4b9fd8969428 | 213 | * @param mosi SPI master-out pin |
Wayne Roberts |
33:4b9fd8969428 | 214 | * @param miso SPI master-in pin |
Wayne Roberts |
33:4b9fd8969428 | 215 | * @param sclk SPI clock pin |
Wayne Roberts |
33:4b9fd8969428 | 216 | * @param cs SPI chip-select pin |
Wayne Roberts |
33:4b9fd8969428 | 217 | * @param rst radio hardware reset pin |
Wayne Roberts |
33:4b9fd8969428 | 218 | * @param dio_0 interrupt pin from radio |
Wayne Roberts |
33:4b9fd8969428 | 219 | * @param fem_ctx rx-tx switch for HF bands (800/900) |
Wayne Roberts |
33:4b9fd8969428 | 220 | * @param fem_cps rx-tx switch for LF bands (vhf/433) |
Wayne Roberts |
33:4b9fd8969428 | 221 | */ |
Wayne Roberts |
33:4b9fd8969428 | 222 | |
Wayne Roberts |
33:4b9fd8969428 | 223 | SX127x(PinName dio0, PinName dio_1, PinName cs, SPI&, PinName rst); |
Wayne Roberts |
33:4b9fd8969428 | 224 | |
Wayne Roberts |
33:4b9fd8969428 | 225 | ~SX127x(); |
Wayne Roberts |
33:4b9fd8969428 | 226 | |
Wayne Roberts |
33:4b9fd8969428 | 227 | /** set center operating frequency |
Wayne Roberts |
33:4b9fd8969428 | 228 | * @param MHz operating frequency in MHz |
Wayne Roberts |
33:4b9fd8969428 | 229 | */ |
Wayne Roberts |
33:4b9fd8969428 | 230 | void set_frf_MHz( float MHz ); |
Wayne Roberts |
33:4b9fd8969428 | 231 | |
Wayne Roberts |
33:4b9fd8969428 | 232 | /** get center operating frequency |
Wayne Roberts |
33:4b9fd8969428 | 233 | * @returns operating frequency in MHz |
Wayne Roberts |
33:4b9fd8969428 | 234 | */ |
Wayne Roberts |
33:4b9fd8969428 | 235 | float get_frf_MHz(void); |
Wayne Roberts |
33:4b9fd8969428 | 236 | |
Wayne Roberts |
33:4b9fd8969428 | 237 | void set_opmode(chip_mode_e mode); |
Wayne Roberts |
33:4b9fd8969428 | 238 | |
Wayne Roberts |
33:4b9fd8969428 | 239 | /** reset radio using pin |
Wayne Roberts |
33:4b9fd8969428 | 240 | */ |
Wayne Roberts |
33:4b9fd8969428 | 241 | void hw_reset(void); |
Wayne Roberts |
33:4b9fd8969428 | 242 | /** initialise SX1232 class to radio |
Wayne Roberts |
33:4b9fd8969428 | 243 | * @note this is called from class instantiation, but must also be manually called after hardware reset |
Wayne Roberts |
33:4b9fd8969428 | 244 | */ |
Wayne Roberts |
33:4b9fd8969428 | 245 | void init(void); |
Wayne Roberts |
33:4b9fd8969428 | 246 | void get_type(void); // identify radio chip |
Wayne Roberts |
33:4b9fd8969428 | 247 | |
Wayne Roberts |
33:4b9fd8969428 | 248 | /** read register from radio |
Wayne Roberts |
33:4b9fd8969428 | 249 | * @param addr register address |
Wayne Roberts |
33:4b9fd8969428 | 250 | * @returns the value read from the register |
Wayne Roberts |
33:4b9fd8969428 | 251 | */ |
Wayne Roberts |
33:4b9fd8969428 | 252 | uint8_t read_reg(uint8_t addr); |
Wayne Roberts |
33:4b9fd8969428 | 253 | uint16_t read_u16(uint8_t addr); |
Wayne Roberts |
33:4b9fd8969428 | 254 | int16_t read_s16(uint8_t addr); |
Wayne Roberts |
33:4b9fd8969428 | 255 | |
Wayne Roberts |
33:4b9fd8969428 | 256 | /** read register from radio. from an arbitrary amount of registers following the first |
Wayne Roberts |
33:4b9fd8969428 | 257 | * @param addr register address |
Wayne Roberts |
33:4b9fd8969428 | 258 | * @param buffer the read values will be placed here |
Wayne Roberts |
33:4b9fd8969428 | 259 | * @param size how many registers to read |
Wayne Roberts |
33:4b9fd8969428 | 260 | */ |
Wayne Roberts |
33:4b9fd8969428 | 261 | void ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ); |
Wayne Roberts |
33:4b9fd8969428 | 262 | |
Wayne Roberts |
33:4b9fd8969428 | 263 | /** write register to radio |
Wayne Roberts |
33:4b9fd8969428 | 264 | * @param addr register address |
Wayne Roberts |
33:4b9fd8969428 | 265 | * @param data byte to write |
Wayne Roberts |
33:4b9fd8969428 | 266 | */ |
Wayne Roberts |
33:4b9fd8969428 | 267 | void write_reg(uint8_t addr, uint8_t data); |
Wayne Roberts |
33:4b9fd8969428 | 268 | void write_u16(uint8_t addr, uint16_t data); |
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33:4b9fd8969428 | 269 | void write_u24(uint8_t addr, uint32_t data); |
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33:4b9fd8969428 | 270 | |
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33:4b9fd8969428 | 271 | /** write register(s) to radio, to an arbitrary amount of registers following first |
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33:4b9fd8969428 | 272 | * @param addr register address |
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33:4b9fd8969428 | 273 | * @param buffer byte(s) to write |
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33:4b9fd8969428 | 274 | * @param size count of registers to write to |
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33:4b9fd8969428 | 275 | */ |
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33:4b9fd8969428 | 276 | void WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size ); |
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33:4b9fd8969428 | 277 | |
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33:4b9fd8969428 | 278 | /* *switch between FSK or LoRa modes */ |
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33:4b9fd8969428 | 279 | //void SetLoRaOn(bool); |
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33:4b9fd8969428 | 280 | |
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33:4b9fd8969428 | 281 | /*****************************************************/ |
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33:4b9fd8969428 | 282 | |
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33:4b9fd8969428 | 283 | //! RF transmit packet buffer |
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33:4b9fd8969428 | 284 | uint8_t tx_buf[256]; // lora fifo size |
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33:4b9fd8969428 | 285 | |
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33:4b9fd8969428 | 286 | //! RF receive packet buffer |
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33:4b9fd8969428 | 287 | uint8_t rx_buf[256]; // lora fifo size |
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33:4b9fd8969428 | 288 | |
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33:4b9fd8969428 | 289 | //! radio chip type plugged in |
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33:4b9fd8969428 | 290 | type_e type; |
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33:4b9fd8969428 | 291 | |
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33:4b9fd8969428 | 292 | //! operating mode |
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33:4b9fd8969428 | 293 | RegOpMode_t RegOpMode; |
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33:4b9fd8969428 | 294 | |
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33:4b9fd8969428 | 295 | //! transmitter power configuration |
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33:4b9fd8969428 | 296 | RegPaConfig_t RegPaConfig; |
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33:4b9fd8969428 | 297 | |
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33:4b9fd8969428 | 298 | RegOcp_t RegOcp; // 0x0b |
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33:4b9fd8969428 | 299 | |
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33:4b9fd8969428 | 300 | // receiver front-end |
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33:4b9fd8969428 | 301 | RegLna_t RegLna; // 0x0c |
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33:4b9fd8969428 | 302 | |
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33:4b9fd8969428 | 303 | //! pin assignments |
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33:4b9fd8969428 | 304 | RegDioMapping1_t RegDioMapping1; |
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33:4b9fd8969428 | 305 | |
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33:4b9fd8969428 | 306 | //! pin assignments |
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33:4b9fd8969428 | 307 | RegDioMapping2_t RegDioMapping2; |
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33:4b9fd8969428 | 308 | |
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33:4b9fd8969428 | 309 | DigitalIn dio0; |
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33:4b9fd8969428 | 310 | DigitalIn dio1; |
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33:4b9fd8969428 | 311 | DigitalOut m_cs; |
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33:4b9fd8969428 | 312 | SPI& m_spi; |
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33:4b9fd8969428 | 313 | bool HF; // sx1272 is always HF |
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33:4b9fd8969428 | 314 | |
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33:4b9fd8969428 | 315 | /*! board-specific RF switch callback, called whenever operating mode is changed |
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33:4b9fd8969428 | 316 | * This function should also set RegPaConfig.bits.PaSelect to use PA_BOOST or RFO during TX. |
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33:4b9fd8969428 | 317 | * examples: |
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33:4b9fd8969428 | 318 | * PE4259-63: controlled directly by radio chip, no software function needed |
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33:4b9fd8969428 | 319 | * SKY13350-385LF: two separate control lines, requires two DigitalOut pins |
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33:4b9fd8969428 | 320 | */ |
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33:4b9fd8969428 | 321 | Callback<void()> rf_switch; |
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33:4b9fd8969428 | 322 | |
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33:4b9fd8969428 | 323 | private: |
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33:4b9fd8969428 | 324 | DigitalInOut reset_pin; |
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33:4b9fd8969428 | 325 | |
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33:4b9fd8969428 | 326 | protected: |
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33:4b9fd8969428 | 327 | |
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33:4b9fd8969428 | 328 | }; |
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33:4b9fd8969428 | 329 | |
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33:4b9fd8969428 | 330 | #endif /* SX127x_H */ |