Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/core_cm7.h@3:993b4d6ff61e, 2021-03-09 (annotated)

Committer:
adimmit
Date:
Tue Mar 09 20:33:24 2021 +0000
Revision:
3:993b4d6ff61e
Parent:
0:083111ae2a11 
added CAN3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file core_cm7.h
saloutos 0:083111ae2a11 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
saloutos 0:083111ae2a11 4 * @version V5.0.2
saloutos 0:083111ae2a11 5 * @date 13. February 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #if defined ( __ICCARM__ )
saloutos 0:083111ae2a11 26 #pragma system_include /* treat file as system include file for MISRA check */
saloutos 0:083111ae2a11 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 28 #pragma clang system_header /* treat file as system include file */
saloutos 0:083111ae2a11 29 #endif
saloutos 0:083111ae2a11 30
saloutos 0:083111ae2a11 31 #ifndef __CORE_CM7_H_GENERIC
saloutos 0:083111ae2a11 32 #define __CORE_CM7_H_GENERIC
saloutos 0:083111ae2a11 33
saloutos 0:083111ae2a11 34 #include <stdint.h>
saloutos 0:083111ae2a11 35
saloutos 0:083111ae2a11 36 #ifdef __cplusplus
saloutos 0:083111ae2a11 37 extern "C" {
saloutos 0:083111ae2a11 38 #endif
saloutos 0:083111ae2a11 39
saloutos 0:083111ae2a11 40 /**
saloutos 0:083111ae2a11 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
saloutos 0:083111ae2a11 42 CMSIS violates the following MISRA-C:2004 rules:
saloutos 0:083111ae2a11 43
saloutos 0:083111ae2a11 44 \li Required Rule 8.5, object/function definition in header file.<br>
saloutos 0:083111ae2a11 45 Function definitions in header files are used to allow 'inlining'.
saloutos 0:083111ae2a11 46
saloutos 0:083111ae2a11 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
saloutos 0:083111ae2a11 48 Unions are used for effective representation of core registers.
saloutos 0:083111ae2a11 49
saloutos 0:083111ae2a11 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
saloutos 0:083111ae2a11 51 Function-like macros are used to allow more efficient code.
saloutos 0:083111ae2a11 52 */
saloutos 0:083111ae2a11 53
saloutos 0:083111ae2a11 54
saloutos 0:083111ae2a11 55 /*******************************************************************************
saloutos 0:083111ae2a11 56 * CMSIS definitions
saloutos 0:083111ae2a11 57 ******************************************************************************/
saloutos 0:083111ae2a11 58 /**
saloutos 0:083111ae2a11 59 \ingroup Cortex_M7
saloutos 0:083111ae2a11 60 @{
saloutos 0:083111ae2a11 61 */
saloutos 0:083111ae2a11 62
saloutos 0:083111ae2a11 63 /* CMSIS CM7 definitions */
saloutos 0:083111ae2a11 64 #define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
saloutos 0:083111ae2a11 65 #define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
saloutos 0:083111ae2a11 66 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
saloutos 0:083111ae2a11 67 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
saloutos 0:083111ae2a11 68
saloutos 0:083111ae2a11 69 #define __CORTEX_M (7U) /*!< Cortex-M Core */
saloutos 0:083111ae2a11 70
saloutos 0:083111ae2a11 71 /** __FPU_USED indicates whether an FPU is used or not.
saloutos 0:083111ae2a11 72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
saloutos 0:083111ae2a11 73 */
saloutos 0:083111ae2a11 74 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 75 #if defined __TARGET_FPU_VFP
saloutos 0:083111ae2a11 76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 77 #define __FPU_USED 1U
saloutos 0:083111ae2a11 78 #else
saloutos 0:083111ae2a11 79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 80 #define __FPU_USED 0U
saloutos 0:083111ae2a11 81 #endif
saloutos 0:083111ae2a11 82 #else
saloutos 0:083111ae2a11 83 #define __FPU_USED 0U
saloutos 0:083111ae2a11 84 #endif
saloutos 0:083111ae2a11 85
saloutos 0:083111ae2a11 86 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 87 #if defined __ARM_PCS_VFP
saloutos 0:083111ae2a11 88 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 89 #define __FPU_USED 1U
saloutos 0:083111ae2a11 90 #else
saloutos 0:083111ae2a11 91 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 92 #define __FPU_USED 0U
saloutos 0:083111ae2a11 93 #endif
saloutos 0:083111ae2a11 94 #else
saloutos 0:083111ae2a11 95 #define __FPU_USED 0U
saloutos 0:083111ae2a11 96 #endif
saloutos 0:083111ae2a11 97
saloutos 0:083111ae2a11 98 #elif defined ( __GNUC__ )
saloutos 0:083111ae2a11 99 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
saloutos 0:083111ae2a11 100 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 101 #define __FPU_USED 1U
saloutos 0:083111ae2a11 102 #else
saloutos 0:083111ae2a11 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 104 #define __FPU_USED 0U
saloutos 0:083111ae2a11 105 #endif
saloutos 0:083111ae2a11 106 #else
saloutos 0:083111ae2a11 107 #define __FPU_USED 0U
saloutos 0:083111ae2a11 108 #endif
saloutos 0:083111ae2a11 109
saloutos 0:083111ae2a11 110 #elif defined ( __ICCARM__ )
saloutos 0:083111ae2a11 111 #if defined __ARMVFP__
saloutos 0:083111ae2a11 112 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 113 #define __FPU_USED 1U
saloutos 0:083111ae2a11 114 #else
saloutos 0:083111ae2a11 115 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 116 #define __FPU_USED 0U
saloutos 0:083111ae2a11 117 #endif
saloutos 0:083111ae2a11 118 #else
saloutos 0:083111ae2a11 119 #define __FPU_USED 0U
saloutos 0:083111ae2a11 120 #endif
saloutos 0:083111ae2a11 121
saloutos 0:083111ae2a11 122 #elif defined ( __TI_ARM__ )
saloutos 0:083111ae2a11 123 #if defined __TI_VFP_SUPPORT__
saloutos 0:083111ae2a11 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 125 #define __FPU_USED 1U
saloutos 0:083111ae2a11 126 #else
saloutos 0:083111ae2a11 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 128 #define __FPU_USED 0U
saloutos 0:083111ae2a11 129 #endif
saloutos 0:083111ae2a11 130 #else
saloutos 0:083111ae2a11 131 #define __FPU_USED 0U
saloutos 0:083111ae2a11 132 #endif
saloutos 0:083111ae2a11 133
saloutos 0:083111ae2a11 134 #elif defined ( __TASKING__ )
saloutos 0:083111ae2a11 135 #if defined __FPU_VFP__
saloutos 0:083111ae2a11 136 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 137 #define __FPU_USED 1U
saloutos 0:083111ae2a11 138 #else
saloutos 0:083111ae2a11 139 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 140 #define __FPU_USED 0U
saloutos 0:083111ae2a11 141 #endif
saloutos 0:083111ae2a11 142 #else
saloutos 0:083111ae2a11 143 #define __FPU_USED 0U
saloutos 0:083111ae2a11 144 #endif
saloutos 0:083111ae2a11 145
saloutos 0:083111ae2a11 146 #elif defined ( __CSMC__ )
saloutos 0:083111ae2a11 147 #if ( __CSMC__ & 0x400U)
saloutos 0:083111ae2a11 148 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
saloutos 0:083111ae2a11 149 #define __FPU_USED 1U
saloutos 0:083111ae2a11 150 #else
saloutos 0:083111ae2a11 151 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 152 #define __FPU_USED 0U
saloutos 0:083111ae2a11 153 #endif
saloutos 0:083111ae2a11 154 #else
saloutos 0:083111ae2a11 155 #define __FPU_USED 0U
saloutos 0:083111ae2a11 156 #endif
saloutos 0:083111ae2a11 157
saloutos 0:083111ae2a11 158 #endif
saloutos 0:083111ae2a11 159
saloutos 0:083111ae2a11 160 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 161
saloutos 0:083111ae2a11 162
saloutos 0:083111ae2a11 163 #ifdef __cplusplus
saloutos 0:083111ae2a11 164 }
saloutos 0:083111ae2a11 165 #endif
saloutos 0:083111ae2a11 166
saloutos 0:083111ae2a11 167 #endif /* __CORE_CM7_H_GENERIC */
saloutos 0:083111ae2a11 168
saloutos 0:083111ae2a11 169 #ifndef __CMSIS_GENERIC
saloutos 0:083111ae2a11 170
saloutos 0:083111ae2a11 171 #ifndef __CORE_CM7_H_DEPENDANT
saloutos 0:083111ae2a11 172 #define __CORE_CM7_H_DEPENDANT
saloutos 0:083111ae2a11 173
saloutos 0:083111ae2a11 174 #ifdef __cplusplus
saloutos 0:083111ae2a11 175 extern "C" {
saloutos 0:083111ae2a11 176 #endif
saloutos 0:083111ae2a11 177
saloutos 0:083111ae2a11 178 /* check device defines and use defaults */
saloutos 0:083111ae2a11 179 #if defined __CHECK_DEVICE_DEFINES
saloutos 0:083111ae2a11 180 #ifndef __CM7_REV
saloutos 0:083111ae2a11 181 #define __CM7_REV 0x0000U
saloutos 0:083111ae2a11 182 #warning "__CM7_REV not defined in device header file; using default!"
saloutos 0:083111ae2a11 183 #endif
saloutos 0:083111ae2a11 184
saloutos 0:083111ae2a11 185 #ifndef __FPU_PRESENT
saloutos 0:083111ae2a11 186 #define __FPU_PRESENT 0U
saloutos 0:083111ae2a11 187 #warning "__FPU_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 188 #endif
saloutos 0:083111ae2a11 189
saloutos 0:083111ae2a11 190 #ifndef __MPU_PRESENT
saloutos 0:083111ae2a11 191 #define __MPU_PRESENT 0U
saloutos 0:083111ae2a11 192 #warning "__MPU_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 193 #endif
saloutos 0:083111ae2a11 194
saloutos 0:083111ae2a11 195 #ifndef __ICACHE_PRESENT
saloutos 0:083111ae2a11 196 #define __ICACHE_PRESENT 0U
saloutos 0:083111ae2a11 197 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 198 #endif
saloutos 0:083111ae2a11 199
saloutos 0:083111ae2a11 200 #ifndef __DCACHE_PRESENT
saloutos 0:083111ae2a11 201 #define __DCACHE_PRESENT 0U
saloutos 0:083111ae2a11 202 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 203 #endif
saloutos 0:083111ae2a11 204
saloutos 0:083111ae2a11 205 #ifndef __DTCM_PRESENT
saloutos 0:083111ae2a11 206 #define __DTCM_PRESENT 0U
saloutos 0:083111ae2a11 207 #warning "__DTCM_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 208 #endif
saloutos 0:083111ae2a11 209
saloutos 0:083111ae2a11 210 #ifndef __NVIC_PRIO_BITS
saloutos 0:083111ae2a11 211 #define __NVIC_PRIO_BITS 3U
saloutos 0:083111ae2a11 212 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
saloutos 0:083111ae2a11 213 #endif
saloutos 0:083111ae2a11 214
saloutos 0:083111ae2a11 215 #ifndef __Vendor_SysTickConfig
saloutos 0:083111ae2a11 216 #define __Vendor_SysTickConfig 0U
saloutos 0:083111ae2a11 217 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
saloutos 0:083111ae2a11 218 #endif
saloutos 0:083111ae2a11 219 #endif
saloutos 0:083111ae2a11 220
saloutos 0:083111ae2a11 221 /* IO definitions (access restrictions to peripheral registers) */
saloutos 0:083111ae2a11 222 /**
saloutos 0:083111ae2a11 223 \defgroup CMSIS_glob_defs CMSIS Global Defines
saloutos 0:083111ae2a11 224
saloutos 0:083111ae2a11 225 <strong>IO Type Qualifiers</strong> are used
saloutos 0:083111ae2a11 226 \li to specify the access to peripheral variables.
saloutos 0:083111ae2a11 227 \li for automatic generation of peripheral register debug information.
saloutos 0:083111ae2a11 228 */
saloutos 0:083111ae2a11 229 #ifdef __cplusplus
saloutos 0:083111ae2a11 230 #define __I volatile /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 231 #else
saloutos 0:083111ae2a11 232 #define __I volatile const /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 233 #endif
saloutos 0:083111ae2a11 234 #define __O volatile /*!< Defines 'write only' permissions */
saloutos 0:083111ae2a11 235 #define __IO volatile /*!< Defines 'read / write' permissions */
saloutos 0:083111ae2a11 236
saloutos 0:083111ae2a11 237 /* following defines should be used for structure members */
saloutos 0:083111ae2a11 238 #define __IM volatile const /*! Defines 'read only' structure member permissions */
saloutos 0:083111ae2a11 239 #define __OM volatile /*! Defines 'write only' structure member permissions */
saloutos 0:083111ae2a11 240 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
saloutos 0:083111ae2a11 241
saloutos 0:083111ae2a11 242 /*@} end of group Cortex_M7 */
saloutos 0:083111ae2a11 243
saloutos 0:083111ae2a11 244
saloutos 0:083111ae2a11 245
saloutos 0:083111ae2a11 246 /*******************************************************************************
saloutos 0:083111ae2a11 247 * Register Abstraction
saloutos 0:083111ae2a11 248 Core Register contain:
saloutos 0:083111ae2a11 249 - Core Register
saloutos 0:083111ae2a11 250 - Core NVIC Register
saloutos 0:083111ae2a11 251 - Core SCB Register
saloutos 0:083111ae2a11 252 - Core SysTick Register
saloutos 0:083111ae2a11 253 - Core Debug Register
saloutos 0:083111ae2a11 254 - Core MPU Register
saloutos 0:083111ae2a11 255 - Core FPU Register
saloutos 0:083111ae2a11 256 ******************************************************************************/
saloutos 0:083111ae2a11 257 /**
saloutos 0:083111ae2a11 258 \defgroup CMSIS_core_register Defines and Type Definitions
saloutos 0:083111ae2a11 259 \brief Type definitions and defines for Cortex-M processor based devices.
saloutos 0:083111ae2a11 260 */
saloutos 0:083111ae2a11 261
saloutos 0:083111ae2a11 262 /**
saloutos 0:083111ae2a11 263 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 264 \defgroup CMSIS_CORE Status and Control Registers
saloutos 0:083111ae2a11 265 \brief Core Register type definitions.
saloutos 0:083111ae2a11 266 @{
saloutos 0:083111ae2a11 267 */
saloutos 0:083111ae2a11 268
saloutos 0:083111ae2a11 269 /**
saloutos 0:083111ae2a11 270 \brief Union type to access the Application Program Status Register (APSR).
saloutos 0:083111ae2a11 271 */
saloutos 0:083111ae2a11 272 typedef union
saloutos 0:083111ae2a11 273 {
saloutos 0:083111ae2a11 274 struct
saloutos 0:083111ae2a11 275 {
saloutos 0:083111ae2a11 276 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
saloutos 0:083111ae2a11 277 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
saloutos 0:083111ae2a11 278 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
saloutos 0:083111ae2a11 279 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
saloutos 0:083111ae2a11 280 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 281 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 282 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 283 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 284 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 285 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 286 } APSR_Type;
saloutos 0:083111ae2a11 287
saloutos 0:083111ae2a11 288 /* APSR Register Definitions */
saloutos 0:083111ae2a11 289 #define APSR_N_Pos 31U /*!< APSR: N Position */
saloutos 0:083111ae2a11 290 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
saloutos 0:083111ae2a11 291
saloutos 0:083111ae2a11 292 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
saloutos 0:083111ae2a11 293 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
saloutos 0:083111ae2a11 294
saloutos 0:083111ae2a11 295 #define APSR_C_Pos 29U /*!< APSR: C Position */
saloutos 0:083111ae2a11 296 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
saloutos 0:083111ae2a11 297
saloutos 0:083111ae2a11 298 #define APSR_V_Pos 28U /*!< APSR: V Position */
saloutos 0:083111ae2a11 299 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
saloutos 0:083111ae2a11 300
saloutos 0:083111ae2a11 301 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
saloutos 0:083111ae2a11 302 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
saloutos 0:083111ae2a11 303
saloutos 0:083111ae2a11 304 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
saloutos 0:083111ae2a11 305 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
saloutos 0:083111ae2a11 306
saloutos 0:083111ae2a11 307
saloutos 0:083111ae2a11 308 /**
saloutos 0:083111ae2a11 309 \brief Union type to access the Interrupt Program Status Register (IPSR).
saloutos 0:083111ae2a11 310 */
saloutos 0:083111ae2a11 311 typedef union
saloutos 0:083111ae2a11 312 {
saloutos 0:083111ae2a11 313 struct
saloutos 0:083111ae2a11 314 {
saloutos 0:083111ae2a11 315 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 316 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
saloutos 0:083111ae2a11 317 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 318 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 319 } IPSR_Type;
saloutos 0:083111ae2a11 320
saloutos 0:083111ae2a11 321 /* IPSR Register Definitions */
saloutos 0:083111ae2a11 322 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
saloutos 0:083111ae2a11 323 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
saloutos 0:083111ae2a11 324
saloutos 0:083111ae2a11 325
saloutos 0:083111ae2a11 326 /**
saloutos 0:083111ae2a11 327 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
saloutos 0:083111ae2a11 328 */
saloutos 0:083111ae2a11 329 typedef union
saloutos 0:083111ae2a11 330 {
saloutos 0:083111ae2a11 331 struct
saloutos 0:083111ae2a11 332 {
saloutos 0:083111ae2a11 333 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 334 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
saloutos 0:083111ae2a11 335 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
saloutos 0:083111ae2a11 336 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
saloutos 0:083111ae2a11 337 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
saloutos 0:083111ae2a11 338 uint32_t T:1; /*!< bit: 24 Thumb bit */
saloutos 0:083111ae2a11 339 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
saloutos 0:083111ae2a11 340 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
saloutos 0:083111ae2a11 341 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 342 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 343 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 344 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 345 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 346 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 347 } xPSR_Type;
saloutos 0:083111ae2a11 348
saloutos 0:083111ae2a11 349 /* xPSR Register Definitions */
saloutos 0:083111ae2a11 350 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
saloutos 0:083111ae2a11 351 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
saloutos 0:083111ae2a11 352
saloutos 0:083111ae2a11 353 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
saloutos 0:083111ae2a11 354 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
saloutos 0:083111ae2a11 355
saloutos 0:083111ae2a11 356 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
saloutos 0:083111ae2a11 357 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
saloutos 0:083111ae2a11 358
saloutos 0:083111ae2a11 359 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
saloutos 0:083111ae2a11 360 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
saloutos 0:083111ae2a11 361
saloutos 0:083111ae2a11 362 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
saloutos 0:083111ae2a11 363 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
saloutos 0:083111ae2a11 364
saloutos 0:083111ae2a11 365 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
saloutos 0:083111ae2a11 366 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
saloutos 0:083111ae2a11 367
saloutos 0:083111ae2a11 368 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
saloutos 0:083111ae2a11 369 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
saloutos 0:083111ae2a11 370
saloutos 0:083111ae2a11 371 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
saloutos 0:083111ae2a11 372 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
saloutos 0:083111ae2a11 373
saloutos 0:083111ae2a11 374 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
saloutos 0:083111ae2a11 375 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
saloutos 0:083111ae2a11 376
saloutos 0:083111ae2a11 377 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
saloutos 0:083111ae2a11 378 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
saloutos 0:083111ae2a11 379
saloutos 0:083111ae2a11 380
saloutos 0:083111ae2a11 381 /**
saloutos 0:083111ae2a11 382 \brief Union type to access the Control Registers (CONTROL).
saloutos 0:083111ae2a11 383 */
saloutos 0:083111ae2a11 384 typedef union
saloutos 0:083111ae2a11 385 {
saloutos 0:083111ae2a11 386 struct
saloutos 0:083111ae2a11 387 {
saloutos 0:083111ae2a11 388 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
saloutos 0:083111ae2a11 389 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
saloutos 0:083111ae2a11 390 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
saloutos 0:083111ae2a11 391 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
saloutos 0:083111ae2a11 392 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 393 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 394 } CONTROL_Type;
saloutos 0:083111ae2a11 395
saloutos 0:083111ae2a11 396 /* CONTROL Register Definitions */
saloutos 0:083111ae2a11 397 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
saloutos 0:083111ae2a11 398 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
saloutos 0:083111ae2a11 399
saloutos 0:083111ae2a11 400 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
saloutos 0:083111ae2a11 401 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
saloutos 0:083111ae2a11 402
saloutos 0:083111ae2a11 403 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
saloutos 0:083111ae2a11 404 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
saloutos 0:083111ae2a11 405
saloutos 0:083111ae2a11 406 /*@} end of group CMSIS_CORE */
saloutos 0:083111ae2a11 407
saloutos 0:083111ae2a11 408
saloutos 0:083111ae2a11 409 /**
saloutos 0:083111ae2a11 410 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 411 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
saloutos 0:083111ae2a11 412 \brief Type definitions for the NVIC Registers
saloutos 0:083111ae2a11 413 @{
saloutos 0:083111ae2a11 414 */
saloutos 0:083111ae2a11 415
saloutos 0:083111ae2a11 416 /**
saloutos 0:083111ae2a11 417 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
saloutos 0:083111ae2a11 418 */
saloutos 0:083111ae2a11 419 typedef struct
saloutos 0:083111ae2a11 420 {
saloutos 0:083111ae2a11 421 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
saloutos 0:083111ae2a11 422 uint32_t RESERVED0[24U];
saloutos 0:083111ae2a11 423 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
saloutos 0:083111ae2a11 424 uint32_t RSERVED1[24U];
saloutos 0:083111ae2a11 425 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
saloutos 0:083111ae2a11 426 uint32_t RESERVED2[24U];
saloutos 0:083111ae2a11 427 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
saloutos 0:083111ae2a11 428 uint32_t RESERVED3[24U];
saloutos 0:083111ae2a11 429 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
saloutos 0:083111ae2a11 430 uint32_t RESERVED4[56U];
saloutos 0:083111ae2a11 431 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
saloutos 0:083111ae2a11 432 uint32_t RESERVED5[644U];
saloutos 0:083111ae2a11 433 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
saloutos 0:083111ae2a11 434 } NVIC_Type;
saloutos 0:083111ae2a11 435
saloutos 0:083111ae2a11 436 /* Software Triggered Interrupt Register Definitions */
saloutos 0:083111ae2a11 437 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
saloutos 0:083111ae2a11 438 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
saloutos 0:083111ae2a11 439
saloutos 0:083111ae2a11 440 /*@} end of group CMSIS_NVIC */
saloutos 0:083111ae2a11 441
saloutos 0:083111ae2a11 442
saloutos 0:083111ae2a11 443 /**
saloutos 0:083111ae2a11 444 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 445 \defgroup CMSIS_SCB System Control Block (SCB)
saloutos 0:083111ae2a11 446 \brief Type definitions for the System Control Block Registers
saloutos 0:083111ae2a11 447 @{
saloutos 0:083111ae2a11 448 */
saloutos 0:083111ae2a11 449
saloutos 0:083111ae2a11 450 /**
saloutos 0:083111ae2a11 451 \brief Structure type to access the System Control Block (SCB).
saloutos 0:083111ae2a11 452 */
saloutos 0:083111ae2a11 453 typedef struct
saloutos 0:083111ae2a11 454 {
saloutos 0:083111ae2a11 455 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
saloutos 0:083111ae2a11 456 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
saloutos 0:083111ae2a11 457 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
saloutos 0:083111ae2a11 458 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
saloutos 0:083111ae2a11 459 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
saloutos 0:083111ae2a11 460 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
saloutos 0:083111ae2a11 461 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
saloutos 0:083111ae2a11 462 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
saloutos 0:083111ae2a11 463 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
saloutos 0:083111ae2a11 464 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
saloutos 0:083111ae2a11 465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
saloutos 0:083111ae2a11 466 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
saloutos 0:083111ae2a11 467 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
saloutos 0:083111ae2a11 468 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
saloutos 0:083111ae2a11 469 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
saloutos 0:083111ae2a11 470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
saloutos 0:083111ae2a11 471 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
saloutos 0:083111ae2a11 472 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
saloutos 0:083111ae2a11 473 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
saloutos 0:083111ae2a11 474 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 475 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
saloutos 0:083111ae2a11 476 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
saloutos 0:083111ae2a11 477 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
saloutos 0:083111ae2a11 478 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
saloutos 0:083111ae2a11 479 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
saloutos 0:083111ae2a11 480 uint32_t RESERVED3[93U];
saloutos 0:083111ae2a11 481 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
saloutos 0:083111ae2a11 482 uint32_t RESERVED4[15U];
saloutos 0:083111ae2a11 483 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
saloutos 0:083111ae2a11 484 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
saloutos 0:083111ae2a11 485 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
saloutos 0:083111ae2a11 486 uint32_t RESERVED5[1U];
saloutos 0:083111ae2a11 487 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
saloutos 0:083111ae2a11 488 uint32_t RESERVED6[1U];
saloutos 0:083111ae2a11 489 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
saloutos 0:083111ae2a11 490 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
saloutos 0:083111ae2a11 491 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
saloutos 0:083111ae2a11 492 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
saloutos 0:083111ae2a11 493 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
saloutos 0:083111ae2a11 494 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
saloutos 0:083111ae2a11 495 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
saloutos 0:083111ae2a11 496 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
saloutos 0:083111ae2a11 497 uint32_t RESERVED7[6U];
saloutos 0:083111ae2a11 498 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
saloutos 0:083111ae2a11 499 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
saloutos 0:083111ae2a11 500 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
saloutos 0:083111ae2a11 501 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
saloutos 0:083111ae2a11 502 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
saloutos 0:083111ae2a11 503 uint32_t RESERVED8[1U];
saloutos 0:083111ae2a11 504 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
saloutos 0:083111ae2a11 505 } SCB_Type;
saloutos 0:083111ae2a11 506
saloutos 0:083111ae2a11 507 /* SCB CPUID Register Definitions */
saloutos 0:083111ae2a11 508 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
saloutos 0:083111ae2a11 509 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
saloutos 0:083111ae2a11 510
saloutos 0:083111ae2a11 511 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
saloutos 0:083111ae2a11 512 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
saloutos 0:083111ae2a11 513
saloutos 0:083111ae2a11 514 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
saloutos 0:083111ae2a11 515 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
saloutos 0:083111ae2a11 516
saloutos 0:083111ae2a11 517 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
saloutos 0:083111ae2a11 518 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
saloutos 0:083111ae2a11 519
saloutos 0:083111ae2a11 520 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
saloutos 0:083111ae2a11 521 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
saloutos 0:083111ae2a11 522
saloutos 0:083111ae2a11 523 /* SCB Interrupt Control State Register Definitions */
saloutos 0:083111ae2a11 524 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
saloutos 0:083111ae2a11 525 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
saloutos 0:083111ae2a11 526
saloutos 0:083111ae2a11 527 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
saloutos 0:083111ae2a11 528 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
saloutos 0:083111ae2a11 529
saloutos 0:083111ae2a11 530 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
saloutos 0:083111ae2a11 531 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
saloutos 0:083111ae2a11 532
saloutos 0:083111ae2a11 533 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
saloutos 0:083111ae2a11 534 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
saloutos 0:083111ae2a11 535
saloutos 0:083111ae2a11 536 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
saloutos 0:083111ae2a11 537 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
saloutos 0:083111ae2a11 538
saloutos 0:083111ae2a11 539 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
saloutos 0:083111ae2a11 540 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
saloutos 0:083111ae2a11 541
saloutos 0:083111ae2a11 542 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
saloutos 0:083111ae2a11 543 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
saloutos 0:083111ae2a11 544
saloutos 0:083111ae2a11 545 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
saloutos 0:083111ae2a11 546 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
saloutos 0:083111ae2a11 547
saloutos 0:083111ae2a11 548 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
saloutos 0:083111ae2a11 549 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
saloutos 0:083111ae2a11 550
saloutos 0:083111ae2a11 551 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
saloutos 0:083111ae2a11 552 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
saloutos 0:083111ae2a11 553
saloutos 0:083111ae2a11 554 /* SCB Vector Table Offset Register Definitions */
saloutos 0:083111ae2a11 555 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
saloutos 0:083111ae2a11 556 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
saloutos 0:083111ae2a11 557
saloutos 0:083111ae2a11 558 /* SCB Application Interrupt and Reset Control Register Definitions */
saloutos 0:083111ae2a11 559 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
saloutos 0:083111ae2a11 560 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
saloutos 0:083111ae2a11 561
saloutos 0:083111ae2a11 562 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
saloutos 0:083111ae2a11 563 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
saloutos 0:083111ae2a11 564
saloutos 0:083111ae2a11 565 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
saloutos 0:083111ae2a11 566 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
saloutos 0:083111ae2a11 567
saloutos 0:083111ae2a11 568 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
saloutos 0:083111ae2a11 569 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
saloutos 0:083111ae2a11 570
saloutos 0:083111ae2a11 571 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
saloutos 0:083111ae2a11 572 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
saloutos 0:083111ae2a11 573
saloutos 0:083111ae2a11 574 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
saloutos 0:083111ae2a11 575 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
saloutos 0:083111ae2a11 576
saloutos 0:083111ae2a11 577 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
saloutos 0:083111ae2a11 578 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
saloutos 0:083111ae2a11 579
saloutos 0:083111ae2a11 580 /* SCB System Control Register Definitions */
saloutos 0:083111ae2a11 581 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
saloutos 0:083111ae2a11 582 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
saloutos 0:083111ae2a11 583
saloutos 0:083111ae2a11 584 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
saloutos 0:083111ae2a11 585 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
saloutos 0:083111ae2a11 586
saloutos 0:083111ae2a11 587 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
saloutos 0:083111ae2a11 588 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
saloutos 0:083111ae2a11 589
saloutos 0:083111ae2a11 590 /* SCB Configuration Control Register Definitions */
saloutos 0:083111ae2a11 591 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
saloutos 0:083111ae2a11 592 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
saloutos 0:083111ae2a11 593
saloutos 0:083111ae2a11 594 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
saloutos 0:083111ae2a11 595 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
saloutos 0:083111ae2a11 596
saloutos 0:083111ae2a11 597 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
saloutos 0:083111ae2a11 598 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
saloutos 0:083111ae2a11 599
saloutos 0:083111ae2a11 600 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
saloutos 0:083111ae2a11 601 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
saloutos 0:083111ae2a11 602
saloutos 0:083111ae2a11 603 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
saloutos 0:083111ae2a11 604 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
saloutos 0:083111ae2a11 605
saloutos 0:083111ae2a11 606 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
saloutos 0:083111ae2a11 607 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
saloutos 0:083111ae2a11 608
saloutos 0:083111ae2a11 609 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
saloutos 0:083111ae2a11 610 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
saloutos 0:083111ae2a11 611
saloutos 0:083111ae2a11 612 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
saloutos 0:083111ae2a11 613 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
saloutos 0:083111ae2a11 614
saloutos 0:083111ae2a11 615 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
saloutos 0:083111ae2a11 616 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
saloutos 0:083111ae2a11 617
saloutos 0:083111ae2a11 618 /* SCB System Handler Control and State Register Definitions */
saloutos 0:083111ae2a11 619 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
saloutos 0:083111ae2a11 620 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
saloutos 0:083111ae2a11 621
saloutos 0:083111ae2a11 622 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
saloutos 0:083111ae2a11 623 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
saloutos 0:083111ae2a11 624
saloutos 0:083111ae2a11 625 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
saloutos 0:083111ae2a11 626 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
saloutos 0:083111ae2a11 627
saloutos 0:083111ae2a11 628 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
saloutos 0:083111ae2a11 629 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
saloutos 0:083111ae2a11 630
saloutos 0:083111ae2a11 631 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
saloutos 0:083111ae2a11 632 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
saloutos 0:083111ae2a11 633
saloutos 0:083111ae2a11 634 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
saloutos 0:083111ae2a11 635 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
saloutos 0:083111ae2a11 636
saloutos 0:083111ae2a11 637 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
saloutos 0:083111ae2a11 638 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
saloutos 0:083111ae2a11 639
saloutos 0:083111ae2a11 640 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
saloutos 0:083111ae2a11 641 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
saloutos 0:083111ae2a11 642
saloutos 0:083111ae2a11 643 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
saloutos 0:083111ae2a11 644 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
saloutos 0:083111ae2a11 645
saloutos 0:083111ae2a11 646 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
saloutos 0:083111ae2a11 647 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
saloutos 0:083111ae2a11 648
saloutos 0:083111ae2a11 649 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
saloutos 0:083111ae2a11 650 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
saloutos 0:083111ae2a11 651
saloutos 0:083111ae2a11 652 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
saloutos 0:083111ae2a11 653 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
saloutos 0:083111ae2a11 654
saloutos 0:083111ae2a11 655 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
saloutos 0:083111ae2a11 656 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
saloutos 0:083111ae2a11 657
saloutos 0:083111ae2a11 658 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
saloutos 0:083111ae2a11 659 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
saloutos 0:083111ae2a11 660
saloutos 0:083111ae2a11 661 /* SCB Configurable Fault Status Register Definitions */
saloutos 0:083111ae2a11 662 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
saloutos 0:083111ae2a11 663 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
saloutos 0:083111ae2a11 664
saloutos 0:083111ae2a11 665 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
saloutos 0:083111ae2a11 666 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
saloutos 0:083111ae2a11 667
saloutos 0:083111ae2a11 668 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
saloutos 0:083111ae2a11 669 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
saloutos 0:083111ae2a11 670
saloutos 0:083111ae2a11 671 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 672 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
saloutos 0:083111ae2a11 673 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
saloutos 0:083111ae2a11 674
saloutos 0:083111ae2a11 675 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
saloutos 0:083111ae2a11 676 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
saloutos 0:083111ae2a11 677
saloutos 0:083111ae2a11 678 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
saloutos 0:083111ae2a11 679 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
saloutos 0:083111ae2a11 680
saloutos 0:083111ae2a11 681 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
saloutos 0:083111ae2a11 682 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
saloutos 0:083111ae2a11 683
saloutos 0:083111ae2a11 684 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
saloutos 0:083111ae2a11 685 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
saloutos 0:083111ae2a11 686
saloutos 0:083111ae2a11 687 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
saloutos 0:083111ae2a11 688 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
saloutos 0:083111ae2a11 689
saloutos 0:083111ae2a11 690 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 691 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
saloutos 0:083111ae2a11 692 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
saloutos 0:083111ae2a11 693
saloutos 0:083111ae2a11 694 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
saloutos 0:083111ae2a11 695 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
saloutos 0:083111ae2a11 696
saloutos 0:083111ae2a11 697 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
saloutos 0:083111ae2a11 698 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
saloutos 0:083111ae2a11 699
saloutos 0:083111ae2a11 700 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
saloutos 0:083111ae2a11 701 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
saloutos 0:083111ae2a11 702
saloutos 0:083111ae2a11 703 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
saloutos 0:083111ae2a11 704 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
saloutos 0:083111ae2a11 705
saloutos 0:083111ae2a11 706 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
saloutos 0:083111ae2a11 707 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
saloutos 0:083111ae2a11 708
saloutos 0:083111ae2a11 709 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
saloutos 0:083111ae2a11 710 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
saloutos 0:083111ae2a11 711
saloutos 0:083111ae2a11 712 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
saloutos 0:083111ae2a11 713 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
saloutos 0:083111ae2a11 714 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
saloutos 0:083111ae2a11 715
saloutos 0:083111ae2a11 716 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
saloutos 0:083111ae2a11 717 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
saloutos 0:083111ae2a11 718
saloutos 0:083111ae2a11 719 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
saloutos 0:083111ae2a11 720 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
saloutos 0:083111ae2a11 721
saloutos 0:083111ae2a11 722 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
saloutos 0:083111ae2a11 723 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
saloutos 0:083111ae2a11 724
saloutos 0:083111ae2a11 725 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
saloutos 0:083111ae2a11 726 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
saloutos 0:083111ae2a11 727
saloutos 0:083111ae2a11 728 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
saloutos 0:083111ae2a11 729 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
saloutos 0:083111ae2a11 730
saloutos 0:083111ae2a11 731 /* SCB Hard Fault Status Register Definitions */
saloutos 0:083111ae2a11 732 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
saloutos 0:083111ae2a11 733 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
saloutos 0:083111ae2a11 734
saloutos 0:083111ae2a11 735 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
saloutos 0:083111ae2a11 736 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
saloutos 0:083111ae2a11 737
saloutos 0:083111ae2a11 738 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
saloutos 0:083111ae2a11 739 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
saloutos 0:083111ae2a11 740
saloutos 0:083111ae2a11 741 /* SCB Debug Fault Status Register Definitions */
saloutos 0:083111ae2a11 742 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
saloutos 0:083111ae2a11 743 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
saloutos 0:083111ae2a11 744
saloutos 0:083111ae2a11 745 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
saloutos 0:083111ae2a11 746 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
saloutos 0:083111ae2a11 747
saloutos 0:083111ae2a11 748 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
saloutos 0:083111ae2a11 749 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
saloutos 0:083111ae2a11 750
saloutos 0:083111ae2a11 751 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
saloutos 0:083111ae2a11 752 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
saloutos 0:083111ae2a11 753
saloutos 0:083111ae2a11 754 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
saloutos 0:083111ae2a11 755 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
saloutos 0:083111ae2a11 756
saloutos 0:083111ae2a11 757 /* SCB Cache Level ID Register Definitions */
saloutos 0:083111ae2a11 758 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
saloutos 0:083111ae2a11 759 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
saloutos 0:083111ae2a11 760
saloutos 0:083111ae2a11 761 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
saloutos 0:083111ae2a11 762 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
saloutos 0:083111ae2a11 763
saloutos 0:083111ae2a11 764 /* SCB Cache Type Register Definitions */
saloutos 0:083111ae2a11 765 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
saloutos 0:083111ae2a11 766 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
saloutos 0:083111ae2a11 767
saloutos 0:083111ae2a11 768 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
saloutos 0:083111ae2a11 769 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
saloutos 0:083111ae2a11 770
saloutos 0:083111ae2a11 771 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
saloutos 0:083111ae2a11 772 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
saloutos 0:083111ae2a11 773
saloutos 0:083111ae2a11 774 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
saloutos 0:083111ae2a11 775 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
saloutos 0:083111ae2a11 776
saloutos 0:083111ae2a11 777 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
saloutos 0:083111ae2a11 778 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
saloutos 0:083111ae2a11 779
saloutos 0:083111ae2a11 780 /* SCB Cache Size ID Register Definitions */
saloutos 0:083111ae2a11 781 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
saloutos 0:083111ae2a11 782 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
saloutos 0:083111ae2a11 783
saloutos 0:083111ae2a11 784 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
saloutos 0:083111ae2a11 785 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
saloutos 0:083111ae2a11 786
saloutos 0:083111ae2a11 787 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
saloutos 0:083111ae2a11 788 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
saloutos 0:083111ae2a11 789
saloutos 0:083111ae2a11 790 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
saloutos 0:083111ae2a11 791 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
saloutos 0:083111ae2a11 792
saloutos 0:083111ae2a11 793 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
saloutos 0:083111ae2a11 794 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
saloutos 0:083111ae2a11 795
saloutos 0:083111ae2a11 796 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
saloutos 0:083111ae2a11 797 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
saloutos 0:083111ae2a11 798
saloutos 0:083111ae2a11 799 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
saloutos 0:083111ae2a11 800 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
saloutos 0:083111ae2a11 801
saloutos 0:083111ae2a11 802 /* SCB Cache Size Selection Register Definitions */
saloutos 0:083111ae2a11 803 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
saloutos 0:083111ae2a11 804 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
saloutos 0:083111ae2a11 805
saloutos 0:083111ae2a11 806 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
saloutos 0:083111ae2a11 807 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
saloutos 0:083111ae2a11 808
saloutos 0:083111ae2a11 809 /* SCB Software Triggered Interrupt Register Definitions */
saloutos 0:083111ae2a11 810 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
saloutos 0:083111ae2a11 811 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
saloutos 0:083111ae2a11 812
saloutos 0:083111ae2a11 813 /* SCB D-Cache Invalidate by Set-way Register Definitions */
saloutos 0:083111ae2a11 814 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
saloutos 0:083111ae2a11 815 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
saloutos 0:083111ae2a11 816
saloutos 0:083111ae2a11 817 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
saloutos 0:083111ae2a11 818 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
saloutos 0:083111ae2a11 819
saloutos 0:083111ae2a11 820 /* SCB D-Cache Clean by Set-way Register Definitions */
saloutos 0:083111ae2a11 821 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
saloutos 0:083111ae2a11 822 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
saloutos 0:083111ae2a11 823
saloutos 0:083111ae2a11 824 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
saloutos 0:083111ae2a11 825 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
saloutos 0:083111ae2a11 826
saloutos 0:083111ae2a11 827 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
saloutos 0:083111ae2a11 828 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
saloutos 0:083111ae2a11 829 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
saloutos 0:083111ae2a11 830
saloutos 0:083111ae2a11 831 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
saloutos 0:083111ae2a11 832 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
saloutos 0:083111ae2a11 833
saloutos 0:083111ae2a11 834 /* Instruction Tightly-Coupled Memory Control Register Definitions */
saloutos 0:083111ae2a11 835 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
saloutos 0:083111ae2a11 836 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
saloutos 0:083111ae2a11 837
saloutos 0:083111ae2a11 838 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
saloutos 0:083111ae2a11 839 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
saloutos 0:083111ae2a11 840
saloutos 0:083111ae2a11 841 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
saloutos 0:083111ae2a11 842 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
saloutos 0:083111ae2a11 843
saloutos 0:083111ae2a11 844 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
saloutos 0:083111ae2a11 845 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
saloutos 0:083111ae2a11 846
saloutos 0:083111ae2a11 847 /* Data Tightly-Coupled Memory Control Register Definitions */
saloutos 0:083111ae2a11 848 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
saloutos 0:083111ae2a11 849 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
saloutos 0:083111ae2a11 850
saloutos 0:083111ae2a11 851 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
saloutos 0:083111ae2a11 852 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
saloutos 0:083111ae2a11 853
saloutos 0:083111ae2a11 854 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
saloutos 0:083111ae2a11 855 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
saloutos 0:083111ae2a11 856
saloutos 0:083111ae2a11 857 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
saloutos 0:083111ae2a11 858 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
saloutos 0:083111ae2a11 859
saloutos 0:083111ae2a11 860 /* AHBP Control Register Definitions */
saloutos 0:083111ae2a11 861 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
saloutos 0:083111ae2a11 862 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
saloutos 0:083111ae2a11 863
saloutos 0:083111ae2a11 864 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
saloutos 0:083111ae2a11 865 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
saloutos 0:083111ae2a11 866
saloutos 0:083111ae2a11 867 /* L1 Cache Control Register Definitions */
saloutos 0:083111ae2a11 868 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
saloutos 0:083111ae2a11 869 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
saloutos 0:083111ae2a11 870
saloutos 0:083111ae2a11 871 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
saloutos 0:083111ae2a11 872 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
saloutos 0:083111ae2a11 873
saloutos 0:083111ae2a11 874 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
saloutos 0:083111ae2a11 875 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
saloutos 0:083111ae2a11 876
saloutos 0:083111ae2a11 877 /* AHBS Control Register Definitions */
saloutos 0:083111ae2a11 878 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
saloutos 0:083111ae2a11 879 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
saloutos 0:083111ae2a11 880
saloutos 0:083111ae2a11 881 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
saloutos 0:083111ae2a11 882 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
saloutos 0:083111ae2a11 883
saloutos 0:083111ae2a11 884 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
saloutos 0:083111ae2a11 885 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
saloutos 0:083111ae2a11 886
saloutos 0:083111ae2a11 887 /* Auxiliary Bus Fault Status Register Definitions */
saloutos 0:083111ae2a11 888 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
saloutos 0:083111ae2a11 889 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
saloutos 0:083111ae2a11 890
saloutos 0:083111ae2a11 891 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
saloutos 0:083111ae2a11 892 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
saloutos 0:083111ae2a11 893
saloutos 0:083111ae2a11 894 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
saloutos 0:083111ae2a11 895 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
saloutos 0:083111ae2a11 896
saloutos 0:083111ae2a11 897 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
saloutos 0:083111ae2a11 898 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
saloutos 0:083111ae2a11 899
saloutos 0:083111ae2a11 900 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
saloutos 0:083111ae2a11 901 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
saloutos 0:083111ae2a11 902
saloutos 0:083111ae2a11 903 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
saloutos 0:083111ae2a11 904 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
saloutos 0:083111ae2a11 905
saloutos 0:083111ae2a11 906 /*@} end of group CMSIS_SCB */
saloutos 0:083111ae2a11 907
saloutos 0:083111ae2a11 908
saloutos 0:083111ae2a11 909 /**
saloutos 0:083111ae2a11 910 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 911 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
saloutos 0:083111ae2a11 912 \brief Type definitions for the System Control and ID Register not in the SCB
saloutos 0:083111ae2a11 913 @{
saloutos 0:083111ae2a11 914 */
saloutos 0:083111ae2a11 915
saloutos 0:083111ae2a11 916 /**
saloutos 0:083111ae2a11 917 \brief Structure type to access the System Control and ID Register not in the SCB.
saloutos 0:083111ae2a11 918 */
saloutos 0:083111ae2a11 919 typedef struct
saloutos 0:083111ae2a11 920 {
saloutos 0:083111ae2a11 921 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 922 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
saloutos 0:083111ae2a11 923 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
saloutos 0:083111ae2a11 924 } SCnSCB_Type;
saloutos 0:083111ae2a11 925
saloutos 0:083111ae2a11 926 /* Interrupt Controller Type Register Definitions */
saloutos 0:083111ae2a11 927 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
saloutos 0:083111ae2a11 928 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
saloutos 0:083111ae2a11 929
saloutos 0:083111ae2a11 930 /* Auxiliary Control Register Definitions */
saloutos 0:083111ae2a11 931 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
saloutos 0:083111ae2a11 932 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
saloutos 0:083111ae2a11 933
saloutos 0:083111ae2a11 934 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
saloutos 0:083111ae2a11 935 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
saloutos 0:083111ae2a11 936
saloutos 0:083111ae2a11 937 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
saloutos 0:083111ae2a11 938 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
saloutos 0:083111ae2a11 939
saloutos 0:083111ae2a11 940 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
saloutos 0:083111ae2a11 941 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
saloutos 0:083111ae2a11 942
saloutos 0:083111ae2a11 943 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
saloutos 0:083111ae2a11 944 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
saloutos 0:083111ae2a11 945
saloutos 0:083111ae2a11 946 /*@} end of group CMSIS_SCnotSCB */
saloutos 0:083111ae2a11 947
saloutos 0:083111ae2a11 948
saloutos 0:083111ae2a11 949 /**
saloutos 0:083111ae2a11 950 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 951 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
saloutos 0:083111ae2a11 952 \brief Type definitions for the System Timer Registers.
saloutos 0:083111ae2a11 953 @{
saloutos 0:083111ae2a11 954 */
saloutos 0:083111ae2a11 955
saloutos 0:083111ae2a11 956 /**
saloutos 0:083111ae2a11 957 \brief Structure type to access the System Timer (SysTick).
saloutos 0:083111ae2a11 958 */
saloutos 0:083111ae2a11 959 typedef struct
saloutos 0:083111ae2a11 960 {
saloutos 0:083111ae2a11 961 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
saloutos 0:083111ae2a11 962 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
saloutos 0:083111ae2a11 963 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
saloutos 0:083111ae2a11 964 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
saloutos 0:083111ae2a11 965 } SysTick_Type;
saloutos 0:083111ae2a11 966
saloutos 0:083111ae2a11 967 /* SysTick Control / Status Register Definitions */
saloutos 0:083111ae2a11 968 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
saloutos 0:083111ae2a11 969 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
saloutos 0:083111ae2a11 970
saloutos 0:083111ae2a11 971 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
saloutos 0:083111ae2a11 972 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
saloutos 0:083111ae2a11 973
saloutos 0:083111ae2a11 974 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
saloutos 0:083111ae2a11 975 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
saloutos 0:083111ae2a11 976
saloutos 0:083111ae2a11 977 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
saloutos 0:083111ae2a11 978 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 979
saloutos 0:083111ae2a11 980 /* SysTick Reload Register Definitions */
saloutos 0:083111ae2a11 981 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
saloutos 0:083111ae2a11 982 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
saloutos 0:083111ae2a11 983
saloutos 0:083111ae2a11 984 /* SysTick Current Register Definitions */
saloutos 0:083111ae2a11 985 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
saloutos 0:083111ae2a11 986 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
saloutos 0:083111ae2a11 987
saloutos 0:083111ae2a11 988 /* SysTick Calibration Register Definitions */
saloutos 0:083111ae2a11 989 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
saloutos 0:083111ae2a11 990 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
saloutos 0:083111ae2a11 991
saloutos 0:083111ae2a11 992 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
saloutos 0:083111ae2a11 993 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
saloutos 0:083111ae2a11 994
saloutos 0:083111ae2a11 995 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
saloutos 0:083111ae2a11 996 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
saloutos 0:083111ae2a11 997
saloutos 0:083111ae2a11 998 /*@} end of group CMSIS_SysTick */
saloutos 0:083111ae2a11 999
saloutos 0:083111ae2a11 1000
saloutos 0:083111ae2a11 1001 /**
saloutos 0:083111ae2a11 1002 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1003 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
saloutos 0:083111ae2a11 1004 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
saloutos 0:083111ae2a11 1005 @{
saloutos 0:083111ae2a11 1006 */
saloutos 0:083111ae2a11 1007
saloutos 0:083111ae2a11 1008 /**
saloutos 0:083111ae2a11 1009 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
saloutos 0:083111ae2a11 1010 */
saloutos 0:083111ae2a11 1011 typedef struct
saloutos 0:083111ae2a11 1012 {
saloutos 0:083111ae2a11 1013 __OM union
saloutos 0:083111ae2a11 1014 {
saloutos 0:083111ae2a11 1015 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
saloutos 0:083111ae2a11 1016 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
saloutos 0:083111ae2a11 1017 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
saloutos 0:083111ae2a11 1018 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
saloutos 0:083111ae2a11 1019 uint32_t RESERVED0[864U];
saloutos 0:083111ae2a11 1020 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
saloutos 0:083111ae2a11 1021 uint32_t RESERVED1[15U];
saloutos 0:083111ae2a11 1022 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
saloutos 0:083111ae2a11 1023 uint32_t RESERVED2[15U];
saloutos 0:083111ae2a11 1024 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
saloutos 0:083111ae2a11 1025 uint32_t RESERVED3[29U];
saloutos 0:083111ae2a11 1026 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
saloutos 0:083111ae2a11 1027 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
saloutos 0:083111ae2a11 1028 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
saloutos 0:083111ae2a11 1029 uint32_t RESERVED4[43U];
saloutos 0:083111ae2a11 1030 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
saloutos 0:083111ae2a11 1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
saloutos 0:083111ae2a11 1032 uint32_t RESERVED5[6U];
saloutos 0:083111ae2a11 1033 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
saloutos 0:083111ae2a11 1034 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
saloutos 0:083111ae2a11 1035 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
saloutos 0:083111ae2a11 1036 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
saloutos 0:083111ae2a11 1037 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
saloutos 0:083111ae2a11 1038 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
saloutos 0:083111ae2a11 1039 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
saloutos 0:083111ae2a11 1040 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
saloutos 0:083111ae2a11 1041 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
saloutos 0:083111ae2a11 1042 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
saloutos 0:083111ae2a11 1043 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
saloutos 0:083111ae2a11 1044 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
saloutos 0:083111ae2a11 1045 } ITM_Type;
saloutos 0:083111ae2a11 1046
saloutos 0:083111ae2a11 1047 /* ITM Trace Privilege Register Definitions */
saloutos 0:083111ae2a11 1048 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
saloutos 0:083111ae2a11 1049 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
saloutos 0:083111ae2a11 1050
saloutos 0:083111ae2a11 1051 /* ITM Trace Control Register Definitions */
saloutos 0:083111ae2a11 1052 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
saloutos 0:083111ae2a11 1053 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
saloutos 0:083111ae2a11 1054
saloutos 0:083111ae2a11 1055 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
saloutos 0:083111ae2a11 1056 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
saloutos 0:083111ae2a11 1057
saloutos 0:083111ae2a11 1058 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
saloutos 0:083111ae2a11 1059 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
saloutos 0:083111ae2a11 1060
saloutos 0:083111ae2a11 1061 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
saloutos 0:083111ae2a11 1062 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
saloutos 0:083111ae2a11 1063
saloutos 0:083111ae2a11 1064 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
saloutos 0:083111ae2a11 1065 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
saloutos 0:083111ae2a11 1066
saloutos 0:083111ae2a11 1067 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
saloutos 0:083111ae2a11 1068 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
saloutos 0:083111ae2a11 1069
saloutos 0:083111ae2a11 1070 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
saloutos 0:083111ae2a11 1071 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
saloutos 0:083111ae2a11 1072
saloutos 0:083111ae2a11 1073 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
saloutos 0:083111ae2a11 1074 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
saloutos 0:083111ae2a11 1075
saloutos 0:083111ae2a11 1076 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
saloutos 0:083111ae2a11 1077 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
saloutos 0:083111ae2a11 1078
saloutos 0:083111ae2a11 1079 /* ITM Integration Write Register Definitions */
saloutos 0:083111ae2a11 1080 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
saloutos 0:083111ae2a11 1081 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
saloutos 0:083111ae2a11 1082
saloutos 0:083111ae2a11 1083 /* ITM Integration Read Register Definitions */
saloutos 0:083111ae2a11 1084 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
saloutos 0:083111ae2a11 1085 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
saloutos 0:083111ae2a11 1086
saloutos 0:083111ae2a11 1087 /* ITM Integration Mode Control Register Definitions */
saloutos 0:083111ae2a11 1088 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
saloutos 0:083111ae2a11 1089 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
saloutos 0:083111ae2a11 1090
saloutos 0:083111ae2a11 1091 /* ITM Lock Status Register Definitions */
saloutos 0:083111ae2a11 1092 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
saloutos 0:083111ae2a11 1093 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
saloutos 0:083111ae2a11 1094
saloutos 0:083111ae2a11 1095 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
saloutos 0:083111ae2a11 1096 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
saloutos 0:083111ae2a11 1097
saloutos 0:083111ae2a11 1098 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
saloutos 0:083111ae2a11 1099 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
saloutos 0:083111ae2a11 1100
saloutos 0:083111ae2a11 1101 /*@}*/ /* end of group CMSIS_ITM */
saloutos 0:083111ae2a11 1102
saloutos 0:083111ae2a11 1103
saloutos 0:083111ae2a11 1104 /**
saloutos 0:083111ae2a11 1105 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1106 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
saloutos 0:083111ae2a11 1107 \brief Type definitions for the Data Watchpoint and Trace (DWT)
saloutos 0:083111ae2a11 1108 @{
saloutos 0:083111ae2a11 1109 */
saloutos 0:083111ae2a11 1110
saloutos 0:083111ae2a11 1111 /**
saloutos 0:083111ae2a11 1112 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
saloutos 0:083111ae2a11 1113 */
saloutos 0:083111ae2a11 1114 typedef struct
saloutos 0:083111ae2a11 1115 {
saloutos 0:083111ae2a11 1116 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
saloutos 0:083111ae2a11 1117 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
saloutos 0:083111ae2a11 1118 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
saloutos 0:083111ae2a11 1119 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
saloutos 0:083111ae2a11 1120 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
saloutos 0:083111ae2a11 1121 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
saloutos 0:083111ae2a11 1122 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
saloutos 0:083111ae2a11 1123 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
saloutos 0:083111ae2a11 1124 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
saloutos 0:083111ae2a11 1125 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
saloutos 0:083111ae2a11 1126 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
saloutos 0:083111ae2a11 1127 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 1128 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
saloutos 0:083111ae2a11 1129 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
saloutos 0:083111ae2a11 1130 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
saloutos 0:083111ae2a11 1131 uint32_t RESERVED1[1U];
saloutos 0:083111ae2a11 1132 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
saloutos 0:083111ae2a11 1133 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
saloutos 0:083111ae2a11 1134 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
saloutos 0:083111ae2a11 1135 uint32_t RESERVED2[1U];
saloutos 0:083111ae2a11 1136 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
saloutos 0:083111ae2a11 1137 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
saloutos 0:083111ae2a11 1138 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
saloutos 0:083111ae2a11 1139 uint32_t RESERVED3[981U];
saloutos 0:083111ae2a11 1140 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
saloutos 0:083111ae2a11 1141 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
saloutos 0:083111ae2a11 1142 } DWT_Type;
saloutos 0:083111ae2a11 1143
saloutos 0:083111ae2a11 1144 /* DWT Control Register Definitions */
saloutos 0:083111ae2a11 1145 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
saloutos 0:083111ae2a11 1146 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
saloutos 0:083111ae2a11 1147
saloutos 0:083111ae2a11 1148 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
saloutos 0:083111ae2a11 1149 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
saloutos 0:083111ae2a11 1150
saloutos 0:083111ae2a11 1151 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
saloutos 0:083111ae2a11 1152 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
saloutos 0:083111ae2a11 1153
saloutos 0:083111ae2a11 1154 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
saloutos 0:083111ae2a11 1155 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
saloutos 0:083111ae2a11 1156
saloutos 0:083111ae2a11 1157 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
saloutos 0:083111ae2a11 1158 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
saloutos 0:083111ae2a11 1159
saloutos 0:083111ae2a11 1160 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
saloutos 0:083111ae2a11 1161 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
saloutos 0:083111ae2a11 1162
saloutos 0:083111ae2a11 1163 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
saloutos 0:083111ae2a11 1164 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
saloutos 0:083111ae2a11 1165
saloutos 0:083111ae2a11 1166 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
saloutos 0:083111ae2a11 1167 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
saloutos 0:083111ae2a11 1168
saloutos 0:083111ae2a11 1169 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
saloutos 0:083111ae2a11 1170 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
saloutos 0:083111ae2a11 1171
saloutos 0:083111ae2a11 1172 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
saloutos 0:083111ae2a11 1173 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
saloutos 0:083111ae2a11 1174
saloutos 0:083111ae2a11 1175 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
saloutos 0:083111ae2a11 1176 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
saloutos 0:083111ae2a11 1177
saloutos 0:083111ae2a11 1178 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
saloutos 0:083111ae2a11 1179 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
saloutos 0:083111ae2a11 1180
saloutos 0:083111ae2a11 1181 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
saloutos 0:083111ae2a11 1182 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
saloutos 0:083111ae2a11 1183
saloutos 0:083111ae2a11 1184 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
saloutos 0:083111ae2a11 1185 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
saloutos 0:083111ae2a11 1186
saloutos 0:083111ae2a11 1187 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
saloutos 0:083111ae2a11 1188 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
saloutos 0:083111ae2a11 1189
saloutos 0:083111ae2a11 1190 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
saloutos 0:083111ae2a11 1191 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
saloutos 0:083111ae2a11 1192
saloutos 0:083111ae2a11 1193 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
saloutos 0:083111ae2a11 1194 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
saloutos 0:083111ae2a11 1195
saloutos 0:083111ae2a11 1196 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
saloutos 0:083111ae2a11 1197 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
saloutos 0:083111ae2a11 1198
saloutos 0:083111ae2a11 1199 /* DWT CPI Count Register Definitions */
saloutos 0:083111ae2a11 1200 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
saloutos 0:083111ae2a11 1201 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
saloutos 0:083111ae2a11 1202
saloutos 0:083111ae2a11 1203 /* DWT Exception Overhead Count Register Definitions */
saloutos 0:083111ae2a11 1204 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
saloutos 0:083111ae2a11 1205 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
saloutos 0:083111ae2a11 1206
saloutos 0:083111ae2a11 1207 /* DWT Sleep Count Register Definitions */
saloutos 0:083111ae2a11 1208 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
saloutos 0:083111ae2a11 1209 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
saloutos 0:083111ae2a11 1210
saloutos 0:083111ae2a11 1211 /* DWT LSU Count Register Definitions */
saloutos 0:083111ae2a11 1212 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
saloutos 0:083111ae2a11 1213 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
saloutos 0:083111ae2a11 1214
saloutos 0:083111ae2a11 1215 /* DWT Folded-instruction Count Register Definitions */
saloutos 0:083111ae2a11 1216 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
saloutos 0:083111ae2a11 1217 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
saloutos 0:083111ae2a11 1218
saloutos 0:083111ae2a11 1219 /* DWT Comparator Mask Register Definitions */
saloutos 0:083111ae2a11 1220 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
saloutos 0:083111ae2a11 1221 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
saloutos 0:083111ae2a11 1222
saloutos 0:083111ae2a11 1223 /* DWT Comparator Function Register Definitions */
saloutos 0:083111ae2a11 1224 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
saloutos 0:083111ae2a11 1225 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
saloutos 0:083111ae2a11 1226
saloutos 0:083111ae2a11 1227 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
saloutos 0:083111ae2a11 1228 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
saloutos 0:083111ae2a11 1229
saloutos 0:083111ae2a11 1230 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
saloutos 0:083111ae2a11 1231 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
saloutos 0:083111ae2a11 1232
saloutos 0:083111ae2a11 1233 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
saloutos 0:083111ae2a11 1234 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
saloutos 0:083111ae2a11 1235
saloutos 0:083111ae2a11 1236 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
saloutos 0:083111ae2a11 1237 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
saloutos 0:083111ae2a11 1238
saloutos 0:083111ae2a11 1239 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
saloutos 0:083111ae2a11 1240 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
saloutos 0:083111ae2a11 1241
saloutos 0:083111ae2a11 1242 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
saloutos 0:083111ae2a11 1243 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
saloutos 0:083111ae2a11 1244
saloutos 0:083111ae2a11 1245 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
saloutos 0:083111ae2a11 1246 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
saloutos 0:083111ae2a11 1247
saloutos 0:083111ae2a11 1248 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
saloutos 0:083111ae2a11 1249 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
saloutos 0:083111ae2a11 1250
saloutos 0:083111ae2a11 1251 /*@}*/ /* end of group CMSIS_DWT */
saloutos 0:083111ae2a11 1252
saloutos 0:083111ae2a11 1253
saloutos 0:083111ae2a11 1254 /**
saloutos 0:083111ae2a11 1255 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1256 \defgroup CMSIS_TPI Trace Port Interface (TPI)
saloutos 0:083111ae2a11 1257 \brief Type definitions for the Trace Port Interface (TPI)
saloutos 0:083111ae2a11 1258 @{
saloutos 0:083111ae2a11 1259 */
saloutos 0:083111ae2a11 1260
saloutos 0:083111ae2a11 1261 /**
saloutos 0:083111ae2a11 1262 \brief Structure type to access the Trace Port Interface Register (TPI).
saloutos 0:083111ae2a11 1263 */
saloutos 0:083111ae2a11 1264 typedef struct
saloutos 0:083111ae2a11 1265 {
saloutos 0:083111ae2a11 1266 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
saloutos 0:083111ae2a11 1267 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
saloutos 0:083111ae2a11 1268 uint32_t RESERVED0[2U];
saloutos 0:083111ae2a11 1269 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
saloutos 0:083111ae2a11 1270 uint32_t RESERVED1[55U];
saloutos 0:083111ae2a11 1271 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
saloutos 0:083111ae2a11 1272 uint32_t RESERVED2[131U];
saloutos 0:083111ae2a11 1273 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
saloutos 0:083111ae2a11 1274 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
saloutos 0:083111ae2a11 1275 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
saloutos 0:083111ae2a11 1276 uint32_t RESERVED3[759U];
saloutos 0:083111ae2a11 1277 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
saloutos 0:083111ae2a11 1278 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
saloutos 0:083111ae2a11 1279 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
saloutos 0:083111ae2a11 1280 uint32_t RESERVED4[1U];
saloutos 0:083111ae2a11 1281 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
saloutos 0:083111ae2a11 1282 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
saloutos 0:083111ae2a11 1283 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
saloutos 0:083111ae2a11 1284 uint32_t RESERVED5[39U];
saloutos 0:083111ae2a11 1285 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
saloutos 0:083111ae2a11 1286 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
saloutos 0:083111ae2a11 1287 uint32_t RESERVED7[8U];
saloutos 0:083111ae2a11 1288 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
saloutos 0:083111ae2a11 1289 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
saloutos 0:083111ae2a11 1290 } TPI_Type;
saloutos 0:083111ae2a11 1291
saloutos 0:083111ae2a11 1292 /* TPI Asynchronous Clock Prescaler Register Definitions */
saloutos 0:083111ae2a11 1293 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
saloutos 0:083111ae2a11 1294 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
saloutos 0:083111ae2a11 1295
saloutos 0:083111ae2a11 1296 /* TPI Selected Pin Protocol Register Definitions */
saloutos 0:083111ae2a11 1297 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
saloutos 0:083111ae2a11 1298 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
saloutos 0:083111ae2a11 1299
saloutos 0:083111ae2a11 1300 /* TPI Formatter and Flush Status Register Definitions */
saloutos 0:083111ae2a11 1301 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
saloutos 0:083111ae2a11 1302 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
saloutos 0:083111ae2a11 1303
saloutos 0:083111ae2a11 1304 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
saloutos 0:083111ae2a11 1305 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
saloutos 0:083111ae2a11 1306
saloutos 0:083111ae2a11 1307 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
saloutos 0:083111ae2a11 1308 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
saloutos 0:083111ae2a11 1309
saloutos 0:083111ae2a11 1310 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
saloutos 0:083111ae2a11 1311 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
saloutos 0:083111ae2a11 1312
saloutos 0:083111ae2a11 1313 /* TPI Formatter and Flush Control Register Definitions */
saloutos 0:083111ae2a11 1314 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
saloutos 0:083111ae2a11 1315 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
saloutos 0:083111ae2a11 1316
saloutos 0:083111ae2a11 1317 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
saloutos 0:083111ae2a11 1318 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
saloutos 0:083111ae2a11 1319
saloutos 0:083111ae2a11 1320 /* TPI TRIGGER Register Definitions */
saloutos 0:083111ae2a11 1321 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
saloutos 0:083111ae2a11 1322 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
saloutos 0:083111ae2a11 1323
saloutos 0:083111ae2a11 1324 /* TPI Integration ETM Data Register Definitions (FIFO0) */
saloutos 0:083111ae2a11 1325 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
saloutos 0:083111ae2a11 1326 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
saloutos 0:083111ae2a11 1327
saloutos 0:083111ae2a11 1328 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
saloutos 0:083111ae2a11 1329 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
saloutos 0:083111ae2a11 1330
saloutos 0:083111ae2a11 1331 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
saloutos 0:083111ae2a11 1332 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
saloutos 0:083111ae2a11 1333
saloutos 0:083111ae2a11 1334 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
saloutos 0:083111ae2a11 1335 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
saloutos 0:083111ae2a11 1336
saloutos 0:083111ae2a11 1337 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
saloutos 0:083111ae2a11 1338 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
saloutos 0:083111ae2a11 1339
saloutos 0:083111ae2a11 1340 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
saloutos 0:083111ae2a11 1341 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
saloutos 0:083111ae2a11 1342
saloutos 0:083111ae2a11 1343 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
saloutos 0:083111ae2a11 1344 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
saloutos 0:083111ae2a11 1345
saloutos 0:083111ae2a11 1346 /* TPI ITATBCTR2 Register Definitions */
saloutos 0:083111ae2a11 1347 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
saloutos 0:083111ae2a11 1348 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
saloutos 0:083111ae2a11 1349
saloutos 0:083111ae2a11 1350 /* TPI Integration ITM Data Register Definitions (FIFO1) */
saloutos 0:083111ae2a11 1351 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
saloutos 0:083111ae2a11 1352 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
saloutos 0:083111ae2a11 1353
saloutos 0:083111ae2a11 1354 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
saloutos 0:083111ae2a11 1355 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
saloutos 0:083111ae2a11 1356
saloutos 0:083111ae2a11 1357 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
saloutos 0:083111ae2a11 1358 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
saloutos 0:083111ae2a11 1359
saloutos 0:083111ae2a11 1360 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
saloutos 0:083111ae2a11 1361 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
saloutos 0:083111ae2a11 1362
saloutos 0:083111ae2a11 1363 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
saloutos 0:083111ae2a11 1364 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
saloutos 0:083111ae2a11 1365
saloutos 0:083111ae2a11 1366 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
saloutos 0:083111ae2a11 1367 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
saloutos 0:083111ae2a11 1368
saloutos 0:083111ae2a11 1369 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
saloutos 0:083111ae2a11 1370 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
saloutos 0:083111ae2a11 1371
saloutos 0:083111ae2a11 1372 /* TPI ITATBCTR0 Register Definitions */
saloutos 0:083111ae2a11 1373 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
saloutos 0:083111ae2a11 1374 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
saloutos 0:083111ae2a11 1375
saloutos 0:083111ae2a11 1376 /* TPI Integration Mode Control Register Definitions */
saloutos 0:083111ae2a11 1377 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
saloutos 0:083111ae2a11 1378 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
saloutos 0:083111ae2a11 1379
saloutos 0:083111ae2a11 1380 /* TPI DEVID Register Definitions */
saloutos 0:083111ae2a11 1381 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
saloutos 0:083111ae2a11 1382 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
saloutos 0:083111ae2a11 1383
saloutos 0:083111ae2a11 1384 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
saloutos 0:083111ae2a11 1385 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
saloutos 0:083111ae2a11 1386
saloutos 0:083111ae2a11 1387 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
saloutos 0:083111ae2a11 1388 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
saloutos 0:083111ae2a11 1389
saloutos 0:083111ae2a11 1390 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
saloutos 0:083111ae2a11 1391 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
saloutos 0:083111ae2a11 1392
saloutos 0:083111ae2a11 1393 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
saloutos 0:083111ae2a11 1394 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
saloutos 0:083111ae2a11 1395
saloutos 0:083111ae2a11 1396 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
saloutos 0:083111ae2a11 1397 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
saloutos 0:083111ae2a11 1398
saloutos 0:083111ae2a11 1399 /* TPI DEVTYPE Register Definitions */
saloutos 0:083111ae2a11 1400 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
saloutos 0:083111ae2a11 1401 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
saloutos 0:083111ae2a11 1402
saloutos 0:083111ae2a11 1403 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
saloutos 0:083111ae2a11 1404 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
saloutos 0:083111ae2a11 1405
saloutos 0:083111ae2a11 1406 /*@}*/ /* end of group CMSIS_TPI */
saloutos 0:083111ae2a11 1407
saloutos 0:083111ae2a11 1408
saloutos 0:083111ae2a11 1409 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 1410 /**
saloutos 0:083111ae2a11 1411 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1412 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 1413 \brief Type definitions for the Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 1414 @{
saloutos 0:083111ae2a11 1415 */
saloutos 0:083111ae2a11 1416
saloutos 0:083111ae2a11 1417 /**
saloutos 0:083111ae2a11 1418 \brief Structure type to access the Memory Protection Unit (MPU).
saloutos 0:083111ae2a11 1419 */
saloutos 0:083111ae2a11 1420 typedef struct
saloutos 0:083111ae2a11 1421 {
saloutos 0:083111ae2a11 1422 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
saloutos 0:083111ae2a11 1423 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
saloutos 0:083111ae2a11 1424 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
saloutos 0:083111ae2a11 1425 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
saloutos 0:083111ae2a11 1426 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
saloutos 0:083111ae2a11 1427 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
saloutos 0:083111ae2a11 1428 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1429 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
saloutos 0:083111ae2a11 1430 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1431 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
saloutos 0:083111ae2a11 1432 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
saloutos 0:083111ae2a11 1433 } MPU_Type;
saloutos 0:083111ae2a11 1434
saloutos 0:083111ae2a11 1435 /* MPU Type Register Definitions */
saloutos 0:083111ae2a11 1436 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
saloutos 0:083111ae2a11 1437 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
saloutos 0:083111ae2a11 1438
saloutos 0:083111ae2a11 1439 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
saloutos 0:083111ae2a11 1440 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
saloutos 0:083111ae2a11 1441
saloutos 0:083111ae2a11 1442 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
saloutos 0:083111ae2a11 1443 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
saloutos 0:083111ae2a11 1444
saloutos 0:083111ae2a11 1445 /* MPU Control Register Definitions */
saloutos 0:083111ae2a11 1446 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
saloutos 0:083111ae2a11 1447 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
saloutos 0:083111ae2a11 1448
saloutos 0:083111ae2a11 1449 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
saloutos 0:083111ae2a11 1450 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
saloutos 0:083111ae2a11 1451
saloutos 0:083111ae2a11 1452 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
saloutos 0:083111ae2a11 1453 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 1454
saloutos 0:083111ae2a11 1455 /* MPU Region Number Register Definitions */
saloutos 0:083111ae2a11 1456 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
saloutos 0:083111ae2a11 1457 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
saloutos 0:083111ae2a11 1458
saloutos 0:083111ae2a11 1459 /* MPU Region Base Address Register Definitions */
saloutos 0:083111ae2a11 1460 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
saloutos 0:083111ae2a11 1461 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
saloutos 0:083111ae2a11 1462
saloutos 0:083111ae2a11 1463 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
saloutos 0:083111ae2a11 1464 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
saloutos 0:083111ae2a11 1465
saloutos 0:083111ae2a11 1466 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
saloutos 0:083111ae2a11 1467 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
saloutos 0:083111ae2a11 1468
saloutos 0:083111ae2a11 1469 /* MPU Region Attribute and Size Register Definitions */
saloutos 0:083111ae2a11 1470 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
saloutos 0:083111ae2a11 1471 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
saloutos 0:083111ae2a11 1472
saloutos 0:083111ae2a11 1473 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
saloutos 0:083111ae2a11 1474 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
saloutos 0:083111ae2a11 1475
saloutos 0:083111ae2a11 1476 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
saloutos 0:083111ae2a11 1477 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
saloutos 0:083111ae2a11 1478
saloutos 0:083111ae2a11 1479 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
saloutos 0:083111ae2a11 1480 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
saloutos 0:083111ae2a11 1481
saloutos 0:083111ae2a11 1482 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
saloutos 0:083111ae2a11 1483 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
saloutos 0:083111ae2a11 1484
saloutos 0:083111ae2a11 1485 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
saloutos 0:083111ae2a11 1486 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
saloutos 0:083111ae2a11 1487
saloutos 0:083111ae2a11 1488 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
saloutos 0:083111ae2a11 1489 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
saloutos 0:083111ae2a11 1490
saloutos 0:083111ae2a11 1491 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
saloutos 0:083111ae2a11 1492 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
saloutos 0:083111ae2a11 1493
saloutos 0:083111ae2a11 1494 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
saloutos 0:083111ae2a11 1495 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
saloutos 0:083111ae2a11 1496
saloutos 0:083111ae2a11 1497 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
saloutos 0:083111ae2a11 1498 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
saloutos 0:083111ae2a11 1499
saloutos 0:083111ae2a11 1500 /*@} end of group CMSIS_MPU */
saloutos 0:083111ae2a11 1501 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
saloutos 0:083111ae2a11 1502
saloutos 0:083111ae2a11 1503
saloutos 0:083111ae2a11 1504 /**
saloutos 0:083111ae2a11 1505 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1506 \defgroup CMSIS_FPU Floating Point Unit (FPU)
saloutos 0:083111ae2a11 1507 \brief Type definitions for the Floating Point Unit (FPU)
saloutos 0:083111ae2a11 1508 @{
saloutos 0:083111ae2a11 1509 */
saloutos 0:083111ae2a11 1510
saloutos 0:083111ae2a11 1511 /**
saloutos 0:083111ae2a11 1512 \brief Structure type to access the Floating Point Unit (FPU).
saloutos 0:083111ae2a11 1513 */
saloutos 0:083111ae2a11 1514 typedef struct
saloutos 0:083111ae2a11 1515 {
saloutos 0:083111ae2a11 1516 uint32_t RESERVED0[1U];
saloutos 0:083111ae2a11 1517 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
saloutos 0:083111ae2a11 1518 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
saloutos 0:083111ae2a11 1519 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
saloutos 0:083111ae2a11 1520 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
saloutos 0:083111ae2a11 1521 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
saloutos 0:083111ae2a11 1522 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
saloutos 0:083111ae2a11 1523 } FPU_Type;
saloutos 0:083111ae2a11 1524
saloutos 0:083111ae2a11 1525 /* Floating-Point Context Control Register Definitions */
saloutos 0:083111ae2a11 1526 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
saloutos 0:083111ae2a11 1527 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
saloutos 0:083111ae2a11 1528
saloutos 0:083111ae2a11 1529 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
saloutos 0:083111ae2a11 1530 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
saloutos 0:083111ae2a11 1531
saloutos 0:083111ae2a11 1532 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
saloutos 0:083111ae2a11 1533 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
saloutos 0:083111ae2a11 1534
saloutos 0:083111ae2a11 1535 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
saloutos 0:083111ae2a11 1536 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
saloutos 0:083111ae2a11 1537
saloutos 0:083111ae2a11 1538 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
saloutos 0:083111ae2a11 1539 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
saloutos 0:083111ae2a11 1540
saloutos 0:083111ae2a11 1541 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
saloutos 0:083111ae2a11 1542 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
saloutos 0:083111ae2a11 1543
saloutos 0:083111ae2a11 1544 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
saloutos 0:083111ae2a11 1545 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
saloutos 0:083111ae2a11 1546
saloutos 0:083111ae2a11 1547 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
saloutos 0:083111ae2a11 1548 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
saloutos 0:083111ae2a11 1549
saloutos 0:083111ae2a11 1550 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
saloutos 0:083111ae2a11 1551 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
saloutos 0:083111ae2a11 1552
saloutos 0:083111ae2a11 1553 /* Floating-Point Context Address Register Definitions */
saloutos 0:083111ae2a11 1554 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
saloutos 0:083111ae2a11 1555 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
saloutos 0:083111ae2a11 1556
saloutos 0:083111ae2a11 1557 /* Floating-Point Default Status Control Register Definitions */
saloutos 0:083111ae2a11 1558 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
saloutos 0:083111ae2a11 1559 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
saloutos 0:083111ae2a11 1560
saloutos 0:083111ae2a11 1561 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
saloutos 0:083111ae2a11 1562 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
saloutos 0:083111ae2a11 1563
saloutos 0:083111ae2a11 1564 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
saloutos 0:083111ae2a11 1565 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
saloutos 0:083111ae2a11 1566
saloutos 0:083111ae2a11 1567 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
saloutos 0:083111ae2a11 1568 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
saloutos 0:083111ae2a11 1569
saloutos 0:083111ae2a11 1570 /* Media and FP Feature Register 0 Definitions */
saloutos 0:083111ae2a11 1571 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
saloutos 0:083111ae2a11 1572 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
saloutos 0:083111ae2a11 1573
saloutos 0:083111ae2a11 1574 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
saloutos 0:083111ae2a11 1575 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
saloutos 0:083111ae2a11 1576
saloutos 0:083111ae2a11 1577 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
saloutos 0:083111ae2a11 1578 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
saloutos 0:083111ae2a11 1579
saloutos 0:083111ae2a11 1580 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
saloutos 0:083111ae2a11 1581 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
saloutos 0:083111ae2a11 1582
saloutos 0:083111ae2a11 1583 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
saloutos 0:083111ae2a11 1584 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
saloutos 0:083111ae2a11 1585
saloutos 0:083111ae2a11 1586 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
saloutos 0:083111ae2a11 1587 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
saloutos 0:083111ae2a11 1588
saloutos 0:083111ae2a11 1589 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
saloutos 0:083111ae2a11 1590 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
saloutos 0:083111ae2a11 1591
saloutos 0:083111ae2a11 1592 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
saloutos 0:083111ae2a11 1593 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
saloutos 0:083111ae2a11 1594
saloutos 0:083111ae2a11 1595 /* Media and FP Feature Register 1 Definitions */
saloutos 0:083111ae2a11 1596 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
saloutos 0:083111ae2a11 1597 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
saloutos 0:083111ae2a11 1598
saloutos 0:083111ae2a11 1599 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
saloutos 0:083111ae2a11 1600 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
saloutos 0:083111ae2a11 1601
saloutos 0:083111ae2a11 1602 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
saloutos 0:083111ae2a11 1603 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
saloutos 0:083111ae2a11 1604
saloutos 0:083111ae2a11 1605 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
saloutos 0:083111ae2a11 1606 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
saloutos 0:083111ae2a11 1607
saloutos 0:083111ae2a11 1608 /* Media and FP Feature Register 2 Definitions */
saloutos 0:083111ae2a11 1609
saloutos 0:083111ae2a11 1610 /*@} end of group CMSIS_FPU */
saloutos 0:083111ae2a11 1611
saloutos 0:083111ae2a11 1612
saloutos 0:083111ae2a11 1613 /**
saloutos 0:083111ae2a11 1614 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
saloutos 0:083111ae2a11 1616 \brief Type definitions for the Core Debug Registers
saloutos 0:083111ae2a11 1617 @{
saloutos 0:083111ae2a11 1618 */
saloutos 0:083111ae2a11 1619
saloutos 0:083111ae2a11 1620 /**
saloutos 0:083111ae2a11 1621 \brief Structure type to access the Core Debug Register (CoreDebug).
saloutos 0:083111ae2a11 1622 */
saloutos 0:083111ae2a11 1623 typedef struct
saloutos 0:083111ae2a11 1624 {
saloutos 0:083111ae2a11 1625 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
saloutos 0:083111ae2a11 1626 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
saloutos 0:083111ae2a11 1627 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
saloutos 0:083111ae2a11 1628 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
saloutos 0:083111ae2a11 1629 } CoreDebug_Type;
saloutos 0:083111ae2a11 1630
saloutos 0:083111ae2a11 1631 /* Debug Halting Control and Status Register Definitions */
saloutos 0:083111ae2a11 1632 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
saloutos 0:083111ae2a11 1633 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
saloutos 0:083111ae2a11 1634
saloutos 0:083111ae2a11 1635 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
saloutos 0:083111ae2a11 1636 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
saloutos 0:083111ae2a11 1637
saloutos 0:083111ae2a11 1638 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
saloutos 0:083111ae2a11 1639 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
saloutos 0:083111ae2a11 1640
saloutos 0:083111ae2a11 1641 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
saloutos 0:083111ae2a11 1642 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
saloutos 0:083111ae2a11 1643
saloutos 0:083111ae2a11 1644 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
saloutos 0:083111ae2a11 1645 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
saloutos 0:083111ae2a11 1646
saloutos 0:083111ae2a11 1647 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
saloutos 0:083111ae2a11 1648 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
saloutos 0:083111ae2a11 1649
saloutos 0:083111ae2a11 1650 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
saloutos 0:083111ae2a11 1651 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
saloutos 0:083111ae2a11 1652
saloutos 0:083111ae2a11 1653 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
saloutos 0:083111ae2a11 1654 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
saloutos 0:083111ae2a11 1655
saloutos 0:083111ae2a11 1656 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
saloutos 0:083111ae2a11 1657 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
saloutos 0:083111ae2a11 1658
saloutos 0:083111ae2a11 1659 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
saloutos 0:083111ae2a11 1660 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
saloutos 0:083111ae2a11 1661
saloutos 0:083111ae2a11 1662 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
saloutos 0:083111ae2a11 1663 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
saloutos 0:083111ae2a11 1664
saloutos 0:083111ae2a11 1665 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
saloutos 0:083111ae2a11 1666 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
saloutos 0:083111ae2a11 1667
saloutos 0:083111ae2a11 1668 /* Debug Core Register Selector Register Definitions */
saloutos 0:083111ae2a11 1669 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
saloutos 0:083111ae2a11 1670 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
saloutos 0:083111ae2a11 1671
saloutos 0:083111ae2a11 1672 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
saloutos 0:083111ae2a11 1673 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
saloutos 0:083111ae2a11 1674
saloutos 0:083111ae2a11 1675 /* Debug Exception and Monitor Control Register Definitions */
saloutos 0:083111ae2a11 1676 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
saloutos 0:083111ae2a11 1677 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
saloutos 0:083111ae2a11 1678
saloutos 0:083111ae2a11 1679 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
saloutos 0:083111ae2a11 1680 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
saloutos 0:083111ae2a11 1681
saloutos 0:083111ae2a11 1682 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
saloutos 0:083111ae2a11 1683 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
saloutos 0:083111ae2a11 1684
saloutos 0:083111ae2a11 1685 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
saloutos 0:083111ae2a11 1686 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
saloutos 0:083111ae2a11 1687
saloutos 0:083111ae2a11 1688 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
saloutos 0:083111ae2a11 1689 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
saloutos 0:083111ae2a11 1690
saloutos 0:083111ae2a11 1691 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
saloutos 0:083111ae2a11 1692 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
saloutos 0:083111ae2a11 1693
saloutos 0:083111ae2a11 1694 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
saloutos 0:083111ae2a11 1695 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
saloutos 0:083111ae2a11 1696
saloutos 0:083111ae2a11 1697 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
saloutos 0:083111ae2a11 1698 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
saloutos 0:083111ae2a11 1699
saloutos 0:083111ae2a11 1700 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
saloutos 0:083111ae2a11 1701 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
saloutos 0:083111ae2a11 1702
saloutos 0:083111ae2a11 1703 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
saloutos 0:083111ae2a11 1704 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
saloutos 0:083111ae2a11 1705
saloutos 0:083111ae2a11 1706 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
saloutos 0:083111ae2a11 1707 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
saloutos 0:083111ae2a11 1708
saloutos 0:083111ae2a11 1709 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
saloutos 0:083111ae2a11 1710 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
saloutos 0:083111ae2a11 1711
saloutos 0:083111ae2a11 1712 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
saloutos 0:083111ae2a11 1713 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
saloutos 0:083111ae2a11 1714
saloutos 0:083111ae2a11 1715 /*@} end of group CMSIS_CoreDebug */
saloutos 0:083111ae2a11 1716
saloutos 0:083111ae2a11 1717
saloutos 0:083111ae2a11 1718 /**
saloutos 0:083111ae2a11 1719 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1720 \defgroup CMSIS_core_bitfield Core register bit field macros
saloutos 0:083111ae2a11 1721 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
saloutos 0:083111ae2a11 1722 @{
saloutos 0:083111ae2a11 1723 */
saloutos 0:083111ae2a11 1724
saloutos 0:083111ae2a11 1725 /**
saloutos 0:083111ae2a11 1726 \brief Mask and shift a bit field value for use in a register bit range.
saloutos 0:083111ae2a11 1727 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 1728 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 1729 \return Masked and shifted value.
saloutos 0:083111ae2a11 1730 */
saloutos 0:083111ae2a11 1731 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
saloutos 0:083111ae2a11 1732
saloutos 0:083111ae2a11 1733 /**
saloutos 0:083111ae2a11 1734 \brief Mask and shift a register value to extract a bit filed value.
saloutos 0:083111ae2a11 1735 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 1736 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 1737 \return Masked and shifted bit field value.
saloutos 0:083111ae2a11 1738 */
saloutos 0:083111ae2a11 1739 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
saloutos 0:083111ae2a11 1740
saloutos 0:083111ae2a11 1741 /*@} end of group CMSIS_core_bitfield */
saloutos 0:083111ae2a11 1742
saloutos 0:083111ae2a11 1743
saloutos 0:083111ae2a11 1744 /**
saloutos 0:083111ae2a11 1745 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 1746 \defgroup CMSIS_core_base Core Definitions
saloutos 0:083111ae2a11 1747 \brief Definitions for base addresses, unions, and structures.
saloutos 0:083111ae2a11 1748 @{
saloutos 0:083111ae2a11 1749 */
saloutos 0:083111ae2a11 1750
saloutos 0:083111ae2a11 1751 /* Memory mapping of Core Hardware */
saloutos 0:083111ae2a11 1752 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
saloutos 0:083111ae2a11 1753 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
saloutos 0:083111ae2a11 1754 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
saloutos 0:083111ae2a11 1755 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
saloutos 0:083111ae2a11 1756 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
saloutos 0:083111ae2a11 1757 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
saloutos 0:083111ae2a11 1758 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
saloutos 0:083111ae2a11 1759 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
saloutos 0:083111ae2a11 1760
saloutos 0:083111ae2a11 1761 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
saloutos 0:083111ae2a11 1762 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
saloutos 0:083111ae2a11 1763 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
saloutos 0:083111ae2a11 1764 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
saloutos 0:083111ae2a11 1765 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
saloutos 0:083111ae2a11 1766 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
saloutos 0:083111ae2a11 1767 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
saloutos 0:083111ae2a11 1768 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
saloutos 0:083111ae2a11 1769
saloutos 0:083111ae2a11 1770 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 1771 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 1772 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 1773 #endif
saloutos 0:083111ae2a11 1774
saloutos 0:083111ae2a11 1775 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
saloutos 0:083111ae2a11 1776 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
saloutos 0:083111ae2a11 1777
saloutos 0:083111ae2a11 1778 /*@} */
saloutos 0:083111ae2a11 1779
saloutos 0:083111ae2a11 1780
saloutos 0:083111ae2a11 1781
saloutos 0:083111ae2a11 1782 /*******************************************************************************
saloutos 0:083111ae2a11 1783 * Hardware Abstraction Layer
saloutos 0:083111ae2a11 1784 Core Function Interface contains:
saloutos 0:083111ae2a11 1785 - Core NVIC Functions
saloutos 0:083111ae2a11 1786 - Core SysTick Functions
saloutos 0:083111ae2a11 1787 - Core Debug Functions
saloutos 0:083111ae2a11 1788 - Core Register Access Functions
saloutos 0:083111ae2a11 1789 ******************************************************************************/
saloutos 0:083111ae2a11 1790 /**
saloutos 0:083111ae2a11 1791 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
saloutos 0:083111ae2a11 1792 */
saloutos 0:083111ae2a11 1793
saloutos 0:083111ae2a11 1794
saloutos 0:083111ae2a11 1795
saloutos 0:083111ae2a11 1796 /* ########################## NVIC functions #################################### */
saloutos 0:083111ae2a11 1797 /**
saloutos 0:083111ae2a11 1798 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 1799 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
saloutos 0:083111ae2a11 1800 \brief Functions that manage interrupts and exceptions via the NVIC.
saloutos 0:083111ae2a11 1801 @{
saloutos 0:083111ae2a11 1802 */
saloutos 0:083111ae2a11 1803
saloutos 0:083111ae2a11 1804 #ifdef CMSIS_NVIC_VIRTUAL
saloutos 0:083111ae2a11 1805 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1806 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
saloutos 0:083111ae2a11 1807 #endif
saloutos 0:083111ae2a11 1808 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1809 #else
saloutos 0:083111ae2a11 1810 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
saloutos 0:083111ae2a11 1811 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
saloutos 0:083111ae2a11 1812 #define NVIC_EnableIRQ __NVIC_EnableIRQ
saloutos 0:083111ae2a11 1813 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
saloutos 0:083111ae2a11 1814 #define NVIC_DisableIRQ __NVIC_DisableIRQ
saloutos 0:083111ae2a11 1815 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
saloutos 0:083111ae2a11 1816 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
saloutos 0:083111ae2a11 1817 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
saloutos 0:083111ae2a11 1818 #define NVIC_GetActive __NVIC_GetActive
saloutos 0:083111ae2a11 1819 #define NVIC_SetPriority __NVIC_SetPriority
saloutos 0:083111ae2a11 1820 #define NVIC_GetPriority __NVIC_GetPriority
saloutos 0:083111ae2a11 1821 #define NVIC_SystemReset __NVIC_SystemReset
saloutos 0:083111ae2a11 1822 #endif /* CMSIS_NVIC_VIRTUAL */
saloutos 0:083111ae2a11 1823
saloutos 0:083111ae2a11 1824 #ifdef CMSIS_VECTAB_VIRTUAL
saloutos 0:083111ae2a11 1825 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1826 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
saloutos 0:083111ae2a11 1827 #endif
saloutos 0:083111ae2a11 1828 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 1829 #else
saloutos 0:083111ae2a11 1830 #define NVIC_SetVector __NVIC_SetVector
saloutos 0:083111ae2a11 1831 #define NVIC_GetVector __NVIC_GetVector
saloutos 0:083111ae2a11 1832 #endif /* (CMSIS_VECTAB_VIRTUAL) */
saloutos 0:083111ae2a11 1833
saloutos 0:083111ae2a11 1834 #define NVIC_USER_IRQ_OFFSET 16
saloutos 0:083111ae2a11 1835
saloutos 0:083111ae2a11 1836
saloutos 0:083111ae2a11 1837
saloutos 0:083111ae2a11 1838 /**
saloutos 0:083111ae2a11 1839 \brief Set Priority Grouping
saloutos 0:083111ae2a11 1840 \details Sets the priority grouping field using the required unlock sequence.
saloutos 0:083111ae2a11 1841 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
saloutos 0:083111ae2a11 1842 Only values from 0..7 are used.
saloutos 0:083111ae2a11 1843 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 1844 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos 0:083111ae2a11 1845 \param [in] PriorityGroup Priority grouping field.
saloutos 0:083111ae2a11 1846 */
saloutos 0:083111ae2a11 1847 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
saloutos 0:083111ae2a11 1848 {
saloutos 0:083111ae2a11 1849 uint32_t reg_value;
saloutos 0:083111ae2a11 1850 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 1851
saloutos 0:083111ae2a11 1852 reg_value = SCB->AIRCR; /* read old register configuration */
saloutos 0:083111ae2a11 1853 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
saloutos 0:083111ae2a11 1854 reg_value = (reg_value |
saloutos 0:083111ae2a11 1855 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
saloutos 0:083111ae2a11 1856 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
saloutos 0:083111ae2a11 1857 SCB->AIRCR = reg_value;
saloutos 0:083111ae2a11 1858 }
saloutos 0:083111ae2a11 1859
saloutos 0:083111ae2a11 1860
saloutos 0:083111ae2a11 1861 /**
saloutos 0:083111ae2a11 1862 \brief Get Priority Grouping
saloutos 0:083111ae2a11 1863 \details Reads the priority grouping field from the NVIC Interrupt Controller.
saloutos 0:083111ae2a11 1864 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
saloutos 0:083111ae2a11 1865 */
saloutos 0:083111ae2a11 1866 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
saloutos 0:083111ae2a11 1867 {
saloutos 0:083111ae2a11 1868 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
saloutos 0:083111ae2a11 1869 }
saloutos 0:083111ae2a11 1870
saloutos 0:083111ae2a11 1871
saloutos 0:083111ae2a11 1872 /**
saloutos 0:083111ae2a11 1873 \brief Enable Interrupt
saloutos 0:083111ae2a11 1874 \details Enables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 1875 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1876 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1877 */
saloutos 0:083111ae2a11 1878 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1879 {
saloutos 0:083111ae2a11 1880 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1881 {
saloutos 0:083111ae2a11 1882 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1883 }
saloutos 0:083111ae2a11 1884 }
saloutos 0:083111ae2a11 1885
saloutos 0:083111ae2a11 1886
saloutos 0:083111ae2a11 1887 /**
saloutos 0:083111ae2a11 1888 \brief Get Interrupt Enable status
saloutos 0:083111ae2a11 1889 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
saloutos 0:083111ae2a11 1890 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1891 \return 0 Interrupt is not enabled.
saloutos 0:083111ae2a11 1892 \return 1 Interrupt is enabled.
saloutos 0:083111ae2a11 1893 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1894 */
saloutos 0:083111ae2a11 1895 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1896 {
saloutos 0:083111ae2a11 1897 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1898 {
saloutos 0:083111ae2a11 1899 return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1900 }
saloutos 0:083111ae2a11 1901 else
saloutos 0:083111ae2a11 1902 {
saloutos 0:083111ae2a11 1903 return(0U);
saloutos 0:083111ae2a11 1904 }
saloutos 0:083111ae2a11 1905 }
saloutos 0:083111ae2a11 1906
saloutos 0:083111ae2a11 1907
saloutos 0:083111ae2a11 1908 /**
saloutos 0:083111ae2a11 1909 \brief Disable Interrupt
saloutos 0:083111ae2a11 1910 \details Disables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 1911 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1912 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1913 */
saloutos 0:083111ae2a11 1914 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1915 {
saloutos 0:083111ae2a11 1916 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1917 {
saloutos 0:083111ae2a11 1918 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1919 __DSB();
saloutos 0:083111ae2a11 1920 __ISB();
saloutos 0:083111ae2a11 1921 }
saloutos 0:083111ae2a11 1922 }
saloutos 0:083111ae2a11 1923
saloutos 0:083111ae2a11 1924
saloutos 0:083111ae2a11 1925 /**
saloutos 0:083111ae2a11 1926 \brief Get Pending Interrupt
saloutos 0:083111ae2a11 1927 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
saloutos 0:083111ae2a11 1928 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1929 \return 0 Interrupt status is not pending.
saloutos 0:083111ae2a11 1930 \return 1 Interrupt status is pending.
saloutos 0:083111ae2a11 1931 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1932 */
saloutos 0:083111ae2a11 1933 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1934 {
saloutos 0:083111ae2a11 1935 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1936 {
saloutos 0:083111ae2a11 1937 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1938 }
saloutos 0:083111ae2a11 1939 else
saloutos 0:083111ae2a11 1940 {
saloutos 0:083111ae2a11 1941 return(0U);
saloutos 0:083111ae2a11 1942 }
saloutos 0:083111ae2a11 1943 }
saloutos 0:083111ae2a11 1944
saloutos 0:083111ae2a11 1945
saloutos 0:083111ae2a11 1946 /**
saloutos 0:083111ae2a11 1947 \brief Set Pending Interrupt
saloutos 0:083111ae2a11 1948 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 1949 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1950 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1951 */
saloutos 0:083111ae2a11 1952 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1953 {
saloutos 0:083111ae2a11 1954 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1955 {
saloutos 0:083111ae2a11 1956 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1957 }
saloutos 0:083111ae2a11 1958 }
saloutos 0:083111ae2a11 1959
saloutos 0:083111ae2a11 1960
saloutos 0:083111ae2a11 1961 /**
saloutos 0:083111ae2a11 1962 \brief Clear Pending Interrupt
saloutos 0:083111ae2a11 1963 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 1964 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1965 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1966 */
saloutos 0:083111ae2a11 1967 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1968 {
saloutos 0:083111ae2a11 1969 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1970 {
saloutos 0:083111ae2a11 1971 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 1972 }
saloutos 0:083111ae2a11 1973 }
saloutos 0:083111ae2a11 1974
saloutos 0:083111ae2a11 1975
saloutos 0:083111ae2a11 1976 /**
saloutos 0:083111ae2a11 1977 \brief Get Active Interrupt
saloutos 0:083111ae2a11 1978 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
saloutos 0:083111ae2a11 1979 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 1980 \return 0 Interrupt status is not active.
saloutos 0:083111ae2a11 1981 \return 1 Interrupt status is active.
saloutos 0:083111ae2a11 1982 \note IRQn must not be negative.
saloutos 0:083111ae2a11 1983 */
saloutos 0:083111ae2a11 1984 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
saloutos 0:083111ae2a11 1985 {
saloutos 0:083111ae2a11 1986 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 1987 {
saloutos 0:083111ae2a11 1988 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 1989 }
saloutos 0:083111ae2a11 1990 else
saloutos 0:083111ae2a11 1991 {
saloutos 0:083111ae2a11 1992 return(0U);
saloutos 0:083111ae2a11 1993 }
saloutos 0:083111ae2a11 1994 }
saloutos 0:083111ae2a11 1995
saloutos 0:083111ae2a11 1996
saloutos 0:083111ae2a11 1997 /**
saloutos 0:083111ae2a11 1998 \brief Set Interrupt Priority
saloutos 0:083111ae2a11 1999 \details Sets the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 2000 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 2001 or negative to specify a processor exception.
saloutos 0:083111ae2a11 2002 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 2003 \param [in] priority Priority to set.
saloutos 0:083111ae2a11 2004 \note The priority cannot be set for every processor exception.
saloutos 0:083111ae2a11 2005 */
saloutos 0:083111ae2a11 2006 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
saloutos 0:083111ae2a11 2007 {
saloutos 0:083111ae2a11 2008 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 2009 {
saloutos 0:083111ae2a11 2010 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos 0:083111ae2a11 2011 }
saloutos 0:083111ae2a11 2012 else
saloutos 0:083111ae2a11 2013 {
saloutos 0:083111ae2a11 2014 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
saloutos 0:083111ae2a11 2015 }
saloutos 0:083111ae2a11 2016 }
saloutos 0:083111ae2a11 2017
saloutos 0:083111ae2a11 2018
saloutos 0:083111ae2a11 2019 /**
saloutos 0:083111ae2a11 2020 \brief Get Interrupt Priority
saloutos 0:083111ae2a11 2021 \details Reads the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 2022 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 2023 or negative to specify a processor exception.
saloutos 0:083111ae2a11 2024 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 2025 \return Interrupt Priority.
saloutos 0:083111ae2a11 2026 Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos 0:083111ae2a11 2027 */
saloutos 0:083111ae2a11 2028 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
saloutos 0:083111ae2a11 2029 {
saloutos 0:083111ae2a11 2030
saloutos 0:083111ae2a11 2031 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 2032 {
saloutos 0:083111ae2a11 2033 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 2034 }
saloutos 0:083111ae2a11 2035 else
saloutos 0:083111ae2a11 2036 {
saloutos 0:083111ae2a11 2037 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 2038 }
saloutos 0:083111ae2a11 2039 }
saloutos 0:083111ae2a11 2040
saloutos 0:083111ae2a11 2041
saloutos 0:083111ae2a11 2042 /**
saloutos 0:083111ae2a11 2043 \brief Encode Priority
saloutos 0:083111ae2a11 2044 \details Encodes the priority for an interrupt with the given priority group,
saloutos 0:083111ae2a11 2045 preemptive priority value, and subpriority value.
saloutos 0:083111ae2a11 2046 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 2047 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
saloutos 0:083111ae2a11 2048 \param [in] PriorityGroup Used priority group.
saloutos 0:083111ae2a11 2049 \param [in] PreemptPriority Preemptive priority value (starting from 0).
saloutos 0:083111ae2a11 2050 \param [in] SubPriority Subpriority value (starting from 0).
saloutos 0:083111ae2a11 2051 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
saloutos 0:083111ae2a11 2052 */
saloutos 0:083111ae2a11 2053 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
saloutos 0:083111ae2a11 2054 {
saloutos 0:083111ae2a11 2055 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 2056 uint32_t PreemptPriorityBits;
saloutos 0:083111ae2a11 2057 uint32_t SubPriorityBits;
saloutos 0:083111ae2a11 2058
saloutos 0:083111ae2a11 2059 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos 0:083111ae2a11 2060 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos 0:083111ae2a11 2061
saloutos 0:083111ae2a11 2062 return (
saloutos 0:083111ae2a11 2063 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
saloutos 0:083111ae2a11 2064 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
saloutos 0:083111ae2a11 2065 );
saloutos 0:083111ae2a11 2066 }
saloutos 0:083111ae2a11 2067
saloutos 0:083111ae2a11 2068
saloutos 0:083111ae2a11 2069 /**
saloutos 0:083111ae2a11 2070 \brief Decode Priority
saloutos 0:083111ae2a11 2071 \details Decodes an interrupt priority value with a given priority group to
saloutos 0:083111ae2a11 2072 preemptive priority value and subpriority value.
saloutos 0:083111ae2a11 2073 In case of a conflict between priority grouping and available
saloutos 0:083111ae2a11 2074 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
saloutos 0:083111ae2a11 2075 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
saloutos 0:083111ae2a11 2076 \param [in] PriorityGroup Used priority group.
saloutos 0:083111ae2a11 2077 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
saloutos 0:083111ae2a11 2078 \param [out] pSubPriority Subpriority value (starting from 0).
saloutos 0:083111ae2a11 2079 */
saloutos 0:083111ae2a11 2080 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
saloutos 0:083111ae2a11 2081 {
saloutos 0:083111ae2a11 2082 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
saloutos 0:083111ae2a11 2083 uint32_t PreemptPriorityBits;
saloutos 0:083111ae2a11 2084 uint32_t SubPriorityBits;
saloutos 0:083111ae2a11 2085
saloutos 0:083111ae2a11 2086 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
saloutos 0:083111ae2a11 2087 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
saloutos 0:083111ae2a11 2088
saloutos 0:083111ae2a11 2089 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
saloutos 0:083111ae2a11 2090 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
saloutos 0:083111ae2a11 2091 }
saloutos 0:083111ae2a11 2092
saloutos 0:083111ae2a11 2093
saloutos 0:083111ae2a11 2094 /**
saloutos 0:083111ae2a11 2095 \brief Set Interrupt Vector
saloutos 0:083111ae2a11 2096 \details Sets an interrupt vector in SRAM based interrupt vector table.
saloutos 0:083111ae2a11 2097 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 2098 or negative to specify a processor exception.
saloutos 0:083111ae2a11 2099 VTOR must been relocated to SRAM before.
saloutos 0:083111ae2a11 2100 \param [in] IRQn Interrupt number
saloutos 0:083111ae2a11 2101 \param [in] vector Address of interrupt handler function
saloutos 0:083111ae2a11 2102 */
saloutos 0:083111ae2a11 2103 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
saloutos 0:083111ae2a11 2104 {
saloutos 0:083111ae2a11 2105 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 2106 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
saloutos 0:083111ae2a11 2107 }
saloutos 0:083111ae2a11 2108
saloutos 0:083111ae2a11 2109
saloutos 0:083111ae2a11 2110 /**
saloutos 0:083111ae2a11 2111 \brief Get Interrupt Vector
saloutos 0:083111ae2a11 2112 \details Reads an interrupt vector from interrupt vector table.
saloutos 0:083111ae2a11 2113 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 2114 or negative to specify a processor exception.
saloutos 0:083111ae2a11 2115 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 2116 \return Address of interrupt handler function
saloutos 0:083111ae2a11 2117 */
saloutos 0:083111ae2a11 2118 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
saloutos 0:083111ae2a11 2119 {
saloutos 0:083111ae2a11 2120 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 2121 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
saloutos 0:083111ae2a11 2122 }
saloutos 0:083111ae2a11 2123
saloutos 0:083111ae2a11 2124
saloutos 0:083111ae2a11 2125 /**
saloutos 0:083111ae2a11 2126 \brief System Reset
saloutos 0:083111ae2a11 2127 \details Initiates a system reset request to reset the MCU.
saloutos 0:083111ae2a11 2128 */
saloutos 0:083111ae2a11 2129 __STATIC_INLINE void __NVIC_SystemReset(void)
saloutos 0:083111ae2a11 2130 {
saloutos 0:083111ae2a11 2131 __DSB(); /* Ensure all outstanding memory accesses included
saloutos 0:083111ae2a11 2132 buffered write are completed before reset */
saloutos 0:083111ae2a11 2133 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
saloutos 0:083111ae2a11 2134 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
saloutos 0:083111ae2a11 2135 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
saloutos 0:083111ae2a11 2136 __DSB(); /* Ensure completion of memory access */
saloutos 0:083111ae2a11 2137
saloutos 0:083111ae2a11 2138 for(;;) /* wait until reset */
saloutos 0:083111ae2a11 2139 {
saloutos 0:083111ae2a11 2140 __NOP();
saloutos 0:083111ae2a11 2141 }
saloutos 0:083111ae2a11 2142 }
saloutos 0:083111ae2a11 2143
saloutos 0:083111ae2a11 2144 /*@} end of CMSIS_Core_NVICFunctions */
saloutos 0:083111ae2a11 2145
saloutos 0:083111ae2a11 2146
saloutos 0:083111ae2a11 2147 /* ########################## FPU functions #################################### */
saloutos 0:083111ae2a11 2148 /**
saloutos 0:083111ae2a11 2149 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 2150 \defgroup CMSIS_Core_FpuFunctions FPU Functions
saloutos 0:083111ae2a11 2151 \brief Function that provides FPU type.
saloutos 0:083111ae2a11 2152 @{
saloutos 0:083111ae2a11 2153 */
saloutos 0:083111ae2a11 2154
saloutos 0:083111ae2a11 2155 /**
saloutos 0:083111ae2a11 2156 \brief get FPU type
saloutos 0:083111ae2a11 2157 \details returns the FPU type
saloutos 0:083111ae2a11 2158 \returns
saloutos 0:083111ae2a11 2159 - \b 0: No FPU
saloutos 0:083111ae2a11 2160 - \b 1: Single precision FPU
saloutos 0:083111ae2a11 2161 - \b 2: Double + Single precision FPU
saloutos 0:083111ae2a11 2162 */
saloutos 0:083111ae2a11 2163 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
saloutos 0:083111ae2a11 2164 {
saloutos 0:083111ae2a11 2165 uint32_t mvfr0;
saloutos 0:083111ae2a11 2166
saloutos 0:083111ae2a11 2167 mvfr0 = SCB->MVFR0;
saloutos 0:083111ae2a11 2168 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
saloutos 0:083111ae2a11 2169 {
saloutos 0:083111ae2a11 2170 return 2U; /* Double + Single precision FPU */
saloutos 0:083111ae2a11 2171 }
saloutos 0:083111ae2a11 2172 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
saloutos 0:083111ae2a11 2173 {
saloutos 0:083111ae2a11 2174 return 1U; /* Single precision FPU */
saloutos 0:083111ae2a11 2175 }
saloutos 0:083111ae2a11 2176 else
saloutos 0:083111ae2a11 2177 {
saloutos 0:083111ae2a11 2178 return 0U; /* No FPU */
saloutos 0:083111ae2a11 2179 }
saloutos 0:083111ae2a11 2180 }
saloutos 0:083111ae2a11 2181
saloutos 0:083111ae2a11 2182
saloutos 0:083111ae2a11 2183 /*@} end of CMSIS_Core_FpuFunctions */
saloutos 0:083111ae2a11 2184
saloutos 0:083111ae2a11 2185
saloutos 0:083111ae2a11 2186
saloutos 0:083111ae2a11 2187 /* ########################## Cache functions #################################### */
saloutos 0:083111ae2a11 2188 /**
saloutos 0:083111ae2a11 2189 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 2190 \defgroup CMSIS_Core_CacheFunctions Cache Functions
saloutos 0:083111ae2a11 2191 \brief Functions that configure Instruction and Data cache.
saloutos 0:083111ae2a11 2192 @{
saloutos 0:083111ae2a11 2193 */
saloutos 0:083111ae2a11 2194
saloutos 0:083111ae2a11 2195 /* Cache Size ID Register Macros */
saloutos 0:083111ae2a11 2196 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
saloutos 0:083111ae2a11 2197 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
saloutos 0:083111ae2a11 2198
saloutos 0:083111ae2a11 2199
saloutos 0:083111ae2a11 2200 /**
saloutos 0:083111ae2a11 2201 \brief Enable I-Cache
saloutos 0:083111ae2a11 2202 \details Turns on I-Cache
saloutos 0:083111ae2a11 2203 */
saloutos 0:083111ae2a11 2204 __STATIC_INLINE void SCB_EnableICache (void)
saloutos 0:083111ae2a11 2205 {
saloutos 0:083111ae2a11 2206 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2207 __DSB();
saloutos 0:083111ae2a11 2208 __ISB();
saloutos 0:083111ae2a11 2209 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
saloutos 0:083111ae2a11 2210 __DSB();
saloutos 0:083111ae2a11 2211 __ISB();
saloutos 0:083111ae2a11 2212 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
saloutos 0:083111ae2a11 2213 __DSB();
saloutos 0:083111ae2a11 2214 __ISB();
saloutos 0:083111ae2a11 2215 #endif
saloutos 0:083111ae2a11 2216 }
saloutos 0:083111ae2a11 2217
saloutos 0:083111ae2a11 2218
saloutos 0:083111ae2a11 2219 /**
saloutos 0:083111ae2a11 2220 \brief Disable I-Cache
saloutos 0:083111ae2a11 2221 \details Turns off I-Cache
saloutos 0:083111ae2a11 2222 */
saloutos 0:083111ae2a11 2223 __STATIC_INLINE void SCB_DisableICache (void)
saloutos 0:083111ae2a11 2224 {
saloutos 0:083111ae2a11 2225 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2226 __DSB();
saloutos 0:083111ae2a11 2227 __ISB();
saloutos 0:083111ae2a11 2228 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
saloutos 0:083111ae2a11 2229 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
saloutos 0:083111ae2a11 2230 __DSB();
saloutos 0:083111ae2a11 2231 __ISB();
saloutos 0:083111ae2a11 2232 #endif
saloutos 0:083111ae2a11 2233 }
saloutos 0:083111ae2a11 2234
saloutos 0:083111ae2a11 2235
saloutos 0:083111ae2a11 2236 /**
saloutos 0:083111ae2a11 2237 \brief Invalidate I-Cache
saloutos 0:083111ae2a11 2238 \details Invalidates I-Cache
saloutos 0:083111ae2a11 2239 */
saloutos 0:083111ae2a11 2240 __STATIC_INLINE void SCB_InvalidateICache (void)
saloutos 0:083111ae2a11 2241 {
saloutos 0:083111ae2a11 2242 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2243 __DSB();
saloutos 0:083111ae2a11 2244 __ISB();
saloutos 0:083111ae2a11 2245 SCB->ICIALLU = 0UL;
saloutos 0:083111ae2a11 2246 __DSB();
saloutos 0:083111ae2a11 2247 __ISB();
saloutos 0:083111ae2a11 2248 #endif
saloutos 0:083111ae2a11 2249 }
saloutos 0:083111ae2a11 2250
saloutos 0:083111ae2a11 2251
saloutos 0:083111ae2a11 2252 /**
saloutos 0:083111ae2a11 2253 \brief Enable D-Cache
saloutos 0:083111ae2a11 2254 \details Turns on D-Cache
saloutos 0:083111ae2a11 2255 */
saloutos 0:083111ae2a11 2256 __STATIC_INLINE void SCB_EnableDCache (void)
saloutos 0:083111ae2a11 2257 {
saloutos 0:083111ae2a11 2258 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2259 uint32_t ccsidr;
saloutos 0:083111ae2a11 2260 uint32_t sets;
saloutos 0:083111ae2a11 2261 uint32_t ways;
saloutos 0:083111ae2a11 2262
saloutos 0:083111ae2a11 2263 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
saloutos 0:083111ae2a11 2264 __DSB();
saloutos 0:083111ae2a11 2265
saloutos 0:083111ae2a11 2266 ccsidr = SCB->CCSIDR;
saloutos 0:083111ae2a11 2267
saloutos 0:083111ae2a11 2268 /* invalidate D-Cache */
saloutos 0:083111ae2a11 2269 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
saloutos 0:083111ae2a11 2270 do {
saloutos 0:083111ae2a11 2271 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
saloutos 0:083111ae2a11 2272 do {
saloutos 0:083111ae2a11 2273 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
saloutos 0:083111ae2a11 2274 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
saloutos 0:083111ae2a11 2275 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 2276 __schedule_barrier();
saloutos 0:083111ae2a11 2277 #endif
saloutos 0:083111ae2a11 2278 } while (ways-- != 0U);
saloutos 0:083111ae2a11 2279 } while(sets-- != 0U);
saloutos 0:083111ae2a11 2280 __DSB();
saloutos 0:083111ae2a11 2281
saloutos 0:083111ae2a11 2282 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
saloutos 0:083111ae2a11 2283
saloutos 0:083111ae2a11 2284 __DSB();
saloutos 0:083111ae2a11 2285 __ISB();
saloutos 0:083111ae2a11 2286 #endif
saloutos 0:083111ae2a11 2287 }
saloutos 0:083111ae2a11 2288
saloutos 0:083111ae2a11 2289
saloutos 0:083111ae2a11 2290 /**
saloutos 0:083111ae2a11 2291 \brief Disable D-Cache
saloutos 0:083111ae2a11 2292 \details Turns off D-Cache
saloutos 0:083111ae2a11 2293 */
saloutos 0:083111ae2a11 2294 __STATIC_INLINE void SCB_DisableDCache (void)
saloutos 0:083111ae2a11 2295 {
saloutos 0:083111ae2a11 2296 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2297 register uint32_t ccsidr;
saloutos 0:083111ae2a11 2298 register uint32_t sets;
saloutos 0:083111ae2a11 2299 register uint32_t ways;
saloutos 0:083111ae2a11 2300
saloutos 0:083111ae2a11 2301 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
saloutos 0:083111ae2a11 2302 __DSB();
saloutos 0:083111ae2a11 2303
saloutos 0:083111ae2a11 2304 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
saloutos 0:083111ae2a11 2305 __DSB();
saloutos 0:083111ae2a11 2306
saloutos 0:083111ae2a11 2307 ccsidr = SCB->CCSIDR;
saloutos 0:083111ae2a11 2308
saloutos 0:083111ae2a11 2309 /* clean & invalidate D-Cache */
saloutos 0:083111ae2a11 2310 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
saloutos 0:083111ae2a11 2311 do {
saloutos 0:083111ae2a11 2312 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
saloutos 0:083111ae2a11 2313 do {
saloutos 0:083111ae2a11 2314 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
saloutos 0:083111ae2a11 2315 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
saloutos 0:083111ae2a11 2316 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 2317 __schedule_barrier();
saloutos 0:083111ae2a11 2318 #endif
saloutos 0:083111ae2a11 2319 } while (ways-- != 0U);
saloutos 0:083111ae2a11 2320 } while(sets-- != 0U);
saloutos 0:083111ae2a11 2321
saloutos 0:083111ae2a11 2322 __DSB();
saloutos 0:083111ae2a11 2323 __ISB();
saloutos 0:083111ae2a11 2324 #endif
saloutos 0:083111ae2a11 2325 }
saloutos 0:083111ae2a11 2326
saloutos 0:083111ae2a11 2327
saloutos 0:083111ae2a11 2328 /**
saloutos 0:083111ae2a11 2329 \brief Invalidate D-Cache
saloutos 0:083111ae2a11 2330 \details Invalidates D-Cache
saloutos 0:083111ae2a11 2331 */
saloutos 0:083111ae2a11 2332 __STATIC_INLINE void SCB_InvalidateDCache (void)
saloutos 0:083111ae2a11 2333 {
saloutos 0:083111ae2a11 2334 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2335 uint32_t ccsidr;
saloutos 0:083111ae2a11 2336 uint32_t sets;
saloutos 0:083111ae2a11 2337 uint32_t ways;
saloutos 0:083111ae2a11 2338
saloutos 0:083111ae2a11 2339 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
saloutos 0:083111ae2a11 2340 __DSB();
saloutos 0:083111ae2a11 2341
saloutos 0:083111ae2a11 2342 ccsidr = SCB->CCSIDR;
saloutos 0:083111ae2a11 2343
saloutos 0:083111ae2a11 2344 /* invalidate D-Cache */
saloutos 0:083111ae2a11 2345 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
saloutos 0:083111ae2a11 2346 do {
saloutos 0:083111ae2a11 2347 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
saloutos 0:083111ae2a11 2348 do {
saloutos 0:083111ae2a11 2349 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
saloutos 0:083111ae2a11 2350 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
saloutos 0:083111ae2a11 2351 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 2352 __schedule_barrier();
saloutos 0:083111ae2a11 2353 #endif
saloutos 0:083111ae2a11 2354 } while (ways-- != 0U);
saloutos 0:083111ae2a11 2355 } while(sets-- != 0U);
saloutos 0:083111ae2a11 2356
saloutos 0:083111ae2a11 2357 __DSB();
saloutos 0:083111ae2a11 2358 __ISB();
saloutos 0:083111ae2a11 2359 #endif
saloutos 0:083111ae2a11 2360 }
saloutos 0:083111ae2a11 2361
saloutos 0:083111ae2a11 2362
saloutos 0:083111ae2a11 2363 /**
saloutos 0:083111ae2a11 2364 \brief Clean D-Cache
saloutos 0:083111ae2a11 2365 \details Cleans D-Cache
saloutos 0:083111ae2a11 2366 */
saloutos 0:083111ae2a11 2367 __STATIC_INLINE void SCB_CleanDCache (void)
saloutos 0:083111ae2a11 2368 {
saloutos 0:083111ae2a11 2369 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2370 uint32_t ccsidr;
saloutos 0:083111ae2a11 2371 uint32_t sets;
saloutos 0:083111ae2a11 2372 uint32_t ways;
saloutos 0:083111ae2a11 2373
saloutos 0:083111ae2a11 2374 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
saloutos 0:083111ae2a11 2375 __DSB();
saloutos 0:083111ae2a11 2376
saloutos 0:083111ae2a11 2377 ccsidr = SCB->CCSIDR;
saloutos 0:083111ae2a11 2378
saloutos 0:083111ae2a11 2379 /* clean D-Cache */
saloutos 0:083111ae2a11 2380 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
saloutos 0:083111ae2a11 2381 do {
saloutos 0:083111ae2a11 2382 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
saloutos 0:083111ae2a11 2383 do {
saloutos 0:083111ae2a11 2384 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
saloutos 0:083111ae2a11 2385 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
saloutos 0:083111ae2a11 2386 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 2387 __schedule_barrier();
saloutos 0:083111ae2a11 2388 #endif
saloutos 0:083111ae2a11 2389 } while (ways-- != 0U);
saloutos 0:083111ae2a11 2390 } while(sets-- != 0U);
saloutos 0:083111ae2a11 2391
saloutos 0:083111ae2a11 2392 __DSB();
saloutos 0:083111ae2a11 2393 __ISB();
saloutos 0:083111ae2a11 2394 #endif
saloutos 0:083111ae2a11 2395 }
saloutos 0:083111ae2a11 2396
saloutos 0:083111ae2a11 2397
saloutos 0:083111ae2a11 2398 /**
saloutos 0:083111ae2a11 2399 \brief Clean & Invalidate D-Cache
saloutos 0:083111ae2a11 2400 \details Cleans and Invalidates D-Cache
saloutos 0:083111ae2a11 2401 */
saloutos 0:083111ae2a11 2402 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
saloutos 0:083111ae2a11 2403 {
saloutos 0:083111ae2a11 2404 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2405 uint32_t ccsidr;
saloutos 0:083111ae2a11 2406 uint32_t sets;
saloutos 0:083111ae2a11 2407 uint32_t ways;
saloutos 0:083111ae2a11 2408
saloutos 0:083111ae2a11 2409 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
saloutos 0:083111ae2a11 2410 __DSB();
saloutos 0:083111ae2a11 2411
saloutos 0:083111ae2a11 2412 ccsidr = SCB->CCSIDR;
saloutos 0:083111ae2a11 2413
saloutos 0:083111ae2a11 2414 /* clean & invalidate D-Cache */
saloutos 0:083111ae2a11 2415 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
saloutos 0:083111ae2a11 2416 do {
saloutos 0:083111ae2a11 2417 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
saloutos 0:083111ae2a11 2418 do {
saloutos 0:083111ae2a11 2419 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
saloutos 0:083111ae2a11 2420 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
saloutos 0:083111ae2a11 2421 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 2422 __schedule_barrier();
saloutos 0:083111ae2a11 2423 #endif
saloutos 0:083111ae2a11 2424 } while (ways-- != 0U);
saloutos 0:083111ae2a11 2425 } while(sets-- != 0U);
saloutos 0:083111ae2a11 2426
saloutos 0:083111ae2a11 2427 __DSB();
saloutos 0:083111ae2a11 2428 __ISB();
saloutos 0:083111ae2a11 2429 #endif
saloutos 0:083111ae2a11 2430 }
saloutos 0:083111ae2a11 2431
saloutos 0:083111ae2a11 2432
saloutos 0:083111ae2a11 2433 /**
saloutos 0:083111ae2a11 2434 \brief D-Cache Invalidate by address
saloutos 0:083111ae2a11 2435 \details Invalidates D-Cache for the given address
saloutos 0:083111ae2a11 2436 \param[in] addr address (aligned to 32-byte boundary)
saloutos 0:083111ae2a11 2437 \param[in] dsize size of memory block (in number of bytes)
saloutos 0:083111ae2a11 2438 */
saloutos 0:083111ae2a11 2439 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
saloutos 0:083111ae2a11 2440 {
saloutos 0:083111ae2a11 2441 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2442 int32_t op_size = dsize;
saloutos 0:083111ae2a11 2443 uint32_t op_addr = (uint32_t)addr;
saloutos 0:083111ae2a11 2444 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
saloutos 0:083111ae2a11 2445
saloutos 0:083111ae2a11 2446 __DSB();
saloutos 0:083111ae2a11 2447
saloutos 0:083111ae2a11 2448 while (op_size > 0) {
saloutos 0:083111ae2a11 2449 SCB->DCIMVAC = op_addr;
saloutos 0:083111ae2a11 2450 op_addr += (uint32_t)linesize;
saloutos 0:083111ae2a11 2451 op_size -= linesize;
saloutos 0:083111ae2a11 2452 }
saloutos 0:083111ae2a11 2453
saloutos 0:083111ae2a11 2454 __DSB();
saloutos 0:083111ae2a11 2455 __ISB();
saloutos 0:083111ae2a11 2456 #endif
saloutos 0:083111ae2a11 2457 }
saloutos 0:083111ae2a11 2458
saloutos 0:083111ae2a11 2459
saloutos 0:083111ae2a11 2460 /**
saloutos 0:083111ae2a11 2461 \brief D-Cache Clean by address
saloutos 0:083111ae2a11 2462 \details Cleans D-Cache for the given address
saloutos 0:083111ae2a11 2463 \param[in] addr address (aligned to 32-byte boundary)
saloutos 0:083111ae2a11 2464 \param[in] dsize size of memory block (in number of bytes)
saloutos 0:083111ae2a11 2465 */
saloutos 0:083111ae2a11 2466 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
saloutos 0:083111ae2a11 2467 {
saloutos 0:083111ae2a11 2468 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2469 int32_t op_size = dsize;
saloutos 0:083111ae2a11 2470 uint32_t op_addr = (uint32_t) addr;
saloutos 0:083111ae2a11 2471 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
saloutos 0:083111ae2a11 2472
saloutos 0:083111ae2a11 2473 __DSB();
saloutos 0:083111ae2a11 2474
saloutos 0:083111ae2a11 2475 while (op_size > 0) {
saloutos 0:083111ae2a11 2476 SCB->DCCMVAC = op_addr;
saloutos 0:083111ae2a11 2477 op_addr += (uint32_t)linesize;
saloutos 0:083111ae2a11 2478 op_size -= linesize;
saloutos 0:083111ae2a11 2479 }
saloutos 0:083111ae2a11 2480
saloutos 0:083111ae2a11 2481 __DSB();
saloutos 0:083111ae2a11 2482 __ISB();
saloutos 0:083111ae2a11 2483 #endif
saloutos 0:083111ae2a11 2484 }
saloutos 0:083111ae2a11 2485
saloutos 0:083111ae2a11 2486
saloutos 0:083111ae2a11 2487 /**
saloutos 0:083111ae2a11 2488 \brief D-Cache Clean and Invalidate by address
saloutos 0:083111ae2a11 2489 \details Cleans and invalidates D_Cache for the given address
saloutos 0:083111ae2a11 2490 \param[in] addr address (aligned to 32-byte boundary)
saloutos 0:083111ae2a11 2491 \param[in] dsize size of memory block (in number of bytes)
saloutos 0:083111ae2a11 2492 */
saloutos 0:083111ae2a11 2493 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
saloutos 0:083111ae2a11 2494 {
saloutos 0:083111ae2a11 2495 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
saloutos 0:083111ae2a11 2496 int32_t op_size = dsize;
saloutos 0:083111ae2a11 2497 uint32_t op_addr = (uint32_t) addr;
saloutos 0:083111ae2a11 2498 int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
saloutos 0:083111ae2a11 2499
saloutos 0:083111ae2a11 2500 __DSB();
saloutos 0:083111ae2a11 2501
saloutos 0:083111ae2a11 2502 while (op_size > 0) {
saloutos 0:083111ae2a11 2503 SCB->DCCIMVAC = op_addr;
saloutos 0:083111ae2a11 2504 op_addr += (uint32_t)linesize;
saloutos 0:083111ae2a11 2505 op_size -= linesize;
saloutos 0:083111ae2a11 2506 }
saloutos 0:083111ae2a11 2507
saloutos 0:083111ae2a11 2508 __DSB();
saloutos 0:083111ae2a11 2509 __ISB();
saloutos 0:083111ae2a11 2510 #endif
saloutos 0:083111ae2a11 2511 }
saloutos 0:083111ae2a11 2512
saloutos 0:083111ae2a11 2513
saloutos 0:083111ae2a11 2514 /*@} end of CMSIS_Core_CacheFunctions */
saloutos 0:083111ae2a11 2515
saloutos 0:083111ae2a11 2516
saloutos 0:083111ae2a11 2517
saloutos 0:083111ae2a11 2518 /* ################################## SysTick function ############################################ */
saloutos 0:083111ae2a11 2519 /**
saloutos 0:083111ae2a11 2520 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 2521 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
saloutos 0:083111ae2a11 2522 \brief Functions that configure the System.
saloutos 0:083111ae2a11 2523 @{
saloutos 0:083111ae2a11 2524 */
saloutos 0:083111ae2a11 2525
saloutos 0:083111ae2a11 2526 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
saloutos 0:083111ae2a11 2527
saloutos 0:083111ae2a11 2528 /**
saloutos 0:083111ae2a11 2529 \brief System Tick Configuration
saloutos 0:083111ae2a11 2530 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
saloutos 0:083111ae2a11 2531 Counter is in free running mode to generate periodic interrupts.
saloutos 0:083111ae2a11 2532 \param [in] ticks Number of ticks between two interrupts.
saloutos 0:083111ae2a11 2533 \return 0 Function succeeded.
saloutos 0:083111ae2a11 2534 \return 1 Function failed.
saloutos 0:083111ae2a11 2535 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos 0:083111ae2a11 2536 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos 0:083111ae2a11 2537 must contain a vendor-specific implementation of this function.
saloutos 0:083111ae2a11 2538 */
saloutos 0:083111ae2a11 2539 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
saloutos 0:083111ae2a11 2540 {
saloutos 0:083111ae2a11 2541 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos 0:083111ae2a11 2542 {
saloutos 0:083111ae2a11 2543 return (1UL); /* Reload value impossible */
saloutos 0:083111ae2a11 2544 }
saloutos 0:083111ae2a11 2545
saloutos 0:083111ae2a11 2546 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos 0:083111ae2a11 2547 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos 0:083111ae2a11 2548 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos 0:083111ae2a11 2549 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
saloutos 0:083111ae2a11 2550 SysTick_CTRL_TICKINT_Msk |
saloutos 0:083111ae2a11 2551 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos 0:083111ae2a11 2552 return (0UL); /* Function successful */
saloutos 0:083111ae2a11 2553 }
saloutos 0:083111ae2a11 2554
saloutos 0:083111ae2a11 2555 #endif
saloutos 0:083111ae2a11 2556
saloutos 0:083111ae2a11 2557 /*@} end of CMSIS_Core_SysTickFunctions */
saloutos 0:083111ae2a11 2558
saloutos 0:083111ae2a11 2559
saloutos 0:083111ae2a11 2560
saloutos 0:083111ae2a11 2561 /* ##################################### Debug In/Output function ########################################### */
saloutos 0:083111ae2a11 2562 /**
saloutos 0:083111ae2a11 2563 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 2564 \defgroup CMSIS_core_DebugFunctions ITM Functions
saloutos 0:083111ae2a11 2565 \brief Functions that access the ITM debug interface.
saloutos 0:083111ae2a11 2566 @{
saloutos 0:083111ae2a11 2567 */
saloutos 0:083111ae2a11 2568
saloutos 0:083111ae2a11 2569 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
saloutos 0:083111ae2a11 2570 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
saloutos 0:083111ae2a11 2571
saloutos 0:083111ae2a11 2572
saloutos 0:083111ae2a11 2573 /**
saloutos 0:083111ae2a11 2574 \brief ITM Send Character
saloutos 0:083111ae2a11 2575 \details Transmits a character via the ITM channel 0, and
saloutos 0:083111ae2a11 2576 \li Just returns when no debugger is connected that has booked the output.
saloutos 0:083111ae2a11 2577 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
saloutos 0:083111ae2a11 2578 \param [in] ch Character to transmit.
saloutos 0:083111ae2a11 2579 \returns Character to transmit.
saloutos 0:083111ae2a11 2580 */
saloutos 0:083111ae2a11 2581 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
saloutos 0:083111ae2a11 2582 {
saloutos 0:083111ae2a11 2583 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
saloutos 0:083111ae2a11 2584 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
saloutos 0:083111ae2a11 2585 {
saloutos 0:083111ae2a11 2586 while (ITM->PORT[0U].u32 == 0UL)
saloutos 0:083111ae2a11 2587 {
saloutos 0:083111ae2a11 2588 __NOP();
saloutos 0:083111ae2a11 2589 }
saloutos 0:083111ae2a11 2590 ITM->PORT[0U].u8 = (uint8_t)ch;
saloutos 0:083111ae2a11 2591 }
saloutos 0:083111ae2a11 2592 return (ch);
saloutos 0:083111ae2a11 2593 }
saloutos 0:083111ae2a11 2594
saloutos 0:083111ae2a11 2595
saloutos 0:083111ae2a11 2596 /**
saloutos 0:083111ae2a11 2597 \brief ITM Receive Character
saloutos 0:083111ae2a11 2598 \details Inputs a character via the external variable \ref ITM_RxBuffer.
saloutos 0:083111ae2a11 2599 \return Received character.
saloutos 0:083111ae2a11 2600 \return -1 No character pending.
saloutos 0:083111ae2a11 2601 */
saloutos 0:083111ae2a11 2602 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
saloutos 0:083111ae2a11 2603 {
saloutos 0:083111ae2a11 2604 int32_t ch = -1; /* no character available */
saloutos 0:083111ae2a11 2605
saloutos 0:083111ae2a11 2606 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
saloutos 0:083111ae2a11 2607 {
saloutos 0:083111ae2a11 2608 ch = ITM_RxBuffer;
saloutos 0:083111ae2a11 2609 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
saloutos 0:083111ae2a11 2610 }
saloutos 0:083111ae2a11 2611
saloutos 0:083111ae2a11 2612 return (ch);
saloutos 0:083111ae2a11 2613 }
saloutos 0:083111ae2a11 2614
saloutos 0:083111ae2a11 2615
saloutos 0:083111ae2a11 2616 /**
saloutos 0:083111ae2a11 2617 \brief ITM Check Character
saloutos 0:083111ae2a11 2618 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
saloutos 0:083111ae2a11 2619 \return 0 No character available.
saloutos 0:083111ae2a11 2620 \return 1 Character available.
saloutos 0:083111ae2a11 2621 */
saloutos 0:083111ae2a11 2622 __STATIC_INLINE int32_t ITM_CheckChar (void)
saloutos 0:083111ae2a11 2623 {
saloutos 0:083111ae2a11 2624
saloutos 0:083111ae2a11 2625 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
saloutos 0:083111ae2a11 2626 {
saloutos 0:083111ae2a11 2627 return (0); /* no character available */
saloutos 0:083111ae2a11 2628 }
saloutos 0:083111ae2a11 2629 else
saloutos 0:083111ae2a11 2630 {
saloutos 0:083111ae2a11 2631 return (1); /* character available */
saloutos 0:083111ae2a11 2632 }
saloutos 0:083111ae2a11 2633 }
saloutos 0:083111ae2a11 2634
saloutos 0:083111ae2a11 2635 /*@} end of CMSIS_core_DebugFunctions */
saloutos 0:083111ae2a11 2636
saloutos 0:083111ae2a11 2637
saloutos 0:083111ae2a11 2638
saloutos 0:083111ae2a11 2639
saloutos 0:083111ae2a11 2640 #ifdef __cplusplus
saloutos 0:083111ae2a11 2641 }
saloutos 0:083111ae2a11 2642 #endif
saloutos 0:083111ae2a11 2643
saloutos 0:083111ae2a11 2644 #endif /* __CORE_CM7_H_DEPENDANT */
saloutos 0:083111ae2a11 2645
saloutos 0:083111ae2a11 2646 #endif /* __CMSIS_GENERIC */