Aditya Mehrotra / mbed-dev

Biomimetics MBED Library w/ Added Support for CAN3

Dependents:   CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/core_cm0plus.h@3:993b4d6ff61e, 2021-03-09 (annotated)

Committer:
adimmit
Date:
Tue Mar 09 20:33:24 2021 +0000
Revision:
3:993b4d6ff61e
Parent:
0:083111ae2a11 
added CAN3

Who changed what in which revision?

UserRevisionLine numberNew contents of line
saloutos 0:083111ae2a11 1 /**************************************************************************//**
saloutos 0:083111ae2a11 2 * @file core_cm0plus.h
saloutos 0:083111ae2a11 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
saloutos 0:083111ae2a11 4 * @version V5.0.2
saloutos 0:083111ae2a11 5 * @date 13. February 2017
saloutos 0:083111ae2a11 6 ******************************************************************************/
saloutos 0:083111ae2a11 7 /*
saloutos 0:083111ae2a11 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos 0:083111ae2a11 9 *
saloutos 0:083111ae2a11 10 * SPDX-License-Identifier: Apache-2.0
saloutos 0:083111ae2a11 11 *
saloutos 0:083111ae2a11 12 * Licensed under the Apache License, Version 2.0 (the License); you may
saloutos 0:083111ae2a11 13 * not use this file except in compliance with the License.
saloutos 0:083111ae2a11 14 * You may obtain a copy of the License at
saloutos 0:083111ae2a11 15 *
saloutos 0:083111ae2a11 16 * www.apache.org/licenses/LICENSE-2.0
saloutos 0:083111ae2a11 17 *
saloutos 0:083111ae2a11 18 * Unless required by applicable law or agreed to in writing, software
saloutos 0:083111ae2a11 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos 0:083111ae2a11 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos 0:083111ae2a11 21 * See the License for the specific language governing permissions and
saloutos 0:083111ae2a11 22 * limitations under the License.
saloutos 0:083111ae2a11 23 */
saloutos 0:083111ae2a11 24
saloutos 0:083111ae2a11 25 #if defined ( __ICCARM__ )
saloutos 0:083111ae2a11 26 #pragma system_include /* treat file as system include file for MISRA check */
saloutos 0:083111ae2a11 27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 28 #pragma clang system_header /* treat file as system include file */
saloutos 0:083111ae2a11 29 #endif
saloutos 0:083111ae2a11 30
saloutos 0:083111ae2a11 31 #ifndef __CORE_CM0PLUS_H_GENERIC
saloutos 0:083111ae2a11 32 #define __CORE_CM0PLUS_H_GENERIC
saloutos 0:083111ae2a11 33
saloutos 0:083111ae2a11 34 #include <stdint.h>
saloutos 0:083111ae2a11 35
saloutos 0:083111ae2a11 36 #ifdef __cplusplus
saloutos 0:083111ae2a11 37 extern "C" {
saloutos 0:083111ae2a11 38 #endif
saloutos 0:083111ae2a11 39
saloutos 0:083111ae2a11 40 /**
saloutos 0:083111ae2a11 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
saloutos 0:083111ae2a11 42 CMSIS violates the following MISRA-C:2004 rules:
saloutos 0:083111ae2a11 43
saloutos 0:083111ae2a11 44 \li Required Rule 8.5, object/function definition in header file.<br>
saloutos 0:083111ae2a11 45 Function definitions in header files are used to allow 'inlining'.
saloutos 0:083111ae2a11 46
saloutos 0:083111ae2a11 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
saloutos 0:083111ae2a11 48 Unions are used for effective representation of core registers.
saloutos 0:083111ae2a11 49
saloutos 0:083111ae2a11 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
saloutos 0:083111ae2a11 51 Function-like macros are used to allow more efficient code.
saloutos 0:083111ae2a11 52 */
saloutos 0:083111ae2a11 53
saloutos 0:083111ae2a11 54
saloutos 0:083111ae2a11 55 /*******************************************************************************
saloutos 0:083111ae2a11 56 * CMSIS definitions
saloutos 0:083111ae2a11 57 ******************************************************************************/
saloutos 0:083111ae2a11 58 /**
saloutos 0:083111ae2a11 59 \ingroup Cortex-M0+
saloutos 0:083111ae2a11 60 @{
saloutos 0:083111ae2a11 61 */
saloutos 0:083111ae2a11 62
saloutos 0:083111ae2a11 63 /* CMSIS CM0+ definitions */
saloutos 0:083111ae2a11 64 #define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
saloutos 0:083111ae2a11 65 #define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
saloutos 0:083111ae2a11 66 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
saloutos 0:083111ae2a11 67 __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
saloutos 0:083111ae2a11 68
saloutos 0:083111ae2a11 69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
saloutos 0:083111ae2a11 70
saloutos 0:083111ae2a11 71 /** __FPU_USED indicates whether an FPU is used or not.
saloutos 0:083111ae2a11 72 This core does not support an FPU at all
saloutos 0:083111ae2a11 73 */
saloutos 0:083111ae2a11 74 #define __FPU_USED 0U
saloutos 0:083111ae2a11 75
saloutos 0:083111ae2a11 76 #if defined ( __CC_ARM )
saloutos 0:083111ae2a11 77 #if defined __TARGET_FPU_VFP
saloutos 0:083111ae2a11 78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 79 #endif
saloutos 0:083111ae2a11 80
saloutos 0:083111ae2a11 81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos 0:083111ae2a11 82 #if defined __ARM_PCS_VFP
saloutos 0:083111ae2a11 83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 84 #endif
saloutos 0:083111ae2a11 85
saloutos 0:083111ae2a11 86 #elif defined ( __GNUC__ )
saloutos 0:083111ae2a11 87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
saloutos 0:083111ae2a11 88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 89 #endif
saloutos 0:083111ae2a11 90
saloutos 0:083111ae2a11 91 #elif defined ( __ICCARM__ )
saloutos 0:083111ae2a11 92 #if defined __ARMVFP__
saloutos 0:083111ae2a11 93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 94 #endif
saloutos 0:083111ae2a11 95
saloutos 0:083111ae2a11 96 #elif defined ( __TI_ARM__ )
saloutos 0:083111ae2a11 97 #if defined __TI_VFP_SUPPORT__
saloutos 0:083111ae2a11 98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 99 #endif
saloutos 0:083111ae2a11 100
saloutos 0:083111ae2a11 101 #elif defined ( __TASKING__ )
saloutos 0:083111ae2a11 102 #if defined __FPU_VFP__
saloutos 0:083111ae2a11 103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 104 #endif
saloutos 0:083111ae2a11 105
saloutos 0:083111ae2a11 106 #elif defined ( __CSMC__ )
saloutos 0:083111ae2a11 107 #if ( __CSMC__ & 0x400U)
saloutos 0:083111ae2a11 108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos 0:083111ae2a11 109 #endif
saloutos 0:083111ae2a11 110
saloutos 0:083111ae2a11 111 #endif
saloutos 0:083111ae2a11 112
saloutos 0:083111ae2a11 113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
saloutos 0:083111ae2a11 114
saloutos 0:083111ae2a11 115
saloutos 0:083111ae2a11 116 #ifdef __cplusplus
saloutos 0:083111ae2a11 117 }
saloutos 0:083111ae2a11 118 #endif
saloutos 0:083111ae2a11 119
saloutos 0:083111ae2a11 120 #endif /* __CORE_CM0PLUS_H_GENERIC */
saloutos 0:083111ae2a11 121
saloutos 0:083111ae2a11 122 #ifndef __CMSIS_GENERIC
saloutos 0:083111ae2a11 123
saloutos 0:083111ae2a11 124 #ifndef __CORE_CM0PLUS_H_DEPENDANT
saloutos 0:083111ae2a11 125 #define __CORE_CM0PLUS_H_DEPENDANT
saloutos 0:083111ae2a11 126
saloutos 0:083111ae2a11 127 #ifdef __cplusplus
saloutos 0:083111ae2a11 128 extern "C" {
saloutos 0:083111ae2a11 129 #endif
saloutos 0:083111ae2a11 130
saloutos 0:083111ae2a11 131 /* check device defines and use defaults */
saloutos 0:083111ae2a11 132 #if defined __CHECK_DEVICE_DEFINES
saloutos 0:083111ae2a11 133 #ifndef __CM0PLUS_REV
saloutos 0:083111ae2a11 134 #define __CM0PLUS_REV 0x0000U
saloutos 0:083111ae2a11 135 #warning "__CM0PLUS_REV not defined in device header file; using default!"
saloutos 0:083111ae2a11 136 #endif
saloutos 0:083111ae2a11 137
saloutos 0:083111ae2a11 138 #ifndef __MPU_PRESENT
saloutos 0:083111ae2a11 139 #define __MPU_PRESENT 0U
saloutos 0:083111ae2a11 140 #warning "__MPU_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 141 #endif
saloutos 0:083111ae2a11 142
saloutos 0:083111ae2a11 143 #ifndef __VTOR_PRESENT
saloutos 0:083111ae2a11 144 #define __VTOR_PRESENT 0U
saloutos 0:083111ae2a11 145 #warning "__VTOR_PRESENT not defined in device header file; using default!"
saloutos 0:083111ae2a11 146 #endif
saloutos 0:083111ae2a11 147
saloutos 0:083111ae2a11 148 #ifndef __NVIC_PRIO_BITS
saloutos 0:083111ae2a11 149 #define __NVIC_PRIO_BITS 2U
saloutos 0:083111ae2a11 150 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
saloutos 0:083111ae2a11 151 #endif
saloutos 0:083111ae2a11 152
saloutos 0:083111ae2a11 153 #ifndef __Vendor_SysTickConfig
saloutos 0:083111ae2a11 154 #define __Vendor_SysTickConfig 0U
saloutos 0:083111ae2a11 155 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
saloutos 0:083111ae2a11 156 #endif
saloutos 0:083111ae2a11 157 #endif
saloutos 0:083111ae2a11 158
saloutos 0:083111ae2a11 159 /* IO definitions (access restrictions to peripheral registers) */
saloutos 0:083111ae2a11 160 /**
saloutos 0:083111ae2a11 161 \defgroup CMSIS_glob_defs CMSIS Global Defines
saloutos 0:083111ae2a11 162
saloutos 0:083111ae2a11 163 <strong>IO Type Qualifiers</strong> are used
saloutos 0:083111ae2a11 164 \li to specify the access to peripheral variables.
saloutos 0:083111ae2a11 165 \li for automatic generation of peripheral register debug information.
saloutos 0:083111ae2a11 166 */
saloutos 0:083111ae2a11 167 #ifdef __cplusplus
saloutos 0:083111ae2a11 168 #define __I volatile /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 169 #else
saloutos 0:083111ae2a11 170 #define __I volatile const /*!< Defines 'read only' permissions */
saloutos 0:083111ae2a11 171 #endif
saloutos 0:083111ae2a11 172 #define __O volatile /*!< Defines 'write only' permissions */
saloutos 0:083111ae2a11 173 #define __IO volatile /*!< Defines 'read / write' permissions */
saloutos 0:083111ae2a11 174
saloutos 0:083111ae2a11 175 /* following defines should be used for structure members */
saloutos 0:083111ae2a11 176 #define __IM volatile const /*! Defines 'read only' structure member permissions */
saloutos 0:083111ae2a11 177 #define __OM volatile /*! Defines 'write only' structure member permissions */
saloutos 0:083111ae2a11 178 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
saloutos 0:083111ae2a11 179
saloutos 0:083111ae2a11 180 /*@} end of group Cortex-M0+ */
saloutos 0:083111ae2a11 181
saloutos 0:083111ae2a11 182
saloutos 0:083111ae2a11 183
saloutos 0:083111ae2a11 184 /*******************************************************************************
saloutos 0:083111ae2a11 185 * Register Abstraction
saloutos 0:083111ae2a11 186 Core Register contain:
saloutos 0:083111ae2a11 187 - Core Register
saloutos 0:083111ae2a11 188 - Core NVIC Register
saloutos 0:083111ae2a11 189 - Core SCB Register
saloutos 0:083111ae2a11 190 - Core SysTick Register
saloutos 0:083111ae2a11 191 - Core MPU Register
saloutos 0:083111ae2a11 192 ******************************************************************************/
saloutos 0:083111ae2a11 193 /**
saloutos 0:083111ae2a11 194 \defgroup CMSIS_core_register Defines and Type Definitions
saloutos 0:083111ae2a11 195 \brief Type definitions and defines for Cortex-M processor based devices.
saloutos 0:083111ae2a11 196 */
saloutos 0:083111ae2a11 197
saloutos 0:083111ae2a11 198 /**
saloutos 0:083111ae2a11 199 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 200 \defgroup CMSIS_CORE Status and Control Registers
saloutos 0:083111ae2a11 201 \brief Core Register type definitions.
saloutos 0:083111ae2a11 202 @{
saloutos 0:083111ae2a11 203 */
saloutos 0:083111ae2a11 204
saloutos 0:083111ae2a11 205 /**
saloutos 0:083111ae2a11 206 \brief Union type to access the Application Program Status Register (APSR).
saloutos 0:083111ae2a11 207 */
saloutos 0:083111ae2a11 208 typedef union
saloutos 0:083111ae2a11 209 {
saloutos 0:083111ae2a11 210 struct
saloutos 0:083111ae2a11 211 {
saloutos 0:083111ae2a11 212 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
saloutos 0:083111ae2a11 213 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 214 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 215 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 216 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 217 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 218 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 219 } APSR_Type;
saloutos 0:083111ae2a11 220
saloutos 0:083111ae2a11 221 /* APSR Register Definitions */
saloutos 0:083111ae2a11 222 #define APSR_N_Pos 31U /*!< APSR: N Position */
saloutos 0:083111ae2a11 223 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
saloutos 0:083111ae2a11 224
saloutos 0:083111ae2a11 225 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
saloutos 0:083111ae2a11 226 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
saloutos 0:083111ae2a11 227
saloutos 0:083111ae2a11 228 #define APSR_C_Pos 29U /*!< APSR: C Position */
saloutos 0:083111ae2a11 229 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
saloutos 0:083111ae2a11 230
saloutos 0:083111ae2a11 231 #define APSR_V_Pos 28U /*!< APSR: V Position */
saloutos 0:083111ae2a11 232 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
saloutos 0:083111ae2a11 233
saloutos 0:083111ae2a11 234
saloutos 0:083111ae2a11 235 /**
saloutos 0:083111ae2a11 236 \brief Union type to access the Interrupt Program Status Register (IPSR).
saloutos 0:083111ae2a11 237 */
saloutos 0:083111ae2a11 238 typedef union
saloutos 0:083111ae2a11 239 {
saloutos 0:083111ae2a11 240 struct
saloutos 0:083111ae2a11 241 {
saloutos 0:083111ae2a11 242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 243 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
saloutos 0:083111ae2a11 244 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 245 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 246 } IPSR_Type;
saloutos 0:083111ae2a11 247
saloutos 0:083111ae2a11 248 /* IPSR Register Definitions */
saloutos 0:083111ae2a11 249 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
saloutos 0:083111ae2a11 250 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
saloutos 0:083111ae2a11 251
saloutos 0:083111ae2a11 252
saloutos 0:083111ae2a11 253 /**
saloutos 0:083111ae2a11 254 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
saloutos 0:083111ae2a11 255 */
saloutos 0:083111ae2a11 256 typedef union
saloutos 0:083111ae2a11 257 {
saloutos 0:083111ae2a11 258 struct
saloutos 0:083111ae2a11 259 {
saloutos 0:083111ae2a11 260 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
saloutos 0:083111ae2a11 261 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
saloutos 0:083111ae2a11 262 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
saloutos 0:083111ae2a11 263 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
saloutos 0:083111ae2a11 264 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
saloutos 0:083111ae2a11 265 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
saloutos 0:083111ae2a11 266 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
saloutos 0:083111ae2a11 267 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
saloutos 0:083111ae2a11 268 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 269 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 270 } xPSR_Type;
saloutos 0:083111ae2a11 271
saloutos 0:083111ae2a11 272 /* xPSR Register Definitions */
saloutos 0:083111ae2a11 273 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
saloutos 0:083111ae2a11 274 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
saloutos 0:083111ae2a11 275
saloutos 0:083111ae2a11 276 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
saloutos 0:083111ae2a11 277 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
saloutos 0:083111ae2a11 278
saloutos 0:083111ae2a11 279 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
saloutos 0:083111ae2a11 280 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
saloutos 0:083111ae2a11 281
saloutos 0:083111ae2a11 282 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
saloutos 0:083111ae2a11 283 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
saloutos 0:083111ae2a11 284
saloutos 0:083111ae2a11 285 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
saloutos 0:083111ae2a11 286 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
saloutos 0:083111ae2a11 287
saloutos 0:083111ae2a11 288 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
saloutos 0:083111ae2a11 289 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
saloutos 0:083111ae2a11 290
saloutos 0:083111ae2a11 291
saloutos 0:083111ae2a11 292 /**
saloutos 0:083111ae2a11 293 \brief Union type to access the Control Registers (CONTROL).
saloutos 0:083111ae2a11 294 */
saloutos 0:083111ae2a11 295 typedef union
saloutos 0:083111ae2a11 296 {
saloutos 0:083111ae2a11 297 struct
saloutos 0:083111ae2a11 298 {
saloutos 0:083111ae2a11 299 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
saloutos 0:083111ae2a11 300 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
saloutos 0:083111ae2a11 301 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
saloutos 0:083111ae2a11 302 } b; /*!< Structure used for bit access */
saloutos 0:083111ae2a11 303 uint32_t w; /*!< Type used for word access */
saloutos 0:083111ae2a11 304 } CONTROL_Type;
saloutos 0:083111ae2a11 305
saloutos 0:083111ae2a11 306 /* CONTROL Register Definitions */
saloutos 0:083111ae2a11 307 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
saloutos 0:083111ae2a11 308 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
saloutos 0:083111ae2a11 309
saloutos 0:083111ae2a11 310 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
saloutos 0:083111ae2a11 311 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
saloutos 0:083111ae2a11 312
saloutos 0:083111ae2a11 313 /*@} end of group CMSIS_CORE */
saloutos 0:083111ae2a11 314
saloutos 0:083111ae2a11 315
saloutos 0:083111ae2a11 316 /**
saloutos 0:083111ae2a11 317 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 318 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
saloutos 0:083111ae2a11 319 \brief Type definitions for the NVIC Registers
saloutos 0:083111ae2a11 320 @{
saloutos 0:083111ae2a11 321 */
saloutos 0:083111ae2a11 322
saloutos 0:083111ae2a11 323 /**
saloutos 0:083111ae2a11 324 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
saloutos 0:083111ae2a11 325 */
saloutos 0:083111ae2a11 326 typedef struct
saloutos 0:083111ae2a11 327 {
saloutos 0:083111ae2a11 328 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
saloutos 0:083111ae2a11 329 uint32_t RESERVED0[31U];
saloutos 0:083111ae2a11 330 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
saloutos 0:083111ae2a11 331 uint32_t RSERVED1[31U];
saloutos 0:083111ae2a11 332 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
saloutos 0:083111ae2a11 333 uint32_t RESERVED2[31U];
saloutos 0:083111ae2a11 334 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
saloutos 0:083111ae2a11 335 uint32_t RESERVED3[31U];
saloutos 0:083111ae2a11 336 uint32_t RESERVED4[64U];
saloutos 0:083111ae2a11 337 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
saloutos 0:083111ae2a11 338 } NVIC_Type;
saloutos 0:083111ae2a11 339
saloutos 0:083111ae2a11 340 /*@} end of group CMSIS_NVIC */
saloutos 0:083111ae2a11 341
saloutos 0:083111ae2a11 342
saloutos 0:083111ae2a11 343 /**
saloutos 0:083111ae2a11 344 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 345 \defgroup CMSIS_SCB System Control Block (SCB)
saloutos 0:083111ae2a11 346 \brief Type definitions for the System Control Block Registers
saloutos 0:083111ae2a11 347 @{
saloutos 0:083111ae2a11 348 */
saloutos 0:083111ae2a11 349
saloutos 0:083111ae2a11 350 /**
saloutos 0:083111ae2a11 351 \brief Structure type to access the System Control Block (SCB).
saloutos 0:083111ae2a11 352 */
saloutos 0:083111ae2a11 353 typedef struct
saloutos 0:083111ae2a11 354 {
saloutos 0:083111ae2a11 355 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
saloutos 0:083111ae2a11 356 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
saloutos 0:083111ae2a11 357 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos 0:083111ae2a11 358 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
saloutos 0:083111ae2a11 359 #else
saloutos 0:083111ae2a11 360 uint32_t RESERVED0;
saloutos 0:083111ae2a11 361 #endif
saloutos 0:083111ae2a11 362 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
saloutos 0:083111ae2a11 363 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
saloutos 0:083111ae2a11 364 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
saloutos 0:083111ae2a11 365 uint32_t RESERVED1;
saloutos 0:083111ae2a11 366 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
saloutos 0:083111ae2a11 367 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
saloutos 0:083111ae2a11 368 } SCB_Type;
saloutos 0:083111ae2a11 369
saloutos 0:083111ae2a11 370 /* SCB CPUID Register Definitions */
saloutos 0:083111ae2a11 371 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
saloutos 0:083111ae2a11 372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
saloutos 0:083111ae2a11 373
saloutos 0:083111ae2a11 374 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
saloutos 0:083111ae2a11 375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
saloutos 0:083111ae2a11 376
saloutos 0:083111ae2a11 377 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
saloutos 0:083111ae2a11 378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
saloutos 0:083111ae2a11 379
saloutos 0:083111ae2a11 380 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
saloutos 0:083111ae2a11 381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
saloutos 0:083111ae2a11 382
saloutos 0:083111ae2a11 383 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
saloutos 0:083111ae2a11 384 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
saloutos 0:083111ae2a11 385
saloutos 0:083111ae2a11 386 /* SCB Interrupt Control State Register Definitions */
saloutos 0:083111ae2a11 387 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
saloutos 0:083111ae2a11 388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
saloutos 0:083111ae2a11 389
saloutos 0:083111ae2a11 390 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
saloutos 0:083111ae2a11 391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
saloutos 0:083111ae2a11 392
saloutos 0:083111ae2a11 393 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
saloutos 0:083111ae2a11 394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
saloutos 0:083111ae2a11 395
saloutos 0:083111ae2a11 396 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
saloutos 0:083111ae2a11 397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
saloutos 0:083111ae2a11 398
saloutos 0:083111ae2a11 399 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
saloutos 0:083111ae2a11 400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
saloutos 0:083111ae2a11 401
saloutos 0:083111ae2a11 402 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
saloutos 0:083111ae2a11 403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
saloutos 0:083111ae2a11 404
saloutos 0:083111ae2a11 405 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
saloutos 0:083111ae2a11 406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
saloutos 0:083111ae2a11 407
saloutos 0:083111ae2a11 408 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
saloutos 0:083111ae2a11 409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
saloutos 0:083111ae2a11 410
saloutos 0:083111ae2a11 411 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
saloutos 0:083111ae2a11 412 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
saloutos 0:083111ae2a11 413
saloutos 0:083111ae2a11 414 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos 0:083111ae2a11 415 /* SCB Interrupt Control State Register Definitions */
saloutos 0:083111ae2a11 416 #define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
saloutos 0:083111ae2a11 417 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
saloutos 0:083111ae2a11 418 #endif
saloutos 0:083111ae2a11 419
saloutos 0:083111ae2a11 420 /* SCB Application Interrupt and Reset Control Register Definitions */
saloutos 0:083111ae2a11 421 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
saloutos 0:083111ae2a11 422 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
saloutos 0:083111ae2a11 423
saloutos 0:083111ae2a11 424 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
saloutos 0:083111ae2a11 425 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
saloutos 0:083111ae2a11 426
saloutos 0:083111ae2a11 427 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
saloutos 0:083111ae2a11 428 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
saloutos 0:083111ae2a11 429
saloutos 0:083111ae2a11 430 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
saloutos 0:083111ae2a11 431 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
saloutos 0:083111ae2a11 432
saloutos 0:083111ae2a11 433 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
saloutos 0:083111ae2a11 434 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
saloutos 0:083111ae2a11 435
saloutos 0:083111ae2a11 436 /* SCB System Control Register Definitions */
saloutos 0:083111ae2a11 437 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
saloutos 0:083111ae2a11 438 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
saloutos 0:083111ae2a11 439
saloutos 0:083111ae2a11 440 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
saloutos 0:083111ae2a11 441 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
saloutos 0:083111ae2a11 442
saloutos 0:083111ae2a11 443 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
saloutos 0:083111ae2a11 444 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
saloutos 0:083111ae2a11 445
saloutos 0:083111ae2a11 446 /* SCB Configuration Control Register Definitions */
saloutos 0:083111ae2a11 447 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
saloutos 0:083111ae2a11 448 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
saloutos 0:083111ae2a11 449
saloutos 0:083111ae2a11 450 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
saloutos 0:083111ae2a11 451 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
saloutos 0:083111ae2a11 452
saloutos 0:083111ae2a11 453 /* SCB System Handler Control and State Register Definitions */
saloutos 0:083111ae2a11 454 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
saloutos 0:083111ae2a11 455 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
saloutos 0:083111ae2a11 456
saloutos 0:083111ae2a11 457 /*@} end of group CMSIS_SCB */
saloutos 0:083111ae2a11 458
saloutos 0:083111ae2a11 459
saloutos 0:083111ae2a11 460 /**
saloutos 0:083111ae2a11 461 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
saloutos 0:083111ae2a11 463 \brief Type definitions for the System Timer Registers.
saloutos 0:083111ae2a11 464 @{
saloutos 0:083111ae2a11 465 */
saloutos 0:083111ae2a11 466
saloutos 0:083111ae2a11 467 /**
saloutos 0:083111ae2a11 468 \brief Structure type to access the System Timer (SysTick).
saloutos 0:083111ae2a11 469 */
saloutos 0:083111ae2a11 470 typedef struct
saloutos 0:083111ae2a11 471 {
saloutos 0:083111ae2a11 472 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
saloutos 0:083111ae2a11 473 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
saloutos 0:083111ae2a11 474 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
saloutos 0:083111ae2a11 475 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
saloutos 0:083111ae2a11 476 } SysTick_Type;
saloutos 0:083111ae2a11 477
saloutos 0:083111ae2a11 478 /* SysTick Control / Status Register Definitions */
saloutos 0:083111ae2a11 479 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
saloutos 0:083111ae2a11 480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
saloutos 0:083111ae2a11 481
saloutos 0:083111ae2a11 482 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
saloutos 0:083111ae2a11 483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
saloutos 0:083111ae2a11 484
saloutos 0:083111ae2a11 485 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
saloutos 0:083111ae2a11 486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
saloutos 0:083111ae2a11 487
saloutos 0:083111ae2a11 488 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
saloutos 0:083111ae2a11 489 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 490
saloutos 0:083111ae2a11 491 /* SysTick Reload Register Definitions */
saloutos 0:083111ae2a11 492 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
saloutos 0:083111ae2a11 493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
saloutos 0:083111ae2a11 494
saloutos 0:083111ae2a11 495 /* SysTick Current Register Definitions */
saloutos 0:083111ae2a11 496 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
saloutos 0:083111ae2a11 497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
saloutos 0:083111ae2a11 498
saloutos 0:083111ae2a11 499 /* SysTick Calibration Register Definitions */
saloutos 0:083111ae2a11 500 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
saloutos 0:083111ae2a11 501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
saloutos 0:083111ae2a11 502
saloutos 0:083111ae2a11 503 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
saloutos 0:083111ae2a11 504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
saloutos 0:083111ae2a11 505
saloutos 0:083111ae2a11 506 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
saloutos 0:083111ae2a11 507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
saloutos 0:083111ae2a11 508
saloutos 0:083111ae2a11 509 /*@} end of group CMSIS_SysTick */
saloutos 0:083111ae2a11 510
saloutos 0:083111ae2a11 511 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 512 /**
saloutos 0:083111ae2a11 513 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 514 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 515 \brief Type definitions for the Memory Protection Unit (MPU)
saloutos 0:083111ae2a11 516 @{
saloutos 0:083111ae2a11 517 */
saloutos 0:083111ae2a11 518
saloutos 0:083111ae2a11 519 /**
saloutos 0:083111ae2a11 520 \brief Structure type to access the Memory Protection Unit (MPU).
saloutos 0:083111ae2a11 521 */
saloutos 0:083111ae2a11 522 typedef struct
saloutos 0:083111ae2a11 523 {
saloutos 0:083111ae2a11 524 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
saloutos 0:083111ae2a11 525 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
saloutos 0:083111ae2a11 526 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
saloutos 0:083111ae2a11 527 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
saloutos 0:083111ae2a11 528 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
saloutos 0:083111ae2a11 529 } MPU_Type;
saloutos 0:083111ae2a11 530
saloutos 0:083111ae2a11 531 /* MPU Type Register Definitions */
saloutos 0:083111ae2a11 532 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
saloutos 0:083111ae2a11 533 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
saloutos 0:083111ae2a11 534
saloutos 0:083111ae2a11 535 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
saloutos 0:083111ae2a11 536 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
saloutos 0:083111ae2a11 537
saloutos 0:083111ae2a11 538 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
saloutos 0:083111ae2a11 539 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
saloutos 0:083111ae2a11 540
saloutos 0:083111ae2a11 541 /* MPU Control Register Definitions */
saloutos 0:083111ae2a11 542 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
saloutos 0:083111ae2a11 543 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
saloutos 0:083111ae2a11 544
saloutos 0:083111ae2a11 545 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
saloutos 0:083111ae2a11 546 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
saloutos 0:083111ae2a11 547
saloutos 0:083111ae2a11 548 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
saloutos 0:083111ae2a11 549 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
saloutos 0:083111ae2a11 550
saloutos 0:083111ae2a11 551 /* MPU Region Number Register Definitions */
saloutos 0:083111ae2a11 552 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
saloutos 0:083111ae2a11 553 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
saloutos 0:083111ae2a11 554
saloutos 0:083111ae2a11 555 /* MPU Region Base Address Register Definitions */
saloutos 0:083111ae2a11 556 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
saloutos 0:083111ae2a11 557 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
saloutos 0:083111ae2a11 558
saloutos 0:083111ae2a11 559 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
saloutos 0:083111ae2a11 560 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
saloutos 0:083111ae2a11 561
saloutos 0:083111ae2a11 562 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
saloutos 0:083111ae2a11 563 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
saloutos 0:083111ae2a11 564
saloutos 0:083111ae2a11 565 /* MPU Region Attribute and Size Register Definitions */
saloutos 0:083111ae2a11 566 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
saloutos 0:083111ae2a11 567 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
saloutos 0:083111ae2a11 568
saloutos 0:083111ae2a11 569 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
saloutos 0:083111ae2a11 570 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
saloutos 0:083111ae2a11 571
saloutos 0:083111ae2a11 572 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
saloutos 0:083111ae2a11 573 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
saloutos 0:083111ae2a11 574
saloutos 0:083111ae2a11 575 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
saloutos 0:083111ae2a11 576 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
saloutos 0:083111ae2a11 577
saloutos 0:083111ae2a11 578 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
saloutos 0:083111ae2a11 579 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
saloutos 0:083111ae2a11 580
saloutos 0:083111ae2a11 581 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
saloutos 0:083111ae2a11 582 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
saloutos 0:083111ae2a11 583
saloutos 0:083111ae2a11 584 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
saloutos 0:083111ae2a11 585 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
saloutos 0:083111ae2a11 586
saloutos 0:083111ae2a11 587 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
saloutos 0:083111ae2a11 588 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
saloutos 0:083111ae2a11 589
saloutos 0:083111ae2a11 590 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
saloutos 0:083111ae2a11 591 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
saloutos 0:083111ae2a11 592
saloutos 0:083111ae2a11 593 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
saloutos 0:083111ae2a11 594 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
saloutos 0:083111ae2a11 595
saloutos 0:083111ae2a11 596 /*@} end of group CMSIS_MPU */
saloutos 0:083111ae2a11 597 #endif
saloutos 0:083111ae2a11 598
saloutos 0:083111ae2a11 599
saloutos 0:083111ae2a11 600 /**
saloutos 0:083111ae2a11 601 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 602 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
saloutos 0:083111ae2a11 603 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
saloutos 0:083111ae2a11 604 Therefore they are not covered by the Cortex-M0+ header file.
saloutos 0:083111ae2a11 605 @{
saloutos 0:083111ae2a11 606 */
saloutos 0:083111ae2a11 607 /*@} end of group CMSIS_CoreDebug */
saloutos 0:083111ae2a11 608
saloutos 0:083111ae2a11 609
saloutos 0:083111ae2a11 610 /**
saloutos 0:083111ae2a11 611 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 612 \defgroup CMSIS_core_bitfield Core register bit field macros
saloutos 0:083111ae2a11 613 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
saloutos 0:083111ae2a11 614 @{
saloutos 0:083111ae2a11 615 */
saloutos 0:083111ae2a11 616
saloutos 0:083111ae2a11 617 /**
saloutos 0:083111ae2a11 618 \brief Mask and shift a bit field value for use in a register bit range.
saloutos 0:083111ae2a11 619 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 620 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 621 \return Masked and shifted value.
saloutos 0:083111ae2a11 622 */
saloutos 0:083111ae2a11 623 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
saloutos 0:083111ae2a11 624
saloutos 0:083111ae2a11 625 /**
saloutos 0:083111ae2a11 626 \brief Mask and shift a register value to extract a bit filed value.
saloutos 0:083111ae2a11 627 \param[in] field Name of the register bit field.
saloutos 0:083111ae2a11 628 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
saloutos 0:083111ae2a11 629 \return Masked and shifted bit field value.
saloutos 0:083111ae2a11 630 */
saloutos 0:083111ae2a11 631 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
saloutos 0:083111ae2a11 632
saloutos 0:083111ae2a11 633 /*@} end of group CMSIS_core_bitfield */
saloutos 0:083111ae2a11 634
saloutos 0:083111ae2a11 635
saloutos 0:083111ae2a11 636 /**
saloutos 0:083111ae2a11 637 \ingroup CMSIS_core_register
saloutos 0:083111ae2a11 638 \defgroup CMSIS_core_base Core Definitions
saloutos 0:083111ae2a11 639 \brief Definitions for base addresses, unions, and structures.
saloutos 0:083111ae2a11 640 @{
saloutos 0:083111ae2a11 641 */
saloutos 0:083111ae2a11 642
saloutos 0:083111ae2a11 643 /* Memory mapping of Core Hardware */
saloutos 0:083111ae2a11 644 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
saloutos 0:083111ae2a11 645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
saloutos 0:083111ae2a11 646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
saloutos 0:083111ae2a11 647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
saloutos 0:083111ae2a11 648
saloutos 0:083111ae2a11 649 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
saloutos 0:083111ae2a11 650 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
saloutos 0:083111ae2a11 651 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
saloutos 0:083111ae2a11 652
saloutos 0:083111ae2a11 653 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos 0:083111ae2a11 654 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 655 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
saloutos 0:083111ae2a11 656 #endif
saloutos 0:083111ae2a11 657
saloutos 0:083111ae2a11 658 /*@} */
saloutos 0:083111ae2a11 659
saloutos 0:083111ae2a11 660
saloutos 0:083111ae2a11 661
saloutos 0:083111ae2a11 662 /*******************************************************************************
saloutos 0:083111ae2a11 663 * Hardware Abstraction Layer
saloutos 0:083111ae2a11 664 Core Function Interface contains:
saloutos 0:083111ae2a11 665 - Core NVIC Functions
saloutos 0:083111ae2a11 666 - Core SysTick Functions
saloutos 0:083111ae2a11 667 - Core Register Access Functions
saloutos 0:083111ae2a11 668 ******************************************************************************/
saloutos 0:083111ae2a11 669 /**
saloutos 0:083111ae2a11 670 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
saloutos 0:083111ae2a11 671 */
saloutos 0:083111ae2a11 672
saloutos 0:083111ae2a11 673
saloutos 0:083111ae2a11 674
saloutos 0:083111ae2a11 675 /* ########################## NVIC functions #################################### */
saloutos 0:083111ae2a11 676 /**
saloutos 0:083111ae2a11 677 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 678 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
saloutos 0:083111ae2a11 679 \brief Functions that manage interrupts and exceptions via the NVIC.
saloutos 0:083111ae2a11 680 @{
saloutos 0:083111ae2a11 681 */
saloutos 0:083111ae2a11 682
saloutos 0:083111ae2a11 683 #ifdef CMSIS_NVIC_VIRTUAL
saloutos 0:083111ae2a11 684 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 685 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
saloutos 0:083111ae2a11 686 #endif
saloutos 0:083111ae2a11 687 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 688 #else
saloutos 0:083111ae2a11 689 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */
saloutos 0:083111ae2a11 690 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */
saloutos 0:083111ae2a11 691 #define NVIC_EnableIRQ __NVIC_EnableIRQ
saloutos 0:083111ae2a11 692 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
saloutos 0:083111ae2a11 693 #define NVIC_DisableIRQ __NVIC_DisableIRQ
saloutos 0:083111ae2a11 694 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
saloutos 0:083111ae2a11 695 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
saloutos 0:083111ae2a11 696 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
saloutos 0:083111ae2a11 697 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
saloutos 0:083111ae2a11 698 #define NVIC_SetPriority __NVIC_SetPriority
saloutos 0:083111ae2a11 699 #define NVIC_GetPriority __NVIC_GetPriority
saloutos 0:083111ae2a11 700 #define NVIC_SystemReset __NVIC_SystemReset
saloutos 0:083111ae2a11 701 #endif /* CMSIS_NVIC_VIRTUAL */
saloutos 0:083111ae2a11 702
saloutos 0:083111ae2a11 703 #ifdef CMSIS_VECTAB_VIRTUAL
saloutos 0:083111ae2a11 704 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 705 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
saloutos 0:083111ae2a11 706 #endif
saloutos 0:083111ae2a11 707 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos 0:083111ae2a11 708 #else
saloutos 0:083111ae2a11 709 #define NVIC_SetVector __NVIC_SetVector
saloutos 0:083111ae2a11 710 #define NVIC_GetVector __NVIC_GetVector
saloutos 0:083111ae2a11 711 #endif /* (CMSIS_VECTAB_VIRTUAL) */
saloutos 0:083111ae2a11 712
saloutos 0:083111ae2a11 713 #define NVIC_USER_IRQ_OFFSET 16
saloutos 0:083111ae2a11 714
saloutos 0:083111ae2a11 715
saloutos 0:083111ae2a11 716 /* Interrupt Priorities are WORD accessible only under ARMv6M */
saloutos 0:083111ae2a11 717 /* The following MACROS handle generation of the register offset and byte masks */
saloutos 0:083111ae2a11 718 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
saloutos 0:083111ae2a11 719 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
saloutos 0:083111ae2a11 720 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
saloutos 0:083111ae2a11 721
saloutos 0:083111ae2a11 722
saloutos 0:083111ae2a11 723 /**
saloutos 0:083111ae2a11 724 \brief Enable Interrupt
saloutos 0:083111ae2a11 725 \details Enables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 726 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 727 \note IRQn must not be negative.
saloutos 0:083111ae2a11 728 */
saloutos 0:083111ae2a11 729 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 730 {
saloutos 0:083111ae2a11 731 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 732 {
saloutos 0:083111ae2a11 733 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 734 }
saloutos 0:083111ae2a11 735 }
saloutos 0:083111ae2a11 736
saloutos 0:083111ae2a11 737
saloutos 0:083111ae2a11 738 /**
saloutos 0:083111ae2a11 739 \brief Get Interrupt Enable status
saloutos 0:083111ae2a11 740 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
saloutos 0:083111ae2a11 741 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 742 \return 0 Interrupt is not enabled.
saloutos 0:083111ae2a11 743 \return 1 Interrupt is enabled.
saloutos 0:083111ae2a11 744 \note IRQn must not be negative.
saloutos 0:083111ae2a11 745 */
saloutos 0:083111ae2a11 746 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 747 {
saloutos 0:083111ae2a11 748 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 749 {
saloutos 0:083111ae2a11 750 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 751 }
saloutos 0:083111ae2a11 752 else
saloutos 0:083111ae2a11 753 {
saloutos 0:083111ae2a11 754 return(0U);
saloutos 0:083111ae2a11 755 }
saloutos 0:083111ae2a11 756 }
saloutos 0:083111ae2a11 757
saloutos 0:083111ae2a11 758
saloutos 0:083111ae2a11 759 /**
saloutos 0:083111ae2a11 760 \brief Disable Interrupt
saloutos 0:083111ae2a11 761 \details Disables a device specific interrupt in the NVIC interrupt controller.
saloutos 0:083111ae2a11 762 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 763 \note IRQn must not be negative.
saloutos 0:083111ae2a11 764 */
saloutos 0:083111ae2a11 765 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 766 {
saloutos 0:083111ae2a11 767 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 768 {
saloutos 0:083111ae2a11 769 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 770 __DSB();
saloutos 0:083111ae2a11 771 __ISB();
saloutos 0:083111ae2a11 772 }
saloutos 0:083111ae2a11 773 }
saloutos 0:083111ae2a11 774
saloutos 0:083111ae2a11 775
saloutos 0:083111ae2a11 776 /**
saloutos 0:083111ae2a11 777 \brief Get Pending Interrupt
saloutos 0:083111ae2a11 778 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
saloutos 0:083111ae2a11 779 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 780 \return 0 Interrupt status is not pending.
saloutos 0:083111ae2a11 781 \return 1 Interrupt status is pending.
saloutos 0:083111ae2a11 782 \note IRQn must not be negative.
saloutos 0:083111ae2a11 783 */
saloutos 0:083111ae2a11 784 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 785 {
saloutos 0:083111ae2a11 786 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 787 {
saloutos 0:083111ae2a11 788 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos 0:083111ae2a11 789 }
saloutos 0:083111ae2a11 790 else
saloutos 0:083111ae2a11 791 {
saloutos 0:083111ae2a11 792 return(0U);
saloutos 0:083111ae2a11 793 }
saloutos 0:083111ae2a11 794 }
saloutos 0:083111ae2a11 795
saloutos 0:083111ae2a11 796
saloutos 0:083111ae2a11 797 /**
saloutos 0:083111ae2a11 798 \brief Set Pending Interrupt
saloutos 0:083111ae2a11 799 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 800 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 801 \note IRQn must not be negative.
saloutos 0:083111ae2a11 802 */
saloutos 0:083111ae2a11 803 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 804 {
saloutos 0:083111ae2a11 805 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 806 {
saloutos 0:083111ae2a11 807 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 808 }
saloutos 0:083111ae2a11 809 }
saloutos 0:083111ae2a11 810
saloutos 0:083111ae2a11 811
saloutos 0:083111ae2a11 812 /**
saloutos 0:083111ae2a11 813 \brief Clear Pending Interrupt
saloutos 0:083111ae2a11 814 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
saloutos 0:083111ae2a11 815 \param [in] IRQn Device specific interrupt number.
saloutos 0:083111ae2a11 816 \note IRQn must not be negative.
saloutos 0:083111ae2a11 817 */
saloutos 0:083111ae2a11 818 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
saloutos 0:083111ae2a11 819 {
saloutos 0:083111ae2a11 820 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 821 {
saloutos 0:083111ae2a11 822 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos 0:083111ae2a11 823 }
saloutos 0:083111ae2a11 824 }
saloutos 0:083111ae2a11 825
saloutos 0:083111ae2a11 826
saloutos 0:083111ae2a11 827 /**
saloutos 0:083111ae2a11 828 \brief Set Interrupt Priority
saloutos 0:083111ae2a11 829 \details Sets the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 830 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 831 or negative to specify a processor exception.
saloutos 0:083111ae2a11 832 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 833 \param [in] priority Priority to set.
saloutos 0:083111ae2a11 834 \note The priority cannot be set for every processor exception.
saloutos 0:083111ae2a11 835 */
saloutos 0:083111ae2a11 836 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
saloutos 0:083111ae2a11 837 {
saloutos 0:083111ae2a11 838 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 839 {
saloutos 0:083111ae2a11 840 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
saloutos 0:083111ae2a11 841 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos 0:083111ae2a11 842 }
saloutos 0:083111ae2a11 843 else
saloutos 0:083111ae2a11 844 {
saloutos 0:083111ae2a11 845 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
saloutos 0:083111ae2a11 846 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos 0:083111ae2a11 847 }
saloutos 0:083111ae2a11 848 }
saloutos 0:083111ae2a11 849
saloutos 0:083111ae2a11 850
saloutos 0:083111ae2a11 851 /**
saloutos 0:083111ae2a11 852 \brief Get Interrupt Priority
saloutos 0:083111ae2a11 853 \details Reads the priority of a device specific interrupt or a processor exception.
saloutos 0:083111ae2a11 854 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 855 or negative to specify a processor exception.
saloutos 0:083111ae2a11 856 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 857 \return Interrupt Priority.
saloutos 0:083111ae2a11 858 Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos 0:083111ae2a11 859 */
saloutos 0:083111ae2a11 860 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
saloutos 0:083111ae2a11 861 {
saloutos 0:083111ae2a11 862
saloutos 0:083111ae2a11 863 if ((int32_t)(IRQn) >= 0)
saloutos 0:083111ae2a11 864 {
saloutos 0:083111ae2a11 865 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 866 }
saloutos 0:083111ae2a11 867 else
saloutos 0:083111ae2a11 868 {
saloutos 0:083111ae2a11 869 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos 0:083111ae2a11 870 }
saloutos 0:083111ae2a11 871 }
saloutos 0:083111ae2a11 872
saloutos 0:083111ae2a11 873
saloutos 0:083111ae2a11 874 /**
saloutos 0:083111ae2a11 875 \brief Set Interrupt Vector
saloutos 0:083111ae2a11 876 \details Sets an interrupt vector in SRAM based interrupt vector table.
saloutos 0:083111ae2a11 877 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 878 or negative to specify a processor exception.
saloutos 0:083111ae2a11 879 VTOR must been relocated to SRAM before.
saloutos 0:083111ae2a11 880 If VTOR is not present address 0 must be mapped to SRAM.
saloutos 0:083111ae2a11 881 \param [in] IRQn Interrupt number
saloutos 0:083111ae2a11 882 \param [in] vector Address of interrupt handler function
saloutos 0:083111ae2a11 883 */
saloutos 0:083111ae2a11 884 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
saloutos 0:083111ae2a11 885 {
saloutos 0:083111ae2a11 886 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos 0:083111ae2a11 887 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 888 #else
saloutos 0:083111ae2a11 889 uint32_t *vectors = (uint32_t *)0x0U;
saloutos 0:083111ae2a11 890 #endif
saloutos 0:083111ae2a11 891 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
saloutos 0:083111ae2a11 892 }
saloutos 0:083111ae2a11 893
saloutos 0:083111ae2a11 894
saloutos 0:083111ae2a11 895 /**
saloutos 0:083111ae2a11 896 \brief Get Interrupt Vector
saloutos 0:083111ae2a11 897 \details Reads an interrupt vector from interrupt vector table.
saloutos 0:083111ae2a11 898 The interrupt number can be positive to specify a device specific interrupt,
saloutos 0:083111ae2a11 899 or negative to specify a processor exception.
saloutos 0:083111ae2a11 900 \param [in] IRQn Interrupt number.
saloutos 0:083111ae2a11 901 \return Address of interrupt handler function
saloutos 0:083111ae2a11 902 */
saloutos 0:083111ae2a11 903 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
saloutos 0:083111ae2a11 904 {
saloutos 0:083111ae2a11 905 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos 0:083111ae2a11 906 uint32_t *vectors = (uint32_t *)SCB->VTOR;
saloutos 0:083111ae2a11 907 #else
saloutos 0:083111ae2a11 908 uint32_t *vectors = (uint32_t *)0x0U;
saloutos 0:083111ae2a11 909 #endif
saloutos 0:083111ae2a11 910 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
saloutos 0:083111ae2a11 911
saloutos 0:083111ae2a11 912 }
saloutos 0:083111ae2a11 913
saloutos 0:083111ae2a11 914
saloutos 0:083111ae2a11 915 /**
saloutos 0:083111ae2a11 916 \brief System Reset
saloutos 0:083111ae2a11 917 \details Initiates a system reset request to reset the MCU.
saloutos 0:083111ae2a11 918 */
saloutos 0:083111ae2a11 919 __STATIC_INLINE void __NVIC_SystemReset(void)
saloutos 0:083111ae2a11 920 {
saloutos 0:083111ae2a11 921 __DSB(); /* Ensure all outstanding memory accesses included
saloutos 0:083111ae2a11 922 buffered write are completed before reset */
saloutos 0:083111ae2a11 923 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
saloutos 0:083111ae2a11 924 SCB_AIRCR_SYSRESETREQ_Msk);
saloutos 0:083111ae2a11 925 __DSB(); /* Ensure completion of memory access */
saloutos 0:083111ae2a11 926
saloutos 0:083111ae2a11 927 for(;;) /* wait until reset */
saloutos 0:083111ae2a11 928 {
saloutos 0:083111ae2a11 929 __NOP();
saloutos 0:083111ae2a11 930 }
saloutos 0:083111ae2a11 931 }
saloutos 0:083111ae2a11 932
saloutos 0:083111ae2a11 933 /*@} end of CMSIS_Core_NVICFunctions */
saloutos 0:083111ae2a11 934
saloutos 0:083111ae2a11 935
saloutos 0:083111ae2a11 936 /* ########################## FPU functions #################################### */
saloutos 0:083111ae2a11 937 /**
saloutos 0:083111ae2a11 938 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 939 \defgroup CMSIS_Core_FpuFunctions FPU Functions
saloutos 0:083111ae2a11 940 \brief Function that provides FPU type.
saloutos 0:083111ae2a11 941 @{
saloutos 0:083111ae2a11 942 */
saloutos 0:083111ae2a11 943
saloutos 0:083111ae2a11 944 /**
saloutos 0:083111ae2a11 945 \brief get FPU type
saloutos 0:083111ae2a11 946 \details returns the FPU type
saloutos 0:083111ae2a11 947 \returns
saloutos 0:083111ae2a11 948 - \b 0: No FPU
saloutos 0:083111ae2a11 949 - \b 1: Single precision FPU
saloutos 0:083111ae2a11 950 - \b 2: Double + Single precision FPU
saloutos 0:083111ae2a11 951 */
saloutos 0:083111ae2a11 952 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
saloutos 0:083111ae2a11 953 {
saloutos 0:083111ae2a11 954 return 0U; /* No FPU */
saloutos 0:083111ae2a11 955 }
saloutos 0:083111ae2a11 956
saloutos 0:083111ae2a11 957
saloutos 0:083111ae2a11 958 /*@} end of CMSIS_Core_FpuFunctions */
saloutos 0:083111ae2a11 959
saloutos 0:083111ae2a11 960
saloutos 0:083111ae2a11 961
saloutos 0:083111ae2a11 962 /* ################################## SysTick function ############################################ */
saloutos 0:083111ae2a11 963 /**
saloutos 0:083111ae2a11 964 \ingroup CMSIS_Core_FunctionInterface
saloutos 0:083111ae2a11 965 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
saloutos 0:083111ae2a11 966 \brief Functions that configure the System.
saloutos 0:083111ae2a11 967 @{
saloutos 0:083111ae2a11 968 */
saloutos 0:083111ae2a11 969
saloutos 0:083111ae2a11 970 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
saloutos 0:083111ae2a11 971
saloutos 0:083111ae2a11 972 /**
saloutos 0:083111ae2a11 973 \brief System Tick Configuration
saloutos 0:083111ae2a11 974 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
saloutos 0:083111ae2a11 975 Counter is in free running mode to generate periodic interrupts.
saloutos 0:083111ae2a11 976 \param [in] ticks Number of ticks between two interrupts.
saloutos 0:083111ae2a11 977 \return 0 Function succeeded.
saloutos 0:083111ae2a11 978 \return 1 Function failed.
saloutos 0:083111ae2a11 979 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos 0:083111ae2a11 980 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos 0:083111ae2a11 981 must contain a vendor-specific implementation of this function.
saloutos 0:083111ae2a11 982 */
saloutos 0:083111ae2a11 983 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
saloutos 0:083111ae2a11 984 {
saloutos 0:083111ae2a11 985 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos 0:083111ae2a11 986 {
saloutos 0:083111ae2a11 987 return (1UL); /* Reload value impossible */
saloutos 0:083111ae2a11 988 }
saloutos 0:083111ae2a11 989
saloutos 0:083111ae2a11 990 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos 0:083111ae2a11 991 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos 0:083111ae2a11 992 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos 0:083111ae2a11 993 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
saloutos 0:083111ae2a11 994 SysTick_CTRL_TICKINT_Msk |
saloutos 0:083111ae2a11 995 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos 0:083111ae2a11 996 return (0UL); /* Function successful */
saloutos 0:083111ae2a11 997 }
saloutos 0:083111ae2a11 998
saloutos 0:083111ae2a11 999 #endif
saloutos 0:083111ae2a11 1000
saloutos 0:083111ae2a11 1001 /*@} end of CMSIS_Core_SysTickFunctions */
saloutos 0:083111ae2a11 1002
saloutos 0:083111ae2a11 1003
saloutos 0:083111ae2a11 1004
saloutos 0:083111ae2a11 1005
saloutos 0:083111ae2a11 1006 #ifdef __cplusplus
saloutos 0:083111ae2a11 1007 }
saloutos 0:083111ae2a11 1008 #endif
saloutos 0:083111ae2a11 1009
saloutos 0:083111ae2a11 1010 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
saloutos 0:083111ae2a11 1011
saloutos 0:083111ae2a11 1012 #endif /* __CMSIS_GENERIC */