mbed-dev - Biomimetics MBED Library w/ Added Support for CAN3

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Biomimetics MBED Library w/ Added Support for CAN3

Dependents: CAN_TEST SPIne_Plus_DYNO_SENSORS SPIne_Plus_v2 SPIne_Plus_Dyno_v2

cmsis/core_cm23.h@0:083111ae2a11, 2020-11-26 (annotated)

Committer:: saloutos
Date:: Thu Nov 26 04:08:56 2020 +0000
Revision:: 0:083111ae2a11

first commit of leaned mbed dev lib

Who changed what in which revision?

User	Revision	Line number	New contents of line
saloutos	0:083111ae2a11	1	/************************************************************************//
saloutos	0:083111ae2a11	2	* @file core_cm23.h
saloutos	0:083111ae2a11	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
saloutos	0:083111ae2a11	4	* @version V5.0.2
saloutos	0:083111ae2a11	5	* @date 13. February 2017
saloutos	0:083111ae2a11	6	******************************************************************************/
saloutos	0:083111ae2a11	7	/*
saloutos	0:083111ae2a11	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
saloutos	0:083111ae2a11	9	*
saloutos	0:083111ae2a11	10	* SPDX-License-Identifier: Apache-2.0
saloutos	0:083111ae2a11	11	*
saloutos	0:083111ae2a11	12	* Licensed under the Apache License, Version 2.0 (the License); you may
saloutos	0:083111ae2a11	13	* not use this file except in compliance with the License.
saloutos	0:083111ae2a11	14	* You may obtain a copy of the License at
saloutos	0:083111ae2a11	15	*
saloutos	0:083111ae2a11	16	* www.apache.org/licenses/LICENSE-2.0
saloutos	0:083111ae2a11	17	*
saloutos	0:083111ae2a11	18	* Unless required by applicable law or agreed to in writing, software
saloutos	0:083111ae2a11	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
saloutos	0:083111ae2a11	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
saloutos	0:083111ae2a11	21	* See the License for the specific language governing permissions and
saloutos	0:083111ae2a11	22	* limitations under the License.
saloutos	0:083111ae2a11	23	*/
saloutos	0:083111ae2a11	24
saloutos	0:083111ae2a11	25	#if defined ( __ICCARM__ )
saloutos	0:083111ae2a11	26	#pragma system_include /* treat file as system include file for MISRA check */
saloutos	0:083111ae2a11	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos	0:083111ae2a11	28	#pragma clang system_header /* treat file as system include file */
saloutos	0:083111ae2a11	29	#endif
saloutos	0:083111ae2a11	30
saloutos	0:083111ae2a11	31	#ifndef __CORE_CM23_H_GENERIC
saloutos	0:083111ae2a11	32	#define __CORE_CM23_H_GENERIC
saloutos	0:083111ae2a11	33
saloutos	0:083111ae2a11	34	#include <stdint.h>
saloutos	0:083111ae2a11	35
saloutos	0:083111ae2a11	36	#ifdef __cplusplus
saloutos	0:083111ae2a11	37	extern "C" {
saloutos	0:083111ae2a11	38	#endif
saloutos	0:083111ae2a11	39
saloutos	0:083111ae2a11	40	/**
saloutos	0:083111ae2a11	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
saloutos	0:083111ae2a11	42	CMSIS violates the following MISRA-C:2004 rules:
saloutos	0:083111ae2a11	43
saloutos	0:083111ae2a11	44	\li Required Rule 8.5, object/function definition in header file.<br>
saloutos	0:083111ae2a11	45	Function definitions in header files are used to allow 'inlining'.
saloutos	0:083111ae2a11	46
saloutos	0:083111ae2a11	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
saloutos	0:083111ae2a11	48	Unions are used for effective representation of core registers.
saloutos	0:083111ae2a11	49
saloutos	0:083111ae2a11	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
saloutos	0:083111ae2a11	51	Function-like macros are used to allow more efficient code.
saloutos	0:083111ae2a11	52	*/
saloutos	0:083111ae2a11	53
saloutos	0:083111ae2a11	54
saloutos	0:083111ae2a11	55	/*******************************************************************************
saloutos	0:083111ae2a11	56	* CMSIS definitions
saloutos	0:083111ae2a11	57	******************************************************************************/
saloutos	0:083111ae2a11	58	/**
saloutos	0:083111ae2a11	59	\ingroup Cortex_M23
saloutos	0:083111ae2a11	60	@{
saloutos	0:083111ae2a11	61	*/
saloutos	0:083111ae2a11	62
saloutos	0:083111ae2a11	63	/* CMSIS cmGrebe definitions */
saloutos	0:083111ae2a11	64	#define __CM23_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
saloutos	0:083111ae2a11	65	#define __CM23_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
saloutos	0:083111ae2a11	66	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
saloutos	0:083111ae2a11	67	__CM23_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
saloutos	0:083111ae2a11	68
saloutos	0:083111ae2a11	69	#define __CORTEX_M (23U) /!< Cortex-M Core /
saloutos	0:083111ae2a11	70
saloutos	0:083111ae2a11	71	/** __FPU_USED indicates whether an FPU is used or not.
saloutos	0:083111ae2a11	72	This core does not support an FPU at all
saloutos	0:083111ae2a11	73	*/
saloutos	0:083111ae2a11	74	#define __FPU_USED 0U
saloutos	0:083111ae2a11	75
saloutos	0:083111ae2a11	76	#if defined ( __CC_ARM )
saloutos	0:083111ae2a11	77	#if defined __TARGET_FPU_VFP
saloutos	0:083111ae2a11	78	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	79	#endif
saloutos	0:083111ae2a11	80
saloutos	0:083111ae2a11	81	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
saloutos	0:083111ae2a11	82	#if defined __ARM_PCS_VFP
saloutos	0:083111ae2a11	83	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	84	#endif
saloutos	0:083111ae2a11	85
saloutos	0:083111ae2a11	86	#elif defined ( __GNUC__ )
saloutos	0:083111ae2a11	87	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
saloutos	0:083111ae2a11	88	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	89	#endif
saloutos	0:083111ae2a11	90
saloutos	0:083111ae2a11	91	#elif defined ( __ICCARM__ )
saloutos	0:083111ae2a11	92	#if defined __ARMVFP__
saloutos	0:083111ae2a11	93	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	94	#endif
saloutos	0:083111ae2a11	95
saloutos	0:083111ae2a11	96	#elif defined ( __TI_ARM__ )
saloutos	0:083111ae2a11	97	#if defined __TI_VFP_SUPPORT__
saloutos	0:083111ae2a11	98	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	99	#endif
saloutos	0:083111ae2a11	100
saloutos	0:083111ae2a11	101	#elif defined ( __TASKING__ )
saloutos	0:083111ae2a11	102	#if defined __FPU_VFP__
saloutos	0:083111ae2a11	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	104	#endif
saloutos	0:083111ae2a11	105
saloutos	0:083111ae2a11	106	#elif defined ( __CSMC__ )
saloutos	0:083111ae2a11	107	#if ( __CSMC__ & 0x400U)
saloutos	0:083111ae2a11	108	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
saloutos	0:083111ae2a11	109	#endif
saloutos	0:083111ae2a11	110
saloutos	0:083111ae2a11	111	#endif
saloutos	0:083111ae2a11	112
saloutos	0:083111ae2a11	113	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
saloutos	0:083111ae2a11	114
saloutos	0:083111ae2a11	115
saloutos	0:083111ae2a11	116	#ifdef __cplusplus
saloutos	0:083111ae2a11	117	}
saloutos	0:083111ae2a11	118	#endif
saloutos	0:083111ae2a11	119
saloutos	0:083111ae2a11	120	#endif /* __CORE_CM23_H_GENERIC */
saloutos	0:083111ae2a11	121
saloutos	0:083111ae2a11	122	#ifndef __CMSIS_GENERIC
saloutos	0:083111ae2a11	123
saloutos	0:083111ae2a11	124	#ifndef __CORE_CM23_H_DEPENDANT
saloutos	0:083111ae2a11	125	#define __CORE_CM23_H_DEPENDANT
saloutos	0:083111ae2a11	126
saloutos	0:083111ae2a11	127	#ifdef __cplusplus
saloutos	0:083111ae2a11	128	extern "C" {
saloutos	0:083111ae2a11	129	#endif
saloutos	0:083111ae2a11	130
saloutos	0:083111ae2a11	131	/* check device defines and use defaults */
saloutos	0:083111ae2a11	132	#if defined __CHECK_DEVICE_DEFINES
saloutos	0:083111ae2a11	133	#ifndef __CM23_REV
saloutos	0:083111ae2a11	134	#define __CM23_REV 0x0000U
saloutos	0:083111ae2a11	135	#warning "__CM23_REV not defined in device header file; using default!"
saloutos	0:083111ae2a11	136	#endif
saloutos	0:083111ae2a11	137
saloutos	0:083111ae2a11	138	#ifndef __FPU_PRESENT
saloutos	0:083111ae2a11	139	#define __FPU_PRESENT 0U
saloutos	0:083111ae2a11	140	#warning "__FPU_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	141	#endif
saloutos	0:083111ae2a11	142
saloutos	0:083111ae2a11	143	#ifndef __MPU_PRESENT
saloutos	0:083111ae2a11	144	#define __MPU_PRESENT 0U
saloutos	0:083111ae2a11	145	#warning "__MPU_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	146	#endif
saloutos	0:083111ae2a11	147
saloutos	0:083111ae2a11	148	#ifndef __SAUREGION_PRESENT
saloutos	0:083111ae2a11	149	#define __SAUREGION_PRESENT 0U
saloutos	0:083111ae2a11	150	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	151	#endif
saloutos	0:083111ae2a11	152
saloutos	0:083111ae2a11	153	#ifndef __VTOR_PRESENT
saloutos	0:083111ae2a11	154	#define __VTOR_PRESENT 0U
saloutos	0:083111ae2a11	155	#warning "__VTOR_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	156	#endif
saloutos	0:083111ae2a11	157
saloutos	0:083111ae2a11	158	#ifndef __NVIC_PRIO_BITS
saloutos	0:083111ae2a11	159	#define __NVIC_PRIO_BITS 2U
saloutos	0:083111ae2a11	160	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
saloutos	0:083111ae2a11	161	#endif
saloutos	0:083111ae2a11	162
saloutos	0:083111ae2a11	163	#ifndef __Vendor_SysTickConfig
saloutos	0:083111ae2a11	164	#define __Vendor_SysTickConfig 0U
saloutos	0:083111ae2a11	165	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
saloutos	0:083111ae2a11	166	#endif
saloutos	0:083111ae2a11	167
saloutos	0:083111ae2a11	168	#ifndef __ETM_PRESENT
saloutos	0:083111ae2a11	169	#define __ETM_PRESENT 0U
saloutos	0:083111ae2a11	170	#warning "__ETM_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	171	#endif
saloutos	0:083111ae2a11	172
saloutos	0:083111ae2a11	173	#ifndef __MTB_PRESENT
saloutos	0:083111ae2a11	174	#define __MTB_PRESENT 0U
saloutos	0:083111ae2a11	175	#warning "__MTB_PRESENT not defined in device header file; using default!"
saloutos	0:083111ae2a11	176	#endif
saloutos	0:083111ae2a11	177
saloutos	0:083111ae2a11	178	#endif
saloutos	0:083111ae2a11	179
saloutos	0:083111ae2a11	180	/* IO definitions (access restrictions to peripheral registers) */
saloutos	0:083111ae2a11	181	/**
saloutos	0:083111ae2a11	182	\defgroup CMSIS_glob_defs CMSIS Global Defines
saloutos	0:083111ae2a11	183
saloutos	0:083111ae2a11	184	<strong>IO Type Qualifiers</strong> are used
saloutos	0:083111ae2a11	185	\li to specify the access to peripheral variables.
saloutos	0:083111ae2a11	186	\li for automatic generation of peripheral register debug information.
saloutos	0:083111ae2a11	187	*/
saloutos	0:083111ae2a11	188	#ifdef __cplusplus
saloutos	0:083111ae2a11	189	#define __I volatile /!< Defines 'read only' permissions /
saloutos	0:083111ae2a11	190	#else
saloutos	0:083111ae2a11	191	#define __I volatile const /!< Defines 'read only' permissions /
saloutos	0:083111ae2a11	192	#endif
saloutos	0:083111ae2a11	193	#define __O volatile /!< Defines 'write only' permissions /
saloutos	0:083111ae2a11	194	#define __IO volatile /!< Defines 'read / write' permissions /
saloutos	0:083111ae2a11	195
saloutos	0:083111ae2a11	196	/* following defines should be used for structure members */
saloutos	0:083111ae2a11	197	#define __IM volatile const /! Defines 'read only' structure member permissions /
saloutos	0:083111ae2a11	198	#define __OM volatile /! Defines 'write only' structure member permissions /
saloutos	0:083111ae2a11	199	#define __IOM volatile /! Defines 'read / write' structure member permissions /
saloutos	0:083111ae2a11	200
saloutos	0:083111ae2a11	201	/@} end of group Cortex_M23 /
saloutos	0:083111ae2a11	202
saloutos	0:083111ae2a11	203
saloutos	0:083111ae2a11	204
saloutos	0:083111ae2a11	205	/*******************************************************************************
saloutos	0:083111ae2a11	206	* Register Abstraction
saloutos	0:083111ae2a11	207	Core Register contain:
saloutos	0:083111ae2a11	208	- Core Register
saloutos	0:083111ae2a11	209	- Core NVIC Register
saloutos	0:083111ae2a11	210	- Core SCB Register
saloutos	0:083111ae2a11	211	- Core SysTick Register
saloutos	0:083111ae2a11	212	- Core Debug Register
saloutos	0:083111ae2a11	213	- Core MPU Register
saloutos	0:083111ae2a11	214	- Core SAU Register
saloutos	0:083111ae2a11	215	******************************************************************************/
saloutos	0:083111ae2a11	216	/**
saloutos	0:083111ae2a11	217	\defgroup CMSIS_core_register Defines and Type Definitions
saloutos	0:083111ae2a11	218	\brief Type definitions and defines for Cortex-M processor based devices.
saloutos	0:083111ae2a11	219	*/
saloutos	0:083111ae2a11	220
saloutos	0:083111ae2a11	221	/**
saloutos	0:083111ae2a11	222	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	223	\defgroup CMSIS_CORE Status and Control Registers
saloutos	0:083111ae2a11	224	\brief Core Register type definitions.
saloutos	0:083111ae2a11	225	@{
saloutos	0:083111ae2a11	226	*/
saloutos	0:083111ae2a11	227
saloutos	0:083111ae2a11	228	/**
saloutos	0:083111ae2a11	229	\brief Union type to access the Application Program Status Register (APSR).
saloutos	0:083111ae2a11	230	*/
saloutos	0:083111ae2a11	231	typedef union
saloutos	0:083111ae2a11	232	{
saloutos	0:083111ae2a11	233	struct
saloutos	0:083111ae2a11	234	{
saloutos	0:083111ae2a11	235	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
saloutos	0:083111ae2a11	236	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
saloutos	0:083111ae2a11	237	uint32_t C:1; /!< bit: 29 Carry condition code flag /
saloutos	0:083111ae2a11	238	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
saloutos	0:083111ae2a11	239	uint32_t N:1; /!< bit: 31 Negative condition code flag /
saloutos	0:083111ae2a11	240	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	241	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	242	} APSR_Type;
saloutos	0:083111ae2a11	243
saloutos	0:083111ae2a11	244	/* APSR Register Definitions */
saloutos	0:083111ae2a11	245	#define APSR_N_Pos 31U /!< APSR: N Position /
saloutos	0:083111ae2a11	246	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
saloutos	0:083111ae2a11	247
saloutos	0:083111ae2a11	248	#define APSR_Z_Pos 30U /!< APSR: Z Position /
saloutos	0:083111ae2a11	249	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
saloutos	0:083111ae2a11	250
saloutos	0:083111ae2a11	251	#define APSR_C_Pos 29U /!< APSR: C Position /
saloutos	0:083111ae2a11	252	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
saloutos	0:083111ae2a11	253
saloutos	0:083111ae2a11	254	#define APSR_V_Pos 28U /!< APSR: V Position /
saloutos	0:083111ae2a11	255	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
saloutos	0:083111ae2a11	256
saloutos	0:083111ae2a11	257
saloutos	0:083111ae2a11	258	/**
saloutos	0:083111ae2a11	259	\brief Union type to access the Interrupt Program Status Register (IPSR).
saloutos	0:083111ae2a11	260	*/
saloutos	0:083111ae2a11	261	typedef union
saloutos	0:083111ae2a11	262	{
saloutos	0:083111ae2a11	263	struct
saloutos	0:083111ae2a11	264	{
saloutos	0:083111ae2a11	265	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
saloutos	0:083111ae2a11	266	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
saloutos	0:083111ae2a11	267	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	268	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	269	} IPSR_Type;
saloutos	0:083111ae2a11	270
saloutos	0:083111ae2a11	271	/* IPSR Register Definitions */
saloutos	0:083111ae2a11	272	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
saloutos	0:083111ae2a11	273	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
saloutos	0:083111ae2a11	274
saloutos	0:083111ae2a11	275
saloutos	0:083111ae2a11	276	/**
saloutos	0:083111ae2a11	277	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
saloutos	0:083111ae2a11	278	*/
saloutos	0:083111ae2a11	279	typedef union
saloutos	0:083111ae2a11	280	{
saloutos	0:083111ae2a11	281	struct
saloutos	0:083111ae2a11	282	{
saloutos	0:083111ae2a11	283	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
saloutos	0:083111ae2a11	284	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
saloutos	0:083111ae2a11	285	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
saloutos	0:083111ae2a11	286	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
saloutos	0:083111ae2a11	287	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
saloutos	0:083111ae2a11	288	uint32_t C:1; /!< bit: 29 Carry condition code flag /
saloutos	0:083111ae2a11	289	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
saloutos	0:083111ae2a11	290	uint32_t N:1; /!< bit: 31 Negative condition code flag /
saloutos	0:083111ae2a11	291	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	292	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	293	} xPSR_Type;
saloutos	0:083111ae2a11	294
saloutos	0:083111ae2a11	295	/* xPSR Register Definitions */
saloutos	0:083111ae2a11	296	#define xPSR_N_Pos 31U /!< xPSR: N Position /
saloutos	0:083111ae2a11	297	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
saloutos	0:083111ae2a11	298
saloutos	0:083111ae2a11	299	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
saloutos	0:083111ae2a11	300	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
saloutos	0:083111ae2a11	301
saloutos	0:083111ae2a11	302	#define xPSR_C_Pos 29U /!< xPSR: C Position /
saloutos	0:083111ae2a11	303	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
saloutos	0:083111ae2a11	304
saloutos	0:083111ae2a11	305	#define xPSR_V_Pos 28U /!< xPSR: V Position /
saloutos	0:083111ae2a11	306	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
saloutos	0:083111ae2a11	307
saloutos	0:083111ae2a11	308	#define xPSR_T_Pos 24U /!< xPSR: T Position /
saloutos	0:083111ae2a11	309	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
saloutos	0:083111ae2a11	310
saloutos	0:083111ae2a11	311	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
saloutos	0:083111ae2a11	312	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
saloutos	0:083111ae2a11	313
saloutos	0:083111ae2a11	314
saloutos	0:083111ae2a11	315	/**
saloutos	0:083111ae2a11	316	\brief Union type to access the Control Registers (CONTROL).
saloutos	0:083111ae2a11	317	*/
saloutos	0:083111ae2a11	318	typedef union
saloutos	0:083111ae2a11	319	{
saloutos	0:083111ae2a11	320	struct
saloutos	0:083111ae2a11	321	{
saloutos	0:083111ae2a11	322	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
saloutos	0:083111ae2a11	323	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
saloutos	0:083111ae2a11	324	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
saloutos	0:083111ae2a11	325	} b; /!< Structure used for bit access /
saloutos	0:083111ae2a11	326	uint32_t w; /!< Type used for word access /
saloutos	0:083111ae2a11	327	} CONTROL_Type;
saloutos	0:083111ae2a11	328
saloutos	0:083111ae2a11	329	/* CONTROL Register Definitions */
saloutos	0:083111ae2a11	330	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
saloutos	0:083111ae2a11	331	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
saloutos	0:083111ae2a11	332
saloutos	0:083111ae2a11	333	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
saloutos	0:083111ae2a11	334	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
saloutos	0:083111ae2a11	335
saloutos	0:083111ae2a11	336	/@} end of group CMSIS_CORE /
saloutos	0:083111ae2a11	337
saloutos	0:083111ae2a11	338
saloutos	0:083111ae2a11	339	/**
saloutos	0:083111ae2a11	340	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	341	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
saloutos	0:083111ae2a11	342	\brief Type definitions for the NVIC Registers
saloutos	0:083111ae2a11	343	@{
saloutos	0:083111ae2a11	344	*/
saloutos	0:083111ae2a11	345
saloutos	0:083111ae2a11	346	/**
saloutos	0:083111ae2a11	347	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
saloutos	0:083111ae2a11	348	*/
saloutos	0:083111ae2a11	349	typedef struct
saloutos	0:083111ae2a11	350	{
saloutos	0:083111ae2a11	351	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
saloutos	0:083111ae2a11	352	uint32_t RESERVED0[16U];
saloutos	0:083111ae2a11	353	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
saloutos	0:083111ae2a11	354	uint32_t RSERVED1[16U];
saloutos	0:083111ae2a11	355	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
saloutos	0:083111ae2a11	356	uint32_t RESERVED2[16U];
saloutos	0:083111ae2a11	357	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
saloutos	0:083111ae2a11	358	uint32_t RESERVED3[16U];
saloutos	0:083111ae2a11	359	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
saloutos	0:083111ae2a11	360	uint32_t RESERVED4[16U];
saloutos	0:083111ae2a11	361	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
saloutos	0:083111ae2a11	362	uint32_t RESERVED5[16U];
saloutos	0:083111ae2a11	363	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
saloutos	0:083111ae2a11	364	} NVIC_Type;
saloutos	0:083111ae2a11	365
saloutos	0:083111ae2a11	366	/@} end of group CMSIS_NVIC /
saloutos	0:083111ae2a11	367
saloutos	0:083111ae2a11	368
saloutos	0:083111ae2a11	369	/**
saloutos	0:083111ae2a11	370	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	371	\defgroup CMSIS_SCB System Control Block (SCB)
saloutos	0:083111ae2a11	372	\brief Type definitions for the System Control Block Registers
saloutos	0:083111ae2a11	373	@{
saloutos	0:083111ae2a11	374	*/
saloutos	0:083111ae2a11	375
saloutos	0:083111ae2a11	376	/**
saloutos	0:083111ae2a11	377	\brief Structure type to access the System Control Block (SCB).
saloutos	0:083111ae2a11	378	*/
saloutos	0:083111ae2a11	379	typedef struct
saloutos	0:083111ae2a11	380	{
saloutos	0:083111ae2a11	381	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
saloutos	0:083111ae2a11	382	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
saloutos	0:083111ae2a11	383	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos	0:083111ae2a11	384	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
saloutos	0:083111ae2a11	385	#else
saloutos	0:083111ae2a11	386	uint32_t RESERVED0;
saloutos	0:083111ae2a11	387	#endif
saloutos	0:083111ae2a11	388	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
saloutos	0:083111ae2a11	389	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
saloutos	0:083111ae2a11	390	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
saloutos	0:083111ae2a11	391	uint32_t RESERVED1;
saloutos	0:083111ae2a11	392	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
saloutos	0:083111ae2a11	393	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
saloutos	0:083111ae2a11	394	} SCB_Type;
saloutos	0:083111ae2a11	395
saloutos	0:083111ae2a11	396	/* SCB CPUID Register Definitions */
saloutos	0:083111ae2a11	397	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
saloutos	0:083111ae2a11	398	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
saloutos	0:083111ae2a11	399
saloutos	0:083111ae2a11	400	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
saloutos	0:083111ae2a11	401	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
saloutos	0:083111ae2a11	402
saloutos	0:083111ae2a11	403	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
saloutos	0:083111ae2a11	404	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
saloutos	0:083111ae2a11	405
saloutos	0:083111ae2a11	406	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
saloutos	0:083111ae2a11	407	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
saloutos	0:083111ae2a11	408
saloutos	0:083111ae2a11	409	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
saloutos	0:083111ae2a11	410	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
saloutos	0:083111ae2a11	411
saloutos	0:083111ae2a11	412	/* SCB Interrupt Control State Register Definitions */
saloutos	0:083111ae2a11	413	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
saloutos	0:083111ae2a11	414	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
saloutos	0:083111ae2a11	415
saloutos	0:083111ae2a11	416	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
saloutos	0:083111ae2a11	417	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
saloutos	0:083111ae2a11	418
saloutos	0:083111ae2a11	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
saloutos	0:083111ae2a11	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
saloutos	0:083111ae2a11	421
saloutos	0:083111ae2a11	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
saloutos	0:083111ae2a11	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
saloutos	0:083111ae2a11	424
saloutos	0:083111ae2a11	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
saloutos	0:083111ae2a11	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
saloutos	0:083111ae2a11	427
saloutos	0:083111ae2a11	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
saloutos	0:083111ae2a11	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
saloutos	0:083111ae2a11	430
saloutos	0:083111ae2a11	431	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
saloutos	0:083111ae2a11	432	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
saloutos	0:083111ae2a11	433
saloutos	0:083111ae2a11	434	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
saloutos	0:083111ae2a11	435	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
saloutos	0:083111ae2a11	436
saloutos	0:083111ae2a11	437	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
saloutos	0:083111ae2a11	438	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
saloutos	0:083111ae2a11	439
saloutos	0:083111ae2a11	440	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
saloutos	0:083111ae2a11	441	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
saloutos	0:083111ae2a11	442
saloutos	0:083111ae2a11	443	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
saloutos	0:083111ae2a11	444	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
saloutos	0:083111ae2a11	445
saloutos	0:083111ae2a11	446	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
saloutos	0:083111ae2a11	447	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
saloutos	0:083111ae2a11	448
saloutos	0:083111ae2a11	449	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos	0:083111ae2a11	450	/* SCB Vector Table Offset Register Definitions */
saloutos	0:083111ae2a11	451	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
saloutos	0:083111ae2a11	452	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
saloutos	0:083111ae2a11	453	#endif
saloutos	0:083111ae2a11	454
saloutos	0:083111ae2a11	455	/* SCB Application Interrupt and Reset Control Register Definitions */
saloutos	0:083111ae2a11	456	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
saloutos	0:083111ae2a11	457	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
saloutos	0:083111ae2a11	458
saloutos	0:083111ae2a11	459	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
saloutos	0:083111ae2a11	460	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
saloutos	0:083111ae2a11	461
saloutos	0:083111ae2a11	462	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
saloutos	0:083111ae2a11	463	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
saloutos	0:083111ae2a11	464
saloutos	0:083111ae2a11	465	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
saloutos	0:083111ae2a11	466	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
saloutos	0:083111ae2a11	467
saloutos	0:083111ae2a11	468	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
saloutos	0:083111ae2a11	469	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
saloutos	0:083111ae2a11	470
saloutos	0:083111ae2a11	471	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
saloutos	0:083111ae2a11	472	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
saloutos	0:083111ae2a11	473
saloutos	0:083111ae2a11	474	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
saloutos	0:083111ae2a11	475	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
saloutos	0:083111ae2a11	476
saloutos	0:083111ae2a11	477	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
saloutos	0:083111ae2a11	478	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
saloutos	0:083111ae2a11	479
saloutos	0:083111ae2a11	480	/* SCB System Control Register Definitions */
saloutos	0:083111ae2a11	481	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
saloutos	0:083111ae2a11	482	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
saloutos	0:083111ae2a11	483
saloutos	0:083111ae2a11	484	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
saloutos	0:083111ae2a11	485	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
saloutos	0:083111ae2a11	486
saloutos	0:083111ae2a11	487	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
saloutos	0:083111ae2a11	488	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
saloutos	0:083111ae2a11	489
saloutos	0:083111ae2a11	490	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
saloutos	0:083111ae2a11	491	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
saloutos	0:083111ae2a11	492
saloutos	0:083111ae2a11	493	/* SCB Configuration Control Register Definitions */
saloutos	0:083111ae2a11	494	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
saloutos	0:083111ae2a11	495	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
saloutos	0:083111ae2a11	496
saloutos	0:083111ae2a11	497	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
saloutos	0:083111ae2a11	498	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
saloutos	0:083111ae2a11	499
saloutos	0:083111ae2a11	500	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
saloutos	0:083111ae2a11	501	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
saloutos	0:083111ae2a11	502
saloutos	0:083111ae2a11	503	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
saloutos	0:083111ae2a11	504	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
saloutos	0:083111ae2a11	505
saloutos	0:083111ae2a11	506	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
saloutos	0:083111ae2a11	507	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
saloutos	0:083111ae2a11	508
saloutos	0:083111ae2a11	509	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
saloutos	0:083111ae2a11	510	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
saloutos	0:083111ae2a11	511
saloutos	0:083111ae2a11	512	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
saloutos	0:083111ae2a11	513	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
saloutos	0:083111ae2a11	514
saloutos	0:083111ae2a11	515	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
saloutos	0:083111ae2a11	516	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
saloutos	0:083111ae2a11	517
saloutos	0:083111ae2a11	518	/* SCB System Handler Control and State Register Definitions */
saloutos	0:083111ae2a11	519	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
saloutos	0:083111ae2a11	520	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
saloutos	0:083111ae2a11	521
saloutos	0:083111ae2a11	522	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
saloutos	0:083111ae2a11	523	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
saloutos	0:083111ae2a11	524
saloutos	0:083111ae2a11	525	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
saloutos	0:083111ae2a11	526	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
saloutos	0:083111ae2a11	527
saloutos	0:083111ae2a11	528	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
saloutos	0:083111ae2a11	529	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
saloutos	0:083111ae2a11	530
saloutos	0:083111ae2a11	531	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
saloutos	0:083111ae2a11	532	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
saloutos	0:083111ae2a11	533
saloutos	0:083111ae2a11	534	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
saloutos	0:083111ae2a11	535	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
saloutos	0:083111ae2a11	536
saloutos	0:083111ae2a11	537	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
saloutos	0:083111ae2a11	538	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
saloutos	0:083111ae2a11	539
saloutos	0:083111ae2a11	540	/@} end of group CMSIS_SCB /
saloutos	0:083111ae2a11	541
saloutos	0:083111ae2a11	542
saloutos	0:083111ae2a11	543	/**
saloutos	0:083111ae2a11	544	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	545	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
saloutos	0:083111ae2a11	546	\brief Type definitions for the System Timer Registers.
saloutos	0:083111ae2a11	547	@{
saloutos	0:083111ae2a11	548	*/
saloutos	0:083111ae2a11	549
saloutos	0:083111ae2a11	550	/**
saloutos	0:083111ae2a11	551	\brief Structure type to access the System Timer (SysTick).
saloutos	0:083111ae2a11	552	*/
saloutos	0:083111ae2a11	553	typedef struct
saloutos	0:083111ae2a11	554	{
saloutos	0:083111ae2a11	555	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
saloutos	0:083111ae2a11	556	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
saloutos	0:083111ae2a11	557	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
saloutos	0:083111ae2a11	558	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
saloutos	0:083111ae2a11	559	} SysTick_Type;
saloutos	0:083111ae2a11	560
saloutos	0:083111ae2a11	561	/* SysTick Control / Status Register Definitions */
saloutos	0:083111ae2a11	562	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
saloutos	0:083111ae2a11	563	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
saloutos	0:083111ae2a11	564
saloutos	0:083111ae2a11	565	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
saloutos	0:083111ae2a11	566	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
saloutos	0:083111ae2a11	567
saloutos	0:083111ae2a11	568	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
saloutos	0:083111ae2a11	569	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
saloutos	0:083111ae2a11	570
saloutos	0:083111ae2a11	571	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
saloutos	0:083111ae2a11	572	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	573
saloutos	0:083111ae2a11	574	/* SysTick Reload Register Definitions */
saloutos	0:083111ae2a11	575	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
saloutos	0:083111ae2a11	576	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
saloutos	0:083111ae2a11	577
saloutos	0:083111ae2a11	578	/* SysTick Current Register Definitions */
saloutos	0:083111ae2a11	579	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
saloutos	0:083111ae2a11	580	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
saloutos	0:083111ae2a11	581
saloutos	0:083111ae2a11	582	/* SysTick Calibration Register Definitions */
saloutos	0:083111ae2a11	583	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
saloutos	0:083111ae2a11	584	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
saloutos	0:083111ae2a11	585
saloutos	0:083111ae2a11	586	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
saloutos	0:083111ae2a11	587	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
saloutos	0:083111ae2a11	588
saloutos	0:083111ae2a11	589	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
saloutos	0:083111ae2a11	590	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
saloutos	0:083111ae2a11	591
saloutos	0:083111ae2a11	592	/@} end of group CMSIS_SysTick /
saloutos	0:083111ae2a11	593
saloutos	0:083111ae2a11	594
saloutos	0:083111ae2a11	595	/**
saloutos	0:083111ae2a11	596	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	597	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
saloutos	0:083111ae2a11	598	\brief Type definitions for the Data Watchpoint and Trace (DWT)
saloutos	0:083111ae2a11	599	@{
saloutos	0:083111ae2a11	600	*/
saloutos	0:083111ae2a11	601
saloutos	0:083111ae2a11	602	/**
saloutos	0:083111ae2a11	603	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
saloutos	0:083111ae2a11	604	*/
saloutos	0:083111ae2a11	605	typedef struct
saloutos	0:083111ae2a11	606	{
saloutos	0:083111ae2a11	607	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
saloutos	0:083111ae2a11	608	uint32_t RESERVED0[6U];
saloutos	0:083111ae2a11	609	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
saloutos	0:083111ae2a11	610	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
saloutos	0:083111ae2a11	611	uint32_t RESERVED1[1U];
saloutos	0:083111ae2a11	612	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
saloutos	0:083111ae2a11	613	uint32_t RESERVED2[1U];
saloutos	0:083111ae2a11	614	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
saloutos	0:083111ae2a11	615	uint32_t RESERVED3[1U];
saloutos	0:083111ae2a11	616	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
saloutos	0:083111ae2a11	617	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	618	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
saloutos	0:083111ae2a11	619	uint32_t RESERVED5[1U];
saloutos	0:083111ae2a11	620	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
saloutos	0:083111ae2a11	621	uint32_t RESERVED6[1U];
saloutos	0:083111ae2a11	622	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
saloutos	0:083111ae2a11	623	uint32_t RESERVED7[1U];
saloutos	0:083111ae2a11	624	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
saloutos	0:083111ae2a11	625	uint32_t RESERVED8[1U];
saloutos	0:083111ae2a11	626	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
saloutos	0:083111ae2a11	627	uint32_t RESERVED9[1U];
saloutos	0:083111ae2a11	628	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
saloutos	0:083111ae2a11	629	uint32_t RESERVED10[1U];
saloutos	0:083111ae2a11	630	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
saloutos	0:083111ae2a11	631	uint32_t RESERVED11[1U];
saloutos	0:083111ae2a11	632	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
saloutos	0:083111ae2a11	633	uint32_t RESERVED12[1U];
saloutos	0:083111ae2a11	634	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
saloutos	0:083111ae2a11	635	uint32_t RESERVED13[1U];
saloutos	0:083111ae2a11	636	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
saloutos	0:083111ae2a11	637	uint32_t RESERVED14[1U];
saloutos	0:083111ae2a11	638	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
saloutos	0:083111ae2a11	639	uint32_t RESERVED15[1U];
saloutos	0:083111ae2a11	640	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
saloutos	0:083111ae2a11	641	uint32_t RESERVED16[1U];
saloutos	0:083111ae2a11	642	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
saloutos	0:083111ae2a11	643	uint32_t RESERVED17[1U];
saloutos	0:083111ae2a11	644	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
saloutos	0:083111ae2a11	645	uint32_t RESERVED18[1U];
saloutos	0:083111ae2a11	646	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
saloutos	0:083111ae2a11	647	uint32_t RESERVED19[1U];
saloutos	0:083111ae2a11	648	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
saloutos	0:083111ae2a11	649	uint32_t RESERVED20[1U];
saloutos	0:083111ae2a11	650	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
saloutos	0:083111ae2a11	651	uint32_t RESERVED21[1U];
saloutos	0:083111ae2a11	652	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
saloutos	0:083111ae2a11	653	uint32_t RESERVED22[1U];
saloutos	0:083111ae2a11	654	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
saloutos	0:083111ae2a11	655	uint32_t RESERVED23[1U];
saloutos	0:083111ae2a11	656	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
saloutos	0:083111ae2a11	657	uint32_t RESERVED24[1U];
saloutos	0:083111ae2a11	658	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
saloutos	0:083111ae2a11	659	uint32_t RESERVED25[1U];
saloutos	0:083111ae2a11	660	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
saloutos	0:083111ae2a11	661	uint32_t RESERVED26[1U];
saloutos	0:083111ae2a11	662	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
saloutos	0:083111ae2a11	663	uint32_t RESERVED27[1U];
saloutos	0:083111ae2a11	664	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
saloutos	0:083111ae2a11	665	uint32_t RESERVED28[1U];
saloutos	0:083111ae2a11	666	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
saloutos	0:083111ae2a11	667	uint32_t RESERVED29[1U];
saloutos	0:083111ae2a11	668	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
saloutos	0:083111ae2a11	669	uint32_t RESERVED30[1U];
saloutos	0:083111ae2a11	670	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
saloutos	0:083111ae2a11	671	uint32_t RESERVED31[1U];
saloutos	0:083111ae2a11	672	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
saloutos	0:083111ae2a11	673	} DWT_Type;
saloutos	0:083111ae2a11	674
saloutos	0:083111ae2a11	675	/* DWT Control Register Definitions */
saloutos	0:083111ae2a11	676	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
saloutos	0:083111ae2a11	677	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
saloutos	0:083111ae2a11	678
saloutos	0:083111ae2a11	679	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
saloutos	0:083111ae2a11	680	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
saloutos	0:083111ae2a11	681
saloutos	0:083111ae2a11	682	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
saloutos	0:083111ae2a11	683	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
saloutos	0:083111ae2a11	684
saloutos	0:083111ae2a11	685	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
saloutos	0:083111ae2a11	686	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
saloutos	0:083111ae2a11	687
saloutos	0:083111ae2a11	688	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
saloutos	0:083111ae2a11	689	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
saloutos	0:083111ae2a11	690
saloutos	0:083111ae2a11	691	/* DWT Comparator Function Register Definitions */
saloutos	0:083111ae2a11	692	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
saloutos	0:083111ae2a11	693	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
saloutos	0:083111ae2a11	694
saloutos	0:083111ae2a11	695	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
saloutos	0:083111ae2a11	696	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
saloutos	0:083111ae2a11	697
saloutos	0:083111ae2a11	698	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
saloutos	0:083111ae2a11	699	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
saloutos	0:083111ae2a11	700
saloutos	0:083111ae2a11	701	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
saloutos	0:083111ae2a11	702	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
saloutos	0:083111ae2a11	703
saloutos	0:083111ae2a11	704	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
saloutos	0:083111ae2a11	705	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
saloutos	0:083111ae2a11	706
saloutos	0:083111ae2a11	707	/@}/ /* end of group CMSIS_DWT */
saloutos	0:083111ae2a11	708
saloutos	0:083111ae2a11	709
saloutos	0:083111ae2a11	710	/**
saloutos	0:083111ae2a11	711	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	712	\defgroup CMSIS_TPI Trace Port Interface (TPI)
saloutos	0:083111ae2a11	713	\brief Type definitions for the Trace Port Interface (TPI)
saloutos	0:083111ae2a11	714	@{
saloutos	0:083111ae2a11	715	*/
saloutos	0:083111ae2a11	716
saloutos	0:083111ae2a11	717	/**
saloutos	0:083111ae2a11	718	\brief Structure type to access the Trace Port Interface Register (TPI).
saloutos	0:083111ae2a11	719	*/
saloutos	0:083111ae2a11	720	typedef struct
saloutos	0:083111ae2a11	721	{
saloutos	0:083111ae2a11	722	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
saloutos	0:083111ae2a11	723	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
saloutos	0:083111ae2a11	724	uint32_t RESERVED0[2U];
saloutos	0:083111ae2a11	725	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
saloutos	0:083111ae2a11	726	uint32_t RESERVED1[55U];
saloutos	0:083111ae2a11	727	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
saloutos	0:083111ae2a11	728	uint32_t RESERVED2[131U];
saloutos	0:083111ae2a11	729	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
saloutos	0:083111ae2a11	730	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
saloutos	0:083111ae2a11	731	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
saloutos	0:083111ae2a11	732	uint32_t RESERVED3[759U];
saloutos	0:083111ae2a11	733	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
saloutos	0:083111ae2a11	734	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
saloutos	0:083111ae2a11	735	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
saloutos	0:083111ae2a11	736	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	737	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
saloutos	0:083111ae2a11	738	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
saloutos	0:083111ae2a11	739	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
saloutos	0:083111ae2a11	740	uint32_t RESERVED5[39U];
saloutos	0:083111ae2a11	741	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
saloutos	0:083111ae2a11	742	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
saloutos	0:083111ae2a11	743	uint32_t RESERVED7[8U];
saloutos	0:083111ae2a11	744	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
saloutos	0:083111ae2a11	745	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
saloutos	0:083111ae2a11	746	} TPI_Type;
saloutos	0:083111ae2a11	747
saloutos	0:083111ae2a11	748	/* TPI Asynchronous Clock Prescaler Register Definitions */
saloutos	0:083111ae2a11	749	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
saloutos	0:083111ae2a11	750	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
saloutos	0:083111ae2a11	751
saloutos	0:083111ae2a11	752	/* TPI Selected Pin Protocol Register Definitions */
saloutos	0:083111ae2a11	753	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
saloutos	0:083111ae2a11	754	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
saloutos	0:083111ae2a11	755
saloutos	0:083111ae2a11	756	/* TPI Formatter and Flush Status Register Definitions */
saloutos	0:083111ae2a11	757	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
saloutos	0:083111ae2a11	758	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
saloutos	0:083111ae2a11	759
saloutos	0:083111ae2a11	760	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
saloutos	0:083111ae2a11	761	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
saloutos	0:083111ae2a11	762
saloutos	0:083111ae2a11	763	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
saloutos	0:083111ae2a11	764	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
saloutos	0:083111ae2a11	765
saloutos	0:083111ae2a11	766	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
saloutos	0:083111ae2a11	767	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
saloutos	0:083111ae2a11	768
saloutos	0:083111ae2a11	769	/* TPI Formatter and Flush Control Register Definitions */
saloutos	0:083111ae2a11	770	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
saloutos	0:083111ae2a11	771	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
saloutos	0:083111ae2a11	772
saloutos	0:083111ae2a11	773	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
saloutos	0:083111ae2a11	774	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
saloutos	0:083111ae2a11	775
saloutos	0:083111ae2a11	776	/* TPI TRIGGER Register Definitions */
saloutos	0:083111ae2a11	777	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
saloutos	0:083111ae2a11	778	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
saloutos	0:083111ae2a11	779
saloutos	0:083111ae2a11	780	/* TPI Integration ETM Data Register Definitions (FIFO0) */
saloutos	0:083111ae2a11	781	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
saloutos	0:083111ae2a11	782	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
saloutos	0:083111ae2a11	783
saloutos	0:083111ae2a11	784	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
saloutos	0:083111ae2a11	785	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
saloutos	0:083111ae2a11	786
saloutos	0:083111ae2a11	787	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
saloutos	0:083111ae2a11	788	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
saloutos	0:083111ae2a11	789
saloutos	0:083111ae2a11	790	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
saloutos	0:083111ae2a11	791	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
saloutos	0:083111ae2a11	792
saloutos	0:083111ae2a11	793	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
saloutos	0:083111ae2a11	794	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
saloutos	0:083111ae2a11	795
saloutos	0:083111ae2a11	796	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
saloutos	0:083111ae2a11	797	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
saloutos	0:083111ae2a11	798
saloutos	0:083111ae2a11	799	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
saloutos	0:083111ae2a11	800	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
saloutos	0:083111ae2a11	801
saloutos	0:083111ae2a11	802	/* TPI ITATBCTR2 Register Definitions */
saloutos	0:083111ae2a11	803	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
saloutos	0:083111ae2a11	804	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
saloutos	0:083111ae2a11	805
saloutos	0:083111ae2a11	806	/* TPI Integration ITM Data Register Definitions (FIFO1) */
saloutos	0:083111ae2a11	807	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
saloutos	0:083111ae2a11	808	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
saloutos	0:083111ae2a11	809
saloutos	0:083111ae2a11	810	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
saloutos	0:083111ae2a11	811	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
saloutos	0:083111ae2a11	812
saloutos	0:083111ae2a11	813	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
saloutos	0:083111ae2a11	814	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
saloutos	0:083111ae2a11	815
saloutos	0:083111ae2a11	816	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
saloutos	0:083111ae2a11	817	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
saloutos	0:083111ae2a11	818
saloutos	0:083111ae2a11	819	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
saloutos	0:083111ae2a11	820	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
saloutos	0:083111ae2a11	821
saloutos	0:083111ae2a11	822	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
saloutos	0:083111ae2a11	823	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
saloutos	0:083111ae2a11	824
saloutos	0:083111ae2a11	825	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
saloutos	0:083111ae2a11	826	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
saloutos	0:083111ae2a11	827
saloutos	0:083111ae2a11	828	/* TPI ITATBCTR0 Register Definitions */
saloutos	0:083111ae2a11	829	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
saloutos	0:083111ae2a11	830	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
saloutos	0:083111ae2a11	831
saloutos	0:083111ae2a11	832	/* TPI Integration Mode Control Register Definitions */
saloutos	0:083111ae2a11	833	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
saloutos	0:083111ae2a11	834	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
saloutos	0:083111ae2a11	835
saloutos	0:083111ae2a11	836	/* TPI DEVID Register Definitions */
saloutos	0:083111ae2a11	837	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
saloutos	0:083111ae2a11	838	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
saloutos	0:083111ae2a11	839
saloutos	0:083111ae2a11	840	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
saloutos	0:083111ae2a11	841	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
saloutos	0:083111ae2a11	842
saloutos	0:083111ae2a11	843	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
saloutos	0:083111ae2a11	844	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
saloutos	0:083111ae2a11	845
saloutos	0:083111ae2a11	846	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
saloutos	0:083111ae2a11	847	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
saloutos	0:083111ae2a11	848
saloutos	0:083111ae2a11	849	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
saloutos	0:083111ae2a11	850	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
saloutos	0:083111ae2a11	851
saloutos	0:083111ae2a11	852	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
saloutos	0:083111ae2a11	853	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
saloutos	0:083111ae2a11	854
saloutos	0:083111ae2a11	855	/* TPI DEVTYPE Register Definitions */
saloutos	0:083111ae2a11	856	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
saloutos	0:083111ae2a11	857	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
saloutos	0:083111ae2a11	858
saloutos	0:083111ae2a11	859	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
saloutos	0:083111ae2a11	860	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
saloutos	0:083111ae2a11	861
saloutos	0:083111ae2a11	862	/@}/ /* end of group CMSIS_TPI */
saloutos	0:083111ae2a11	863
saloutos	0:083111ae2a11	864
saloutos	0:083111ae2a11	865	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	866	/**
saloutos	0:083111ae2a11	867	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	868	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
saloutos	0:083111ae2a11	869	\brief Type definitions for the Memory Protection Unit (MPU)
saloutos	0:083111ae2a11	870	@{
saloutos	0:083111ae2a11	871	*/
saloutos	0:083111ae2a11	872
saloutos	0:083111ae2a11	873	/**
saloutos	0:083111ae2a11	874	\brief Structure type to access the Memory Protection Unit (MPU).
saloutos	0:083111ae2a11	875	*/
saloutos	0:083111ae2a11	876	typedef struct
saloutos	0:083111ae2a11	877	{
saloutos	0:083111ae2a11	878	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
saloutos	0:083111ae2a11	879	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
saloutos	0:083111ae2a11	880	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
saloutos	0:083111ae2a11	881	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
saloutos	0:083111ae2a11	882	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
saloutos	0:083111ae2a11	883	uint32_t RESERVED0[7U];
saloutos	0:083111ae2a11	884	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
saloutos	0:083111ae2a11	885	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
saloutos	0:083111ae2a11	886	} MPU_Type;
saloutos	0:083111ae2a11	887
saloutos	0:083111ae2a11	888	/* MPU Type Register Definitions */
saloutos	0:083111ae2a11	889	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
saloutos	0:083111ae2a11	890	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
saloutos	0:083111ae2a11	891
saloutos	0:083111ae2a11	892	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
saloutos	0:083111ae2a11	893	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
saloutos	0:083111ae2a11	894
saloutos	0:083111ae2a11	895	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
saloutos	0:083111ae2a11	896	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
saloutos	0:083111ae2a11	897
saloutos	0:083111ae2a11	898	/* MPU Control Register Definitions */
saloutos	0:083111ae2a11	899	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
saloutos	0:083111ae2a11	900	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
saloutos	0:083111ae2a11	901
saloutos	0:083111ae2a11	902	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
saloutos	0:083111ae2a11	903	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
saloutos	0:083111ae2a11	904
saloutos	0:083111ae2a11	905	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
saloutos	0:083111ae2a11	906	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	907
saloutos	0:083111ae2a11	908	/* MPU Region Number Register Definitions */
saloutos	0:083111ae2a11	909	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
saloutos	0:083111ae2a11	910	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
saloutos	0:083111ae2a11	911
saloutos	0:083111ae2a11	912	/* MPU Region Base Address Register Definitions */
saloutos	0:083111ae2a11	913	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
saloutos	0:083111ae2a11	914	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
saloutos	0:083111ae2a11	915
saloutos	0:083111ae2a11	916	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
saloutos	0:083111ae2a11	917	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
saloutos	0:083111ae2a11	918
saloutos	0:083111ae2a11	919	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
saloutos	0:083111ae2a11	920	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
saloutos	0:083111ae2a11	921
saloutos	0:083111ae2a11	922	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
saloutos	0:083111ae2a11	923	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
saloutos	0:083111ae2a11	924
saloutos	0:083111ae2a11	925	/* MPU Region Limit Address Register Definitions */
saloutos	0:083111ae2a11	926	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
saloutos	0:083111ae2a11	927	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
saloutos	0:083111ae2a11	928
saloutos	0:083111ae2a11	929	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
saloutos	0:083111ae2a11	930	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
saloutos	0:083111ae2a11	931
saloutos	0:083111ae2a11	932	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
saloutos	0:083111ae2a11	933	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
saloutos	0:083111ae2a11	934
saloutos	0:083111ae2a11	935	/* MPU Memory Attribute Indirection Register 0 Definitions */
saloutos	0:083111ae2a11	936	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
saloutos	0:083111ae2a11	937	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
saloutos	0:083111ae2a11	938
saloutos	0:083111ae2a11	939	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
saloutos	0:083111ae2a11	940	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
saloutos	0:083111ae2a11	941
saloutos	0:083111ae2a11	942	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
saloutos	0:083111ae2a11	943	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
saloutos	0:083111ae2a11	944
saloutos	0:083111ae2a11	945	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
saloutos	0:083111ae2a11	946	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
saloutos	0:083111ae2a11	947
saloutos	0:083111ae2a11	948	/* MPU Memory Attribute Indirection Register 1 Definitions */
saloutos	0:083111ae2a11	949	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
saloutos	0:083111ae2a11	950	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
saloutos	0:083111ae2a11	951
saloutos	0:083111ae2a11	952	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
saloutos	0:083111ae2a11	953	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
saloutos	0:083111ae2a11	954
saloutos	0:083111ae2a11	955	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
saloutos	0:083111ae2a11	956	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
saloutos	0:083111ae2a11	957
saloutos	0:083111ae2a11	958	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
saloutos	0:083111ae2a11	959	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
saloutos	0:083111ae2a11	960
saloutos	0:083111ae2a11	961	/@} end of group CMSIS_MPU /
saloutos	0:083111ae2a11	962	#endif
saloutos	0:083111ae2a11	963
saloutos	0:083111ae2a11	964
saloutos	0:083111ae2a11	965	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	966	/**
saloutos	0:083111ae2a11	967	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	968	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
saloutos	0:083111ae2a11	969	\brief Type definitions for the Security Attribution Unit (SAU)
saloutos	0:083111ae2a11	970	@{
saloutos	0:083111ae2a11	971	*/
saloutos	0:083111ae2a11	972
saloutos	0:083111ae2a11	973	/**
saloutos	0:083111ae2a11	974	\brief Structure type to access the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	975	*/
saloutos	0:083111ae2a11	976	typedef struct
saloutos	0:083111ae2a11	977	{
saloutos	0:083111ae2a11	978	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
saloutos	0:083111ae2a11	979	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
saloutos	0:083111ae2a11	980	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
saloutos	0:083111ae2a11	981	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
saloutos	0:083111ae2a11	982	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
saloutos	0:083111ae2a11	983	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
saloutos	0:083111ae2a11	984	#endif
saloutos	0:083111ae2a11	985	} SAU_Type;
saloutos	0:083111ae2a11	986
saloutos	0:083111ae2a11	987	/* SAU Control Register Definitions */
saloutos	0:083111ae2a11	988	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
saloutos	0:083111ae2a11	989	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
saloutos	0:083111ae2a11	990
saloutos	0:083111ae2a11	991	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
saloutos	0:083111ae2a11	992	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
saloutos	0:083111ae2a11	993
saloutos	0:083111ae2a11	994	/* SAU Type Register Definitions */
saloutos	0:083111ae2a11	995	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
saloutos	0:083111ae2a11	996	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
saloutos	0:083111ae2a11	997
saloutos	0:083111ae2a11	998	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
saloutos	0:083111ae2a11	999	/* SAU Region Number Register Definitions */
saloutos	0:083111ae2a11	1000	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
saloutos	0:083111ae2a11	1001	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
saloutos	0:083111ae2a11	1002
saloutos	0:083111ae2a11	1003	/* SAU Region Base Address Register Definitions */
saloutos	0:083111ae2a11	1004	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
saloutos	0:083111ae2a11	1005	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
saloutos	0:083111ae2a11	1006
saloutos	0:083111ae2a11	1007	/* SAU Region Limit Address Register Definitions */
saloutos	0:083111ae2a11	1008	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
saloutos	0:083111ae2a11	1009	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
saloutos	0:083111ae2a11	1010
saloutos	0:083111ae2a11	1011	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
saloutos	0:083111ae2a11	1012	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
saloutos	0:083111ae2a11	1013
saloutos	0:083111ae2a11	1014	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
saloutos	0:083111ae2a11	1015	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
saloutos	0:083111ae2a11	1016
saloutos	0:083111ae2a11	1017	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
saloutos	0:083111ae2a11	1018
saloutos	0:083111ae2a11	1019	/@} end of group CMSIS_SAU /
saloutos	0:083111ae2a11	1020	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1021
saloutos	0:083111ae2a11	1022
saloutos	0:083111ae2a11	1023	/**
saloutos	0:083111ae2a11	1024	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1025	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
saloutos	0:083111ae2a11	1026	\brief Type definitions for the Core Debug Registers
saloutos	0:083111ae2a11	1027	@{
saloutos	0:083111ae2a11	1028	*/
saloutos	0:083111ae2a11	1029
saloutos	0:083111ae2a11	1030	/**
saloutos	0:083111ae2a11	1031	\brief Structure type to access the Core Debug Register (CoreDebug).
saloutos	0:083111ae2a11	1032	*/
saloutos	0:083111ae2a11	1033	typedef struct
saloutos	0:083111ae2a11	1034	{
saloutos	0:083111ae2a11	1035	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
saloutos	0:083111ae2a11	1036	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
saloutos	0:083111ae2a11	1037	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
saloutos	0:083111ae2a11	1038	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
saloutos	0:083111ae2a11	1039	uint32_t RESERVED4[1U];
saloutos	0:083111ae2a11	1040	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
saloutos	0:083111ae2a11	1041	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
saloutos	0:083111ae2a11	1042	} CoreDebug_Type;
saloutos	0:083111ae2a11	1043
saloutos	0:083111ae2a11	1044	/* Debug Halting Control and Status Register Definitions */
saloutos	0:083111ae2a11	1045	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
saloutos	0:083111ae2a11	1046	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
saloutos	0:083111ae2a11	1047
saloutos	0:083111ae2a11	1048	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
saloutos	0:083111ae2a11	1049	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
saloutos	0:083111ae2a11	1050
saloutos	0:083111ae2a11	1051	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
saloutos	0:083111ae2a11	1052	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
saloutos	0:083111ae2a11	1053
saloutos	0:083111ae2a11	1054	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
saloutos	0:083111ae2a11	1055	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
saloutos	0:083111ae2a11	1056
saloutos	0:083111ae2a11	1057	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
saloutos	0:083111ae2a11	1058	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
saloutos	0:083111ae2a11	1059
saloutos	0:083111ae2a11	1060	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
saloutos	0:083111ae2a11	1061	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
saloutos	0:083111ae2a11	1062
saloutos	0:083111ae2a11	1063	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
saloutos	0:083111ae2a11	1064	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
saloutos	0:083111ae2a11	1065
saloutos	0:083111ae2a11	1066	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
saloutos	0:083111ae2a11	1067	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
saloutos	0:083111ae2a11	1068
saloutos	0:083111ae2a11	1069	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
saloutos	0:083111ae2a11	1070	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
saloutos	0:083111ae2a11	1071
saloutos	0:083111ae2a11	1072	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
saloutos	0:083111ae2a11	1073	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
saloutos	0:083111ae2a11	1074
saloutos	0:083111ae2a11	1075	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
saloutos	0:083111ae2a11	1076	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
saloutos	0:083111ae2a11	1077
saloutos	0:083111ae2a11	1078	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
saloutos	0:083111ae2a11	1079	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
saloutos	0:083111ae2a11	1080
saloutos	0:083111ae2a11	1081	/* Debug Core Register Selector Register Definitions */
saloutos	0:083111ae2a11	1082	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
saloutos	0:083111ae2a11	1083	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
saloutos	0:083111ae2a11	1084
saloutos	0:083111ae2a11	1085	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
saloutos	0:083111ae2a11	1086	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
saloutos	0:083111ae2a11	1087
saloutos	0:083111ae2a11	1088	/* Debug Exception and Monitor Control Register */
saloutos	0:083111ae2a11	1089	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
saloutos	0:083111ae2a11	1090	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
saloutos	0:083111ae2a11	1091
saloutos	0:083111ae2a11	1092	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
saloutos	0:083111ae2a11	1093	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
saloutos	0:083111ae2a11	1094
saloutos	0:083111ae2a11	1095	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
saloutos	0:083111ae2a11	1096	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
saloutos	0:083111ae2a11	1097
saloutos	0:083111ae2a11	1098	/* Debug Authentication Control Register Definitions */
saloutos	0:083111ae2a11	1099	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
saloutos	0:083111ae2a11	1100	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
saloutos	0:083111ae2a11	1101
saloutos	0:083111ae2a11	1102	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
saloutos	0:083111ae2a11	1103	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
saloutos	0:083111ae2a11	1104
saloutos	0:083111ae2a11	1105	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
saloutos	0:083111ae2a11	1106	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
saloutos	0:083111ae2a11	1107
saloutos	0:083111ae2a11	1108	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
saloutos	0:083111ae2a11	1109	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
saloutos	0:083111ae2a11	1110
saloutos	0:083111ae2a11	1111	/* Debug Security Control and Status Register Definitions */
saloutos	0:083111ae2a11	1112	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
saloutos	0:083111ae2a11	1113	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
saloutos	0:083111ae2a11	1114
saloutos	0:083111ae2a11	1115	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
saloutos	0:083111ae2a11	1116	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
saloutos	0:083111ae2a11	1117
saloutos	0:083111ae2a11	1118	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
saloutos	0:083111ae2a11	1119	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
saloutos	0:083111ae2a11	1120
saloutos	0:083111ae2a11	1121	/@} end of group CMSIS_CoreDebug /
saloutos	0:083111ae2a11	1122
saloutos	0:083111ae2a11	1123
saloutos	0:083111ae2a11	1124	/**
saloutos	0:083111ae2a11	1125	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1126	\defgroup CMSIS_core_bitfield Core register bit field macros
saloutos	0:083111ae2a11	1127	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
saloutos	0:083111ae2a11	1128	@{
saloutos	0:083111ae2a11	1129	*/
saloutos	0:083111ae2a11	1130
saloutos	0:083111ae2a11	1131	/**
saloutos	0:083111ae2a11	1132	\brief Mask and shift a bit field value for use in a register bit range.
saloutos	0:083111ae2a11	1133	\param[in] field Name of the register bit field.
saloutos	0:083111ae2a11	1134	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
saloutos	0:083111ae2a11	1135	\return Masked and shifted value.
saloutos	0:083111ae2a11	1136	*/
saloutos	0:083111ae2a11	1137	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
saloutos	0:083111ae2a11	1138
saloutos	0:083111ae2a11	1139	/**
saloutos	0:083111ae2a11	1140	\brief Mask and shift a register value to extract a bit filed value.
saloutos	0:083111ae2a11	1141	\param[in] field Name of the register bit field.
saloutos	0:083111ae2a11	1142	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
saloutos	0:083111ae2a11	1143	\return Masked and shifted bit field value.
saloutos	0:083111ae2a11	1144	*/
saloutos	0:083111ae2a11	1145	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
saloutos	0:083111ae2a11	1146
saloutos	0:083111ae2a11	1147	/@} end of group CMSIS_core_bitfield /
saloutos	0:083111ae2a11	1148
saloutos	0:083111ae2a11	1149
saloutos	0:083111ae2a11	1150	/**
saloutos	0:083111ae2a11	1151	\ingroup CMSIS_core_register
saloutos	0:083111ae2a11	1152	\defgroup CMSIS_core_base Core Definitions
saloutos	0:083111ae2a11	1153	\brief Definitions for base addresses, unions, and structures.
saloutos	0:083111ae2a11	1154	@{
saloutos	0:083111ae2a11	1155	*/
saloutos	0:083111ae2a11	1156
saloutos	0:083111ae2a11	1157	/* Memory mapping of Core Hardware */
saloutos	0:083111ae2a11	1158	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
saloutos	0:083111ae2a11	1159	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
saloutos	0:083111ae2a11	1160	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
saloutos	0:083111ae2a11	1161	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
saloutos	0:083111ae2a11	1162	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
saloutos	0:083111ae2a11	1163	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
saloutos	0:083111ae2a11	1164	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
saloutos	0:083111ae2a11	1165
saloutos	0:083111ae2a11	1166
saloutos	0:083111ae2a11	1167	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
saloutos	0:083111ae2a11	1168	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
saloutos	0:083111ae2a11	1169	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
saloutos	0:083111ae2a11	1170	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
saloutos	0:083111ae2a11	1171	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
saloutos	0:083111ae2a11	1172	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
saloutos	0:083111ae2a11	1173
saloutos	0:083111ae2a11	1174	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	1175	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
saloutos	0:083111ae2a11	1176	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
saloutos	0:083111ae2a11	1177	#endif
saloutos	0:083111ae2a11	1178
saloutos	0:083111ae2a11	1179	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1180	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
saloutos	0:083111ae2a11	1181	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
saloutos	0:083111ae2a11	1182	#endif
saloutos	0:083111ae2a11	1183
saloutos	0:083111ae2a11	1184	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1185	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
saloutos	0:083111ae2a11	1186	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
saloutos	0:083111ae2a11	1187	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
saloutos	0:083111ae2a11	1188	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
saloutos	0:083111ae2a11	1189	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
saloutos	0:083111ae2a11	1190
saloutos	0:083111ae2a11	1191	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	1192	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	1193	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	1194	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
saloutos	0:083111ae2a11	1195
saloutos	0:083111ae2a11	1196	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
saloutos	0:083111ae2a11	1197	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
saloutos	0:083111ae2a11	1198	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
saloutos	0:083111ae2a11	1199	#endif
saloutos	0:083111ae2a11	1200
saloutos	0:083111ae2a11	1201	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1202	/@} /
saloutos	0:083111ae2a11	1203
saloutos	0:083111ae2a11	1204
saloutos	0:083111ae2a11	1205
saloutos	0:083111ae2a11	1206	/*******************************************************************************
saloutos	0:083111ae2a11	1207	* Hardware Abstraction Layer
saloutos	0:083111ae2a11	1208	Core Function Interface contains:
saloutos	0:083111ae2a11	1209	- Core NVIC Functions
saloutos	0:083111ae2a11	1210	- Core SysTick Functions
saloutos	0:083111ae2a11	1211	- Core Register Access Functions
saloutos	0:083111ae2a11	1212	******************************************************************************/
saloutos	0:083111ae2a11	1213	/**
saloutos	0:083111ae2a11	1214	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
saloutos	0:083111ae2a11	1215	*/
saloutos	0:083111ae2a11	1216
saloutos	0:083111ae2a11	1217
saloutos	0:083111ae2a11	1218
saloutos	0:083111ae2a11	1219	/* ########################## NVIC functions #################################### */
saloutos	0:083111ae2a11	1220	/**
saloutos	0:083111ae2a11	1221	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	1222	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
saloutos	0:083111ae2a11	1223	\brief Functions that manage interrupts and exceptions via the NVIC.
saloutos	0:083111ae2a11	1224	@{
saloutos	0:083111ae2a11	1225	*/
saloutos	0:083111ae2a11	1226
saloutos	0:083111ae2a11	1227	#ifdef CMSIS_NVIC_VIRTUAL
saloutos	0:083111ae2a11	1228	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	1229	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
saloutos	0:083111ae2a11	1230	#endif
saloutos	0:083111ae2a11	1231	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	1232	#else
saloutos	0:083111ae2a11	1233	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
saloutos	0:083111ae2a11	1234	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
saloutos	0:083111ae2a11	1235	#define NVIC_EnableIRQ __NVIC_EnableIRQ
saloutos	0:083111ae2a11	1236	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
saloutos	0:083111ae2a11	1237	#define NVIC_DisableIRQ __NVIC_DisableIRQ
saloutos	0:083111ae2a11	1238	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
saloutos	0:083111ae2a11	1239	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
saloutos	0:083111ae2a11	1240	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
saloutos	0:083111ae2a11	1241	#define NVIC_GetActive __NVIC_GetActive
saloutos	0:083111ae2a11	1242	#define NVIC_SetPriority __NVIC_SetPriority
saloutos	0:083111ae2a11	1243	#define NVIC_GetPriority __NVIC_GetPriority
saloutos	0:083111ae2a11	1244	#define NVIC_SystemReset __NVIC_SystemReset
saloutos	0:083111ae2a11	1245	#endif /* CMSIS_NVIC_VIRTUAL */
saloutos	0:083111ae2a11	1246
saloutos	0:083111ae2a11	1247	#ifdef CMSIS_VECTAB_VIRTUAL
saloutos	0:083111ae2a11	1248	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	1249	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
saloutos	0:083111ae2a11	1250	#endif
saloutos	0:083111ae2a11	1251	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
saloutos	0:083111ae2a11	1252	#else
saloutos	0:083111ae2a11	1253	#define NVIC_SetVector __NVIC_SetVector
saloutos	0:083111ae2a11	1254	#define NVIC_GetVector __NVIC_GetVector
saloutos	0:083111ae2a11	1255	#endif /* (CMSIS_VECTAB_VIRTUAL) */
saloutos	0:083111ae2a11	1256
saloutos	0:083111ae2a11	1257	#define NVIC_USER_IRQ_OFFSET 16
saloutos	0:083111ae2a11	1258
saloutos	0:083111ae2a11	1259
saloutos	0:083111ae2a11	1260	/* Interrupt Priorities are WORD accessible only under ARMv6M */
saloutos	0:083111ae2a11	1261	/* The following MACROS handle generation of the register offset and byte masks */
saloutos	0:083111ae2a11	1262	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
saloutos	0:083111ae2a11	1263	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
saloutos	0:083111ae2a11	1264	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
saloutos	0:083111ae2a11	1265
saloutos	0:083111ae2a11	1266
saloutos	0:083111ae2a11	1267	/**
saloutos	0:083111ae2a11	1268	\brief Enable Interrupt
saloutos	0:083111ae2a11	1269	\details Enables a device specific interrupt in the NVIC interrupt controller.
saloutos	0:083111ae2a11	1270	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1271	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1272	*/
saloutos	0:083111ae2a11	1273	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1274	{
saloutos	0:083111ae2a11	1275	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1276	{
saloutos	0:083111ae2a11	1277	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1278	}
saloutos	0:083111ae2a11	1279	}
saloutos	0:083111ae2a11	1280
saloutos	0:083111ae2a11	1281
saloutos	0:083111ae2a11	1282	/**
saloutos	0:083111ae2a11	1283	\brief Get Interrupt Enable status
saloutos	0:083111ae2a11	1284	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
saloutos	0:083111ae2a11	1285	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1286	\return 0 Interrupt is not enabled.
saloutos	0:083111ae2a11	1287	\return 1 Interrupt is enabled.
saloutos	0:083111ae2a11	1288	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1289	*/
saloutos	0:083111ae2a11	1290	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1291	{
saloutos	0:083111ae2a11	1292	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1293	{
saloutos	0:083111ae2a11	1294	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1295	}
saloutos	0:083111ae2a11	1296	else
saloutos	0:083111ae2a11	1297	{
saloutos	0:083111ae2a11	1298	return(0U);
saloutos	0:083111ae2a11	1299	}
saloutos	0:083111ae2a11	1300	}
saloutos	0:083111ae2a11	1301
saloutos	0:083111ae2a11	1302
saloutos	0:083111ae2a11	1303	/**
saloutos	0:083111ae2a11	1304	\brief Disable Interrupt
saloutos	0:083111ae2a11	1305	\details Disables a device specific interrupt in the NVIC interrupt controller.
saloutos	0:083111ae2a11	1306	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1307	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1308	*/
saloutos	0:083111ae2a11	1309	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1310	{
saloutos	0:083111ae2a11	1311	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1312	{
saloutos	0:083111ae2a11	1313	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1314	__DSB();
saloutos	0:083111ae2a11	1315	__ISB();
saloutos	0:083111ae2a11	1316	}
saloutos	0:083111ae2a11	1317	}
saloutos	0:083111ae2a11	1318
saloutos	0:083111ae2a11	1319
saloutos	0:083111ae2a11	1320	/**
saloutos	0:083111ae2a11	1321	\brief Get Pending Interrupt
saloutos	0:083111ae2a11	1322	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
saloutos	0:083111ae2a11	1323	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1324	\return 0 Interrupt status is not pending.
saloutos	0:083111ae2a11	1325	\return 1 Interrupt status is pending.
saloutos	0:083111ae2a11	1326	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1327	*/
saloutos	0:083111ae2a11	1328	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1329	{
saloutos	0:083111ae2a11	1330	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1331	{
saloutos	0:083111ae2a11	1332	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1333	}
saloutos	0:083111ae2a11	1334	else
saloutos	0:083111ae2a11	1335	{
saloutos	0:083111ae2a11	1336	return(0U);
saloutos	0:083111ae2a11	1337	}
saloutos	0:083111ae2a11	1338	}
saloutos	0:083111ae2a11	1339
saloutos	0:083111ae2a11	1340
saloutos	0:083111ae2a11	1341	/**
saloutos	0:083111ae2a11	1342	\brief Set Pending Interrupt
saloutos	0:083111ae2a11	1343	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
saloutos	0:083111ae2a11	1344	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1345	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1346	*/
saloutos	0:083111ae2a11	1347	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1348	{
saloutos	0:083111ae2a11	1349	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1350	{
saloutos	0:083111ae2a11	1351	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1352	}
saloutos	0:083111ae2a11	1353	}
saloutos	0:083111ae2a11	1354
saloutos	0:083111ae2a11	1355
saloutos	0:083111ae2a11	1356	/**
saloutos	0:083111ae2a11	1357	\brief Clear Pending Interrupt
saloutos	0:083111ae2a11	1358	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
saloutos	0:083111ae2a11	1359	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1360	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1361	*/
saloutos	0:083111ae2a11	1362	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1363	{
saloutos	0:083111ae2a11	1364	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1365	{
saloutos	0:083111ae2a11	1366	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1367	}
saloutos	0:083111ae2a11	1368	}
saloutos	0:083111ae2a11	1369
saloutos	0:083111ae2a11	1370
saloutos	0:083111ae2a11	1371	/**
saloutos	0:083111ae2a11	1372	\brief Get Active Interrupt
saloutos	0:083111ae2a11	1373	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
saloutos	0:083111ae2a11	1374	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1375	\return 0 Interrupt status is not active.
saloutos	0:083111ae2a11	1376	\return 1 Interrupt status is active.
saloutos	0:083111ae2a11	1377	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1378	*/
saloutos	0:083111ae2a11	1379	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1380	{
saloutos	0:083111ae2a11	1381	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1382	{
saloutos	0:083111ae2a11	1383	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1384	}
saloutos	0:083111ae2a11	1385	else
saloutos	0:083111ae2a11	1386	{
saloutos	0:083111ae2a11	1387	return(0U);
saloutos	0:083111ae2a11	1388	}
saloutos	0:083111ae2a11	1389	}
saloutos	0:083111ae2a11	1390
saloutos	0:083111ae2a11	1391
saloutos	0:083111ae2a11	1392	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1393	/**
saloutos	0:083111ae2a11	1394	\brief Get Interrupt Target State
saloutos	0:083111ae2a11	1395	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	1396	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1397	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	1398	\return 1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	1399	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1400	*/
saloutos	0:083111ae2a11	1401	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1402	{
saloutos	0:083111ae2a11	1403	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1404	{
saloutos	0:083111ae2a11	1405	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1406	}
saloutos	0:083111ae2a11	1407	else
saloutos	0:083111ae2a11	1408	{
saloutos	0:083111ae2a11	1409	return(0U);
saloutos	0:083111ae2a11	1410	}
saloutos	0:083111ae2a11	1411	}
saloutos	0:083111ae2a11	1412
saloutos	0:083111ae2a11	1413
saloutos	0:083111ae2a11	1414	/**
saloutos	0:083111ae2a11	1415	\brief Set Interrupt Target State
saloutos	0:083111ae2a11	1416	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	1417	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1418	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	1419	1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	1420	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1421	*/
saloutos	0:083111ae2a11	1422	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1423	{
saloutos	0:083111ae2a11	1424	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1425	{
saloutos	0:083111ae2a11	1426	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
saloutos	0:083111ae2a11	1427	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1428	}
saloutos	0:083111ae2a11	1429	else
saloutos	0:083111ae2a11	1430	{
saloutos	0:083111ae2a11	1431	return(0U);
saloutos	0:083111ae2a11	1432	}
saloutos	0:083111ae2a11	1433	}
saloutos	0:083111ae2a11	1434
saloutos	0:083111ae2a11	1435
saloutos	0:083111ae2a11	1436	/**
saloutos	0:083111ae2a11	1437	\brief Clear Interrupt Target State
saloutos	0:083111ae2a11	1438	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
saloutos	0:083111ae2a11	1439	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1440	\return 0 if interrupt is assigned to Secure
saloutos	0:083111ae2a11	1441	1 if interrupt is assigned to Non Secure
saloutos	0:083111ae2a11	1442	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1443	*/
saloutos	0:083111ae2a11	1444	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1445	{
saloutos	0:083111ae2a11	1446	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1447	{
saloutos	0:083111ae2a11	1448	NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)));
saloutos	0:083111ae2a11	1449	return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1450	}
saloutos	0:083111ae2a11	1451	else
saloutos	0:083111ae2a11	1452	{
saloutos	0:083111ae2a11	1453	return(0U);
saloutos	0:083111ae2a11	1454	}
saloutos	0:083111ae2a11	1455	}
saloutos	0:083111ae2a11	1456	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1457
saloutos	0:083111ae2a11	1458
saloutos	0:083111ae2a11	1459	/**
saloutos	0:083111ae2a11	1460	\brief Set Interrupt Priority
saloutos	0:083111ae2a11	1461	\details Sets the priority of a device specific interrupt or a processor exception.
saloutos	0:083111ae2a11	1462	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1463	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1464	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	1465	\param [in] priority Priority to set.
saloutos	0:083111ae2a11	1466	\note The priority cannot be set for every processor exception.
saloutos	0:083111ae2a11	1467	*/
saloutos	0:083111ae2a11	1468	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
saloutos	0:083111ae2a11	1469	{
saloutos	0:083111ae2a11	1470	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1471	{
saloutos	0:083111ae2a11	1472	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
saloutos	0:083111ae2a11	1473	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos	0:083111ae2a11	1474	}
saloutos	0:083111ae2a11	1475	else
saloutos	0:083111ae2a11	1476	{
saloutos	0:083111ae2a11	1477	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
saloutos	0:083111ae2a11	1478	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos	0:083111ae2a11	1479	}
saloutos	0:083111ae2a11	1480	}
saloutos	0:083111ae2a11	1481
saloutos	0:083111ae2a11	1482
saloutos	0:083111ae2a11	1483	/**
saloutos	0:083111ae2a11	1484	\brief Get Interrupt Priority
saloutos	0:083111ae2a11	1485	\details Reads the priority of a device specific interrupt or a processor exception.
saloutos	0:083111ae2a11	1486	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1487	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1488	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	1489	\return Interrupt Priority.
saloutos	0:083111ae2a11	1490	Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos	0:083111ae2a11	1491	*/
saloutos	0:083111ae2a11	1492	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1493	{
saloutos	0:083111ae2a11	1494
saloutos	0:083111ae2a11	1495	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1496	{
saloutos	0:083111ae2a11	1497	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	1498	}
saloutos	0:083111ae2a11	1499	else
saloutos	0:083111ae2a11	1500	{
saloutos	0:083111ae2a11	1501	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	1502	}
saloutos	0:083111ae2a11	1503	}
saloutos	0:083111ae2a11	1504
saloutos	0:083111ae2a11	1505
saloutos	0:083111ae2a11	1506	/**
saloutos	0:083111ae2a11	1507	\brief Set Interrupt Vector
saloutos	0:083111ae2a11	1508	\details Sets an interrupt vector in SRAM based interrupt vector table.
saloutos	0:083111ae2a11	1509	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1510	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1511	VTOR must been relocated to SRAM before.
saloutos	0:083111ae2a11	1512	If VTOR is not present address 0 must be mapped to SRAM.
saloutos	0:083111ae2a11	1513	\param [in] IRQn Interrupt number
saloutos	0:083111ae2a11	1514	\param [in] vector Address of interrupt handler function
saloutos	0:083111ae2a11	1515	*/
saloutos	0:083111ae2a11	1516	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
saloutos	0:083111ae2a11	1517	{
saloutos	0:083111ae2a11	1518	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos	0:083111ae2a11	1519	uint32_t vectors = (uint32_t )SCB->VTOR;
saloutos	0:083111ae2a11	1520	#else
saloutos	0:083111ae2a11	1521	uint32_t vectors = (uint32_t )0x0U;
saloutos	0:083111ae2a11	1522	#endif
saloutos	0:083111ae2a11	1523	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
saloutos	0:083111ae2a11	1524	}
saloutos	0:083111ae2a11	1525
saloutos	0:083111ae2a11	1526
saloutos	0:083111ae2a11	1527	/**
saloutos	0:083111ae2a11	1528	\brief Get Interrupt Vector
saloutos	0:083111ae2a11	1529	\details Reads an interrupt vector from interrupt vector table.
saloutos	0:083111ae2a11	1530	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1531	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1532	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	1533	\return Address of interrupt handler function
saloutos	0:083111ae2a11	1534	*/
saloutos	0:083111ae2a11	1535	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1536	{
saloutos	0:083111ae2a11	1537	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
saloutos	0:083111ae2a11	1538	uint32_t vectors = (uint32_t )SCB->VTOR;
saloutos	0:083111ae2a11	1539	#else
saloutos	0:083111ae2a11	1540	uint32_t vectors = (uint32_t )0x0U;
saloutos	0:083111ae2a11	1541	#endif
saloutos	0:083111ae2a11	1542	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
saloutos	0:083111ae2a11	1543	}
saloutos	0:083111ae2a11	1544
saloutos	0:083111ae2a11	1545
saloutos	0:083111ae2a11	1546	/**
saloutos	0:083111ae2a11	1547	\brief System Reset
saloutos	0:083111ae2a11	1548	\details Initiates a system reset request to reset the MCU.
saloutos	0:083111ae2a11	1549	*/
saloutos	0:083111ae2a11	1550	__STATIC_INLINE void __NVIC_SystemReset(void)
saloutos	0:083111ae2a11	1551	{
saloutos	0:083111ae2a11	1552	__DSB(); /* Ensure all outstanding memory accesses included
saloutos	0:083111ae2a11	1553	buffered write are completed before reset */
saloutos	0:083111ae2a11	1554	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
saloutos	0:083111ae2a11	1555	SCB_AIRCR_SYSRESETREQ_Msk);
saloutos	0:083111ae2a11	1556	__DSB(); /* Ensure completion of memory access */
saloutos	0:083111ae2a11	1557
saloutos	0:083111ae2a11	1558	for(;;) /* wait until reset */
saloutos	0:083111ae2a11	1559	{
saloutos	0:083111ae2a11	1560	__NOP();
saloutos	0:083111ae2a11	1561	}
saloutos	0:083111ae2a11	1562	}
saloutos	0:083111ae2a11	1563
saloutos	0:083111ae2a11	1564	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1565	/**
saloutos	0:083111ae2a11	1566	\brief Enable Interrupt (non-secure)
saloutos	0:083111ae2a11	1567	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	1568	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1569	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1570	*/
saloutos	0:083111ae2a11	1571	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1572	{
saloutos	0:083111ae2a11	1573	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1574	{
saloutos	0:083111ae2a11	1575	NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1576	}
saloutos	0:083111ae2a11	1577	}
saloutos	0:083111ae2a11	1578
saloutos	0:083111ae2a11	1579
saloutos	0:083111ae2a11	1580	/**
saloutos	0:083111ae2a11	1581	\brief Get Interrupt Enable status (non-secure)
saloutos	0:083111ae2a11	1582	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	1583	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1584	\return 0 Interrupt is not enabled.
saloutos	0:083111ae2a11	1585	\return 1 Interrupt is enabled.
saloutos	0:083111ae2a11	1586	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1587	*/
saloutos	0:083111ae2a11	1588	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1589	{
saloutos	0:083111ae2a11	1590	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1591	{
saloutos	0:083111ae2a11	1592	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1593	}
saloutos	0:083111ae2a11	1594	else
saloutos	0:083111ae2a11	1595	{
saloutos	0:083111ae2a11	1596	return(0U);
saloutos	0:083111ae2a11	1597	}
saloutos	0:083111ae2a11	1598	}
saloutos	0:083111ae2a11	1599
saloutos	0:083111ae2a11	1600
saloutos	0:083111ae2a11	1601	/**
saloutos	0:083111ae2a11	1602	\brief Disable Interrupt (non-secure)
saloutos	0:083111ae2a11	1603	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
saloutos	0:083111ae2a11	1604	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1605	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1606	*/
saloutos	0:083111ae2a11	1607	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1608	{
saloutos	0:083111ae2a11	1609	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1610	{
saloutos	0:083111ae2a11	1611	NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1612	}
saloutos	0:083111ae2a11	1613	}
saloutos	0:083111ae2a11	1614
saloutos	0:083111ae2a11	1615
saloutos	0:083111ae2a11	1616	/**
saloutos	0:083111ae2a11	1617	\brief Get Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	1618	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
saloutos	0:083111ae2a11	1619	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1620	\return 0 Interrupt status is not pending.
saloutos	0:083111ae2a11	1621	\return 1 Interrupt status is pending.
saloutos	0:083111ae2a11	1622	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1623	*/
saloutos	0:083111ae2a11	1624	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1625	{
saloutos	0:083111ae2a11	1626	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1627	{
saloutos	0:083111ae2a11	1628	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1629	}
saloutos	0:083111ae2a11	1630	}
saloutos	0:083111ae2a11	1631
saloutos	0:083111ae2a11	1632
saloutos	0:083111ae2a11	1633	/**
saloutos	0:083111ae2a11	1634	\brief Set Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	1635	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
saloutos	0:083111ae2a11	1636	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1637	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1638	*/
saloutos	0:083111ae2a11	1639	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1640	{
saloutos	0:083111ae2a11	1641	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1642	{
saloutos	0:083111ae2a11	1643	NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1644	}
saloutos	0:083111ae2a11	1645	}
saloutos	0:083111ae2a11	1646
saloutos	0:083111ae2a11	1647
saloutos	0:083111ae2a11	1648	/**
saloutos	0:083111ae2a11	1649	\brief Clear Pending Interrupt (non-secure)
saloutos	0:083111ae2a11	1650	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
saloutos	0:083111ae2a11	1651	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1652	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1653	*/
saloutos	0:083111ae2a11	1654	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1655	{
saloutos	0:083111ae2a11	1656	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1657	{
saloutos	0:083111ae2a11	1658	NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
saloutos	0:083111ae2a11	1659	}
saloutos	0:083111ae2a11	1660	}
saloutos	0:083111ae2a11	1661
saloutos	0:083111ae2a11	1662
saloutos	0:083111ae2a11	1663	/**
saloutos	0:083111ae2a11	1664	\brief Get Active Interrupt (non-secure)
saloutos	0:083111ae2a11	1665	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
saloutos	0:083111ae2a11	1666	\param [in] IRQn Device specific interrupt number.
saloutos	0:083111ae2a11	1667	\return 0 Interrupt status is not active.
saloutos	0:083111ae2a11	1668	\return 1 Interrupt status is active.
saloutos	0:083111ae2a11	1669	\note IRQn must not be negative.
saloutos	0:083111ae2a11	1670	*/
saloutos	0:083111ae2a11	1671	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1672	{
saloutos	0:083111ae2a11	1673	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1674	{
saloutos	0:083111ae2a11	1675	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
saloutos	0:083111ae2a11	1676	}
saloutos	0:083111ae2a11	1677	else
saloutos	0:083111ae2a11	1678	{
saloutos	0:083111ae2a11	1679	return(0U);
saloutos	0:083111ae2a11	1680	}
saloutos	0:083111ae2a11	1681	}
saloutos	0:083111ae2a11	1682
saloutos	0:083111ae2a11	1683
saloutos	0:083111ae2a11	1684	/**
saloutos	0:083111ae2a11	1685	\brief Set Interrupt Priority (non-secure)
saloutos	0:083111ae2a11	1686	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
saloutos	0:083111ae2a11	1687	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1688	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1689	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	1690	\param [in] priority Priority to set.
saloutos	0:083111ae2a11	1691	\note The priority cannot be set for every non-secure processor exception.
saloutos	0:083111ae2a11	1692	*/
saloutos	0:083111ae2a11	1693	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
saloutos	0:083111ae2a11	1694	{
saloutos	0:083111ae2a11	1695	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1696	{
saloutos	0:083111ae2a11	1697	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
saloutos	0:083111ae2a11	1698	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos	0:083111ae2a11	1699	}
saloutos	0:083111ae2a11	1700	else
saloutos	0:083111ae2a11	1701	{
saloutos	0:083111ae2a11	1702	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
saloutos	0:083111ae2a11	1703	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
saloutos	0:083111ae2a11	1704	}
saloutos	0:083111ae2a11	1705	}
saloutos	0:083111ae2a11	1706
saloutos	0:083111ae2a11	1707
saloutos	0:083111ae2a11	1708	/**
saloutos	0:083111ae2a11	1709	\brief Get Interrupt Priority (non-secure)
saloutos	0:083111ae2a11	1710	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
saloutos	0:083111ae2a11	1711	The interrupt number can be positive to specify a device specific interrupt,
saloutos	0:083111ae2a11	1712	or negative to specify a processor exception.
saloutos	0:083111ae2a11	1713	\param [in] IRQn Interrupt number.
saloutos	0:083111ae2a11	1714	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
saloutos	0:083111ae2a11	1715	*/
saloutos	0:083111ae2a11	1716	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
saloutos	0:083111ae2a11	1717	{
saloutos	0:083111ae2a11	1718
saloutos	0:083111ae2a11	1719	if ((int32_t)(IRQn) >= 0)
saloutos	0:083111ae2a11	1720	{
saloutos	0:083111ae2a11	1721	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	1722	}
saloutos	0:083111ae2a11	1723	else
saloutos	0:083111ae2a11	1724	{
saloutos	0:083111ae2a11	1725	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
saloutos	0:083111ae2a11	1726	}
saloutos	0:083111ae2a11	1727	}
saloutos	0:083111ae2a11	1728	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1729
saloutos	0:083111ae2a11	1730	/@} end of CMSIS_Core_NVICFunctions /
saloutos	0:083111ae2a11	1731
saloutos	0:083111ae2a11	1732
saloutos	0:083111ae2a11	1733	/* ########################## FPU functions #################################### */
saloutos	0:083111ae2a11	1734	/**
saloutos	0:083111ae2a11	1735	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	1736	\defgroup CMSIS_Core_FpuFunctions FPU Functions
saloutos	0:083111ae2a11	1737	\brief Function that provides FPU type.
saloutos	0:083111ae2a11	1738	@{
saloutos	0:083111ae2a11	1739	*/
saloutos	0:083111ae2a11	1740
saloutos	0:083111ae2a11	1741	/**
saloutos	0:083111ae2a11	1742	\brief get FPU type
saloutos	0:083111ae2a11	1743	\details returns the FPU type
saloutos	0:083111ae2a11	1744	\returns
saloutos	0:083111ae2a11	1745	- \b 0: No FPU
saloutos	0:083111ae2a11	1746	- \b 1: Single precision FPU
saloutos	0:083111ae2a11	1747	- \b 2: Double + Single precision FPU
saloutos	0:083111ae2a11	1748	*/
saloutos	0:083111ae2a11	1749	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
saloutos	0:083111ae2a11	1750	{
saloutos	0:083111ae2a11	1751	return 0U; /* No FPU */
saloutos	0:083111ae2a11	1752	}
saloutos	0:083111ae2a11	1753
saloutos	0:083111ae2a11	1754
saloutos	0:083111ae2a11	1755	/@} end of CMSIS_Core_FpuFunctions /
saloutos	0:083111ae2a11	1756
saloutos	0:083111ae2a11	1757
saloutos	0:083111ae2a11	1758
saloutos	0:083111ae2a11	1759	/* ########################## SAU functions #################################### */
saloutos	0:083111ae2a11	1760	/**
saloutos	0:083111ae2a11	1761	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	1762	\defgroup CMSIS_Core_SAUFunctions SAU Functions
saloutos	0:083111ae2a11	1763	\brief Functions that configure the SAU.
saloutos	0:083111ae2a11	1764	@{
saloutos	0:083111ae2a11	1765	*/
saloutos	0:083111ae2a11	1766
saloutos	0:083111ae2a11	1767	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1768
saloutos	0:083111ae2a11	1769	/**
saloutos	0:083111ae2a11	1770	\brief Enable SAU
saloutos	0:083111ae2a11	1771	\details Enables the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	1772	*/
saloutos	0:083111ae2a11	1773	__STATIC_INLINE void TZ_SAU_Enable(void)
saloutos	0:083111ae2a11	1774	{
saloutos	0:083111ae2a11	1775	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
saloutos	0:083111ae2a11	1776	}
saloutos	0:083111ae2a11	1777
saloutos	0:083111ae2a11	1778
saloutos	0:083111ae2a11	1779
saloutos	0:083111ae2a11	1780	/**
saloutos	0:083111ae2a11	1781	\brief Disable SAU
saloutos	0:083111ae2a11	1782	\details Disables the Security Attribution Unit (SAU).
saloutos	0:083111ae2a11	1783	*/
saloutos	0:083111ae2a11	1784	__STATIC_INLINE void TZ_SAU_Disable(void)
saloutos	0:083111ae2a11	1785	{
saloutos	0:083111ae2a11	1786	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
saloutos	0:083111ae2a11	1787	}
saloutos	0:083111ae2a11	1788
saloutos	0:083111ae2a11	1789	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1790
saloutos	0:083111ae2a11	1791	/@} end of CMSIS_Core_SAUFunctions /
saloutos	0:083111ae2a11	1792
saloutos	0:083111ae2a11	1793
saloutos	0:083111ae2a11	1794
saloutos	0:083111ae2a11	1795
saloutos	0:083111ae2a11	1796	/* ################################## SysTick function ############################################ */
saloutos	0:083111ae2a11	1797	/**
saloutos	0:083111ae2a11	1798	\ingroup CMSIS_Core_FunctionInterface
saloutos	0:083111ae2a11	1799	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
saloutos	0:083111ae2a11	1800	\brief Functions that configure the System.
saloutos	0:083111ae2a11	1801	@{
saloutos	0:083111ae2a11	1802	*/
saloutos	0:083111ae2a11	1803
saloutos	0:083111ae2a11	1804	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
saloutos	0:083111ae2a11	1805
saloutos	0:083111ae2a11	1806	/**
saloutos	0:083111ae2a11	1807	\brief System Tick Configuration
saloutos	0:083111ae2a11	1808	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
saloutos	0:083111ae2a11	1809	Counter is in free running mode to generate periodic interrupts.
saloutos	0:083111ae2a11	1810	\param [in] ticks Number of ticks between two interrupts.
saloutos	0:083111ae2a11	1811	\return 0 Function succeeded.
saloutos	0:083111ae2a11	1812	\return 1 Function failed.
saloutos	0:083111ae2a11	1813	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos	0:083111ae2a11	1814	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos	0:083111ae2a11	1815	must contain a vendor-specific implementation of this function.
saloutos	0:083111ae2a11	1816	*/
saloutos	0:083111ae2a11	1817	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
saloutos	0:083111ae2a11	1818	{
saloutos	0:083111ae2a11	1819	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos	0:083111ae2a11	1820	{
saloutos	0:083111ae2a11	1821	return (1UL); /* Reload value impossible */
saloutos	0:083111ae2a11	1822	}
saloutos	0:083111ae2a11	1823
saloutos	0:083111ae2a11	1824	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos	0:083111ae2a11	1825	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos	0:083111ae2a11	1826	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos	0:083111ae2a11	1827	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
saloutos	0:083111ae2a11	1828	SysTick_CTRL_TICKINT_Msk \|
saloutos	0:083111ae2a11	1829	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos	0:083111ae2a11	1830	return (0UL); /* Function successful */
saloutos	0:083111ae2a11	1831	}
saloutos	0:083111ae2a11	1832
saloutos	0:083111ae2a11	1833	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
saloutos	0:083111ae2a11	1834	/**
saloutos	0:083111ae2a11	1835	\brief System Tick Configuration (non-secure)
saloutos	0:083111ae2a11	1836	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
saloutos	0:083111ae2a11	1837	Counter is in free running mode to generate periodic interrupts.
saloutos	0:083111ae2a11	1838	\param [in] ticks Number of ticks between two interrupts.
saloutos	0:083111ae2a11	1839	\return 0 Function succeeded.
saloutos	0:083111ae2a11	1840	\return 1 Function failed.
saloutos	0:083111ae2a11	1841	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
saloutos	0:083111ae2a11	1842	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
saloutos	0:083111ae2a11	1843	must contain a vendor-specific implementation of this function.
saloutos	0:083111ae2a11	1844
saloutos	0:083111ae2a11	1845	*/
saloutos	0:083111ae2a11	1846	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
saloutos	0:083111ae2a11	1847	{
saloutos	0:083111ae2a11	1848	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
saloutos	0:083111ae2a11	1849	{
saloutos	0:083111ae2a11	1850	return (1UL); /* Reload value impossible */
saloutos	0:083111ae2a11	1851	}
saloutos	0:083111ae2a11	1852
saloutos	0:083111ae2a11	1853	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
saloutos	0:083111ae2a11	1854	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
saloutos	0:083111ae2a11	1855	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
saloutos	0:083111ae2a11	1856	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
saloutos	0:083111ae2a11	1857	SysTick_CTRL_TICKINT_Msk \|
saloutos	0:083111ae2a11	1858	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
saloutos	0:083111ae2a11	1859	return (0UL); /* Function successful */
saloutos	0:083111ae2a11	1860	}
saloutos	0:083111ae2a11	1861	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
saloutos	0:083111ae2a11	1862
saloutos	0:083111ae2a11	1863	#endif
saloutos	0:083111ae2a11	1864
saloutos	0:083111ae2a11	1865	/@} end of CMSIS_Core_SysTickFunctions /
saloutos	0:083111ae2a11	1866
saloutos	0:083111ae2a11	1867
saloutos	0:083111ae2a11	1868
saloutos	0:083111ae2a11	1869
saloutos	0:083111ae2a11	1870	#ifdef __cplusplus
saloutos	0:083111ae2a11	1871	}
saloutos	0:083111ae2a11	1872	#endif
saloutos	0:083111ae2a11	1873
saloutos	0:083111ae2a11	1874	#endif /* __CORE_CM23_H_DEPENDANT */
saloutos	0:083111ae2a11	1875
saloutos	0:083111ae2a11	1876	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	09 Mar 2021
Imports:	13
Forks:	0
Commits:	4
Dependents:	4
Dependencies:	0
Followers:	1

cmsis/core_cm23.h@0:083111ae2a11, 2020-11-26 (annotated)

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